intel_blit.c revision c40b7910ee1338b9d391816df5391ce43f509ef0
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include "main/mtypes.h" 30#include "main/context.h" 31#include "main/enums.h" 32#include "main/colormac.h" 33 34#include "intel_blit.h" 35#include "intel_buffers.h" 36#include "intel_context.h" 37#include "intel_fbo.h" 38#include "intel_reg.h" 39#include "intel_regions.h" 40#include "intel_batchbuffer.h" 41#include "intel_mipmap_tree.h" 42 43#define FILE_DEBUG_FLAG DEBUG_BLIT 44 45static GLuint translate_raster_op(GLenum logicop) 46{ 47 switch(logicop) { 48 case GL_CLEAR: return 0x00; 49 case GL_AND: return 0x88; 50 case GL_AND_REVERSE: return 0x44; 51 case GL_COPY: return 0xCC; 52 case GL_AND_INVERTED: return 0x22; 53 case GL_NOOP: return 0xAA; 54 case GL_XOR: return 0x66; 55 case GL_OR: return 0xEE; 56 case GL_NOR: return 0x11; 57 case GL_EQUIV: return 0x99; 58 case GL_INVERT: return 0x55; 59 case GL_OR_REVERSE: return 0xDD; 60 case GL_COPY_INVERTED: return 0x33; 61 case GL_OR_INVERTED: return 0xBB; 62 case GL_NAND: return 0x77; 63 case GL_SET: return 0xFF; 64 default: return 0; 65 } 66} 67 68static uint32_t 69br13_for_cpp(int cpp) 70{ 71 switch (cpp) { 72 case 4: 73 return BR13_8888; 74 break; 75 case 2: 76 return BR13_565; 77 break; 78 case 1: 79 return BR13_8; 80 break; 81 default: 82 assert(0); 83 return 0; 84 } 85} 86 87/* Copy BitBlt 88 */ 89GLboolean 90intelEmitCopyBlit(struct intel_context *intel, 91 GLuint cpp, 92 GLshort src_pitch, 93 drm_intel_bo *src_buffer, 94 GLuint src_offset, 95 uint32_t src_tiling, 96 GLshort dst_pitch, 97 drm_intel_bo *dst_buffer, 98 GLuint dst_offset, 99 uint32_t dst_tiling, 100 GLshort src_x, GLshort src_y, 101 GLshort dst_x, GLshort dst_y, 102 GLshort w, GLshort h, 103 GLenum logic_op) 104{ 105 GLuint CMD, BR13, pass = 0; 106 int dst_y2 = dst_y + h; 107 int dst_x2 = dst_x + w; 108 drm_intel_bo *aper_array[3]; 109 BATCH_LOCALS; 110 111 if (dst_tiling != I915_TILING_NONE) { 112 if (dst_offset & 4095) 113 return GL_FALSE; 114 if (dst_tiling == I915_TILING_Y) 115 return GL_FALSE; 116 } 117 if (src_tiling != I915_TILING_NONE) { 118 if (src_offset & 4095) 119 return GL_FALSE; 120 if (src_tiling == I915_TILING_Y) 121 return GL_FALSE; 122 } 123 124 /* do space check before going any further */ 125 do { 126 aper_array[0] = intel->batch.bo; 127 aper_array[1] = dst_buffer; 128 aper_array[2] = src_buffer; 129 130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 131 intel_batchbuffer_flush(intel); 132 pass++; 133 } else 134 break; 135 } while (pass < 2); 136 137 if (pass >= 2) 138 return GL_FALSE; 139 140 intel_batchbuffer_require_space(intel, 8 * 4, true); 141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 142 __FUNCTION__, 143 src_buffer, src_pitch, src_offset, src_x, src_y, 144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 145 146 src_pitch *= cpp; 147 dst_pitch *= cpp; 148 149 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16; 150 151 switch (cpp) { 152 case 1: 153 case 2: 154 CMD = XY_SRC_COPY_BLT_CMD; 155 break; 156 case 4: 157 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 158 break; 159 default: 160 return GL_FALSE; 161 } 162 163#ifndef I915 164 if (dst_tiling != I915_TILING_NONE) { 165 CMD |= XY_DST_TILED; 166 dst_pitch /= 4; 167 } 168 if (src_tiling != I915_TILING_NONE) { 169 CMD |= XY_SRC_TILED; 170 src_pitch /= 4; 171 } 172#endif 173 174 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 175 return GL_TRUE; 176 } 177 178 assert(dst_x < dst_x2); 179 assert(dst_y < dst_y2); 180 181 BEGIN_BATCH_BLT(8); 182 OUT_BATCH(CMD); 183 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 184 OUT_BATCH((dst_y << 16) | dst_x); 185 OUT_BATCH((dst_y2 << 16) | dst_x2); 186 OUT_RELOC_FENCED(dst_buffer, 187 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 188 dst_offset); 189 OUT_BATCH((src_y << 16) | src_x); 190 OUT_BATCH((uint16_t)src_pitch); 191 OUT_RELOC_FENCED(src_buffer, 192 I915_GEM_DOMAIN_RENDER, 0, 193 src_offset); 194 ADVANCE_BATCH(); 195 196 intel_batchbuffer_emit_mi_flush(intel); 197 198 return GL_TRUE; 199} 200 201 202/** 203 * Use blitting to clear the renderbuffers named by 'flags'. 204 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 205 * since that might include software renderbuffers or renderbuffers 206 * which we're clearing with triangles. 207 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 208 */ 209GLbitfield 210intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) 211{ 212 struct intel_context *intel = intel_context(ctx); 213 struct gl_framebuffer *fb = ctx->DrawBuffer; 214 GLuint clear_depth_value, clear_depth_mask; 215 GLboolean all; 216 GLint cx, cy, cw, ch; 217 GLbitfield fail_mask = 0; 218 BATCH_LOCALS; 219 220 /* 221 * Compute values for clearing the buffers. 222 */ 223 clear_depth_value = 0; 224 clear_depth_mask = 0; 225 if (mask & BUFFER_BIT_DEPTH) { 226 clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 227 clear_depth_mask = XY_BLT_WRITE_RGB; 228 } 229 if (mask & BUFFER_BIT_STENCIL) { 230 clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24; 231 clear_depth_mask |= XY_BLT_WRITE_ALPHA; 232 } 233 234 cx = fb->_Xmin; 235 if (fb->Name == 0) 236 cy = ctx->DrawBuffer->Height - fb->_Ymax; 237 else 238 cy = fb->_Ymin; 239 cw = fb->_Xmax - fb->_Xmin; 240 ch = fb->_Ymax - fb->_Ymin; 241 242 if (cw == 0 || ch == 0) 243 return 0; 244 245 all = (cw == fb->Width && ch == fb->Height); 246 247 /* Loop over all renderbuffers */ 248 mask &= (1 << BUFFER_COUNT) - 1; 249 while (mask) { 250 GLuint buf = _mesa_ffs(mask) - 1; 251 GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL; 252 struct intel_renderbuffer *irb; 253 drm_intel_bo *write_buffer; 254 int x1, y1, x2, y2; 255 uint32_t clear_val; 256 uint32_t BR13, CMD; 257 int pitch, cpp; 258 drm_intel_bo *aper_array[2]; 259 260 mask &= ~(1 << buf); 261 262 irb = intel_get_renderbuffer(fb, buf); 263 if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) { 264 fail_mask |= 1 << buf; 265 continue; 266 } 267 268 /* OK, clear this renderbuffer */ 269 write_buffer = intel_region_buffer(intel, irb->region, 270 all ? INTEL_WRITE_FULL : 271 INTEL_WRITE_PART); 272 x1 = cx + irb->region->draw_x; 273 y1 = cy + irb->region->draw_y; 274 x2 = cx + cw + irb->region->draw_x; 275 y2 = cy + ch + irb->region->draw_y; 276 277 pitch = irb->region->pitch; 278 cpp = irb->region->cpp; 279 280 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 281 __FUNCTION__, 282 irb->region->buffer, (pitch * cpp), 283 x1, y1, x2 - x1, y2 - y1); 284 285 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 286 CMD = XY_COLOR_BLT_CMD; 287 288 /* Setup the blit command */ 289 if (cpp == 4) { 290 if (is_depth_stencil) { 291 CMD |= clear_depth_mask; 292 } else { 293 /* clearing RGBA */ 294 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 295 } 296 } 297 298 assert(irb->region->tiling != I915_TILING_Y); 299 300#ifndef I915 301 if (irb->region->tiling != I915_TILING_NONE) { 302 CMD |= XY_DST_TILED; 303 pitch /= 4; 304 } 305#endif 306 BR13 |= (pitch * cpp); 307 308 if (is_depth_stencil) { 309 clear_val = clear_depth_value; 310 } else { 311 uint8_t clear[4]; 312 GLclampf *color = ctx->Color.ClearColor; 313 314 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); 315 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); 316 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); 317 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); 318 319 switch (irb->Base.Format) { 320 case MESA_FORMAT_ARGB8888: 321 case MESA_FORMAT_XRGB8888: 322 clear_val = PACK_COLOR_8888(clear[3], clear[0], 323 clear[1], clear[2]); 324 break; 325 case MESA_FORMAT_RGB565: 326 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]); 327 break; 328 case MESA_FORMAT_ARGB4444: 329 clear_val = PACK_COLOR_4444(clear[3], clear[0], 330 clear[1], clear[2]); 331 break; 332 case MESA_FORMAT_ARGB1555: 333 clear_val = PACK_COLOR_1555(clear[3], clear[0], 334 clear[1], clear[2]); 335 break; 336 case MESA_FORMAT_A8: 337 clear_val = PACK_COLOR_8888(clear[3], clear[3], 338 clear[3], clear[3]); 339 break; 340 default: 341 fail_mask |= 1 << buf; 342 continue; 343 } 344 } 345 346 assert(x1 < x2); 347 assert(y1 < y2); 348 349 /* do space check before going any further */ 350 aper_array[0] = intel->batch.bo; 351 aper_array[1] = write_buffer; 352 353 if (drm_intel_bufmgr_check_aperture_space(aper_array, 354 ARRAY_SIZE(aper_array)) != 0) { 355 intel_batchbuffer_flush(intel); 356 } 357 358 BEGIN_BATCH_BLT(6); 359 OUT_BATCH(CMD); 360 OUT_BATCH(BR13); 361 OUT_BATCH((y1 << 16) | x1); 362 OUT_BATCH((y2 << 16) | x2); 363 OUT_RELOC_FENCED(write_buffer, 364 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 365 0); 366 OUT_BATCH(clear_val); 367 ADVANCE_BATCH(); 368 369 if (intel->always_flush_cache) 370 intel_batchbuffer_emit_mi_flush(intel); 371 372 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) 373 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL); 374 } 375 376 return fail_mask; 377} 378 379GLboolean 380intelEmitImmediateColorExpandBlit(struct intel_context *intel, 381 GLuint cpp, 382 GLubyte *src_bits, GLuint src_size, 383 GLuint fg_color, 384 GLshort dst_pitch, 385 drm_intel_bo *dst_buffer, 386 GLuint dst_offset, 387 uint32_t dst_tiling, 388 GLshort x, GLshort y, 389 GLshort w, GLshort h, 390 GLenum logic_op) 391{ 392 int dwords = ALIGN(src_size, 8) / 4; 393 uint32_t opcode, br13, blit_cmd; 394 395 if (dst_tiling != I915_TILING_NONE) { 396 if (dst_offset & 4095) 397 return GL_FALSE; 398 if (dst_tiling == I915_TILING_Y) 399 return GL_FALSE; 400 } 401 402 assert( logic_op - GL_CLEAR >= 0 ); 403 assert( logic_op - GL_CLEAR < 0x10 ); 404 assert(dst_pitch > 0); 405 406 if (w < 0 || h < 0) 407 return GL_TRUE; 408 409 dst_pitch *= cpp; 410 411 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 412 __FUNCTION__, 413 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 414 415 intel_batchbuffer_require_space(intel, 416 (8 * 4) + 417 (3 * 4) + 418 dwords * 4, true); 419 420 opcode = XY_SETUP_BLT_CMD; 421 if (cpp == 4) 422 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 423#ifndef I915 424 if (dst_tiling != I915_TILING_NONE) { 425 opcode |= XY_DST_TILED; 426 dst_pitch /= 4; 427 } 428#endif 429 430 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 431 br13 |= br13_for_cpp(cpp); 432 433 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 434 if (dst_tiling != I915_TILING_NONE) 435 blit_cmd |= XY_DST_TILED; 436 437 BEGIN_BATCH_BLT(8 + 3); 438 OUT_BATCH(opcode); 439 OUT_BATCH(br13); 440 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 441 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 442 OUT_RELOC_FENCED(dst_buffer, 443 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 444 dst_offset); 445 OUT_BATCH(0); /* bg */ 446 OUT_BATCH(fg_color); /* fg */ 447 OUT_BATCH(0); /* pattern base addr */ 448 449 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 450 OUT_BATCH((y << 16) | x); 451 OUT_BATCH(((y + h) << 16) | (x + w)); 452 ADVANCE_BATCH(); 453 454 intel_batchbuffer_data(intel, src_bits, dwords * 4, true); 455 456 intel_batchbuffer_emit_mi_flush(intel); 457 458 return GL_TRUE; 459} 460 461/* We don't have a memmove-type blit like some other hardware, so we'll do a 462 * rectangular blit covering a large space, then emit 1-scanline blit at the 463 * end to cover the last if we need. 464 */ 465void 466intel_emit_linear_blit(struct intel_context *intel, 467 drm_intel_bo *dst_bo, 468 unsigned int dst_offset, 469 drm_intel_bo *src_bo, 470 unsigned int src_offset, 471 unsigned int size) 472{ 473 GLuint pitch, height; 474 GLboolean ok; 475 476 /* The pitch given to the GPU must be DWORD aligned, and 477 * we want width to match pitch. Max width is (1 << 15 - 1), 478 * rounding that down to the nearest DWORD is 1 << 15 - 4 479 */ 480 pitch = MIN2(size, (1 << 15) - 4); 481 height = size / pitch; 482 ok = intelEmitCopyBlit(intel, 1, 483 pitch, src_bo, src_offset, I915_TILING_NONE, 484 pitch, dst_bo, dst_offset, I915_TILING_NONE, 485 0, 0, /* src x/y */ 486 0, 0, /* dst x/y */ 487 pitch, height, /* w, h */ 488 GL_COPY); 489 assert(ok); 490 491 src_offset += pitch * height; 492 dst_offset += pitch * height; 493 size -= pitch * height; 494 assert (size < (1 << 15)); 495 assert ((size & 3) == 0); /* Pitch must be DWORD aligned */ 496 if (size != 0) { 497 ok = intelEmitCopyBlit(intel, 1, 498 size, src_bo, src_offset, I915_TILING_NONE, 499 size, dst_bo, dst_offset, I915_TILING_NONE, 500 0, 0, /* src x/y */ 501 0, 0, /* dst x/y */ 502 size, 1, /* w, h */ 503 GL_COPY); 504 assert(ok); 505 } 506} 507 508/** 509 * Used to initialize the alpha value of an ARGB8888 teximage after 510 * loading it from an XRGB8888 source. 511 * 512 * This is very common with glCopyTexImage2D(). 513 */ 514void 515intel_set_teximage_alpha_to_one(struct gl_context *ctx, 516 struct intel_texture_image *intel_image) 517{ 518 struct intel_context *intel = intel_context(ctx); 519 unsigned int image_x, image_y; 520 uint32_t x1, y1, x2, y2; 521 uint32_t BR13, CMD; 522 int pitch, cpp; 523 drm_intel_bo *aper_array[2]; 524 struct intel_region *region = intel_image->mt->region; 525 BATCH_LOCALS; 526 527 assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888); 528 529 /* get dest x/y in destination texture */ 530 intel_miptree_get_image_offset(intel_image->mt, 531 intel_image->level, 532 intel_image->face, 533 0, 534 &image_x, &image_y); 535 536 x1 = image_x; 537 y1 = image_y; 538 x2 = image_x + intel_image->base.Width; 539 y2 = image_y + intel_image->base.Height; 540 541 pitch = region->pitch; 542 cpp = region->cpp; 543 544 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", 545 __FUNCTION__, 546 intel_image->mt->region->buffer, (pitch * cpp), 547 x1, y1, x2 - x1, y2 - y1); 548 549 BR13 = br13_for_cpp(cpp) | 0xf0 << 16; 550 CMD = XY_COLOR_BLT_CMD; 551 CMD |= XY_BLT_WRITE_ALPHA; 552 553 assert(region->tiling != I915_TILING_Y); 554 555#ifndef I915 556 if (region->tiling != I915_TILING_NONE) { 557 CMD |= XY_DST_TILED; 558 pitch /= 4; 559 } 560#endif 561 BR13 |= (pitch * cpp); 562 563 /* do space check before going any further */ 564 aper_array[0] = intel->batch.bo; 565 aper_array[1] = region->buffer; 566 567 if (drm_intel_bufmgr_check_aperture_space(aper_array, 568 ARRAY_SIZE(aper_array)) != 0) { 569 intel_batchbuffer_flush(intel); 570 } 571 572 BEGIN_BATCH_BLT(6); 573 OUT_BATCH(CMD); 574 OUT_BATCH(BR13); 575 OUT_BATCH((y1 << 16) | x1); 576 OUT_BATCH((y2 << 16) | x2); 577 OUT_RELOC_FENCED(region->buffer, 578 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 579 0); 580 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ 581 ADVANCE_BATCH(); 582 583 intel_batchbuffer_emit_mi_flush(intel); 584} 585