intel_context.c revision a43599d1d1a583b25c0a63c28c0a5001387fa518 
1/**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29#include "main/glheader.h"
30#include "main/context.h"
31#include "main/extensions.h"
32#include "main/fbobject.h"
33#include "main/framebuffer.h"
34#include "main/imports.h"
35#include "main/points.h"
36#include "main/renderbuffer.h"
37
38#include "swrast/swrast.h"
39#include "swrast_setup/swrast_setup.h"
40#include "tnl/tnl.h"
41#include "drivers/common/driverfuncs.h"
42#include "drivers/common/meta.h"
43
44#include "intel_chipset.h"
45#include "intel_buffers.h"
46#include "intel_tex.h"
47#include "intel_batchbuffer.h"
48#include "intel_clear.h"
49#include "intel_extensions.h"
50#include "intel_pixel.h"
51#include "intel_regions.h"
52#include "intel_buffer_objects.h"
53#include "intel_fbo.h"
54#include "intel_bufmgr.h"
55#include "intel_screen.h"
56#include "intel_mipmap_tree.h"
57
58#include "utils.h"
59#include "../glsl/ralloc.h"
60
61#ifndef INTEL_DEBUG
62int INTEL_DEBUG = (0);
63#endif
64
65
66static const GLubyte *
67intelGetString(struct gl_context * ctx, GLenum name)
68{
69   const struct intel_context *const intel = intel_context(ctx);
70   const char *chipset;
71   static char buffer[128];
72
73   switch (name) {
74   case GL_VENDOR:
75      return (GLubyte *) "Intel Open Source Technology Center";
76      break;
77
78   case GL_RENDERER:
79      switch (intel->intelScreen->deviceID) {
80      case PCI_CHIP_845_G:
81         chipset = "Intel(R) 845G";
82         break;
83      case PCI_CHIP_I830_M:
84         chipset = "Intel(R) 830M";
85         break;
86      case PCI_CHIP_I855_GM:
87         chipset = "Intel(R) 852GM/855GM";
88         break;
89      case PCI_CHIP_I865_G:
90         chipset = "Intel(R) 865G";
91         break;
92      case PCI_CHIP_I915_G:
93         chipset = "Intel(R) 915G";
94         break;
95      case PCI_CHIP_E7221_G:
96	 chipset = "Intel (R) E7221G (i915)";
97	 break;
98      case PCI_CHIP_I915_GM:
99         chipset = "Intel(R) 915GM";
100         break;
101      case PCI_CHIP_I945_G:
102         chipset = "Intel(R) 945G";
103         break;
104      case PCI_CHIP_I945_GM:
105         chipset = "Intel(R) 945GM";
106         break;
107      case PCI_CHIP_I945_GME:
108         chipset = "Intel(R) 945GME";
109         break;
110      case PCI_CHIP_G33_G:
111	 chipset = "Intel(R) G33";
112	 break;
113      case PCI_CHIP_Q35_G:
114	 chipset = "Intel(R) Q35";
115	 break;
116      case PCI_CHIP_Q33_G:
117	 chipset = "Intel(R) Q33";
118	 break;
119      case PCI_CHIP_IGD_GM:
120      case PCI_CHIP_IGD_G:
121	 chipset = "Intel(R) IGD";
122	 break;
123      case PCI_CHIP_I965_Q:
124	 chipset = "Intel(R) 965Q";
125	 break;
126      case PCI_CHIP_I965_G:
127      case PCI_CHIP_I965_G_1:
128	 chipset = "Intel(R) 965G";
129	 break;
130      case PCI_CHIP_I946_GZ:
131	 chipset = "Intel(R) 946GZ";
132	 break;
133      case PCI_CHIP_I965_GM:
134	 chipset = "Intel(R) 965GM";
135	 break;
136      case PCI_CHIP_I965_GME:
137	 chipset = "Intel(R) 965GME/GLE";
138	 break;
139      case PCI_CHIP_GM45_GM:
140	 chipset = "Mobile Intel® GM45 Express Chipset";
141	 break;
142      case PCI_CHIP_IGD_E_G:
143	 chipset = "Intel(R) Integrated Graphics Device";
144	 break;
145      case PCI_CHIP_G45_G:
146         chipset = "Intel(R) G45/G43";
147         break;
148      case PCI_CHIP_Q45_G:
149         chipset = "Intel(R) Q45/Q43";
150         break;
151      case PCI_CHIP_G41_G:
152         chipset = "Intel(R) G41";
153         break;
154      case PCI_CHIP_B43_G:
155      case PCI_CHIP_B43_G1:
156         chipset = "Intel(R) B43";
157         break;
158      case PCI_CHIP_ILD_G:
159         chipset = "Intel(R) Ironlake Desktop";
160         break;
161      case PCI_CHIP_ILM_G:
162         chipset = "Intel(R) Ironlake Mobile";
163         break;
164      case PCI_CHIP_SANDYBRIDGE_GT1:
165      case PCI_CHIP_SANDYBRIDGE_GT2:
166      case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
167	 chipset = "Intel(R) Sandybridge Desktop";
168	 break;
169      case PCI_CHIP_SANDYBRIDGE_M_GT1:
170      case PCI_CHIP_SANDYBRIDGE_M_GT2:
171      case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
172	 chipset = "Intel(R) Sandybridge Mobile";
173	 break;
174      case PCI_CHIP_SANDYBRIDGE_S:
175	 chipset = "Intel(R) Sandybridge Server";
176	 break;
177      case PCI_CHIP_IVYBRIDGE_GT1:
178      case PCI_CHIP_IVYBRIDGE_GT2:
179	 chipset = "Intel(R) Ivybridge Desktop";
180	 break;
181      case PCI_CHIP_IVYBRIDGE_M_GT1:
182      case PCI_CHIP_IVYBRIDGE_M_GT2:
183	 chipset = "Intel(R) Ivybridge Mobile";
184	 break;
185      case PCI_CHIP_IVYBRIDGE_S_GT1:
186      case PCI_CHIP_IVYBRIDGE_S_GT2:
187	 chipset = "Intel(R) Ivybridge Server";
188	 break;
189      case PCI_CHIP_HASWELL_GT1:
190      case PCI_CHIP_HASWELL_GT2:
191      case PCI_CHIP_HASWELL_GT2_PLUS:
192      case PCI_CHIP_HASWELL_SDV_GT1:
193      case PCI_CHIP_HASWELL_SDV_GT2:
194      case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
195      case PCI_CHIP_HASWELL_ULT_GT1:
196      case PCI_CHIP_HASWELL_ULT_GT2:
197      case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
198      case PCI_CHIP_HASWELL_CRW_GT1:
199      case PCI_CHIP_HASWELL_CRW_GT2:
200      case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
201	 chipset = "Intel(R) Haswell Desktop";
202	 break;
203      case PCI_CHIP_HASWELL_M_GT1:
204      case PCI_CHIP_HASWELL_M_GT2:
205      case PCI_CHIP_HASWELL_M_GT2_PLUS:
206      case PCI_CHIP_HASWELL_SDV_M_GT1:
207      case PCI_CHIP_HASWELL_SDV_M_GT2:
208      case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
209      case PCI_CHIP_HASWELL_ULT_M_GT1:
210      case PCI_CHIP_HASWELL_ULT_M_GT2:
211      case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
212      case PCI_CHIP_HASWELL_CRW_M_GT1:
213      case PCI_CHIP_HASWELL_CRW_M_GT2:
214      case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
215	 chipset = "Intel(R) Haswell Mobile";
216	 break;
217      case PCI_CHIP_HASWELL_S_GT1:
218      case PCI_CHIP_HASWELL_S_GT2:
219      case PCI_CHIP_HASWELL_S_GT2_PLUS:
220      case PCI_CHIP_HASWELL_SDV_S_GT1:
221      case PCI_CHIP_HASWELL_SDV_S_GT2:
222      case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
223      case PCI_CHIP_HASWELL_ULT_S_GT1:
224      case PCI_CHIP_HASWELL_ULT_S_GT2:
225      case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
226      case PCI_CHIP_HASWELL_CRW_S_GT1:
227      case PCI_CHIP_HASWELL_CRW_S_GT2:
228      case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
229	 chipset = "Intel(R) Haswell Server";
230	 break;
231      default:
232         chipset = "Unknown Intel Chipset";
233         break;
234      }
235
236      (void) driGetRendererString(buffer, chipset, 0);
237      return (GLubyte *) buffer;
238
239   default:
240      return NULL;
241   }
242}
243
244void
245intel_downsample_for_dri2_flush(struct intel_context *intel,
246                                __DRIdrawable *drawable)
247{
248   if (intel->gen < 6) {
249      /* MSAA is not supported, so don't waste time checking for
250       * a multisample buffer.
251       */
252      return;
253   }
254
255   struct gl_framebuffer *fb = drawable->driverPrivate;
256   struct intel_renderbuffer *rb;
257
258   /* Usually, only the back buffer will need to be downsampled. However,
259    * the front buffer will also need it if the user has rendered into it.
260    */
261   static const gl_buffer_index buffers[2] = {
262         BUFFER_BACK_LEFT,
263         BUFFER_FRONT_LEFT,
264   };
265
266   for (int i = 0; i < 2; ++i) {
267      rb = intel_get_renderbuffer(fb, buffers[i]);
268      if (rb == NULL || rb->mt == NULL)
269         continue;
270      intel_miptree_downsample(intel, rb->mt);
271   }
272}
273
274static void
275intel_flush_front(struct gl_context *ctx)
276{
277   struct intel_context *intel = intel_context(ctx);
278    __DRIcontext *driContext = intel->driContext;
279    __DRIdrawable *driDrawable = driContext->driDrawablePriv;
280    __DRIscreen *const screen = intel->intelScreen->driScrnPriv;
281
282    if (_mesa_is_winsys_fbo(ctx->DrawBuffer) && intel->front_buffer_dirty) {
283      if (screen->dri2.loader->flushFrontBuffer != NULL &&
284          driDrawable &&
285          driDrawable->loaderPrivate) {
286         screen->dri2.loader->flushFrontBuffer(driDrawable,
287                                               driDrawable->loaderPrivate);
288
289	 /* We set the dirty bit in intel_prepare_render() if we're
290	  * front buffer rendering once we get there.
291	  */
292	 intel->front_buffer_dirty = false;
293      }
294   }
295}
296
297static unsigned
298intel_bits_per_pixel(const struct intel_renderbuffer *rb)
299{
300   return _mesa_get_format_bytes(intel_rb_format(rb)) * 8;
301}
302
303static void
304intel_query_dri2_buffers(struct intel_context *intel,
305			 __DRIdrawable *drawable,
306			 __DRIbuffer **buffers,
307			 int *count);
308
309static void
310intel_process_dri2_buffer(struct intel_context *intel,
311			  __DRIdrawable *drawable,
312			  __DRIbuffer *buffer,
313			  struct intel_renderbuffer *rb,
314			  const char *buffer_name);
315
316void
317intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
318{
319   struct gl_framebuffer *fb = drawable->driverPrivate;
320   struct intel_renderbuffer *rb;
321   struct intel_context *intel = context->driverPrivate;
322   __DRIbuffer *buffers = NULL;
323   int i, count;
324   const char *region_name;
325
326   /* If we're rendering to the fake front buffer, make sure all the
327    * pending drawing has landed on the real front buffer.  Otherwise
328    * when we eventually get to DRI2GetBuffersWithFormat the stale
329    * real front buffer contents will get copied to the new fake front
330    * buffer.
331    */
332   if (intel->is_front_buffer_rendering) {
333      intel_flush(&intel->ctx);
334      intel_flush_front(&intel->ctx);
335   }
336
337   /* Set this up front, so that in case our buffers get invalidated
338    * while we're getting new buffers, we don't clobber the stamp and
339    * thus ignore the invalidate. */
340   drawable->lastStamp = drawable->dri2.stamp;
341
342   if (unlikely(INTEL_DEBUG & DEBUG_DRI))
343      fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
344
345   intel_query_dri2_buffers(intel, drawable, &buffers, &count);
346
347   if (buffers == NULL)
348      return;
349
350   for (i = 0; i < count; i++) {
351       switch (buffers[i].attachment) {
352       case __DRI_BUFFER_FRONT_LEFT:
353	   rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
354	   region_name = "dri2 front buffer";
355	   break;
356
357       case __DRI_BUFFER_FAKE_FRONT_LEFT:
358	   rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
359	   region_name = "dri2 fake front buffer";
360	   break;
361
362       case __DRI_BUFFER_BACK_LEFT:
363	   rb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
364	   region_name = "dri2 back buffer";
365	   break;
366
367       case __DRI_BUFFER_DEPTH:
368       case __DRI_BUFFER_HIZ:
369       case __DRI_BUFFER_DEPTH_STENCIL:
370       case __DRI_BUFFER_STENCIL:
371       case __DRI_BUFFER_ACCUM:
372       default:
373	   fprintf(stderr,
374		   "unhandled buffer attach event, attachment type %d\n",
375		   buffers[i].attachment);
376	   return;
377       }
378
379       intel_process_dri2_buffer(intel, drawable, &buffers[i], rb, region_name);
380   }
381
382   driUpdateFramebufferSize(&intel->ctx, drawable);
383}
384
385/**
386 * intel_prepare_render should be called anywhere that curent read/drawbuffer
387 * state is required.
388 */
389void
390intel_prepare_render(struct intel_context *intel)
391{
392   __DRIcontext *driContext = intel->driContext;
393   __DRIdrawable *drawable;
394
395   drawable = driContext->driDrawablePriv;
396   if (drawable && drawable->dri2.stamp != driContext->dri2.draw_stamp) {
397      if (drawable->lastStamp != drawable->dri2.stamp)
398	 intel_update_renderbuffers(driContext, drawable);
399      intel_draw_buffer(&intel->ctx);
400      driContext->dri2.draw_stamp = drawable->dri2.stamp;
401   }
402
403   drawable = driContext->driReadablePriv;
404   if (drawable && drawable->dri2.stamp != driContext->dri2.read_stamp) {
405      if (drawable->lastStamp != drawable->dri2.stamp)
406	 intel_update_renderbuffers(driContext, drawable);
407      driContext->dri2.read_stamp = drawable->dri2.stamp;
408   }
409
410   /* If we're currently rendering to the front buffer, the rendering
411    * that will happen next will probably dirty the front buffer.  So
412    * mark it as dirty here.
413    */
414   if (intel->is_front_buffer_rendering)
415      intel->front_buffer_dirty = true;
416
417   /* Wait for the swapbuffers before the one we just emitted, so we
418    * don't get too many swaps outstanding for apps that are GPU-heavy
419    * but not CPU-heavy.
420    *
421    * We're using intelDRI2Flush (called from the loader before
422    * swapbuffer) and glFlush (for front buffer rendering) as the
423    * indicator that a frame is done and then throttle when we get
424    * here as we prepare to render the next frame.  At this point for
425    * round trips for swap/copy and getting new buffers are done and
426    * we'll spend less time waiting on the GPU.
427    *
428    * Unfortunately, we don't have a handle to the batch containing
429    * the swap, and getting our hands on that doesn't seem worth it,
430    * so we just us the first batch we emitted after the last swap.
431    */
432   if (intel->need_throttle && intel->first_post_swapbuffers_batch) {
433      drm_intel_bo_wait_rendering(intel->first_post_swapbuffers_batch);
434      drm_intel_bo_unreference(intel->first_post_swapbuffers_batch);
435      intel->first_post_swapbuffers_batch = NULL;
436      intel->need_throttle = false;
437   }
438}
439
440static void
441intel_viewport(struct gl_context *ctx, GLint x, GLint y, GLsizei w, GLsizei h)
442{
443    struct intel_context *intel = intel_context(ctx);
444    __DRIcontext *driContext = intel->driContext;
445
446    if (intel->saved_viewport)
447	intel->saved_viewport(ctx, x, y, w, h);
448
449    if (_mesa_is_winsys_fbo(ctx->DrawBuffer)) {
450       dri2InvalidateDrawable(driContext->driDrawablePriv);
451       dri2InvalidateDrawable(driContext->driReadablePriv);
452    }
453}
454
455static const struct dri_debug_control debug_control[] = {
456   { "tex",   DEBUG_TEXTURE},
457   { "state", DEBUG_STATE},
458   { "ioctl", DEBUG_IOCTL},
459   { "blit",  DEBUG_BLIT},
460   { "mip",   DEBUG_MIPTREE},
461   { "fall",  DEBUG_PERF},
462   { "perf",  DEBUG_PERF},
463   { "verb",  DEBUG_VERBOSE},
464   { "bat",   DEBUG_BATCH},
465   { "pix",   DEBUG_PIXEL},
466   { "buf",   DEBUG_BUFMGR},
467   { "reg",   DEBUG_REGION},
468   { "fbo",   DEBUG_FBO},
469   { "gs",    DEBUG_GS},
470   { "sync",  DEBUG_SYNC},
471   { "prim",  DEBUG_PRIMS },
472   { "vert",  DEBUG_VERTS },
473   { "dri",   DEBUG_DRI },
474   { "sf",    DEBUG_SF },
475   { "san",   DEBUG_SANITY },
476   { "sleep", DEBUG_SLEEP },
477   { "stats", DEBUG_STATS },
478   { "tile",  DEBUG_TILE },
479   { "wm",    DEBUG_WM },
480   { "urb",   DEBUG_URB },
481   { "vs",    DEBUG_VS },
482   { "clip",  DEBUG_CLIP },
483   { "aub",   DEBUG_AUB },
484   { NULL,    0 }
485};
486
487
488static void
489intelInvalidateState(struct gl_context * ctx, GLuint new_state)
490{
491    struct intel_context *intel = intel_context(ctx);
492
493   _swrast_InvalidateState(ctx, new_state);
494   _vbo_InvalidateState(ctx, new_state);
495
496   intel->NewGLState |= new_state;
497
498   if (intel->vtbl.invalidate_state)
499      intel->vtbl.invalidate_state( intel, new_state );
500}
501
502void
503intel_flush_rendering_to_batch(struct gl_context *ctx)
504{
505   struct intel_context *intel = intel_context(ctx);
506
507   if (intel->Fallback)
508      _swrast_flush(ctx);
509
510   if (intel->gen < 4)
511      INTEL_FIREVERTICES(intel);
512}
513
514void
515_intel_flush(struct gl_context *ctx, const char *file, int line)
516{
517   struct intel_context *intel = intel_context(ctx);
518
519   intel_flush_rendering_to_batch(ctx);
520
521   if (intel->batch.used)
522      _intel_batchbuffer_flush(intel, file, line);
523}
524
525static void
526intel_glFlush(struct gl_context *ctx)
527{
528   struct intel_context *intel = intel_context(ctx);
529
530   intel_flush(ctx);
531   intel_flush_front(ctx);
532   if (intel->is_front_buffer_rendering)
533      intel->need_throttle = true;
534}
535
536void
537intelFinish(struct gl_context * ctx)
538{
539   struct intel_context *intel = intel_context(ctx);
540
541   intel_flush(ctx);
542   intel_flush_front(ctx);
543
544   if (intel->batch.last_bo)
545      drm_intel_bo_wait_rendering(intel->batch.last_bo);
546}
547
548void
549intelInitDriverFunctions(struct dd_function_table *functions)
550{
551   _mesa_init_driver_functions(functions);
552
553   functions->Flush = intel_glFlush;
554   functions->Finish = intelFinish;
555   functions->GetString = intelGetString;
556   functions->UpdateState = intelInvalidateState;
557
558   intelInitTextureFuncs(functions);
559   intelInitTextureImageFuncs(functions);
560   intelInitTextureSubImageFuncs(functions);
561   intelInitTextureCopyImageFuncs(functions);
562   intelInitStateFuncs(functions);
563   intelInitClearFuncs(functions);
564   intelInitBufferFuncs(functions);
565   intelInitPixelFuncs(functions);
566   intelInitBufferObjectFuncs(functions);
567   intel_init_syncobj_functions(functions);
568}
569
570bool
571intelInitContext(struct intel_context *intel,
572		 int api,
573                 const struct gl_config * mesaVis,
574                 __DRIcontext * driContextPriv,
575                 void *sharedContextPrivate,
576                 struct dd_function_table *functions)
577{
578   struct gl_context *ctx = &intel->ctx;
579   struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
580   __DRIscreen *sPriv = driContextPriv->driScreenPriv;
581   struct intel_screen *intelScreen = sPriv->driverPrivate;
582   int bo_reuse_mode;
583   struct gl_config visual;
584
585   /* we can't do anything without a connection to the device */
586   if (intelScreen->bufmgr == NULL)
587      return false;
588
589   /* Can't rely on invalidate events, fall back to glViewport hack */
590   if (!driContextPriv->driScreenPriv->dri2.useInvalidate) {
591      intel->saved_viewport = functions->Viewport;
592      functions->Viewport = intel_viewport;
593   }
594
595   if (mesaVis == NULL) {
596      memset(&visual, 0, sizeof visual);
597      mesaVis = &visual;
598   }
599
600   if (!_mesa_initialize_context(&intel->ctx, api, mesaVis, shareCtx,
601                                 functions, (void *) intel)) {
602      printf("%s: failed to init mesa context\n", __FUNCTION__);
603      return false;
604   }
605
606   driContextPriv->driverPrivate = intel;
607   intel->intelScreen = intelScreen;
608   intel->driContext = driContextPriv;
609   intel->driFd = sPriv->fd;
610
611   intel->gen = intelScreen->gen;
612
613   const int devID = intelScreen->deviceID;
614   if (IS_SNB_GT1(devID) || IS_IVB_GT1(devID) || IS_HSW_GT1(devID))
615      intel->gt = 1;
616   else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID))
617      intel->gt = 2;
618   else
619      intel->gt = 0;
620
621   if (IS_HASWELL(devID)) {
622      intel->is_haswell = true;
623   } else if (IS_G4X(devID)) {
624      intel->is_g4x = true;
625   } else if (IS_945(devID)) {
626      intel->is_945 = true;
627   }
628
629   if (intel->gen >= 5) {
630      intel->needs_ff_sync = true;
631   }
632
633   intel->has_separate_stencil = intel->intelScreen->hw_has_separate_stencil;
634   intel->must_use_separate_stencil = intel->intelScreen->hw_must_use_separate_stencil;
635   intel->has_hiz = intel->gen >= 6 && !intel->is_haswell;
636   intel->has_llc = intel->intelScreen->hw_has_llc;
637   intel->has_swizzling = intel->intelScreen->hw_has_swizzling;
638
639   memset(&ctx->TextureFormatSupported,
640	  0, sizeof(ctx->TextureFormatSupported));
641
642   driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache,
643                       sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915");
644   if (intel->gen < 4)
645      intel->maxBatchSize = 4096;
646   else
647      intel->maxBatchSize = sizeof(intel->batch.map);
648
649   intel->bufmgr = intelScreen->bufmgr;
650
651   bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse");
652   switch (bo_reuse_mode) {
653   case DRI_CONF_BO_REUSE_DISABLED:
654      break;
655   case DRI_CONF_BO_REUSE_ALL:
656      intel_bufmgr_gem_enable_reuse(intel->bufmgr);
657      break;
658   }
659
660   ctx->Const.MinLineWidth = 1.0;
661   ctx->Const.MinLineWidthAA = 1.0;
662   ctx->Const.MaxLineWidth = 5.0;
663   ctx->Const.MaxLineWidthAA = 5.0;
664   ctx->Const.LineWidthGranularity = 0.5;
665
666   ctx->Const.MinPointSize = 1.0;
667   ctx->Const.MinPointSizeAA = 1.0;
668   ctx->Const.MaxPointSize = 255.0;
669   ctx->Const.MaxPointSizeAA = 3.0;
670   ctx->Const.PointSizeGranularity = 1.0;
671
672   ctx->Const.MaxSamples = 1.0;
673
674   if (intel->gen >= 6)
675      ctx->Const.MaxClipPlanes = 8;
676
677   ctx->Const.StripTextureBorder = GL_TRUE;
678
679   /* reinitialize the context point state.
680    * It depend on constants in __struct gl_contextRec::Const
681    */
682   _mesa_init_point(ctx);
683
684   if (intel->gen >= 4) {
685      ctx->Const.MaxRenderbufferSize = 8192;
686   } else {
687      ctx->Const.MaxRenderbufferSize = 2048;
688   }
689
690   /* Initialize the software rasterizer and helper modules. */
691   _swrast_CreateContext(ctx);
692   _vbo_CreateContext(ctx);
693   _tnl_CreateContext(ctx);
694   _swsetup_CreateContext(ctx);
695
696   /* Configure swrast to match hardware characteristics: */
697   _swrast_allow_pixel_fog(ctx, false);
698   _swrast_allow_vertex_fog(ctx, true);
699
700   _mesa_meta_init(ctx);
701
702   intel->hw_stencil = mesaVis->stencilBits && mesaVis->depthBits == 24;
703   intel->hw_stipple = 1;
704
705   /* XXX FBO: this doesn't seem to be used anywhere */
706   switch (mesaVis->depthBits) {
707   case 0:                     /* what to do in this case? */
708   case 16:
709      intel->polygon_offset_scale = 1.0;
710      break;
711   case 24:
712      intel->polygon_offset_scale = 2.0;     /* req'd to pass glean */
713      break;
714   default:
715      assert(0);
716      break;
717   }
718
719   if (intel->gen >= 4)
720      intel->polygon_offset_scale /= 0xffff;
721
722   intel->RenderIndex = ~0;
723
724   intelInitExtensions(ctx);
725
726   INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control);
727   if (INTEL_DEBUG & DEBUG_BUFMGR)
728      dri_bufmgr_set_debug(intel->bufmgr, true);
729
730   if (INTEL_DEBUG & DEBUG_AUB)
731      drm_intel_bufmgr_gem_set_aub_dump(intel->bufmgr, true);
732
733   intel_batchbuffer_init(intel);
734
735   intel_fbo_init(intel);
736
737   intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
738					       "texture_tiling");
739   intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
740
741   if (!driQueryOptionb(&intel->optionCache, "hiz")) {
742       intel->has_hiz = false;
743       /* On gen6, you can only do separate stencil with HIZ. */
744       if (intel->gen == 6)
745	  intel->has_separate_stencil = false;
746   }
747
748   intel->prim.primitive = ~0;
749
750   /* Force all software fallbacks */
751   if (driQueryOptionb(&intel->optionCache, "no_rast")) {
752      fprintf(stderr, "disabling 3D rasterization\n");
753      intel->no_rast = 1;
754   }
755
756   if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) {
757      fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
758      intel->always_flush_batch = 1;
759   }
760
761   if (driQueryOptionb(&intel->optionCache, "always_flush_cache")) {
762      fprintf(stderr, "flushing GPU caches before/after each draw call\n");
763      intel->always_flush_cache = 1;
764   }
765
766   return true;
767}
768
769void
770intelDestroyContext(__DRIcontext * driContextPriv)
771{
772   struct intel_context *intel =
773      (struct intel_context *) driContextPriv->driverPrivate;
774
775   assert(intel);               /* should never be null */
776   if (intel) {
777      INTEL_FIREVERTICES(intel);
778
779      /* Dump a final BMP in case the application doesn't call SwapBuffers */
780      if (INTEL_DEBUG & DEBUG_AUB) {
781         intel_batchbuffer_flush(intel);
782	 aub_dump_bmp(&intel->ctx);
783      }
784
785      _mesa_meta_free(&intel->ctx);
786
787      intel->vtbl.destroy(intel);
788
789      _swsetup_DestroyContext(&intel->ctx);
790      _tnl_DestroyContext(&intel->ctx);
791      _vbo_DestroyContext(&intel->ctx);
792
793      _swrast_DestroyContext(&intel->ctx);
794      intel->Fallback = 0x0;      /* don't call _swrast_Flush later */
795
796      intel_batchbuffer_free(intel);
797
798      free(intel->prim.vb);
799      intel->prim.vb = NULL;
800      drm_intel_bo_unreference(intel->prim.vb_bo);
801      intel->prim.vb_bo = NULL;
802      drm_intel_bo_unreference(intel->first_post_swapbuffers_batch);
803      intel->first_post_swapbuffers_batch = NULL;
804
805      driDestroyOptionCache(&intel->optionCache);
806
807      /* free the Mesa context */
808      _mesa_free_context_data(&intel->ctx);
809
810      _math_matrix_dtr(&intel->ViewportMatrix);
811
812      ralloc_free(intel);
813      driContextPriv->driverPrivate = NULL;
814   }
815}
816
817GLboolean
818intelUnbindContext(__DRIcontext * driContextPriv)
819{
820   /* Unset current context and dispath table */
821   _mesa_make_current(NULL, NULL, NULL);
822
823   return true;
824}
825
826GLboolean
827intelMakeCurrent(__DRIcontext * driContextPriv,
828                 __DRIdrawable * driDrawPriv,
829                 __DRIdrawable * driReadPriv)
830{
831   struct intel_context *intel;
832   GET_CURRENT_CONTEXT(curCtx);
833
834   if (driContextPriv)
835      intel = (struct intel_context *) driContextPriv->driverPrivate;
836   else
837      intel = NULL;
838
839   /* According to the glXMakeCurrent() man page: "Pending commands to
840    * the previous context, if any, are flushed before it is released."
841    * But only flush if we're actually changing contexts.
842    */
843   if (intel_context(curCtx) && intel_context(curCtx) != intel) {
844      _mesa_flush(curCtx);
845   }
846
847   if (driContextPriv) {
848      struct gl_framebuffer *fb, *readFb;
849
850      if (driDrawPriv == NULL && driReadPriv == NULL) {
851	 fb = _mesa_get_incomplete_framebuffer();
852	 readFb = _mesa_get_incomplete_framebuffer();
853      } else {
854	 fb = driDrawPriv->driverPrivate;
855	 readFb = driReadPriv->driverPrivate;
856	 driContextPriv->dri2.draw_stamp = driDrawPriv->dri2.stamp - 1;
857	 driContextPriv->dri2.read_stamp = driReadPriv->dri2.stamp - 1;
858      }
859
860      intel_prepare_render(intel);
861      _mesa_make_current(&intel->ctx, fb, readFb);
862
863      /* We do this in intel_prepare_render() too, but intel->ctx.DrawBuffer
864       * is NULL at that point.  We can't call _mesa_makecurrent()
865       * first, since we need the buffer size for the initial
866       * viewport.  So just call intel_draw_buffer() again here. */
867      intel_draw_buffer(&intel->ctx);
868   }
869   else {
870      _mesa_make_current(NULL, NULL, NULL);
871   }
872
873   return true;
874}
875
876/**
877 * \brief Query DRI2 to obtain a DRIdrawable's buffers.
878 *
879 * To determine which DRI buffers to request, examine the renderbuffers
880 * attached to the drawable's framebuffer. Then request the buffers with
881 * DRI2GetBuffers() or DRI2GetBuffersWithFormat().
882 *
883 * This is called from intel_update_renderbuffers().
884 *
885 * \param drawable      Drawable whose buffers are queried.
886 * \param buffers       [out] List of buffers returned by DRI2 query.
887 * \param buffer_count  [out] Number of buffers returned.
888 *
889 * \see intel_update_renderbuffers()
890 * \see DRI2GetBuffers()
891 * \see DRI2GetBuffersWithFormat()
892 */
893static void
894intel_query_dri2_buffers(struct intel_context *intel,
895			 __DRIdrawable *drawable,
896			 __DRIbuffer **buffers,
897			 int *buffer_count)
898{
899   __DRIscreen *screen = intel->intelScreen->driScrnPriv;
900   struct gl_framebuffer *fb = drawable->driverPrivate;
901   int i = 0;
902   const int max_attachments = 4;
903   unsigned *attachments = calloc(2 * max_attachments, sizeof(unsigned));
904
905   struct intel_renderbuffer *front_rb;
906   struct intel_renderbuffer *back_rb;
907
908   front_rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
909   back_rb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
910
911   if ((intel->is_front_buffer_rendering ||
912	intel->is_front_buffer_reading ||
913	!back_rb) && front_rb) {
914      attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
915      attachments[i++] = intel_bits_per_pixel(front_rb);
916   }
917
918   if (back_rb) {
919      attachments[i++] = __DRI_BUFFER_BACK_LEFT;
920      attachments[i++] = intel_bits_per_pixel(back_rb);
921   }
922
923   assert(i <= 2 * max_attachments);
924
925   *buffers = screen->dri2.loader->getBuffersWithFormat(drawable,
926							&drawable->w,
927							&drawable->h,
928							attachments, i / 2,
929							buffer_count,
930							drawable->loaderPrivate);
931   free(attachments);
932}
933
934/**
935 * \brief Assign a DRI buffer's DRM region to a renderbuffer.
936 *
937 * This is called from intel_update_renderbuffers().
938 *
939 * \par Note:
940 *    DRI buffers whose attachment point is DRI2BufferStencil or
941 *    DRI2BufferDepthStencil are handled as special cases.
942 *
943 * \param buffer_name is a human readable name, such as "dri2 front buffer",
944 *        that is passed to intel_region_alloc_for_handle().
945 *
946 * \see intel_update_renderbuffers()
947 * \see intel_region_alloc_for_handle()
948 */
949static void
950intel_process_dri2_buffer(struct intel_context *intel,
951			  __DRIdrawable *drawable,
952			  __DRIbuffer *buffer,
953			  struct intel_renderbuffer *rb,
954			  const char *buffer_name)
955{
956   struct intel_region *region = NULL;
957
958   if (!rb)
959      return;
960
961   unsigned num_samples = rb->Base.Base.NumSamples;
962
963   /* We try to avoid closing and reopening the same BO name, because the first
964    * use of a mapping of the buffer involves a bunch of page faulting which is
965    * moderately expensive.
966    */
967   if (num_samples == 0) {
968       if (rb->mt &&
969           rb->mt->region &&
970           rb->mt->region->name == buffer->name)
971          return;
972   } else {
973       if (rb->mt &&
974           rb->mt->singlesample_mt &&
975           rb->mt->singlesample_mt->region &&
976           rb->mt->singlesample_mt->region->name == buffer->name)
977          return;
978   }
979
980   if (unlikely(INTEL_DEBUG & DEBUG_DRI)) {
981      fprintf(stderr,
982	      "attaching buffer %d, at %d, cpp %d, pitch %d\n",
983	      buffer->name, buffer->attachment,
984	      buffer->cpp, buffer->pitch);
985   }
986
987   intel_miptree_release(&rb->mt);
988   region = intel_region_alloc_for_handle(intel->intelScreen,
989                                          buffer->cpp,
990                                          drawable->w,
991                                          drawable->h,
992                                          buffer->pitch / buffer->cpp,
993                                          buffer->name,
994                                          buffer_name);
995   if (!region)
996      return;
997
998   rb->mt = intel_miptree_create_for_dri2_buffer(intel,
999                                                 buffer->attachment,
1000                                                 intel_rb_format(rb),
1001                                                 num_samples,
1002                                                 region);
1003   intel_region_release(&region);
1004}
1005