intel_mipmap_tree.c revision d3746354fbfadf821dc108e072d86b5329737444
1/************************************************************************** 2 * 3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#include <GL/gl.h> 29#include <GL/internal/dri_interface.h> 30 31#include "intel_batchbuffer.h" 32#include "intel_context.h" 33#include "intel_mipmap_tree.h" 34#include "intel_regions.h" 35#include "intel_resolve_map.h" 36#include "intel_span.h" 37#include "intel_tex_layout.h" 38#include "intel_tex.h" 39#include "intel_blit.h" 40 41#ifndef I915 42#include "brw_blorp.h" 43#endif 44 45#include "main/enums.h" 46#include "main/formats.h" 47#include "main/glformats.h" 48#include "main/texcompress_etc.h" 49#include "main/teximage.h" 50 51#define FILE_DEBUG_FLAG DEBUG_MIPTREE 52 53static GLenum 54target_to_target(GLenum target) 55{ 56 switch (target) { 57 case GL_TEXTURE_CUBE_MAP_POSITIVE_X_ARB: 58 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X_ARB: 59 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y_ARB: 60 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y_ARB: 61 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z_ARB: 62 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z_ARB: 63 return GL_TEXTURE_CUBE_MAP_ARB; 64 default: 65 return target; 66 } 67} 68 69/** 70 * @param for_region Indicates that the caller is 71 * intel_miptree_create_for_region(). If true, then do not create 72 * \c stencil_mt. 73 */ 74static struct intel_mipmap_tree * 75intel_miptree_create_internal(struct intel_context *intel, 76 GLenum target, 77 gl_format format, 78 GLuint first_level, 79 GLuint last_level, 80 GLuint width0, 81 GLuint height0, 82 GLuint depth0, 83 bool for_region, 84 GLuint num_samples, 85 enum intel_msaa_layout msaa_layout) 86{ 87 struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1); 88 int compress_byte = 0; 89 90 DBG("%s target %s format %s level %d..%d <-- %p\n", __FUNCTION__, 91 _mesa_lookup_enum_by_nr(target), 92 _mesa_get_format_name(format), 93 first_level, last_level, mt); 94 95 if (_mesa_is_format_compressed(format)) 96 compress_byte = intel_compressed_num_bytes(format); 97 98 mt->target = target_to_target(target); 99 mt->format = format; 100 mt->first_level = first_level; 101 mt->last_level = last_level; 102 mt->width0 = width0; 103 mt->height0 = height0; 104 mt->cpp = compress_byte ? compress_byte : _mesa_get_format_bytes(mt->format); 105 mt->num_samples = num_samples; 106 mt->compressed = compress_byte ? 1 : 0; 107 mt->msaa_layout = msaa_layout; 108 mt->refcount = 1; 109 110 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we 111 * use it elsewhere? 112 */ 113 switch (msaa_layout) { 114 case INTEL_MSAA_LAYOUT_NONE: 115 case INTEL_MSAA_LAYOUT_IMS: 116 mt->array_spacing_lod0 = false; 117 break; 118 case INTEL_MSAA_LAYOUT_UMS: 119 case INTEL_MSAA_LAYOUT_CMS: 120 mt->array_spacing_lod0 = true; 121 break; 122 } 123 124 if (target == GL_TEXTURE_CUBE_MAP) { 125 assert(depth0 == 1); 126 mt->depth0 = 6; 127 } else { 128 mt->depth0 = depth0; 129 } 130 131 if (!for_region && 132 _mesa_is_depthstencil_format(_mesa_get_format_base_format(format)) && 133 (intel->must_use_separate_stencil || 134 (intel->has_separate_stencil && 135 intel->vtbl.is_hiz_depth_format(intel, format)))) { 136 /* MSAA stencil surfaces always use IMS layout. */ 137 enum intel_msaa_layout msaa_layout = 138 num_samples > 1 ? INTEL_MSAA_LAYOUT_IMS : INTEL_MSAA_LAYOUT_NONE; 139 mt->stencil_mt = intel_miptree_create(intel, 140 mt->target, 141 MESA_FORMAT_S8, 142 mt->first_level, 143 mt->last_level, 144 mt->width0, 145 mt->height0, 146 mt->depth0, 147 true, 148 num_samples, 149 msaa_layout); 150 if (!mt->stencil_mt) { 151 intel_miptree_release(&mt); 152 return NULL; 153 } 154 155 /* Fix up the Z miptree format for how we're splitting out separate 156 * stencil. Gen7 expects there to be no stencil bits in its depth buffer. 157 */ 158 if (mt->format == MESA_FORMAT_S8_Z24) { 159 mt->format = MESA_FORMAT_X8_Z24; 160 } else if (mt->format == MESA_FORMAT_Z32_FLOAT_X24S8) { 161 mt->format = MESA_FORMAT_Z32_FLOAT; 162 mt->cpp = 4; 163 } else { 164 _mesa_problem(NULL, "Unknown format %s in separate stencil mt\n", 165 _mesa_get_format_name(mt->format)); 166 } 167 } 168 169 intel_get_texture_alignment_unit(intel, mt->format, 170 &mt->align_w, &mt->align_h); 171 172#ifdef I915 173 (void) intel; 174 if (intel->is_945) 175 i945_miptree_layout(mt); 176 else 177 i915_miptree_layout(mt); 178#else 179 brw_miptree_layout(intel, mt); 180#endif 181 182 return mt; 183} 184 185 186struct intel_mipmap_tree * 187intel_miptree_create(struct intel_context *intel, 188 GLenum target, 189 gl_format format, 190 GLuint first_level, 191 GLuint last_level, 192 GLuint width0, 193 GLuint height0, 194 GLuint depth0, 195 bool expect_accelerated_upload, 196 GLuint num_samples, 197 enum intel_msaa_layout msaa_layout) 198{ 199 struct intel_mipmap_tree *mt; 200 uint32_t tiling = I915_TILING_NONE; 201 GLenum base_format; 202 bool wraps_etc1 = false; 203 204 if (format == MESA_FORMAT_ETC1_RGB8) { 205 format = MESA_FORMAT_RGBX8888_REV; 206 wraps_etc1 = true; 207 } 208 209 base_format = _mesa_get_format_base_format(format); 210 211 if (intel->use_texture_tiling && !_mesa_is_format_compressed(format)) { 212 if (intel->gen >= 4 && 213 (base_format == GL_DEPTH_COMPONENT || 214 base_format == GL_DEPTH_STENCIL_EXT)) 215 tiling = I915_TILING_Y; 216 else if (msaa_layout != INTEL_MSAA_LAYOUT_NONE) { 217 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled 218 * Surface"): 219 * 220 * [DevSNB+]: For multi-sample render targets, this field must be 221 * 1. MSRTs can only be tiled. 222 * 223 * Our usual reason for preferring X tiling (fast blits using the 224 * blitting engine) doesn't apply to MSAA, since we'll generally be 225 * downsampling or upsampling when blitting between the MSAA buffer 226 * and another buffer, and the blitting engine doesn't support that. 227 * So use Y tiling, since it makes better use of the cache. 228 */ 229 tiling = I915_TILING_Y; 230 } else if (width0 >= 64) 231 tiling = I915_TILING_X; 232 } 233 234 if (format == MESA_FORMAT_S8) { 235 /* The stencil buffer is W tiled. However, we request from the kernel a 236 * non-tiled buffer because the GTT is incapable of W fencing. So round 237 * up the width and height to match the size of W tiles (64x64). 238 */ 239 tiling = I915_TILING_NONE; 240 width0 = ALIGN(width0, 64); 241 height0 = ALIGN(height0, 64); 242 } 243 244 mt = intel_miptree_create_internal(intel, target, format, 245 first_level, last_level, width0, 246 height0, depth0, 247 false, num_samples, msaa_layout); 248 /* 249 * pitch == 0 || height == 0 indicates the null texture 250 */ 251 if (!mt || !mt->total_width || !mt->total_height) { 252 intel_miptree_release(&mt); 253 return NULL; 254 } 255 256 mt->wraps_etc1 = wraps_etc1; 257 mt->region = intel_region_alloc(intel->intelScreen, 258 tiling, 259 mt->cpp, 260 mt->total_width, 261 mt->total_height, 262 expect_accelerated_upload); 263 mt->offset = 0; 264 265 if (!mt->region) { 266 intel_miptree_release(&mt); 267 return NULL; 268 } 269 270 return mt; 271} 272 273 274struct intel_mipmap_tree * 275intel_miptree_create_for_region(struct intel_context *intel, 276 GLenum target, 277 gl_format format, 278 struct intel_region *region) 279{ 280 struct intel_mipmap_tree *mt; 281 282 mt = intel_miptree_create_internal(intel, target, format, 283 0, 0, 284 region->width, region->height, 1, 285 true, 0 /* num_samples */, 286 INTEL_MSAA_LAYOUT_NONE); 287 if (!mt) 288 return mt; 289 290 intel_region_reference(&mt->region, region); 291 292 return mt; 293} 294 295/** 296 * Determine which MSAA layout should be used by the MSAA surface being 297 * created, based on the chip generation and the surface type. 298 */ 299static enum intel_msaa_layout 300compute_msaa_layout(struct intel_context *intel, gl_format format) 301{ 302 /* Prior to Gen7, all MSAA surfaces used IMS layout. */ 303 if (intel->gen < 7) 304 return INTEL_MSAA_LAYOUT_IMS; 305 306 /* In Gen7, IMS layout is only used for depth and stencil buffers. */ 307 switch (_mesa_get_format_base_format(format)) { 308 case GL_DEPTH_COMPONENT: 309 case GL_STENCIL_INDEX: 310 case GL_DEPTH_STENCIL: 311 return INTEL_MSAA_LAYOUT_IMS; 312 default: 313 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"): 314 * 315 * This field must be set to 0 for all SINT MSRTs when all RT channels 316 * are not written 317 * 318 * In practice this means that we have to disable MCS for all signed 319 * integer MSAA buffers. The alternative, to disable MCS only when one 320 * of the render target channels is disabled, is impractical because it 321 * would require converting between CMS and UMS MSAA layouts on the fly, 322 * which is expensive. 323 */ 324 if (_mesa_get_format_datatype(format) == GL_INT) { 325 /* TODO: is this workaround needed for future chipsets? */ 326 assert(intel->gen == 7); 327 return INTEL_MSAA_LAYOUT_UMS; 328 } else { 329 return INTEL_MSAA_LAYOUT_CMS; 330 } 331 } 332} 333 334/** 335 * For a singlesample DRI2 buffer, this simply wraps the given region with a miptree. 336 * 337 * For a multisample DRI2 buffer, this wraps the given region with 338 * a singlesample miptree, then creates a multisample miptree into which the 339 * singlesample miptree is embedded as a child. 340 */ 341struct intel_mipmap_tree* 342intel_miptree_create_for_dri2_buffer(struct intel_context *intel, 343 unsigned dri_attachment, 344 gl_format format, 345 uint32_t num_samples, 346 struct intel_region *region) 347{ 348 struct intel_mipmap_tree *singlesample_mt = NULL; 349 struct intel_mipmap_tree *multisample_mt = NULL; 350 GLenum base_format = _mesa_get_format_base_format(format); 351 352 /* Only the front and back buffers, which are color buffers, are shared 353 * through DRI2. 354 */ 355 assert(dri_attachment == __DRI_BUFFER_BACK_LEFT || 356 dri_attachment == __DRI_BUFFER_FRONT_LEFT || 357 dri_attachment == __DRI_BUFFER_FAKE_FRONT_LEFT); 358 assert(base_format == GL_RGB || base_format == GL_RGBA); 359 360 singlesample_mt = intel_miptree_create_for_region(intel, GL_TEXTURE_2D, 361 format, region); 362 if (!singlesample_mt) 363 return NULL; 364 365 if (num_samples == 0) 366 return singlesample_mt; 367 368 multisample_mt = intel_miptree_create_for_renderbuffer(intel, 369 format, 370 region->width, 371 region->height, 372 num_samples); 373 if (!multisample_mt) { 374 intel_miptree_release(&singlesample_mt); 375 return NULL; 376 } 377 378 multisample_mt->singlesample_mt = singlesample_mt; 379 multisample_mt->need_downsample = false; 380 381 if (intel->is_front_buffer_rendering && 382 (dri_attachment == __DRI_BUFFER_FRONT_LEFT || 383 dri_attachment == __DRI_BUFFER_FAKE_FRONT_LEFT)) { 384 intel_miptree_upsample(intel, multisample_mt); 385 } 386 387 return multisample_mt; 388} 389 390struct intel_mipmap_tree* 391intel_miptree_create_for_renderbuffer(struct intel_context *intel, 392 gl_format format, 393 uint32_t width, 394 uint32_t height, 395 uint32_t num_samples) 396{ 397 struct intel_mipmap_tree *mt; 398 uint32_t depth = 1; 399 enum intel_msaa_layout msaa_layout = INTEL_MSAA_LAYOUT_NONE; 400 bool ok; 401 402 if (num_samples > 1) { 403 /* Adjust width/height/depth for MSAA */ 404 msaa_layout = compute_msaa_layout(intel, format); 405 if (msaa_layout == INTEL_MSAA_LAYOUT_IMS) { 406 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says: 407 * 408 * "Any of the other messages (sample*, LOD, load4) used with a 409 * (4x) multisampled surface will in-effect sample a surface with 410 * double the height and width as that indicated in the surface 411 * state. Each pixel position on the original-sized surface is 412 * replaced with a 2x2 of samples with the following arrangement: 413 * 414 * sample 0 sample 2 415 * sample 1 sample 3" 416 * 417 * Thus, when sampling from a multisampled texture, it behaves as 418 * though the layout in memory for (x,y,sample) is: 419 * 420 * (0,0,0) (0,0,2) (1,0,0) (1,0,2) 421 * (0,0,1) (0,0,3) (1,0,1) (1,0,3) 422 * 423 * (0,1,0) (0,1,2) (1,1,0) (1,1,2) 424 * (0,1,1) (0,1,3) (1,1,1) (1,1,3) 425 * 426 * However, the actual layout of multisampled data in memory is: 427 * 428 * (0,0,0) (1,0,0) (0,0,1) (1,0,1) 429 * (0,1,0) (1,1,0) (0,1,1) (1,1,1) 430 * 431 * (0,0,2) (1,0,2) (0,0,3) (1,0,3) 432 * (0,1,2) (1,1,2) (0,1,3) (1,1,3) 433 * 434 * This pattern repeats for each 2x2 pixel block. 435 * 436 * As a result, when calculating the size of our 4-sample buffer for 437 * an odd width or height, we have to align before scaling up because 438 * sample 3 is in that bottom right 2x2 block. 439 */ 440 switch (num_samples) { 441 case 4: 442 width = ALIGN(width, 2) * 2; 443 height = ALIGN(height, 2) * 2; 444 break; 445 case 8: 446 width = ALIGN(width, 2) * 4; 447 height = ALIGN(height, 2) * 2; 448 break; 449 default: 450 /* num_samples should already have been quantized to 0, 1, 4, or 451 * 8. 452 */ 453 assert(false); 454 } 455 } else { 456 /* Non-interleaved */ 457 depth = num_samples; 458 } 459 } 460 461 mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0, 462 width, height, depth, true, num_samples, 463 msaa_layout); 464 if (!mt) 465 goto fail; 466 467 if (intel->vtbl.is_hiz_depth_format(intel, format)) { 468 ok = intel_miptree_alloc_hiz(intel, mt, num_samples); 469 if (!ok) 470 goto fail; 471 } 472 473 if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { 474 ok = intel_miptree_alloc_mcs(intel, mt, num_samples); 475 if (!ok) 476 goto fail; 477 } 478 479 return mt; 480 481fail: 482 intel_miptree_release(&mt); 483 return NULL; 484} 485 486void 487intel_miptree_reference(struct intel_mipmap_tree **dst, 488 struct intel_mipmap_tree *src) 489{ 490 if (*dst == src) 491 return; 492 493 intel_miptree_release(dst); 494 495 if (src) { 496 src->refcount++; 497 DBG("%s %p refcount now %d\n", __FUNCTION__, src, src->refcount); 498 } 499 500 *dst = src; 501} 502 503 504void 505intel_miptree_release(struct intel_mipmap_tree **mt) 506{ 507 if (!*mt) 508 return; 509 510 DBG("%s %p refcount will be %d\n", __FUNCTION__, *mt, (*mt)->refcount - 1); 511 if (--(*mt)->refcount <= 0) { 512 GLuint i; 513 514 DBG("%s deleting %p\n", __FUNCTION__, *mt); 515 516 intel_region_release(&((*mt)->region)); 517 intel_miptree_release(&(*mt)->stencil_mt); 518 intel_miptree_release(&(*mt)->hiz_mt); 519 intel_miptree_release(&(*mt)->mcs_mt); 520 intel_miptree_release(&(*mt)->singlesample_mt); 521 intel_resolve_map_clear(&(*mt)->hiz_map); 522 523 for (i = 0; i < MAX_TEXTURE_LEVELS; i++) { 524 free((*mt)->level[i].slice); 525 } 526 527 free(*mt); 528 } 529 *mt = NULL; 530} 531 532void 533intel_miptree_get_dimensions_for_image(struct gl_texture_image *image, 534 int *width, int *height, int *depth) 535{ 536 switch (image->TexObject->Target) { 537 case GL_TEXTURE_1D_ARRAY: 538 *width = image->Width; 539 *height = 1; 540 *depth = image->Height; 541 break; 542 default: 543 *width = image->Width; 544 *height = image->Height; 545 *depth = image->Depth; 546 break; 547 } 548} 549 550/** 551 * Can the image be pulled into a unified mipmap tree? This mirrors 552 * the completeness test in a lot of ways. 553 * 554 * Not sure whether I want to pass gl_texture_image here. 555 */ 556bool 557intel_miptree_match_image(struct intel_mipmap_tree *mt, 558 struct gl_texture_image *image) 559{ 560 struct intel_texture_image *intelImage = intel_texture_image(image); 561 GLuint level = intelImage->base.Base.Level; 562 int width, height, depth; 563 564 if (target_to_target(image->TexObject->Target) != mt->target) 565 return false; 566 567 if (image->TexFormat != mt->format && 568 !(image->TexFormat == MESA_FORMAT_S8_Z24 && 569 mt->format == MESA_FORMAT_X8_Z24 && 570 mt->stencil_mt)) { 571 return false; 572 } 573 574 intel_miptree_get_dimensions_for_image(image, &width, &height, &depth); 575 576 if (mt->target == GL_TEXTURE_CUBE_MAP) 577 depth = 6; 578 579 /* Test image dimensions against the base level image adjusted for 580 * minification. This will also catch images not present in the 581 * tree, changed targets, etc. 582 */ 583 if (width != mt->level[level].width || 584 height != mt->level[level].height || 585 depth != mt->level[level].depth) 586 return false; 587 588 return true; 589} 590 591 592void 593intel_miptree_set_level_info(struct intel_mipmap_tree *mt, 594 GLuint level, 595 GLuint x, GLuint y, 596 GLuint w, GLuint h, GLuint d) 597{ 598 mt->level[level].width = w; 599 mt->level[level].height = h; 600 mt->level[level].depth = d; 601 mt->level[level].level_x = x; 602 mt->level[level].level_y = y; 603 604 DBG("%s level %d size: %d,%d,%d offset %d,%d\n", __FUNCTION__, 605 level, w, h, d, x, y); 606 607 assert(mt->level[level].slice == NULL); 608 609 mt->level[level].slice = calloc(d, sizeof(*mt->level[0].slice)); 610 mt->level[level].slice[0].x_offset = mt->level[level].level_x; 611 mt->level[level].slice[0].y_offset = mt->level[level].level_y; 612} 613 614 615void 616intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, 617 GLuint level, GLuint img, 618 GLuint x, GLuint y) 619{ 620 if (img == 0 && level == 0) 621 assert(x == 0 && y == 0); 622 623 assert(img < mt->level[level].depth); 624 625 mt->level[level].slice[img].x_offset = mt->level[level].level_x + x; 626 mt->level[level].slice[img].y_offset = mt->level[level].level_y + y; 627 628 DBG("%s level %d img %d pos %d,%d\n", 629 __FUNCTION__, level, img, 630 mt->level[level].slice[img].x_offset, 631 mt->level[level].slice[img].y_offset); 632} 633 634 635/** 636 * For cube map textures, either the \c face parameter can be used, of course, 637 * or the cube face can be interpreted as a depth layer and the \c layer 638 * parameter used. 639 */ 640void 641intel_miptree_get_image_offset(struct intel_mipmap_tree *mt, 642 GLuint level, GLuint face, GLuint layer, 643 GLuint *x, GLuint *y) 644{ 645 int slice; 646 647 if (face > 0) { 648 assert(mt->target == GL_TEXTURE_CUBE_MAP); 649 assert(face < 6); 650 assert(layer == 0); 651 slice = face; 652 } else { 653 /* This branch may be taken even if the texture target is a cube map. In 654 * that case, the caller chose to interpret each cube face as a layer. 655 */ 656 assert(face == 0); 657 slice = layer; 658 } 659 660 *x = mt->level[level].slice[slice].x_offset; 661 *y = mt->level[level].slice[slice].y_offset; 662} 663 664static void 665intel_miptree_copy_slice(struct intel_context *intel, 666 struct intel_mipmap_tree *dst_mt, 667 struct intel_mipmap_tree *src_mt, 668 int level, 669 int face, 670 int depth) 671 672{ 673 gl_format format = src_mt->format; 674 uint32_t width = src_mt->level[level].width; 675 uint32_t height = src_mt->level[level].height; 676 677 assert(depth < src_mt->level[level].depth); 678 679 if (dst_mt->compressed) { 680 height = ALIGN(height, dst_mt->align_h) / dst_mt->align_h; 681 width = ALIGN(width, dst_mt->align_w); 682 } 683 684 uint32_t dst_x, dst_y, src_x, src_y; 685 intel_miptree_get_image_offset(dst_mt, level, face, depth, 686 &dst_x, &dst_y); 687 intel_miptree_get_image_offset(src_mt, level, face, depth, 688 &src_x, &src_y); 689 690 DBG("validate blit mt %p %d,%d/%d -> mt %p %d,%d/%d (%dx%d)\n", 691 src_mt, src_x, src_y, src_mt->region->pitch * src_mt->region->cpp, 692 dst_mt, dst_x, dst_y, dst_mt->region->pitch * dst_mt->region->cpp, 693 width, height); 694 695 if (!intelEmitCopyBlit(intel, 696 dst_mt->region->cpp, 697 src_mt->region->pitch, src_mt->region->bo, 698 0, src_mt->region->tiling, 699 dst_mt->region->pitch, dst_mt->region->bo, 700 0, dst_mt->region->tiling, 701 src_x, src_y, 702 dst_x, dst_y, 703 width, height, 704 GL_COPY)) { 705 706 fallback_debug("miptree validate blit for %s failed\n", 707 _mesa_get_format_name(format)); 708 void *dst = intel_region_map(intel, dst_mt->region, GL_MAP_WRITE_BIT); 709 void *src = intel_region_map(intel, src_mt->region, GL_MAP_READ_BIT); 710 711 _mesa_copy_rect(dst, 712 dst_mt->cpp, 713 dst_mt->region->pitch, 714 dst_x, dst_y, 715 width, height, 716 src, src_mt->region->pitch, 717 src_x, src_y); 718 719 intel_region_unmap(intel, dst_mt->region); 720 intel_region_unmap(intel, src_mt->region); 721 } 722 723 if (src_mt->stencil_mt) { 724 intel_miptree_copy_slice(intel, 725 dst_mt->stencil_mt, src_mt->stencil_mt, 726 level, face, depth); 727 } 728} 729 730/** 731 * Copies the image's current data to the given miptree, and associates that 732 * miptree with the image. 733 */ 734void 735intel_miptree_copy_teximage(struct intel_context *intel, 736 struct intel_texture_image *intelImage, 737 struct intel_mipmap_tree *dst_mt) 738{ 739 struct intel_mipmap_tree *src_mt = intelImage->mt; 740 int level = intelImage->base.Base.Level; 741 int face = intelImage->base.Base.Face; 742 GLuint depth = intelImage->base.Base.Depth; 743 744 for (int slice = 0; slice < depth; slice++) { 745 intel_miptree_copy_slice(intel, dst_mt, src_mt, level, face, slice); 746 } 747 748 intel_miptree_reference(&intelImage->mt, dst_mt); 749} 750 751bool 752intel_miptree_alloc_mcs(struct intel_context *intel, 753 struct intel_mipmap_tree *mt, 754 GLuint num_samples) 755{ 756 assert(mt->mcs_mt == NULL); 757 assert(intel->gen >= 7); /* MCS only used on Gen7+ */ 758 759 /* Choose the correct format for the MCS buffer. All that really matters 760 * is that we allocate the right buffer size, since we'll always be 761 * accessing this miptree using MCS-specific hardware mechanisms, which 762 * infer the correct format based on num_samples. 763 */ 764 gl_format format; 765 switch (num_samples) { 766 case 4: 767 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for 768 * each sample). 769 */ 770 format = MESA_FORMAT_R8; 771 break; 772 case 8: 773 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits 774 * for each sample, plus 8 padding bits). 775 */ 776 format = MESA_FORMAT_R_UINT32; 777 break; 778 default: 779 assert(!"Unrecognized sample count in intel_miptree_alloc_mcs"); 780 break; 781 }; 782 783 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address": 784 * 785 * "The MCS surface must be stored as Tile Y." 786 * 787 * We set msaa_format to INTEL_MSAA_LAYOUT_CMS to force 788 * intel_miptree_create() to use Y tiling. msaa_format is otherwise 789 * ignored for the MCS miptree. 790 */ 791 mt->mcs_mt = intel_miptree_create(intel, 792 mt->target, 793 format, 794 mt->first_level, 795 mt->last_level, 796 mt->width0, 797 mt->height0, 798 mt->depth0, 799 true, 800 0 /* num_samples */, 801 INTEL_MSAA_LAYOUT_CMS); 802 803 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326: 804 * 805 * When MCS buffer is enabled and bound to MSRT, it is required that it 806 * is cleared prior to any rendering. 807 * 808 * Since we don't use the MCS buffer for any purpose other than rendering, 809 * it makes sense to just clear it immediately upon allocation. 810 * 811 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff. 812 */ 813 void *data = intel_region_map(intel, mt->mcs_mt->region, 0); 814 memset(data, 0xff, mt->mcs_mt->region->bo->size); 815 intel_region_unmap(intel, mt->mcs_mt->region); 816 817 return mt->mcs_mt; 818} 819 820bool 821intel_miptree_alloc_hiz(struct intel_context *intel, 822 struct intel_mipmap_tree *mt, 823 GLuint num_samples) 824{ 825 assert(mt->hiz_mt == NULL); 826 /* MSAA HiZ surfaces always use IMS layout. */ 827 mt->hiz_mt = intel_miptree_create(intel, 828 mt->target, 829 MESA_FORMAT_X8_Z24, 830 mt->first_level, 831 mt->last_level, 832 mt->width0, 833 mt->height0, 834 mt->depth0, 835 true, 836 num_samples, 837 INTEL_MSAA_LAYOUT_IMS); 838 839 if (!mt->hiz_mt) 840 return false; 841 842 /* Mark that all slices need a HiZ resolve. */ 843 struct intel_resolve_map *head = &mt->hiz_map; 844 for (int level = mt->first_level; level <= mt->last_level; ++level) { 845 for (int layer = 0; layer < mt->level[level].depth; ++layer) { 846 head->next = malloc(sizeof(*head->next)); 847 head->next->prev = head; 848 head->next->next = NULL; 849 head = head->next; 850 851 head->level = level; 852 head->layer = layer; 853 head->need = GEN6_HIZ_OP_HIZ_RESOLVE; 854 } 855 } 856 857 return true; 858} 859 860void 861intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, 862 uint32_t level, 863 uint32_t layer) 864{ 865 intel_miptree_check_level_layer(mt, level, layer); 866 867 if (!mt->hiz_mt) 868 return; 869 870 intel_resolve_map_set(&mt->hiz_map, 871 level, layer, GEN6_HIZ_OP_HIZ_RESOLVE); 872} 873 874 875void 876intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, 877 uint32_t level, 878 uint32_t layer) 879{ 880 intel_miptree_check_level_layer(mt, level, layer); 881 882 if (!mt->hiz_mt) 883 return; 884 885 intel_resolve_map_set(&mt->hiz_map, 886 level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE); 887} 888 889static bool 890intel_miptree_slice_resolve(struct intel_context *intel, 891 struct intel_mipmap_tree *mt, 892 uint32_t level, 893 uint32_t layer, 894 enum gen6_hiz_op need) 895{ 896 intel_miptree_check_level_layer(mt, level, layer); 897 898 struct intel_resolve_map *item = 899 intel_resolve_map_get(&mt->hiz_map, level, layer); 900 901 if (!item || item->need != need) 902 return false; 903 904 intel_hiz_exec(intel, mt, level, layer, need); 905 intel_resolve_map_remove(item); 906 return true; 907} 908 909bool 910intel_miptree_slice_resolve_hiz(struct intel_context *intel, 911 struct intel_mipmap_tree *mt, 912 uint32_t level, 913 uint32_t layer) 914{ 915 return intel_miptree_slice_resolve(intel, mt, level, layer, 916 GEN6_HIZ_OP_HIZ_RESOLVE); 917} 918 919bool 920intel_miptree_slice_resolve_depth(struct intel_context *intel, 921 struct intel_mipmap_tree *mt, 922 uint32_t level, 923 uint32_t layer) 924{ 925 return intel_miptree_slice_resolve(intel, mt, level, layer, 926 GEN6_HIZ_OP_DEPTH_RESOLVE); 927} 928 929static bool 930intel_miptree_all_slices_resolve(struct intel_context *intel, 931 struct intel_mipmap_tree *mt, 932 enum gen6_hiz_op need) 933{ 934 bool did_resolve = false; 935 struct intel_resolve_map *i, *next; 936 937 for (i = mt->hiz_map.next; i; i = next) { 938 next = i->next; 939 if (i->need != need) 940 continue; 941 942 intel_hiz_exec(intel, mt, i->level, i->layer, need); 943 intel_resolve_map_remove(i); 944 did_resolve = true; 945 } 946 947 return did_resolve; 948} 949 950bool 951intel_miptree_all_slices_resolve_hiz(struct intel_context *intel, 952 struct intel_mipmap_tree *mt) 953{ 954 return intel_miptree_all_slices_resolve(intel, mt, 955 GEN6_HIZ_OP_HIZ_RESOLVE); 956} 957 958bool 959intel_miptree_all_slices_resolve_depth(struct intel_context *intel, 960 struct intel_mipmap_tree *mt) 961{ 962 return intel_miptree_all_slices_resolve(intel, mt, 963 GEN6_HIZ_OP_DEPTH_RESOLVE); 964} 965 966static void 967intel_miptree_updownsample(struct intel_context *intel, 968 struct intel_mipmap_tree *src, 969 struct intel_mipmap_tree *dst, 970 unsigned width, 971 unsigned height) 972{ 973#ifndef I915 974 int src_x0 = 0; 975 int src_y0 = 0; 976 int dst_x0 = 0; 977 int dst_y0 = 0; 978 979 intel_miptree_slice_resolve_depth(intel, src, 0, 0); 980 intel_miptree_slice_resolve_depth(intel, dst, 0, 0); 981 982 brw_blorp_blit_miptrees(intel, 983 src, dst, 984 src_x0, src_y0, 985 dst_x0, dst_y0, 986 width, height, 987 false, false /*mirror x, y*/); 988 989 if (src->stencil_mt) { 990 brw_blorp_blit_miptrees(intel, 991 src->stencil_mt, dst->stencil_mt, 992 src_x0, src_y0, 993 dst_x0, dst_y0, 994 width, height, 995 false, false /*mirror x, y*/); 996 } 997#endif /* I915 */ 998} 999 1000static void 1001assert_is_flat(struct intel_mipmap_tree *mt) 1002{ 1003 assert(mt->target == GL_TEXTURE_2D); 1004 assert(mt->first_level == 0); 1005 assert(mt->last_level == 0); 1006} 1007 1008/** 1009 * \brief Downsample from mt to mt->singlesample_mt. 1010 * 1011 * If the miptree needs no downsample, then skip. 1012 */ 1013void 1014intel_miptree_downsample(struct intel_context *intel, 1015 struct intel_mipmap_tree *mt) 1016{ 1017 /* Only flat, renderbuffer-like miptrees are supported. */ 1018 assert_is_flat(mt); 1019 1020 if (!mt->need_downsample) 1021 return; 1022 intel_miptree_updownsample(intel, 1023 mt, mt->singlesample_mt, 1024 mt->singlesample_mt->width0, 1025 mt->singlesample_mt->height0); 1026 mt->need_downsample = false; 1027 1028 /* Strictly speaking, after a downsample on a depth miptree, a hiz 1029 * resolve is needed on the singlesample miptree. However, since the 1030 * singlesample miptree is never rendered to, the hiz resolve will never 1031 * occur. Therefore we do not mark the needed hiz resolve after 1032 * downsampling. 1033 */ 1034} 1035 1036/** 1037 * \brief Upsample from mt->singlesample_mt to mt. 1038 * 1039 * The upsample is done unconditionally. 1040 */ 1041void 1042intel_miptree_upsample(struct intel_context *intel, 1043 struct intel_mipmap_tree *mt) 1044{ 1045 /* Only flat, renderbuffer-like miptrees are supported. */ 1046 assert_is_flat(mt); 1047 assert(!mt->need_downsample); 1048 1049 intel_miptree_updownsample(intel, 1050 mt->singlesample_mt, mt, 1051 mt->singlesample_mt->width0, 1052 mt->singlesample_mt->height0); 1053 intel_miptree_slice_set_needs_hiz_resolve(mt, 0, 0); 1054} 1055 1056static void 1057intel_miptree_map_gtt(struct intel_context *intel, 1058 struct intel_mipmap_tree *mt, 1059 struct intel_miptree_map *map, 1060 unsigned int level, unsigned int slice) 1061{ 1062 unsigned int bw, bh; 1063 void *base; 1064 unsigned int image_x, image_y; 1065 int x = map->x; 1066 int y = map->y; 1067 1068 /* For compressed formats, the stride is the number of bytes per 1069 * row of blocks. intel_miptree_get_image_offset() already does 1070 * the divide. 1071 */ 1072 _mesa_get_format_block_size(mt->format, &bw, &bh); 1073 assert(y % bh == 0); 1074 y /= bh; 1075 1076 base = intel_region_map(intel, mt->region, map->mode); 1077 1078 if (base == NULL) 1079 map->ptr = NULL; 1080 else { 1081 /* Note that in the case of cube maps, the caller must have passed the 1082 * slice number referencing the face. 1083 */ 1084 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y); 1085 x += image_x; 1086 y += image_y; 1087 1088 map->stride = mt->region->pitch * mt->cpp; 1089 map->ptr = base + y * map->stride + x * mt->cpp; 1090 } 1091 1092 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__, 1093 map->x, map->y, map->w, map->h, 1094 mt, _mesa_get_format_name(mt->format), 1095 x, y, map->ptr, map->stride); 1096} 1097 1098static void 1099intel_miptree_unmap_gtt(struct intel_context *intel, 1100 struct intel_mipmap_tree *mt, 1101 struct intel_miptree_map *map, 1102 unsigned int level, 1103 unsigned int slice) 1104{ 1105 intel_region_unmap(intel, mt->region); 1106} 1107 1108static void 1109intel_miptree_map_blit(struct intel_context *intel, 1110 struct intel_mipmap_tree *mt, 1111 struct intel_miptree_map *map, 1112 unsigned int level, unsigned int slice) 1113{ 1114 unsigned int image_x, image_y; 1115 int x = map->x; 1116 int y = map->y; 1117 int ret; 1118 1119 /* The blitter requires the pitch to be aligned to 4. */ 1120 map->stride = ALIGN(map->w * mt->region->cpp, 4); 1121 1122 map->bo = drm_intel_bo_alloc(intel->bufmgr, "intel_miptree_map_blit() temp", 1123 map->stride * map->h, 4096); 1124 if (!map->bo) { 1125 fprintf(stderr, "Failed to allocate blit temporary\n"); 1126 goto fail; 1127 } 1128 1129 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y); 1130 x += image_x; 1131 y += image_y; 1132 1133 if (!intelEmitCopyBlit(intel, 1134 mt->region->cpp, 1135 mt->region->pitch, mt->region->bo, 1136 0, mt->region->tiling, 1137 map->stride / mt->region->cpp, map->bo, 1138 0, I915_TILING_NONE, 1139 x, y, 1140 0, 0, 1141 map->w, map->h, 1142 GL_COPY)) { 1143 fprintf(stderr, "Failed to blit\n"); 1144 goto fail; 1145 } 1146 1147 intel_batchbuffer_flush(intel); 1148 ret = drm_intel_bo_map(map->bo, (map->mode & GL_MAP_WRITE_BIT) != 0); 1149 if (ret) { 1150 fprintf(stderr, "Failed to map blit temporary\n"); 1151 goto fail; 1152 } 1153 1154 map->ptr = map->bo->virtual; 1155 1156 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__, 1157 map->x, map->y, map->w, map->h, 1158 mt, _mesa_get_format_name(mt->format), 1159 x, y, map->ptr, map->stride); 1160 1161 return; 1162 1163fail: 1164 drm_intel_bo_unreference(map->bo); 1165 map->ptr = NULL; 1166 map->stride = 0; 1167} 1168 1169static void 1170intel_miptree_unmap_blit(struct intel_context *intel, 1171 struct intel_mipmap_tree *mt, 1172 struct intel_miptree_map *map, 1173 unsigned int level, 1174 unsigned int slice) 1175{ 1176 assert(!(map->mode & GL_MAP_WRITE_BIT)); 1177 1178 drm_intel_bo_unmap(map->bo); 1179 drm_intel_bo_unreference(map->bo); 1180} 1181 1182static void 1183intel_miptree_map_s8(struct intel_context *intel, 1184 struct intel_mipmap_tree *mt, 1185 struct intel_miptree_map *map, 1186 unsigned int level, unsigned int slice) 1187{ 1188 map->stride = map->w; 1189 map->buffer = map->ptr = malloc(map->stride * map->h); 1190 if (!map->buffer) 1191 return; 1192 1193 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no 1194 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless 1195 * invalidate is set, since we'll be writing the whole rectangle from our 1196 * temporary buffer back out. 1197 */ 1198 if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) { 1199 uint8_t *untiled_s8_map = map->ptr; 1200 uint8_t *tiled_s8_map = intel_region_map(intel, mt->region, 1201 GL_MAP_READ_BIT); 1202 unsigned int image_x, image_y; 1203 1204 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y); 1205 1206 for (uint32_t y = 0; y < map->h; y++) { 1207 for (uint32_t x = 0; x < map->w; x++) { 1208 ptrdiff_t offset = intel_offset_S8(mt->region->pitch, 1209 x + image_x + map->x, 1210 y + image_y + map->y, 1211 intel->has_swizzling); 1212 untiled_s8_map[y * map->w + x] = tiled_s8_map[offset]; 1213 } 1214 } 1215 1216 intel_region_unmap(intel, mt->region); 1217 1218 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__, 1219 map->x, map->y, map->w, map->h, 1220 mt, map->x + image_x, map->y + image_y, map->ptr, map->stride); 1221 } else { 1222 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__, 1223 map->x, map->y, map->w, map->h, 1224 mt, map->ptr, map->stride); 1225 } 1226} 1227 1228static void 1229intel_miptree_unmap_s8(struct intel_context *intel, 1230 struct intel_mipmap_tree *mt, 1231 struct intel_miptree_map *map, 1232 unsigned int level, 1233 unsigned int slice) 1234{ 1235 if (map->mode & GL_MAP_WRITE_BIT) { 1236 unsigned int image_x, image_y; 1237 uint8_t *untiled_s8_map = map->ptr; 1238 uint8_t *tiled_s8_map = intel_region_map(intel, mt->region, map->mode); 1239 1240 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y); 1241 1242 for (uint32_t y = 0; y < map->h; y++) { 1243 for (uint32_t x = 0; x < map->w; x++) { 1244 ptrdiff_t offset = intel_offset_S8(mt->region->pitch, 1245 x + map->x, 1246 y + map->y, 1247 intel->has_swizzling); 1248 tiled_s8_map[offset] = untiled_s8_map[y * map->w + x]; 1249 } 1250 } 1251 1252 intel_region_unmap(intel, mt->region); 1253 } 1254 1255 free(map->buffer); 1256} 1257 1258static void 1259intel_miptree_map_etc1(struct intel_context *intel, 1260 struct intel_mipmap_tree *mt, 1261 struct intel_miptree_map *map, 1262 unsigned int level, 1263 unsigned int slice) 1264{ 1265 /* For justification of these invariants, 1266 * see intel_mipmap_tree:wraps_etc1. 1267 */ 1268 assert(mt->wraps_etc1); 1269 assert(mt->format == MESA_FORMAT_RGBX8888_REV); 1270 1271 /* From the GL_OES_compressed_ETC1_RGB8_texture spec: 1272 * INVALID_OPERATION is generated by CompressedTexSubImage2D, 1273 * TexSubImage2D, or CopyTexSubImage2D if the texture image <level> 1274 * bound to <target> has internal format ETC1_RGB8_OES. 1275 * 1276 * This implies that intel_miptree_map_etc1() can only be called from 1277 * glCompressedTexImage2D, and hence the assertions below hold. 1278 */ 1279 assert(map->mode & GL_MAP_WRITE_BIT); 1280 assert(map->mode & GL_MAP_INVALIDATE_RANGE_BIT); 1281 assert(map->x == 0); 1282 assert(map->y == 0); 1283 1284 /* Each ETC1 block contains 4x4 pixels in 8 bytes. */ 1285 map->stride = 2 * map->w; 1286 map->buffer = map->ptr = malloc(map->stride * map->h); 1287} 1288 1289static void 1290intel_miptree_unmap_etc1(struct intel_context *intel, 1291 struct intel_mipmap_tree *mt, 1292 struct intel_miptree_map *map, 1293 unsigned int level, 1294 unsigned int slice) 1295{ 1296 uint32_t image_x; 1297 uint32_t image_y; 1298 intel_miptree_get_image_offset(mt, level, 0, slice, &image_x, &image_y); 1299 1300 uint8_t *xbgr = intel_region_map(intel, mt->region, map->mode) 1301 + image_y * mt->region->pitch * mt->region->cpp 1302 + image_x * mt->region->cpp; 1303 1304 _mesa_etc1_unpack_rgba8888(xbgr, mt->region->pitch * mt->region->cpp, 1305 map->ptr, map->stride, 1306 map->w, map->h); 1307 1308 intel_region_unmap(intel, mt->region); 1309 free(map->buffer); 1310} 1311 1312/** 1313 * Mapping function for packed depth/stencil miptrees backed by real separate 1314 * miptrees for depth and stencil. 1315 * 1316 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer 1317 * separate from the depth buffer. Yet at the GL API level, we have to expose 1318 * packed depth/stencil textures and FBO attachments, and Mesa core expects to 1319 * be able to map that memory for texture storage and glReadPixels-type 1320 * operations. We give Mesa core that access by mallocing a temporary and 1321 * copying the data between the actual backing store and the temporary. 1322 */ 1323static void 1324intel_miptree_map_depthstencil(struct intel_context *intel, 1325 struct intel_mipmap_tree *mt, 1326 struct intel_miptree_map *map, 1327 unsigned int level, unsigned int slice) 1328{ 1329 struct intel_mipmap_tree *z_mt = mt; 1330 struct intel_mipmap_tree *s_mt = mt->stencil_mt; 1331 bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT; 1332 int packed_bpp = map_z32f_x24s8 ? 8 : 4; 1333 1334 map->stride = map->w * packed_bpp; 1335 map->buffer = map->ptr = malloc(map->stride * map->h); 1336 if (!map->buffer) 1337 return; 1338 1339 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no 1340 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless 1341 * invalidate is set, since we'll be writing the whole rectangle from our 1342 * temporary buffer back out. 1343 */ 1344 if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) { 1345 uint32_t *packed_map = map->ptr; 1346 uint8_t *s_map = intel_region_map(intel, s_mt->region, GL_MAP_READ_BIT); 1347 uint32_t *z_map = intel_region_map(intel, z_mt->region, GL_MAP_READ_BIT); 1348 unsigned int s_image_x, s_image_y; 1349 unsigned int z_image_x, z_image_y; 1350 1351 intel_miptree_get_image_offset(s_mt, level, 0, slice, 1352 &s_image_x, &s_image_y); 1353 intel_miptree_get_image_offset(z_mt, level, 0, slice, 1354 &z_image_x, &z_image_y); 1355 1356 for (uint32_t y = 0; y < map->h; y++) { 1357 for (uint32_t x = 0; x < map->w; x++) { 1358 int map_x = map->x + x, map_y = map->y + y; 1359 ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch, 1360 map_x + s_image_x, 1361 map_y + s_image_y, 1362 intel->has_swizzling); 1363 ptrdiff_t z_offset = ((map_y + z_image_y) * z_mt->region->pitch + 1364 (map_x + z_image_x)); 1365 uint8_t s = s_map[s_offset]; 1366 uint32_t z = z_map[z_offset]; 1367 1368 if (map_z32f_x24s8) { 1369 packed_map[(y * map->w + x) * 2 + 0] = z; 1370 packed_map[(y * map->w + x) * 2 + 1] = s; 1371 } else { 1372 packed_map[y * map->w + x] = (s << 24) | (z & 0x00ffffff); 1373 } 1374 } 1375 } 1376 1377 intel_region_unmap(intel, s_mt->region); 1378 intel_region_unmap(intel, z_mt->region); 1379 1380 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n", 1381 __FUNCTION__, 1382 map->x, map->y, map->w, map->h, 1383 z_mt, map->x + z_image_x, map->y + z_image_y, 1384 s_mt, map->x + s_image_x, map->y + s_image_y, 1385 map->ptr, map->stride); 1386 } else { 1387 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__, 1388 map->x, map->y, map->w, map->h, 1389 mt, map->ptr, map->stride); 1390 } 1391} 1392 1393static void 1394intel_miptree_unmap_depthstencil(struct intel_context *intel, 1395 struct intel_mipmap_tree *mt, 1396 struct intel_miptree_map *map, 1397 unsigned int level, 1398 unsigned int slice) 1399{ 1400 struct intel_mipmap_tree *z_mt = mt; 1401 struct intel_mipmap_tree *s_mt = mt->stencil_mt; 1402 bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z32_FLOAT; 1403 1404 if (map->mode & GL_MAP_WRITE_BIT) { 1405 uint32_t *packed_map = map->ptr; 1406 uint8_t *s_map = intel_region_map(intel, s_mt->region, map->mode); 1407 uint32_t *z_map = intel_region_map(intel, z_mt->region, map->mode); 1408 unsigned int s_image_x, s_image_y; 1409 unsigned int z_image_x, z_image_y; 1410 1411 intel_miptree_get_image_offset(s_mt, level, 0, slice, 1412 &s_image_x, &s_image_y); 1413 intel_miptree_get_image_offset(z_mt, level, 0, slice, 1414 &z_image_x, &z_image_y); 1415 1416 for (uint32_t y = 0; y < map->h; y++) { 1417 for (uint32_t x = 0; x < map->w; x++) { 1418 ptrdiff_t s_offset = intel_offset_S8(s_mt->region->pitch, 1419 x + s_image_x + map->x, 1420 y + s_image_y + map->y, 1421 intel->has_swizzling); 1422 ptrdiff_t z_offset = ((y + z_image_y) * z_mt->region->pitch + 1423 (x + z_image_x)); 1424 1425 if (map_z32f_x24s8) { 1426 z_map[z_offset] = packed_map[(y * map->w + x) * 2 + 0]; 1427 s_map[s_offset] = packed_map[(y * map->w + x) * 2 + 1]; 1428 } else { 1429 uint32_t packed = packed_map[y * map->w + x]; 1430 s_map[s_offset] = packed >> 24; 1431 z_map[z_offset] = packed; 1432 } 1433 } 1434 } 1435 1436 intel_region_unmap(intel, s_mt->region); 1437 intel_region_unmap(intel, z_mt->region); 1438 1439 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n", 1440 __FUNCTION__, 1441 map->x, map->y, map->w, map->h, 1442 z_mt, _mesa_get_format_name(z_mt->format), 1443 map->x + z_image_x, map->y + z_image_y, 1444 s_mt, map->x + s_image_x, map->y + s_image_y, 1445 map->ptr, map->stride); 1446 } 1447 1448 free(map->buffer); 1449} 1450 1451void 1452intel_miptree_map(struct intel_context *intel, 1453 struct intel_mipmap_tree *mt, 1454 unsigned int level, 1455 unsigned int slice, 1456 unsigned int x, 1457 unsigned int y, 1458 unsigned int w, 1459 unsigned int h, 1460 GLbitfield mode, 1461 void **out_ptr, 1462 int *out_stride) 1463{ 1464 struct intel_miptree_map *map; 1465 1466 map = calloc(1, sizeof(struct intel_miptree_map)); 1467 if (!map){ 1468 *out_ptr = NULL; 1469 *out_stride = 0; 1470 return; 1471 } 1472 1473 assert(!mt->level[level].slice[slice].map); 1474 mt->level[level].slice[slice].map = map; 1475 map->mode = mode; 1476 map->x = x; 1477 map->y = y; 1478 map->w = w; 1479 map->h = h; 1480 1481 intel_miptree_slice_resolve_depth(intel, mt, level, slice); 1482 if (map->mode & GL_MAP_WRITE_BIT) { 1483 intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice); 1484 } 1485 1486 if (mt->format == MESA_FORMAT_S8) { 1487 intel_miptree_map_s8(intel, mt, map, level, slice); 1488 } else if (mt->wraps_etc1) { 1489 intel_miptree_map_etc1(intel, mt, map, level, slice); 1490 } else if (mt->stencil_mt) { 1491 intel_miptree_map_depthstencil(intel, mt, map, level, slice); 1492 } else if (intel->has_llc && 1493 !(mode & GL_MAP_WRITE_BIT) && 1494 !mt->compressed && 1495 mt->region->tiling == I915_TILING_X) { 1496 intel_miptree_map_blit(intel, mt, map, level, slice); 1497 } else { 1498 intel_miptree_map_gtt(intel, mt, map, level, slice); 1499 } 1500 1501 *out_ptr = map->ptr; 1502 *out_stride = map->stride; 1503 1504 if (map->ptr == NULL) { 1505 mt->level[level].slice[slice].map = NULL; 1506 free(map); 1507 } 1508} 1509 1510void 1511intel_miptree_unmap(struct intel_context *intel, 1512 struct intel_mipmap_tree *mt, 1513 unsigned int level, 1514 unsigned int slice) 1515{ 1516 struct intel_miptree_map *map = mt->level[level].slice[slice].map; 1517 1518 if (!map) 1519 return; 1520 1521 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__, 1522 mt, _mesa_get_format_name(mt->format), level, slice); 1523 1524 if (mt->format == MESA_FORMAT_S8) { 1525 intel_miptree_unmap_s8(intel, mt, map, level, slice); 1526 } else if (mt->wraps_etc1) { 1527 intel_miptree_unmap_etc1(intel, mt, map, level, slice); 1528 } else if (mt->stencil_mt) { 1529 intel_miptree_unmap_depthstencil(intel, mt, map, level, slice); 1530 } else if (map->bo) { 1531 intel_miptree_unmap_blit(intel, mt, map, level, slice); 1532 } else { 1533 intel_miptree_unmap_gtt(intel, mt, map, level, slice); 1534 } 1535 1536 mt->level[level].slice[slice].map = NULL; 1537 free(map); 1538} 1539