r200_context.h revision 7d01cb37d94b8966fa089106b902325dbef33a58
1bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/* 2adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellCopyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 4adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThe Weather Channel (TM) funded Tungsten Graphics to develop the 5adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellinitial release of the Radeon 8500 driver under the XFree86 license. 6adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThis notice must be preserved. 7adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 8adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellPermission is hereby granted, free of charge, to any person obtaining 9adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwella copy of this software and associated documentation files (the 10adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell"Software"), to deal in the Software without restriction, including 11adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellwithout limitation the rights to use, copy, modify, merge, publish, 12adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelldistribute, sublicense, and/or sell copies of the Software, and to 13adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellpermit persons to whom the Software is furnished to do so, subject to 14adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellthe following conditions: 15adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 16adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThe above copyright notice and this permission notice (including the 17adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellnext paragraph) shall be included in all copies or substantial 18adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellportions of the Software. 19adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 20adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 28adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell**************************************************************************/ 29adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 30adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* 31adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Authors: 32adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Keith Whitwell <keith@tungstengraphics.com> 33adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 34adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 35adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#ifndef __R200_CONTEXT_H__ 36adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define __R200_CONTEXT_H__ 37adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 38e946688edac5cdf153652defae3ef732a3487416Ian Romanick#include "tnl/t_vertex.h" 39ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl#include "drm.h" 40ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl#include "radeon_drm.h" 41adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "dri_util.h" 42adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "texmem.h" 43adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 44ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/macros.h" 45ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/mtypes.h" 46ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/colormac.h" 47adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "r200_reg.h" 4898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#include "r200_vertprog.h" 49adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5095a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick#define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */ 51adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 52bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#ifndef R200_EMIT_VAP_PVS_CNTL 53bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#error This driver requires a newer libdrm to compile 54bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#endif 55bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger 564637235183b80963536f2364e4d50fcb894886ddDave Airlie#include "radeon_screen.h" 57692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#include "common_context.h" 58d29e96bf33e91d071770b86d87ffc4ef4dfc2f70Dave Airlie#include "common_misc.h" 59692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 60adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_context; 61adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef struct r200_context r200ContextRec; 62adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef struct r200_context *r200ContextPtr; 63adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 64adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "r200_lock.h" 65adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 664637235183b80963536f2364e4d50fcb894886ddDave Airlie#include "main/mm.h" 67adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 6898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheideggerstruct r200_vertex_program { 69122629f27925a9dc50029bebc5079f87f416a7e1Brian Paul struct gl_vertex_program mesa_program; /* Must be first */ 7098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int translated; 71fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger /* need excess instr: 1 for late loop checking, 2 for 72fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger additional instr due to instr/attr, 3 for fog */ 73fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 7498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int pos_end; 7598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int inputs[VERT_ATTRIB_MAX]; 76421ce180f52ff55b866066fabd861a51dd6d2b26Roland Scheidegger GLubyte inputmap_rev[16]; 7798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int native; 78fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger int fogpidx; 79fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger int fogmode; 8098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger}; 8198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 82692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_TEX_ALL 0x3f 83adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 84adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 85adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_texture_env_state { 86692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonTexObjPtr texobj; 8736603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint outputreg; 8836603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint unitneeded; 89adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 90adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 9148ccaf200940613032dfaaafe71382947f398004Roland Scheidegger#define R200_MAX_TEXTURE_UNITS 6 92adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 93adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_texture_state { 94adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 95adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 96adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 97adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 98adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Trying to keep these relatively short as the variables are becoming 99adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * extravagently long. Drop the driver name prefix off the front of 100adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * everything - I think we know which driver we're in by now, and keep the 101adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * prefix to 3 letters unless absolutely impossible. 102adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 103adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 104adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_0 0 105adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_MISC 1 106adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_FOG_COLOR 2 107adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RE_SOLID_COLOR 3 108adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_BLENDCNTL 4 109adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_DEPTHOFFSET 5 110adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_DEPTHPITCH 6 111adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_ZSTENCILCNTL 7 112adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_1 8 113adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_CNTL 9 114adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_CNTL 10 115adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_COLOROFFSET 11 116adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_2 12 /* why */ 117adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_COLORPITCH 13 /* why */ 118033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_STATE_SIZE_OLDDRM 14 119033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_CMD_3 14 120033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_BLENDCOLOR 15 121033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_ABLENDCNTL 16 122033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_CBLENDCNTL 17 123033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_STATE_SIZE_NEWDRM 18 124adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 125adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_CMD_0 0 126adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_SE_CNTL 1 127adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 128adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_STATE_SIZE 3 129adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 130adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_CMD_0 0 131adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_SE_VTE_CNTL 1 132adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_STATE_SIZE 2 133adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 134adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_CMD_0 0 135adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_RE_LINE_PATTERN 1 136adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_RE_LINE_STATE 2 137adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_CMD_1 3 138adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_SE_LINE_WIDTH 4 139adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_STATE_SIZE 5 140adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 141adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_CMD_0 0 142adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_STENCILREFMASK 1 143adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_ROPCNTL 2 144adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_PLANEMASK 3 145adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_STATE_SIZE 4 146adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 147adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_CMD_0 0 148adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_XSCALE 1 149adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_XOFFSET 2 150adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_YSCALE 3 151adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_YOFFSET 4 152adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_ZSCALE 5 153adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_ZOFFSET 6 154adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_STATE_SIZE 7 155adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 156adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_CMD_0 0 157adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_SE_ZBIAS_FACTOR 1 158adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_SE_ZBIAS_CONSTANT 2 159adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_STATE_SIZE 3 160adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 161adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_CMD_0 0 162adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_RE_MISC 1 163adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_STATE_SIZE 2 164adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 165adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_CMD_0 0 166adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_DEBUG3 1 167adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_STATE_SIZE 2 168adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 169adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_CMD_0 0 170adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFILTER 1 /*2c00*/ 171adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFORMAT 2 /*2c04*/ 172adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 173adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXSIZE 4 /*2c0c*/ 174adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXPITCH 5 /*2c10*/ 175adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 176f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_CMD_1_OLDDRM 7 177f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 178f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_STATE_SIZE_OLDDRM 9 179f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_CUBIC_FACES 7 180f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXMULTI_CTL 8 181f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_CMD_1_NEWDRM 9 182f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXOFFSET_NEWDRM 10 183f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_STATE_SIZE_NEWDRM 11 184f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 185f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 186f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 187adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_CMD_1 2 /* 5 registers follow */ 188adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 189adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 190adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 191adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 192adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 193adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_STATE_SIZE 8 194adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 195adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_CMD_0 0 196adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXCBLEND 1 197adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXCBLEND2 2 198adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXABLEND 3 199adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXABLEND2 4 200adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_STATE_SIZE 5 201adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 202adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_CMD_0 0 203adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_0 1 204adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_1 2 205adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_2 3 206adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_3 4 207adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_4 5 208adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_5 6 209adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_STATE_SIZE 7 210adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 211f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_CMD_0 0 212f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_0 1 213f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_1 2 214f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_2 3 215f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_3 4 216f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_4 5 217f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_5 6 218f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_6 7 219f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_7 8 220f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_STATE_SIZE 9 221f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 222f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger/* ATI_FRAGMENT_SHADER */ 223f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_CMD_0 0 224f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IC0 1 /* 2f00 */ 225f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IC1 2 /* 2f04 */ 226f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IA0 3 /* 2f08 */ 227f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IA1 4 /* 2f0c */ 228f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_STATE_SIZE 33 229f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 23098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CMD_0 0 23198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CNTL_1 1 23298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CNTL_2 2 23398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_STATE_SIZE 3 23498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 23598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger/* those are quite big... */ 23698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_CMD_0 0 23798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_OPDST_0 1 23898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC0_0 2 23998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC1_0 3 24098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC2_0 4 24198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_OPDST_63 253 24298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC0_63 254 24398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC1_63 255 24498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC2_63 256 24598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_STATE_SIZE 257 24698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 24798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_CMD_0 0 24898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM0_0 1 24998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM1_0 2 25098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM2_0 3 25198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM3_0 4 25298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM0_95 381 25398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM1_95 382 25498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM2_95 383 25598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM3_95 384 25698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_STATE_SIZE 385 25798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 258adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_CMD_0 0 259adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_LIGHT_MODEL_CTL_0 1 260adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_LIGHT_MODEL_CTL_1 2 261adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_0 3 262adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_1 4 263adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_2 5 264adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_3 6 265adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_CMD_1 7 266adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_UCP_VERT_BLEND_CTL 8 267adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_STATE_SIZE 9 268adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 269adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_CMD_0 0 270adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_0 1 271adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_1 2 272adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_2 3 273adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_3 4 274adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_4 5 275adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_STATE_SIZE 6 276adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 277adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_CMD_0 0 278adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_2 1 279adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_3 2 280adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_0 3 281adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_1 4 282adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_CYL_WRAP_CTL 5 283adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_STATE_SIZE 6 284adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 285adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_CMD_0 0 286adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_RED 1 287adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_GREEN 2 288adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_BLUE 3 289adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_ALPHA 4 290adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_RED 5 291adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_GREEN 6 292adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_BLUE 7 293adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_ALPHA 8 294adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_RED 9 295adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_GREEN 10 296adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_BLUE 11 297adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_ALPHA 12 298adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_RED 13 299adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_GREEN 14 300adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_BLUE 15 301adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_ALPHA 16 302adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_CMD_1 17 303adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SHININESS 18 304adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_STATE_SIZE 19 305adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 306adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_CMD_0 0 307adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_SE_VAP_CNTL 1 308adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_STATE_SIZE 2 309adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 310adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Replaces a lot of packet info from radeon 311adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 312adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_0 0 313adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_VTXFMT_0 1 314adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_VTXFMT_1 2 315adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_VTXFMT_0 3 316adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_VTXFMT_1 4 317adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_1 5 318adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_COMPSEL 6 319adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_2 7 320adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_STATE_CNTL 8 321adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_STATE_SIZE 9 322adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 32344dace86eaf9eded8e6465adfadf6345658686ddRoland Scheidegger/* SPR - point sprite state 32444dace86eaf9eded8e6465adfadf6345658686ddRoland Scheidegger */ 325cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_CMD_0 0 326cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_POINT_SPRITE_CNTL 1 327cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_STATE_SIZE 2 328cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger 329cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CMD_0 0 330cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_0 1 331cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_1 2 332cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_PTSIZE 3 333cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_3 4 334cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CMD_1 5 335cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_QUAD 6 336cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_LIN 7 337cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_CON 8 338cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_3 9 339cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_X 10 340cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_Y 11 341cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_Z 12 342cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_3 13 343cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_MIN 14 344cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_MAX 15 345cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_2 16 346cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_3 17 347cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_STATE_SIZE 18 348adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 349adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 350adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell R200_VTX_COLOR_MASK) 351adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 35295a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick/** 35395a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 35495a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick * how many components are in texture coordinate \c n. 35595a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick */ 35695a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 35795a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick 358adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_CMD_0 0 359adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_ELT_0 1 360adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_STATE_SIZE 17 361adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 362adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_CMD_0 0 363adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_VERT_GUARD_CLIP_ADJ 1 364adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_VERT_GUARD_DISCARD_ADJ 2 365adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_HORZ_GUARD_CLIP_ADJ 3 366adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_HORZ_GUARD_DISCARD_ADJ 4 367adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_STATE_SIZE 5 368adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 369adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* position changes frequently when lighting in modelpos - separate 370adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * out to new state item? 371adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 372adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_CMD_0 0 373adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_RED 1 374adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_GREEN 2 375adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_BLUE 3 376adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_ALPHA 4 377adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_RED 5 378adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_GREEN 6 379adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_BLUE 7 380adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_ALPHA 8 381adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_RED 9 382adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_GREEN 10 383adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_BLUE 11 384adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_ALPHA 12 385adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_X 13 386adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_Y 14 387adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_Z 15 388adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_W 16 389adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_X 17 390adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_Y 18 391adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_Z 19 392adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_W 20 3935d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_QUADRATIC 21 394adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_ATTEN_LINEAR 22 3955d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST 23 396adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_ATTEN_XXX 24 397adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_CMD_1 25 398adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_DCD 26 399adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_DCM 27 400adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_EXPONENT 28 401adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_CUTOFF 29 402adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_THRESH 30 403adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_RANGE_CUTOFF 31 /* ? */ 4045d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST_INV 32 405adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_STATE_SIZE 33 406adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 407adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Fog 408adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 409adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_CMD_0 0 410adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_R 1 411adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_C 2 412adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_D 3 413adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_PAD 4 414adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_STATE_SIZE 5 415adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 416adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* UCP 417adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 418adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_CMD_0 0 419adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_X 1 420adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_Y 2 421adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_Z 3 422adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_W 4 423adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_STATE_SIZE 5 424adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 425adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* GLT - Global ambient 426adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 427adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_CMD_0 0 428adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_RED 1 429adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_GREEN 2 430adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_BLUE 3 431adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_ALPHA 4 432adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_STATE_SIZE 5 433adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 434adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* EYE 435adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 436adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_CMD_0 0 437adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_X 1 438adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_Y 2 439adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_Z 3 440adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_RESCALE_FACTOR 4 441adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_STATE_SIZE 5 442adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 443adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* CST - constant state 444adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 445adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_0 0 446adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_PP_CNTL_X 1 447adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_1 2 448adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RB3D_DEPTHXY_OFFSET 3 449adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_2 4 450adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_AUX_SCISSOR_CNTL 5 451adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_3 6 452adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_SCISSOR_TL_0 7 453adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_SCISSOR_BR_0 8 454adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_4 9 455adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_VAP_CNTL_STATUS 10 456adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_5 11 457adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_POINTSIZE 12 458adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_6 13 459adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_0 14 460adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_1 15 461adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_2 16 462adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_3 17 463adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_STATE_SIZE 18 464adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 465fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_CMD_0 0 466fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_PP_TRI_PERF 1 467fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_PP_PERF_CNTL 2 468fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_STATE_SIZE 3 469adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 470adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 471adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_hw_state { 4720c8f8d3dc9d60ed34eeca7f3606651420a81753cEric Anholt /* Head of the linked list of state atoms. */ 473b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom atomlist; 474adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 475adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Hardware state, stored as cmdbuf commands: 476adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * -- Need to doublebuffer for 477adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * - reviving state after loss of context 478adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * - eliding noop statechange loops? (except line stipple count) 479adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 480b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ctx; 481b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom set; 482b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vte; 483b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom lin; 484b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msk; 485b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpt; 486b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vap; 487b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vtx; 488b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tcl; 489b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msl; 490b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tcg; 491b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msc; 492b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom cst; 493b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tam; 494b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tf; 495b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tex[6]; 496b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom cube[6]; 497b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom zbs; 498b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom mtl[2]; 499b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom mat[9]; 500b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 501b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ucp[6]; 502b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom pix[6]; /* pixshader stages */ 503b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom eye; /* eye pos */ 504b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom grd; /* guard band clipping */ 505b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom fog; 506b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom glt; 507b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom prf; 508b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom afs[2]; 509b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom pvs; 510b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpi[2]; 511b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpp[2]; 512b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom atf; 513b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom spr; 514b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ptp; 5156f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt 5166f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt int max_state_size; /* Number of bytes necessary for a full state emit. */ 5170c8f8d3dc9d60ed34eeca7f3606651420a81753cEric Anholt GLboolean is_dirty, all_dirty; 518adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 519adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 520adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_state { 521adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Derived state for internal purposes: 522adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 523692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_stipple_state stipple; 524adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_texture_state texture; 52536603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint envneeded; 526adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 527adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5284637235183b80963536f2364e4d50fcb894886ddDave Airlie#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ 529adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell (rvb)->address - rmesa->dma.buf0_address + \ 530adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell (rvb)->start) 531adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5328a6182105772280e2727de4a00809c8fb7b13c87Roland Scheidegger#define R200_CMD_BUF_SZ (16*1024) 533adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5347d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie#define R200_ELT_BUF_SZ (16*1024) 535adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* r200_tcl.c 536adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 537adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_tcl_info { 538adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint hw_primitive; 539adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 540029d18cd3d79ff956c50b3486078d968d15bf0fbRoland Scheidegger/* hw can handle 12 components max */ 541ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie struct radeon_aos aos[12]; 542ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie // struct radeon_dma_region *aos_components[12]; 543adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint nr_aos_components; 544adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 545adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint *Elts; 546adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5477d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie struct radeon_bo *elt_dma_bo; 5487d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie int elt_dma_offset; /** Offset into this buffer object, in bytes */ 5497d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie int elt_used; 5507d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie 5517d01cb37d94b8966fa089106b902325dbef33a58Dave Airlie void (*flush) (r200ContextPtr); 552692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma_region vertex_data[15]; 553adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 554adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 555adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 556adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* r200_swtcl.c 557adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 558adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_swtcl_info { 559adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint RenderIndex; 560e946688edac5cdf153652defae3ef732a3487416Ian Romanick 561e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 562e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is 563e946688edac5cdf153652defae3ef732a3487416Ian Romanick * installed in the Mesa state vector. 564e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 565adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint vertex_size; 566e946688edac5cdf153652defae3ef732a3487416Ian Romanick 567e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 568e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Attributes instructing the Mesa TCL pipeline where / how to put vertex 569e946688edac5cdf153652defae3ef732a3487416Ian Romanick * data in the hardware buffer. 570e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 571e946688edac5cdf153652defae3ef732a3487416Ian Romanick struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 572e946688edac5cdf153652defae3ef732a3487416Ian Romanick 573e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 574e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Number of elements of \c ::vertex_attrs that are actually used. 575e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 576e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint vertex_attr_count; 577e946688edac5cdf153652defae3ef732a3487416Ian Romanick 578e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 579e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Cached pointer to the buffer where Mesa will store vertex data. 580e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 5815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLubyte *verts; 582adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 583adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Fallback rasterization functions 584adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 5854637235183b80963536f2364e4d50fcb894886ddDave Airlie radeon_point_func draw_point; 5864637235183b80963536f2364e4d50fcb894886ddDave Airlie radeon_line_func draw_line; 5874637235183b80963536f2364e4d50fcb894886ddDave Airlie radeon_tri_func draw_tri; 588adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 589adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint hw_primitive; 590adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLenum render_primitive; 591adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint numverts; 592adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 593e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 594e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Offset of the 4UB color data within a hardware (swtcl) vertex. 595e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 596e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint coloroffset; 597e946688edac5cdf153652defae3ef732a3487416Ian Romanick 598e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 599e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 600e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 601e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint specoffset; 602e946688edac5cdf153652defae3ef732a3487416Ian Romanick 603e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 604e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Should Mesa project vertex data or will the hardware do it? 605e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 606e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLboolean needproj; 607e946688edac5cdf153652defae3ef732a3487416Ian Romanick 608ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie struct radeon_bo *bo; 609ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie void (*flush) (r200ContextPtr); 610adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 611adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 612adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 613adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 614adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 61548ccaf200940613032dfaaafe71382947f398004Roland Scheidegger /* A maximum total of 29 elements per vertex: 3 floats for position, 3 616adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * floats for normal, 4 floats for color, 4 bytes for secondary color, 61748ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * 3 floats for each texture unit (18 floats total). 618adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * 61948ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * we maybe need add. 4 to prevent segfault if someone specifies 62048ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 621adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * 622adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * The position data is never actually stored here, so 3 elements could be 623adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * trimmed out of the buffer. 624adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 62548ccaf200940613032dfaaafe71382947f398004Roland Scheidegger 62648ccaf200940613032dfaaafe71382947f398004Roland Scheidegger#define R200_MAX_VERTEX_SIZE ((3*6)+11) 62748ccaf200940613032dfaaafe71382947f398004Roland Scheidegger 628adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_context { 6294637235183b80963536f2364e4d50fcb894886ddDave Airlie struct radeon_context radeon; 630adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 631adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Driver and hardware state management 632adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 633adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_hw_state hw; 634adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_state state; 63598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger struct r200_vertex_program *curr_vp_hw; 636adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 637adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Vertex buffers 638adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 639692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_ioctl ioctl; 640692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma dma; 6410217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie struct radeon_store store; 6427a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt /* A full state emit as of the first state emit in the main store, in case 6437a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt * the context is lost. 6447a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt */ 6450217ed2cf9b0a538ca03d26b302a7cd57af7dd21Dave Airlie struct radeon_store backup_store; 646adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 647adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Clientdata textures; 648adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 649ed3a1cce73fcd0d6f4b6e9b5f69a98ad179ddc4bDave Airlie GLuint prefer_gart_client_texturing; 650adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 6517a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt GLboolean save_on_next_emit; 652adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 653adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* TCL stuff 654adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 655adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 656adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 657adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 65824a44d74b6e9880dfc019bd1cfa9ce0351377c85Roland Scheidegger GLuint TexMatEnabled; 659adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexMatCompSel; 660adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexGenEnabled; 661adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexGenCompSel; 662adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLmatrix tmpmat; 663adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 664adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* r200_tcl.c 665adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 666adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_tcl_info tcl; 667adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 668adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* r200_swtcl.c 669adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 670adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_swtcl_info swtcl; 671adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 672b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger GLboolean using_hyperz; 6734837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger GLboolean texmicrotile; 674f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 675f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger struct ati_fragment_shader *afs_loaded; 676adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 677adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 678adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 679adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 680adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 681adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); 682adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern GLboolean r200CreateContext( const __GLcontextModes *glVisual, 683adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell __DRIcontextPrivate *driContextPriv, 684adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell void *sharedContextPrivate); 685adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, 686adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell __DRIdrawablePrivate *driDrawPriv, 687adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell __DRIdrawablePrivate *driReadPriv ); 688adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); 689adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 690adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* ================================================================ 691adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Debugging: 692adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 693adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 69423295cf8e84495af86f62395d32b3116261927e8Dave Airlie#define R200_DEBUG RADEON_DEBUG 695adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 696b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie 697adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 698adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#endif /* __R200_CONTEXT_H__ */ 699