r200_context.h revision b6e486906968d82c7b8a869d7ab51697a7cce80c
1bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/* 2adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellCopyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 4adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThe Weather Channel (TM) funded Tungsten Graphics to develop the 5adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellinitial release of the Radeon 8500 driver under the XFree86 license. 6adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThis notice must be preserved. 7adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 8adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellPermission is hereby granted, free of charge, to any person obtaining 9adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwella copy of this software and associated documentation files (the 10adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell"Software"), to deal in the Software without restriction, including 11adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellwithout limitation the rights to use, copy, modify, merge, publish, 12adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelldistribute, sublicense, and/or sell copies of the Software, and to 13adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellpermit persons to whom the Software is furnished to do so, subject to 14adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellthe following conditions: 15adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 16adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellThe above copyright notice and this permission notice (including the 17adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellnext paragraph) shall be included in all copies or substantial 18adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellportions of the Software. 19adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 20adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26adbec39bbf671ad80f6c557801e274cac0d305faKeith WhitwellWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 28adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell**************************************************************************/ 29adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 30adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* 31adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Authors: 32adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Keith Whitwell <keith@tungstengraphics.com> 33adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 34adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 35adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#ifndef __R200_CONTEXT_H__ 36adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define __R200_CONTEXT_H__ 37adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 38e946688edac5cdf153652defae3ef732a3487416Ian Romanick#include "tnl/t_vertex.h" 39ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl#include "drm.h" 40ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl#include "radeon_drm.h" 41adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "dri_util.h" 42adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "texmem.h" 43adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 44ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/macros.h" 45ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/mtypes.h" 46ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/colormac.h" 47adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "r200_reg.h" 4898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#include "r200_vertprog.h" 49adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5095a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick#define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */ 51adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 52bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#ifndef R200_EMIT_VAP_PVS_CNTL 53bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#error This driver requires a newer libdrm to compile 54bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger#endif 55bf35d70635309e499aee666eb5811446aa8b489eRoland Scheidegger 56692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#include "common_context.h" 57692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie 58adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_context; 59adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef struct r200_context r200ContextRec; 60adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef struct r200_context *r200ContextPtr; 61adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 62adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#include "r200_lock.h" 633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_screen.h" 64ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/mm.h" 65adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 66adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef void (*r200_tri_func)( r200ContextPtr, 67692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonVertex *, 68692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonVertex *, 69692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonVertex * ); 70adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 71adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef void (*r200_line_func)( r200ContextPtr, 72692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonVertex *, 73692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonVertex * ); 74adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 75adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwelltypedef void (*r200_point_func)( r200ContextPtr, 76692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonVertex * ); 77adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 78adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 7998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheideggerstruct r200_vertex_program { 80122629f27925a9dc50029bebc5079f87f416a7e1Brian Paul struct gl_vertex_program mesa_program; /* Must be first */ 8198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int translated; 82fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger /* need excess instr: 1 for late loop checking, 2 for 83fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger additional instr due to instr/attr, 3 for fog */ 84fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 8598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int pos_end; 8698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int inputs[VERT_ATTRIB_MAX]; 87421ce180f52ff55b866066fabd861a51dd6d2b26Roland Scheidegger GLubyte inputmap_rev[16]; 8898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger int native; 89fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger int fogpidx; 90fc606f7db9072d4f40081aea8f92f1d4489a5115Roland Scheidegger int fogmode; 9198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger}; 9298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 93692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie#define R200_TEX_ALL 0x3f 94adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 95adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 96adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_texture_env_state { 97692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie radeonTexObjPtr texobj; 9836603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint outputreg; 9936603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint unitneeded; 100adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 101adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 10248ccaf200940613032dfaaafe71382947f398004Roland Scheidegger#define R200_MAX_TEXTURE_UNITS 6 103adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 104adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_texture_state { 105adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 106adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 107adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 108adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 109adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Trying to keep these relatively short as the variables are becoming 110adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * extravagently long. Drop the driver name prefix off the front of 111adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * everything - I think we know which driver we're in by now, and keep the 112adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * prefix to 3 letters unless absolutely impossible. 113adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 114adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 115adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_0 0 116adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_MISC 1 117adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_FOG_COLOR 2 118adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RE_SOLID_COLOR 3 119adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_BLENDCNTL 4 120adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_DEPTHOFFSET 5 121adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_DEPTHPITCH 6 122adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_ZSTENCILCNTL 7 123adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_1 8 124adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_PP_CNTL 9 125adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_CNTL 10 126adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_COLOROFFSET 11 127adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_CMD_2 12 /* why */ 128adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CTX_RB3D_COLORPITCH 13 /* why */ 129033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_STATE_SIZE_OLDDRM 14 130033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_CMD_3 14 131033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_BLENDCOLOR 15 132033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_ABLENDCNTL 16 133033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_RB3D_CBLENDCNTL 17 134033728555cb2f39d8c77f228e1eccc45329bb40aRoland Scheidegger#define CTX_STATE_SIZE_NEWDRM 18 135adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 136adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_CMD_0 0 137adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_SE_CNTL 1 138adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 139adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define SET_STATE_SIZE 3 140adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 141adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_CMD_0 0 142adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_SE_VTE_CNTL 1 143adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTE_STATE_SIZE 2 144adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 145adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_CMD_0 0 146adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_RE_LINE_PATTERN 1 147adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_RE_LINE_STATE 2 148adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_CMD_1 3 149adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_SE_LINE_WIDTH 4 150adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIN_STATE_SIZE 5 151adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 152adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_CMD_0 0 153adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_STENCILREFMASK 1 154adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_ROPCNTL 2 155adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_RB3D_PLANEMASK 3 156adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSK_STATE_SIZE 4 157adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 158adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_CMD_0 0 159adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_XSCALE 1 160adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_XOFFSET 2 161adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_YSCALE 3 162adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_YOFFSET 4 163adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_ZSCALE 5 164adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_SE_VPORT_ZOFFSET 6 165adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VPT_STATE_SIZE 7 166adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 167adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_CMD_0 0 168adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_SE_ZBIAS_FACTOR 1 169adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_SE_ZBIAS_CONSTANT 2 170adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define ZBS_STATE_SIZE 3 171adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 172adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_CMD_0 0 173adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_RE_MISC 1 174adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSC_STATE_SIZE 2 175adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 176adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_CMD_0 0 177adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_DEBUG3 1 178adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TAM_STATE_SIZE 2 179adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 180adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_CMD_0 0 181adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFILTER 1 /*2c00*/ 182adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFORMAT 2 /*2c04*/ 183adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 184adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXSIZE 4 /*2c0c*/ 185adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_TXPITCH 5 /*2c10*/ 186adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 187f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_CMD_1_OLDDRM 7 188f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 189f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_STATE_SIZE_OLDDRM 9 190f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_CUBIC_FACES 7 191f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXMULTI_CTL 8 192f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_CMD_1_NEWDRM 9 193f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_PP_TXOFFSET_NEWDRM 10 194f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define TEX_STATE_SIZE_NEWDRM 11 195f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 196f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 197f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 198adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_CMD_1 2 /* 5 registers follow */ 199adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 200adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 201adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 202adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 203adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 204adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CUBE_STATE_SIZE 8 205adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 206adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_CMD_0 0 207adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXCBLEND 1 208adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXCBLEND2 2 209adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXABLEND 3 210adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_PP_TXABLEND2 4 211adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define PIX_STATE_SIZE 5 212adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 213adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_CMD_0 0 214adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_0 1 215adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_1 2 216adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_2 3 217adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_3 4 218adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_4 5 219adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_TFACTOR_5 6 220adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TF_STATE_SIZE 7 221adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 222f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_CMD_0 0 223f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_0 1 224f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_1 2 225f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_2 3 226f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_3 4 227f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_4 5 228f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_5 6 229f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_6 7 230f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_TFACTOR_7 8 231f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define ATF_STATE_SIZE 9 232f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 233f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger/* ATI_FRAGMENT_SHADER */ 234f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_CMD_0 0 235f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IC0 1 /* 2f00 */ 236f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IC1 2 /* 2f04 */ 237f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IA0 3 /* 2f08 */ 238f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_IA1 4 /* 2f0c */ 239f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger#define AFS_STATE_SIZE 33 240f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 24198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CMD_0 0 24298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CNTL_1 1 24398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_CNTL_2 2 24498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define PVS_STATE_SIZE 3 24598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 24698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger/* those are quite big... */ 24798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_CMD_0 0 24898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_OPDST_0 1 24998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC0_0 2 25098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC1_0 3 25198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC2_0 4 25298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_OPDST_63 253 25398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC0_63 254 25498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC1_63 255 25598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_SRC2_63 256 25698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPI_STATE_SIZE 257 25798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 25898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_CMD_0 0 25998c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM0_0 1 26098c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM1_0 2 26198c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM2_0 3 26298c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM3_0 4 26398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM0_95 381 26498c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM1_95 382 26598c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM2_95 383 26698c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_PARAM3_95 384 26798c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger#define VPP_STATE_SIZE 385 26898c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger 269adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_CMD_0 0 270adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_LIGHT_MODEL_CTL_0 1 271adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_LIGHT_MODEL_CTL_1 2 272adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_0 3 273adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_1 4 274adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_2 5 275adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_PER_LIGHT_CTL_3 6 276adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_CMD_1 7 277adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_UCP_VERT_BLEND_CTL 8 278adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCL_STATE_SIZE 9 279adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 280adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_CMD_0 0 281adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_0 1 282adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_1 2 283adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_2 3 284adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_3 4 285adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_MATRIX_SELECT_4 5 286adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MSL_STATE_SIZE 6 287adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 288adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_CMD_0 0 289adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_2 1 290adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_3 2 291adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_0 3 292adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_PROC_CTL_1 4 293adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_TEX_CYL_WRAP_CTL 5 294adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define TCG_STATE_SIZE 6 295adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 296adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_CMD_0 0 297adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_RED 1 298adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_GREEN 2 299adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_BLUE 3 300adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_EMMISSIVE_ALPHA 4 301adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_RED 5 302adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_GREEN 6 303adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_BLUE 7 304adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_AMBIENT_ALPHA 8 305adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_RED 9 306adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_GREEN 10 307adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_BLUE 11 308adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_DIFFUSE_ALPHA 12 309adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_RED 13 310adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_GREEN 14 311adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_BLUE 15 312adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SPECULAR_ALPHA 16 313adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_CMD_1 17 314adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_SHININESS 18 315adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MTL_STATE_SIZE 19 316adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 317adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_CMD_0 0 318adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_SE_VAP_CNTL 1 319adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VAP_STATE_SIZE 2 320adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 321adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Replaces a lot of packet info from radeon 322adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 323adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_0 0 324adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_VTXFMT_0 1 325adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_VTXFMT_1 2 326adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_VTXFMT_0 3 327adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_VTXFMT_1 4 328adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_1 5 329adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_TCL_OUTPUT_COMPSEL 6 330adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_CMD_2 7 331adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_STATE_CNTL 8 332adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_STATE_SIZE 9 333adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 33444dace86eaf9eded8e6465adfadf6345658686ddRoland Scheidegger/* SPR - point sprite state 33544dace86eaf9eded8e6465adfadf6345658686ddRoland Scheidegger */ 336cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_CMD_0 0 337cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_POINT_SPRITE_CNTL 1 338cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define SPR_STATE_SIZE 2 339cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger 340cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CMD_0 0 341cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_0 1 342cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_1 2 343cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_PTSIZE 3 344cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_VPORT_SCALE_3 4 345cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CMD_1 5 346cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_QUAD 6 347cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_LIN 7 348cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_CON 8 349cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_ATT_CONST_3 9 350cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_X 10 351cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_Y 11 352cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_Z 12 353cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_EYE_3 13 354cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_MIN 14 355cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_MAX 15 356cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_2 16 357cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_CLAMP_3 17 358cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheidegger#define PTP_STATE_SIZE 18 359adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 360adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 361adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell R200_VTX_COLOR_MASK) 362adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 36395a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick/** 36495a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 36595a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick * how many components are in texture coordinate \c n. 36695a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick */ 36795a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 36895a0bd6762737bb25bdf5c4147da9d1372f6aac3Ian Romanick 369adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_CMD_0 0 370adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_ELT_0 1 371adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define MAT_STATE_SIZE 17 372adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 373adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_CMD_0 0 374adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_VERT_GUARD_CLIP_ADJ 1 375adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_VERT_GUARD_DISCARD_ADJ 2 376adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_HORZ_GUARD_CLIP_ADJ 3 377adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_HORZ_GUARD_DISCARD_ADJ 4 378adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GRD_STATE_SIZE 5 379adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 380adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* position changes frequently when lighting in modelpos - separate 381adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * out to new state item? 382adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 383adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_CMD_0 0 384adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_RED 1 385adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_GREEN 2 386adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_BLUE 3 387adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_AMBIENT_ALPHA 4 388adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_RED 5 389adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_GREEN 6 390adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_BLUE 7 391adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIFFUSE_ALPHA 8 392adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_RED 9 393adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_GREEN 10 394adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_BLUE 11 395adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_ALPHA 12 396adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_X 13 397adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_Y 14 398adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_Z 15 399adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_POSITION_W 16 400adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_X 17 401adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_Y 18 402adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_Z 19 403adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_DIRECTION_W 20 4045d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_QUADRATIC 21 405adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_ATTEN_LINEAR 22 4065d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST 23 407adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_ATTEN_XXX 24 408adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_CMD_1 25 409adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_DCD 26 410adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_DCM 27 411adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_EXPONENT 28 412adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPOT_CUTOFF 29 413adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_SPECULAR_THRESH 30 414adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_RANGE_CUTOFF 31 /* ? */ 4155d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST_INV 32 416adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define LIT_STATE_SIZE 33 417adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 418adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* Fog 419adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 420adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_CMD_0 0 421adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_R 1 422adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_C 2 423adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_D 3 424adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_PAD 4 425adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define FOG_STATE_SIZE 5 426adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 427adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* UCP 428adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 429adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_CMD_0 0 430adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_X 1 431adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_Y 2 432adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_Z 3 433adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_W 4 434adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define UCP_STATE_SIZE 5 435adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 436adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* GLT - Global ambient 437adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 438adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_CMD_0 0 439adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_RED 1 440adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_GREEN 2 441adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_BLUE 3 442adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_ALPHA 4 443adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define GLT_STATE_SIZE 5 444adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 445adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* EYE 446adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 447adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_CMD_0 0 448adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_X 1 449adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_Y 2 450adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_Z 3 451adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_RESCALE_FACTOR 4 452adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define EYE_STATE_SIZE 5 453adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 454adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* CST - constant state 455adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 456adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_0 0 457adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_PP_CNTL_X 1 458adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_1 2 459adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RB3D_DEPTHXY_OFFSET 3 460adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_2 4 461adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_AUX_SCISSOR_CNTL 5 462adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_3 6 463adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_SCISSOR_TL_0 7 464adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_SCISSOR_BR_0 8 465adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_4 9 466adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_VAP_CNTL_STATUS 10 467adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_5 11 468adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_RE_POINTSIZE 12 469adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_CMD_6 13 470adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_0 14 471adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_1 15 472adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_2 16 473adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_SE_TCL_INPUT_VTX_3 17 474adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define CST_STATE_SIZE 18 475adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 476fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_CMD_0 0 477fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_PP_TRI_PERF 1 478fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_PP_PERF_CNTL 2 479fbe5296d1463e1052590b744f3d62ebb9e5d5dd4Roland Scheidegger#define PRF_STATE_SIZE 3 480adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 481adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 482adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_hw_state { 4830c8f8d3dc9d60ed34eeca7f3606651420a81753cEric Anholt /* Head of the linked list of state atoms. */ 484b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom atomlist; 485adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 486adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Hardware state, stored as cmdbuf commands: 487adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * -- Need to doublebuffer for 488adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * - reviving state after loss of context 489adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * - eliding noop statechange loops? (except line stipple count) 490adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 491b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ctx; 492b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom set; 493b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vte; 494b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom lin; 495b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msk; 496b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpt; 497b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vap; 498b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vtx; 499b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tcl; 500b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msl; 501b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tcg; 502b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom msc; 503b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom cst; 504b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tam; 505b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tf; 506b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom tex[6]; 507b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom cube[6]; 508b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom zbs; 509b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom mtl[2]; 510b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom mat[9]; 511b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 512b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ucp[6]; 513b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom pix[6]; /* pixshader stages */ 514b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom eye; /* eye pos */ 515b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom grd; /* guard band clipping */ 516b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom fog; 517b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom glt; 518b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom prf; 519b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom afs[2]; 520b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom pvs; 521b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpi[2]; 522b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom vpp[2]; 523b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom atf; 524b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom spr; 525b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_state_atom ptp; 5266f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt 5276f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt int max_state_size; /* Number of bytes necessary for a full state emit. */ 5280c8f8d3dc9d60ed34eeca7f3606651420a81753cEric Anholt GLboolean is_dirty, all_dirty; 529adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 530adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 531adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_state { 532adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Derived state for internal purposes: 533adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 534692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_colorbuffer_state color; 535692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_depthbuffer_state depth; 536692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_scissor_state scissor; 537692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_stencilbuffer_state stencil; 538692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_stipple_state stipple; 539adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_texture_state texture; 54036603539ccdb1c507724d8a1c314e6c9cc9863d9Roland Scheidegger GLuint envneeded; 541adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 542adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 543bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl#define GET_START(rvb) (rmesa->r200Screen->gart_buffer_offset + \ 544adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell (rvb)->address - rmesa->dma.buf0_address + \ 545adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell (rvb)->start) 546adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 5478a6182105772280e2727de4a00809c8fb7b13c87Roland Scheidegger#define R200_CMD_BUF_SZ (16*1024) 548adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 549adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_store { 550adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint statenr; 551adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint primnr; 552adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell char cmd_buf[R200_CMD_BUF_SZ]; 553adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell int cmd_used; 554adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell int elts_start; 555adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 556adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 557adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 558adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* r200_tcl.c 559adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 560adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_tcl_info { 561adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint hw_primitive; 562adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 563029d18cd3d79ff956c50b3486078d968d15bf0fbRoland Scheidegger/* hw can handle 12 components max */ 564692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma_region *aos_components[12]; 565adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint nr_aos_components; 566adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 567adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint *Elts; 568adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 569692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma_region indexed_verts; 570692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma_region vertex_data[15]; 571adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 572adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 573adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 574adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* r200_swtcl.c 575adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 576adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_swtcl_info { 577adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint RenderIndex; 578e946688edac5cdf153652defae3ef732a3487416Ian Romanick 579e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 580e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is 581e946688edac5cdf153652defae3ef732a3487416Ian Romanick * installed in the Mesa state vector. 582e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 583adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint vertex_size; 584e946688edac5cdf153652defae3ef732a3487416Ian Romanick 585e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 586e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Attributes instructing the Mesa TCL pipeline where / how to put vertex 587e946688edac5cdf153652defae3ef732a3487416Ian Romanick * data in the hardware buffer. 588e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 589e946688edac5cdf153652defae3ef732a3487416Ian Romanick struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 590e946688edac5cdf153652defae3ef732a3487416Ian Romanick 591e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 592e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Number of elements of \c ::vertex_attrs that are actually used. 593e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 594e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint vertex_attr_count; 595e946688edac5cdf153652defae3ef732a3487416Ian Romanick 596e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 597e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Cached pointer to the buffer where Mesa will store vertex data. 598e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 5995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLubyte *verts; 600adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 601adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Fallback rasterization functions 602adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 603adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell r200_point_func draw_point; 604adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell r200_line_func draw_line; 605adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell r200_tri_func draw_tri; 606adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 607adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint hw_primitive; 608adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLenum render_primitive; 609adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint numverts; 610adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 611e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 612e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Offset of the 4UB color data within a hardware (swtcl) vertex. 613e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 614e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint coloroffset; 615e946688edac5cdf153652defae3ef732a3487416Ian Romanick 616e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 617e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 618e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 619e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLuint specoffset; 620e946688edac5cdf153652defae3ef732a3487416Ian Romanick 621e946688edac5cdf153652defae3ef732a3487416Ian Romanick /** 622e946688edac5cdf153652defae3ef732a3487416Ian Romanick * Should Mesa project vertex data or will the hardware do it? 623e946688edac5cdf153652defae3ef732a3487416Ian Romanick */ 624e946688edac5cdf153652defae3ef732a3487416Ian Romanick GLboolean needproj; 625e946688edac5cdf153652defae3ef732a3487416Ian Romanick 626692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma_region indexed_verts; 627adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 628adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 629adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 630adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 631adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 63248ccaf200940613032dfaaafe71382947f398004Roland Scheidegger /* A maximum total of 29 elements per vertex: 3 floats for position, 3 633adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * floats for normal, 4 floats for color, 4 bytes for secondary color, 63448ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * 3 floats for each texture unit (18 floats total). 635adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * 63648ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * we maybe need add. 4 to prevent segfault if someone specifies 63748ccaf200940613032dfaaafe71382947f398004Roland Scheidegger * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 638adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * 639adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * The position data is never actually stored here, so 3 elements could be 640adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * trimmed out of the buffer. 641adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 64248ccaf200940613032dfaaafe71382947f398004Roland Scheidegger 64348ccaf200940613032dfaaafe71382947f398004Roland Scheidegger#define R200_MAX_VERTEX_SIZE ((3*6)+11) 64448ccaf200940613032dfaaafe71382947f398004Roland Scheidegger 645adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 646adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellstruct r200_context { 647adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLcontext *glCtx; /* Mesa context */ 648adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 649adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Driver and hardware state management 650adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 651adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_hw_state hw; 652adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_state state; 65398c791b543c4ba86b8bb54488bd872b33b10b1aaRoland Scheidegger struct r200_vertex_program *curr_vp_hw; 654adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 655adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Texture object bookkeeping 656adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 657adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell unsigned nr_heaps; 6583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 659adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell driTextureObject swapped; 660d907a75498360fb96ec2314bb0abb105be74d500Alan Hourihane int texture_depth; 661d3fd7ba8af15bead2f770d68a893449adeb11397Brian Paul float initialMaxAnisotropy; 662adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 663adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Rasterization and vertex state: 664adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 665adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TclFallback; 666adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint Fallback; 667adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint NewGLState; 668bb38cadb1c5f2dc13096a091bdaf61dc3e3cfa4dMichal Krol DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ 669adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 670adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Vertex buffers 671adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 672692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_ioctl ioctl; 673692ca82116485a9c6191e5265c5b369d5b4f82f3Dave Airlie struct radeon_dma dma; 674adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_store store; 6757a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt /* A full state emit as of the first state emit in the main store, in case 6767a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt * the context is lost. 6777a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt */ 6787a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt struct r200_store backup_store; 679adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 680adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Page flipping 681adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 682adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint doPageFlip; 683adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 684adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Busy waiting 685adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 686adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint do_usleeps; 687adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint do_irqs; 688adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint irqsEmitted; 689ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_irq_wait_t iw; 690adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 691adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Clientdata textures; 692adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 693bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl GLuint prefer_gart_client_texturing; 694adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 695adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Drawable, cliprect and scissor information 696adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 697adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint numClipRects; /* Cliprects for the draw buffer */ 698ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *pClipRects; 699adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell unsigned int lastStamp; 700adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean lost_context; 7017a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt GLboolean save_on_next_emit; 7023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt radeonScreenPtr r200Screen; /* Screen private DRI data */ 703ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_sarea_t *sarea; /* Private SAREA data */ 704adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 705adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* TCL stuff 706adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 707adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 708adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 709adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 71024a44d74b6e9880dfc019bd1cfa9ce0351377c85Roland Scheidegger GLuint TexMatEnabled; 711adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexMatCompSel; 712adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexGenEnabled; 713adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint TexGenCompSel; 714adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLmatrix tmpmat; 715adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 71638fdb47d26055e19d50cd407266b56ed4317ae0aJesse Barnes /* buffer swap 717adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 718afa446db83ecf5dcb38ce46648fb12911628de32Ian Romanick int64_t swap_ust; 719afa446db83ecf5dcb38ce46648fb12911628de32Ian Romanick int64_t swap_missed_ust; 720adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 721adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint swap_count; 722adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell GLuint swap_missed_count; 723adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 724adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 725adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* r200_tcl.c 726adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 727adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_tcl_info tcl; 728adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 729adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* r200_swtcl.c 730adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 731adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell struct r200_swtcl_info swtcl; 732adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 733adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell /* Mirrors of some DRI state 734adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 735b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie struct radeon_dri_mirror dri; 736bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 737bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl /* Configuration cache 738bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl */ 739bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl driOptionCache optionCache; 740b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger 741b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger GLboolean using_hyperz; 7424837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger GLboolean texmicrotile; 743f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger 744f20917de5bd2b1fc152e74304d3649a1f6042422Roland Scheidegger struct ati_fragment_shader *afs_loaded; 745adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell}; 746adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 747adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 748adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 749adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 750adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); 751adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern GLboolean r200CreateContext( const __GLcontextModes *glVisual, 752adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell __DRIcontextPrivate *driContextPriv, 753adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell void *sharedContextPrivate); 754adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern void r200SwapBuffers( __DRIdrawablePrivate *dPriv ); 755f2ad1b60c0da11283b399008f491792790cea294Brian Paulextern void r200CopySubBuffer( __DRIdrawablePrivate * dPriv, 756f2ad1b60c0da11283b399008f491792790cea294Brian Paul int x, int y, int w, int h ); 757adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, 758adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell __DRIdrawablePrivate *driDrawPriv, 759adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell __DRIdrawablePrivate *driReadPriv ); 760adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); 761adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 762adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell/* ================================================================ 763adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell * Debugging: 764adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell */ 765adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define DO_DEBUG 1 766adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 767adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#if DO_DEBUG 768adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwellextern int R200_DEBUG; 769adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#else 770adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#define R200_DEBUG 0 771adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#endif 772adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 773b6e486906968d82c7b8a869d7ab51697a7cce80cDave Airlie 774adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell 775adbec39bbf671ad80f6c557801e274cac0d305faKeith Whitwell#endif /* __R200_CONTEXT_H__ */ 776