r200_context.h revision 23295cf8e84495af86f62395d32b3116261927e8
1/* 2Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4The Weather Channel (TM) funded Tungsten Graphics to develop the 5initial release of the Radeon 8500 driver under the XFree86 license. 6This notice must be preserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35#ifndef __R200_CONTEXT_H__ 36#define __R200_CONTEXT_H__ 37 38#include "tnl/t_vertex.h" 39#include "drm.h" 40#include "radeon_drm.h" 41#include "dri_util.h" 42#include "texmem.h" 43 44#include "main/macros.h" 45#include "main/mtypes.h" 46#include "main/colormac.h" 47#include "r200_reg.h" 48#include "r200_vertprog.h" 49 50#define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */ 51 52#ifndef R200_EMIT_VAP_PVS_CNTL 53#error This driver requires a newer libdrm to compile 54#endif 55 56#include "radeon_screen.h" 57#include "common_context.h" 58#include "common_misc.h" 59 60struct r200_context; 61typedef struct r200_context r200ContextRec; 62typedef struct r200_context *r200ContextPtr; 63 64#include "r200_lock.h" 65 66#include "main/mm.h" 67 68struct r200_vertex_program { 69 struct gl_vertex_program mesa_program; /* Must be first */ 70 int translated; 71 /* need excess instr: 1 for late loop checking, 2 for 72 additional instr due to instr/attr, 3 for fog */ 73 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 74 int pos_end; 75 int inputs[VERT_ATTRIB_MAX]; 76 GLubyte inputmap_rev[16]; 77 int native; 78 int fogpidx; 79 int fogmode; 80}; 81 82#define R200_TEX_ALL 0x3f 83 84 85struct r200_texture_env_state { 86 radeonTexObjPtr texobj; 87 GLuint outputreg; 88 GLuint unitneeded; 89}; 90 91#define R200_MAX_TEXTURE_UNITS 6 92 93struct r200_texture_state { 94 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 95}; 96 97 98/* Trying to keep these relatively short as the variables are becoming 99 * extravagently long. Drop the driver name prefix off the front of 100 * everything - I think we know which driver we're in by now, and keep the 101 * prefix to 3 letters unless absolutely impossible. 102 */ 103 104#define CTX_CMD_0 0 105#define CTX_PP_MISC 1 106#define CTX_PP_FOG_COLOR 2 107#define CTX_RE_SOLID_COLOR 3 108#define CTX_RB3D_BLENDCNTL 4 109#define CTX_RB3D_DEPTHOFFSET 5 110#define CTX_RB3D_DEPTHPITCH 6 111#define CTX_RB3D_ZSTENCILCNTL 7 112#define CTX_CMD_1 8 113#define CTX_PP_CNTL 9 114#define CTX_RB3D_CNTL 10 115#define CTX_RB3D_COLOROFFSET 11 116#define CTX_CMD_2 12 /* why */ 117#define CTX_RB3D_COLORPITCH 13 /* why */ 118#define CTX_STATE_SIZE_OLDDRM 14 119#define CTX_CMD_3 14 120#define CTX_RB3D_BLENDCOLOR 15 121#define CTX_RB3D_ABLENDCNTL 16 122#define CTX_RB3D_CBLENDCNTL 17 123#define CTX_STATE_SIZE_NEWDRM 18 124 125#define SET_CMD_0 0 126#define SET_SE_CNTL 1 127#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 128#define SET_STATE_SIZE 3 129 130#define VTE_CMD_0 0 131#define VTE_SE_VTE_CNTL 1 132#define VTE_STATE_SIZE 2 133 134#define LIN_CMD_0 0 135#define LIN_RE_LINE_PATTERN 1 136#define LIN_RE_LINE_STATE 2 137#define LIN_CMD_1 3 138#define LIN_SE_LINE_WIDTH 4 139#define LIN_STATE_SIZE 5 140 141#define MSK_CMD_0 0 142#define MSK_RB3D_STENCILREFMASK 1 143#define MSK_RB3D_ROPCNTL 2 144#define MSK_RB3D_PLANEMASK 3 145#define MSK_STATE_SIZE 4 146 147#define VPT_CMD_0 0 148#define VPT_SE_VPORT_XSCALE 1 149#define VPT_SE_VPORT_XOFFSET 2 150#define VPT_SE_VPORT_YSCALE 3 151#define VPT_SE_VPORT_YOFFSET 4 152#define VPT_SE_VPORT_ZSCALE 5 153#define VPT_SE_VPORT_ZOFFSET 6 154#define VPT_STATE_SIZE 7 155 156#define ZBS_CMD_0 0 157#define ZBS_SE_ZBIAS_FACTOR 1 158#define ZBS_SE_ZBIAS_CONSTANT 2 159#define ZBS_STATE_SIZE 3 160 161#define MSC_CMD_0 0 162#define MSC_RE_MISC 1 163#define MSC_STATE_SIZE 2 164 165#define TAM_CMD_0 0 166#define TAM_DEBUG3 1 167#define TAM_STATE_SIZE 2 168 169#define TEX_CMD_0 0 170#define TEX_PP_TXFILTER 1 /*2c00*/ 171#define TEX_PP_TXFORMAT 2 /*2c04*/ 172#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 173#define TEX_PP_TXSIZE 4 /*2c0c*/ 174#define TEX_PP_TXPITCH 5 /*2c10*/ 175#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 176#define TEX_CMD_1_OLDDRM 7 177#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 178#define TEX_STATE_SIZE_OLDDRM 9 179#define TEX_PP_CUBIC_FACES 7 180#define TEX_PP_TXMULTI_CTL 8 181#define TEX_CMD_1_NEWDRM 9 182#define TEX_PP_TXOFFSET_NEWDRM 10 183#define TEX_STATE_SIZE_NEWDRM 11 184 185#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 186#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 187#define CUBE_CMD_1 2 /* 5 registers follow */ 188#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 189#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 190#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 191#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 192#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 193#define CUBE_STATE_SIZE 8 194 195#define PIX_CMD_0 0 196#define PIX_PP_TXCBLEND 1 197#define PIX_PP_TXCBLEND2 2 198#define PIX_PP_TXABLEND 3 199#define PIX_PP_TXABLEND2 4 200#define PIX_STATE_SIZE 5 201 202#define TF_CMD_0 0 203#define TF_TFACTOR_0 1 204#define TF_TFACTOR_1 2 205#define TF_TFACTOR_2 3 206#define TF_TFACTOR_3 4 207#define TF_TFACTOR_4 5 208#define TF_TFACTOR_5 6 209#define TF_STATE_SIZE 7 210 211#define ATF_CMD_0 0 212#define ATF_TFACTOR_0 1 213#define ATF_TFACTOR_1 2 214#define ATF_TFACTOR_2 3 215#define ATF_TFACTOR_3 4 216#define ATF_TFACTOR_4 5 217#define ATF_TFACTOR_5 6 218#define ATF_TFACTOR_6 7 219#define ATF_TFACTOR_7 8 220#define ATF_STATE_SIZE 9 221 222/* ATI_FRAGMENT_SHADER */ 223#define AFS_CMD_0 0 224#define AFS_IC0 1 /* 2f00 */ 225#define AFS_IC1 2 /* 2f04 */ 226#define AFS_IA0 3 /* 2f08 */ 227#define AFS_IA1 4 /* 2f0c */ 228#define AFS_STATE_SIZE 33 229 230#define PVS_CMD_0 0 231#define PVS_CNTL_1 1 232#define PVS_CNTL_2 2 233#define PVS_STATE_SIZE 3 234 235/* those are quite big... */ 236#define VPI_CMD_0 0 237#define VPI_OPDST_0 1 238#define VPI_SRC0_0 2 239#define VPI_SRC1_0 3 240#define VPI_SRC2_0 4 241#define VPI_OPDST_63 253 242#define VPI_SRC0_63 254 243#define VPI_SRC1_63 255 244#define VPI_SRC2_63 256 245#define VPI_STATE_SIZE 257 246 247#define VPP_CMD_0 0 248#define VPP_PARAM0_0 1 249#define VPP_PARAM1_0 2 250#define VPP_PARAM2_0 3 251#define VPP_PARAM3_0 4 252#define VPP_PARAM0_95 381 253#define VPP_PARAM1_95 382 254#define VPP_PARAM2_95 383 255#define VPP_PARAM3_95 384 256#define VPP_STATE_SIZE 385 257 258#define TCL_CMD_0 0 259#define TCL_LIGHT_MODEL_CTL_0 1 260#define TCL_LIGHT_MODEL_CTL_1 2 261#define TCL_PER_LIGHT_CTL_0 3 262#define TCL_PER_LIGHT_CTL_1 4 263#define TCL_PER_LIGHT_CTL_2 5 264#define TCL_PER_LIGHT_CTL_3 6 265#define TCL_CMD_1 7 266#define TCL_UCP_VERT_BLEND_CTL 8 267#define TCL_STATE_SIZE 9 268 269#define MSL_CMD_0 0 270#define MSL_MATRIX_SELECT_0 1 271#define MSL_MATRIX_SELECT_1 2 272#define MSL_MATRIX_SELECT_2 3 273#define MSL_MATRIX_SELECT_3 4 274#define MSL_MATRIX_SELECT_4 5 275#define MSL_STATE_SIZE 6 276 277#define TCG_CMD_0 0 278#define TCG_TEX_PROC_CTL_2 1 279#define TCG_TEX_PROC_CTL_3 2 280#define TCG_TEX_PROC_CTL_0 3 281#define TCG_TEX_PROC_CTL_1 4 282#define TCG_TEX_CYL_WRAP_CTL 5 283#define TCG_STATE_SIZE 6 284 285#define MTL_CMD_0 0 286#define MTL_EMMISSIVE_RED 1 287#define MTL_EMMISSIVE_GREEN 2 288#define MTL_EMMISSIVE_BLUE 3 289#define MTL_EMMISSIVE_ALPHA 4 290#define MTL_AMBIENT_RED 5 291#define MTL_AMBIENT_GREEN 6 292#define MTL_AMBIENT_BLUE 7 293#define MTL_AMBIENT_ALPHA 8 294#define MTL_DIFFUSE_RED 9 295#define MTL_DIFFUSE_GREEN 10 296#define MTL_DIFFUSE_BLUE 11 297#define MTL_DIFFUSE_ALPHA 12 298#define MTL_SPECULAR_RED 13 299#define MTL_SPECULAR_GREEN 14 300#define MTL_SPECULAR_BLUE 15 301#define MTL_SPECULAR_ALPHA 16 302#define MTL_CMD_1 17 303#define MTL_SHININESS 18 304#define MTL_STATE_SIZE 19 305 306#define VAP_CMD_0 0 307#define VAP_SE_VAP_CNTL 1 308#define VAP_STATE_SIZE 2 309 310/* Replaces a lot of packet info from radeon 311 */ 312#define VTX_CMD_0 0 313#define VTX_VTXFMT_0 1 314#define VTX_VTXFMT_1 2 315#define VTX_TCL_OUTPUT_VTXFMT_0 3 316#define VTX_TCL_OUTPUT_VTXFMT_1 4 317#define VTX_CMD_1 5 318#define VTX_TCL_OUTPUT_COMPSEL 6 319#define VTX_CMD_2 7 320#define VTX_STATE_CNTL 8 321#define VTX_STATE_SIZE 9 322 323/* SPR - point sprite state 324 */ 325#define SPR_CMD_0 0 326#define SPR_POINT_SPRITE_CNTL 1 327#define SPR_STATE_SIZE 2 328 329#define PTP_CMD_0 0 330#define PTP_VPORT_SCALE_0 1 331#define PTP_VPORT_SCALE_1 2 332#define PTP_VPORT_SCALE_PTSIZE 3 333#define PTP_VPORT_SCALE_3 4 334#define PTP_CMD_1 5 335#define PTP_ATT_CONST_QUAD 6 336#define PTP_ATT_CONST_LIN 7 337#define PTP_ATT_CONST_CON 8 338#define PTP_ATT_CONST_3 9 339#define PTP_EYE_X 10 340#define PTP_EYE_Y 11 341#define PTP_EYE_Z 12 342#define PTP_EYE_3 13 343#define PTP_CLAMP_MIN 14 344#define PTP_CLAMP_MAX 15 345#define PTP_CLAMP_2 16 346#define PTP_CLAMP_3 17 347#define PTP_STATE_SIZE 18 348 349#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 350 R200_VTX_COLOR_MASK) 351 352/** 353 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 354 * how many components are in texture coordinate \c n. 355 */ 356#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 357 358#define MAT_CMD_0 0 359#define MAT_ELT_0 1 360#define MAT_STATE_SIZE 17 361 362#define GRD_CMD_0 0 363#define GRD_VERT_GUARD_CLIP_ADJ 1 364#define GRD_VERT_GUARD_DISCARD_ADJ 2 365#define GRD_HORZ_GUARD_CLIP_ADJ 3 366#define GRD_HORZ_GUARD_DISCARD_ADJ 4 367#define GRD_STATE_SIZE 5 368 369/* position changes frequently when lighting in modelpos - separate 370 * out to new state item? 371 */ 372#define LIT_CMD_0 0 373#define LIT_AMBIENT_RED 1 374#define LIT_AMBIENT_GREEN 2 375#define LIT_AMBIENT_BLUE 3 376#define LIT_AMBIENT_ALPHA 4 377#define LIT_DIFFUSE_RED 5 378#define LIT_DIFFUSE_GREEN 6 379#define LIT_DIFFUSE_BLUE 7 380#define LIT_DIFFUSE_ALPHA 8 381#define LIT_SPECULAR_RED 9 382#define LIT_SPECULAR_GREEN 10 383#define LIT_SPECULAR_BLUE 11 384#define LIT_SPECULAR_ALPHA 12 385#define LIT_POSITION_X 13 386#define LIT_POSITION_Y 14 387#define LIT_POSITION_Z 15 388#define LIT_POSITION_W 16 389#define LIT_DIRECTION_X 17 390#define LIT_DIRECTION_Y 18 391#define LIT_DIRECTION_Z 19 392#define LIT_DIRECTION_W 20 393#define LIT_ATTEN_QUADRATIC 21 394#define LIT_ATTEN_LINEAR 22 395#define LIT_ATTEN_CONST 23 396#define LIT_ATTEN_XXX 24 397#define LIT_CMD_1 25 398#define LIT_SPOT_DCD 26 399#define LIT_SPOT_DCM 27 400#define LIT_SPOT_EXPONENT 28 401#define LIT_SPOT_CUTOFF 29 402#define LIT_SPECULAR_THRESH 30 403#define LIT_RANGE_CUTOFF 31 /* ? */ 404#define LIT_ATTEN_CONST_INV 32 405#define LIT_STATE_SIZE 33 406 407/* Fog 408 */ 409#define FOG_CMD_0 0 410#define FOG_R 1 411#define FOG_C 2 412#define FOG_D 3 413#define FOG_PAD 4 414#define FOG_STATE_SIZE 5 415 416/* UCP 417 */ 418#define UCP_CMD_0 0 419#define UCP_X 1 420#define UCP_Y 2 421#define UCP_Z 3 422#define UCP_W 4 423#define UCP_STATE_SIZE 5 424 425/* GLT - Global ambient 426 */ 427#define GLT_CMD_0 0 428#define GLT_RED 1 429#define GLT_GREEN 2 430#define GLT_BLUE 3 431#define GLT_ALPHA 4 432#define GLT_STATE_SIZE 5 433 434/* EYE 435 */ 436#define EYE_CMD_0 0 437#define EYE_X 1 438#define EYE_Y 2 439#define EYE_Z 3 440#define EYE_RESCALE_FACTOR 4 441#define EYE_STATE_SIZE 5 442 443/* CST - constant state 444 */ 445#define CST_CMD_0 0 446#define CST_PP_CNTL_X 1 447#define CST_CMD_1 2 448#define CST_RB3D_DEPTHXY_OFFSET 3 449#define CST_CMD_2 4 450#define CST_RE_AUX_SCISSOR_CNTL 5 451#define CST_CMD_3 6 452#define CST_RE_SCISSOR_TL_0 7 453#define CST_RE_SCISSOR_BR_0 8 454#define CST_CMD_4 9 455#define CST_SE_VAP_CNTL_STATUS 10 456#define CST_CMD_5 11 457#define CST_RE_POINTSIZE 12 458#define CST_CMD_6 13 459#define CST_SE_TCL_INPUT_VTX_0 14 460#define CST_SE_TCL_INPUT_VTX_1 15 461#define CST_SE_TCL_INPUT_VTX_2 16 462#define CST_SE_TCL_INPUT_VTX_3 17 463#define CST_STATE_SIZE 18 464 465#define PRF_CMD_0 0 466#define PRF_PP_TRI_PERF 1 467#define PRF_PP_PERF_CNTL 2 468#define PRF_STATE_SIZE 3 469 470 471struct r200_hw_state { 472 /* Head of the linked list of state atoms. */ 473 struct radeon_state_atom atomlist; 474 475 /* Hardware state, stored as cmdbuf commands: 476 * -- Need to doublebuffer for 477 * - reviving state after loss of context 478 * - eliding noop statechange loops? (except line stipple count) 479 */ 480 struct radeon_state_atom ctx; 481 struct radeon_state_atom set; 482 struct radeon_state_atom vte; 483 struct radeon_state_atom lin; 484 struct radeon_state_atom msk; 485 struct radeon_state_atom vpt; 486 struct radeon_state_atom vap; 487 struct radeon_state_atom vtx; 488 struct radeon_state_atom tcl; 489 struct radeon_state_atom msl; 490 struct radeon_state_atom tcg; 491 struct radeon_state_atom msc; 492 struct radeon_state_atom cst; 493 struct radeon_state_atom tam; 494 struct radeon_state_atom tf; 495 struct radeon_state_atom tex[6]; 496 struct radeon_state_atom cube[6]; 497 struct radeon_state_atom zbs; 498 struct radeon_state_atom mtl[2]; 499 struct radeon_state_atom mat[9]; 500 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 501 struct radeon_state_atom ucp[6]; 502 struct radeon_state_atom pix[6]; /* pixshader stages */ 503 struct radeon_state_atom eye; /* eye pos */ 504 struct radeon_state_atom grd; /* guard band clipping */ 505 struct radeon_state_atom fog; 506 struct radeon_state_atom glt; 507 struct radeon_state_atom prf; 508 struct radeon_state_atom afs[2]; 509 struct radeon_state_atom pvs; 510 struct radeon_state_atom vpi[2]; 511 struct radeon_state_atom vpp[2]; 512 struct radeon_state_atom atf; 513 struct radeon_state_atom spr; 514 struct radeon_state_atom ptp; 515 516 int max_state_size; /* Number of bytes necessary for a full state emit. */ 517 GLboolean is_dirty, all_dirty; 518}; 519 520struct r200_state { 521 /* Derived state for internal purposes: 522 */ 523 struct radeon_stipple_state stipple; 524 struct r200_texture_state texture; 525 GLuint envneeded; 526}; 527 528#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ 529 (rvb)->address - rmesa->dma.buf0_address + \ 530 (rvb)->start) 531 532#define R200_CMD_BUF_SZ (16*1024) 533 534 535/* r200_tcl.c 536 */ 537struct r200_tcl_info { 538 GLuint hw_primitive; 539 540/* hw can handle 12 components max */ 541 struct radeon_dma_region *aos_components[12]; 542 GLuint nr_aos_components; 543 544 GLuint *Elts; 545 546 struct radeon_dma_region indexed_verts; 547 struct radeon_dma_region vertex_data[15]; 548}; 549 550 551/* r200_swtcl.c 552 */ 553struct r200_swtcl_info { 554 GLuint RenderIndex; 555 556 /** 557 * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is 558 * installed in the Mesa state vector. 559 */ 560 GLuint vertex_size; 561 562 /** 563 * Attributes instructing the Mesa TCL pipeline where / how to put vertex 564 * data in the hardware buffer. 565 */ 566 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 567 568 /** 569 * Number of elements of \c ::vertex_attrs that are actually used. 570 */ 571 GLuint vertex_attr_count; 572 573 /** 574 * Cached pointer to the buffer where Mesa will store vertex data. 575 */ 576 GLubyte *verts; 577 578 /* Fallback rasterization functions 579 */ 580 radeon_point_func draw_point; 581 radeon_line_func draw_line; 582 radeon_tri_func draw_tri; 583 584 GLuint hw_primitive; 585 GLenum render_primitive; 586 GLuint numverts; 587 588 /** 589 * Offset of the 4UB color data within a hardware (swtcl) vertex. 590 */ 591 GLuint coloroffset; 592 593 /** 594 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 595 */ 596 GLuint specoffset; 597 598 /** 599 * Should Mesa project vertex data or will the hardware do it? 600 */ 601 GLboolean needproj; 602 603 struct radeon_dma_region indexed_verts; 604}; 605 606 607 608 609 /* A maximum total of 29 elements per vertex: 3 floats for position, 3 610 * floats for normal, 4 floats for color, 4 bytes for secondary color, 611 * 3 floats for each texture unit (18 floats total). 612 * 613 * we maybe need add. 4 to prevent segfault if someone specifies 614 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 615 * 616 * The position data is never actually stored here, so 3 elements could be 617 * trimmed out of the buffer. 618 */ 619 620#define R200_MAX_VERTEX_SIZE ((3*6)+11) 621 622 623struct r200_context { 624 struct radeon_context radeon; 625 626 /* Driver and hardware state management 627 */ 628 struct r200_hw_state hw; 629 struct r200_state state; 630 struct r200_vertex_program *curr_vp_hw; 631 632 /* Vertex buffers 633 */ 634 struct radeon_ioctl ioctl; 635 struct radeon_dma dma; 636 struct radeon_store store; 637 /* A full state emit as of the first state emit in the main store, in case 638 * the context is lost. 639 */ 640 struct radeon_store backup_store; 641 642 /* Clientdata textures; 643 */ 644 GLuint prefer_gart_client_texturing; 645 646 GLboolean save_on_next_emit; 647 648 /* TCL stuff 649 */ 650 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 651 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 652 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 653 GLuint TexMatEnabled; 654 GLuint TexMatCompSel; 655 GLuint TexGenEnabled; 656 GLuint TexGenCompSel; 657 GLmatrix tmpmat; 658 659 /* r200_tcl.c 660 */ 661 struct r200_tcl_info tcl; 662 663 /* r200_swtcl.c 664 */ 665 struct r200_swtcl_info swtcl; 666 667 GLboolean using_hyperz; 668 GLboolean texmicrotile; 669 670 struct ati_fragment_shader *afs_loaded; 671}; 672 673#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 674 675 676extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); 677extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, 678 __DRIcontextPrivate *driContextPriv, 679 void *sharedContextPrivate); 680extern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, 681 __DRIdrawablePrivate *driDrawPriv, 682 __DRIdrawablePrivate *driReadPriv ); 683extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); 684 685/* ================================================================ 686 * Debugging: 687 */ 688 689#define R200_DEBUG RADEON_DEBUG 690 691 692 693#endif /* __R200_CONTEXT_H__ */ 694