r200_context.h revision 53b382637ca5462b15a430abbfc070e799d70b97
1/* 2Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4The Weather Channel (TM) funded Tungsten Graphics to develop the 5initial release of the Radeon 8500 driver under the XFree86 license. 6This notice must be preserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35#ifndef __R200_CONTEXT_H__ 36#define __R200_CONTEXT_H__ 37 38#include "tnl/t_vertex.h" 39#include "drm.h" 40#include "radeon_drm.h" 41#include "dri_util.h" 42#include "texmem.h" 43 44#include "main/macros.h" 45#include "main/mtypes.h" 46#include "main/colormac.h" 47#include "r200_reg.h" 48#include "r200_vertprog.h" 49 50#ifndef R200_EMIT_VAP_PVS_CNTL 51#error This driver requires a newer libdrm to compile 52#endif 53 54#include "radeon_screen.h" 55#include "radeon_common.h" 56 57struct r200_context; 58typedef struct r200_context r200ContextRec; 59typedef struct r200_context *r200ContextPtr; 60 61#include "main/mm.h" 62 63struct r200_vertex_program { 64 struct gl_vertex_program mesa_program; /* Must be first */ 65 int translated; 66 /* need excess instr: 1 for late loop checking, 2 for 67 additional instr due to instr/attr, 3 for fog */ 68 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 69 int pos_end; 70 int inputs[VERT_ATTRIB_MAX]; 71 GLubyte inputmap_rev[16]; 72 int native; 73 int fogpidx; 74 int fogmode; 75}; 76 77#define R200_TEX_ALL 0x3f 78 79 80struct r200_texture_env_state { 81 radeonTexObjPtr texobj; 82 GLuint outputreg; 83 GLuint unitneeded; 84}; 85 86#define R200_MAX_TEXTURE_UNITS 6 87 88struct r200_texture_state { 89 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 90}; 91 92 93/* Trying to keep these relatively short as the variables are becoming 94 * extravagently long. Drop the driver name prefix off the front of 95 * everything - I think we know which driver we're in by now, and keep the 96 * prefix to 3 letters unless absolutely impossible. 97 */ 98 99#define CTX_CMD_0 0 100#define CTX_PP_MISC 1 101#define CTX_PP_FOG_COLOR 2 102#define CTX_RE_SOLID_COLOR 3 103#define CTX_RB3D_BLENDCNTL 4 104#define CTX_RB3D_DEPTHOFFSET 5 105#define CTX_RB3D_DEPTHPITCH 6 106#define CTX_RB3D_ZSTENCILCNTL 7 107#define CTX_CMD_1 8 108#define CTX_PP_CNTL 9 109#define CTX_RB3D_CNTL 10 110#define CTX_RB3D_COLOROFFSET 11 111#define CTX_CMD_2 12 /* why */ 112#define CTX_RB3D_COLORPITCH 13 /* why */ 113#define CTX_STATE_SIZE_OLDDRM 14 114#define CTX_CMD_3 14 115#define CTX_RB3D_BLENDCOLOR 15 116#define CTX_RB3D_ABLENDCNTL 16 117#define CTX_RB3D_CBLENDCNTL 17 118#define CTX_STATE_SIZE_NEWDRM 18 119 120#define SET_CMD_0 0 121#define SET_SE_CNTL 1 122#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 123#define SET_STATE_SIZE 3 124 125#define VTE_CMD_0 0 126#define VTE_SE_VTE_CNTL 1 127#define VTE_STATE_SIZE 2 128 129#define LIN_CMD_0 0 130#define LIN_RE_LINE_PATTERN 1 131#define LIN_RE_LINE_STATE 2 132#define LIN_CMD_1 3 133#define LIN_SE_LINE_WIDTH 4 134#define LIN_STATE_SIZE 5 135 136#define MSK_CMD_0 0 137#define MSK_RB3D_STENCILREFMASK 1 138#define MSK_RB3D_ROPCNTL 2 139#define MSK_RB3D_PLANEMASK 3 140#define MSK_STATE_SIZE 4 141 142#define VPT_CMD_0 0 143#define VPT_SE_VPORT_XSCALE 1 144#define VPT_SE_VPORT_XOFFSET 2 145#define VPT_SE_VPORT_YSCALE 3 146#define VPT_SE_VPORT_YOFFSET 4 147#define VPT_SE_VPORT_ZSCALE 5 148#define VPT_SE_VPORT_ZOFFSET 6 149#define VPT_STATE_SIZE 7 150 151#define ZBS_CMD_0 0 152#define ZBS_SE_ZBIAS_FACTOR 1 153#define ZBS_SE_ZBIAS_CONSTANT 2 154#define ZBS_STATE_SIZE 3 155 156#define MSC_CMD_0 0 157#define MSC_RE_MISC 1 158#define MSC_STATE_SIZE 2 159 160#define TAM_CMD_0 0 161#define TAM_DEBUG3 1 162#define TAM_STATE_SIZE 2 163 164#define TEX_CMD_0 0 165#define TEX_PP_TXFILTER 1 /*2c00*/ 166#define TEX_PP_TXFORMAT 2 /*2c04*/ 167#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 168#define TEX_PP_TXSIZE 4 /*2c0c*/ 169#define TEX_PP_TXPITCH 5 /*2c10*/ 170#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 171#define TEX_CMD_1_OLDDRM 7 172#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 173#define TEX_STATE_SIZE_OLDDRM 9 174#define TEX_PP_CUBIC_FACES 7 175#define TEX_PP_TXMULTI_CTL 8 176#define TEX_CMD_1_NEWDRM 9 177#define TEX_PP_TXOFFSET_NEWDRM 10 178#define TEX_STATE_SIZE_NEWDRM 11 179 180#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 181#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 182#define CUBE_CMD_1 2 /* 5 registers follow */ 183#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 184#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 185#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 186#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 187#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 188#define CUBE_STATE_SIZE 8 189 190#define PIX_CMD_0 0 191#define PIX_PP_TXCBLEND 1 192#define PIX_PP_TXCBLEND2 2 193#define PIX_PP_TXABLEND 3 194#define PIX_PP_TXABLEND2 4 195#define PIX_STATE_SIZE 5 196 197#define TF_CMD_0 0 198#define TF_TFACTOR_0 1 199#define TF_TFACTOR_1 2 200#define TF_TFACTOR_2 3 201#define TF_TFACTOR_3 4 202#define TF_TFACTOR_4 5 203#define TF_TFACTOR_5 6 204#define TF_STATE_SIZE 7 205 206#define ATF_CMD_0 0 207#define ATF_TFACTOR_0 1 208#define ATF_TFACTOR_1 2 209#define ATF_TFACTOR_2 3 210#define ATF_TFACTOR_3 4 211#define ATF_TFACTOR_4 5 212#define ATF_TFACTOR_5 6 213#define ATF_TFACTOR_6 7 214#define ATF_TFACTOR_7 8 215#define ATF_STATE_SIZE 9 216 217/* ATI_FRAGMENT_SHADER */ 218#define AFS_CMD_0 0 219#define AFS_IC0 1 /* 2f00 */ 220#define AFS_IC1 2 /* 2f04 */ 221#define AFS_IA0 3 /* 2f08 */ 222#define AFS_IA1 4 /* 2f0c */ 223#define AFS_STATE_SIZE 33 224 225#define PVS_CMD_0 0 226#define PVS_CNTL_1 1 227#define PVS_CNTL_2 2 228#define PVS_STATE_SIZE 3 229 230/* those are quite big... */ 231#define VPI_CMD_0 0 232#define VPI_OPDST_0 1 233#define VPI_SRC0_0 2 234#define VPI_SRC1_0 3 235#define VPI_SRC2_0 4 236#define VPI_OPDST_63 253 237#define VPI_SRC0_63 254 238#define VPI_SRC1_63 255 239#define VPI_SRC2_63 256 240#define VPI_STATE_SIZE 257 241 242#define VPP_CMD_0 0 243#define VPP_PARAM0_0 1 244#define VPP_PARAM1_0 2 245#define VPP_PARAM2_0 3 246#define VPP_PARAM3_0 4 247#define VPP_PARAM0_95 381 248#define VPP_PARAM1_95 382 249#define VPP_PARAM2_95 383 250#define VPP_PARAM3_95 384 251#define VPP_STATE_SIZE 385 252 253#define TCL_CMD_0 0 254#define TCL_LIGHT_MODEL_CTL_0 1 255#define TCL_LIGHT_MODEL_CTL_1 2 256#define TCL_PER_LIGHT_CTL_0 3 257#define TCL_PER_LIGHT_CTL_1 4 258#define TCL_PER_LIGHT_CTL_2 5 259#define TCL_PER_LIGHT_CTL_3 6 260#define TCL_CMD_1 7 261#define TCL_UCP_VERT_BLEND_CTL 8 262#define TCL_STATE_SIZE 9 263 264#define MSL_CMD_0 0 265#define MSL_MATRIX_SELECT_0 1 266#define MSL_MATRIX_SELECT_1 2 267#define MSL_MATRIX_SELECT_2 3 268#define MSL_MATRIX_SELECT_3 4 269#define MSL_MATRIX_SELECT_4 5 270#define MSL_STATE_SIZE 6 271 272#define TCG_CMD_0 0 273#define TCG_TEX_PROC_CTL_2 1 274#define TCG_TEX_PROC_CTL_3 2 275#define TCG_TEX_PROC_CTL_0 3 276#define TCG_TEX_PROC_CTL_1 4 277#define TCG_TEX_CYL_WRAP_CTL 5 278#define TCG_STATE_SIZE 6 279 280#define MTL_CMD_0 0 281#define MTL_EMMISSIVE_RED 1 282#define MTL_EMMISSIVE_GREEN 2 283#define MTL_EMMISSIVE_BLUE 3 284#define MTL_EMMISSIVE_ALPHA 4 285#define MTL_AMBIENT_RED 5 286#define MTL_AMBIENT_GREEN 6 287#define MTL_AMBIENT_BLUE 7 288#define MTL_AMBIENT_ALPHA 8 289#define MTL_DIFFUSE_RED 9 290#define MTL_DIFFUSE_GREEN 10 291#define MTL_DIFFUSE_BLUE 11 292#define MTL_DIFFUSE_ALPHA 12 293#define MTL_SPECULAR_RED 13 294#define MTL_SPECULAR_GREEN 14 295#define MTL_SPECULAR_BLUE 15 296#define MTL_SPECULAR_ALPHA 16 297#define MTL_CMD_1 17 298#define MTL_SHININESS 18 299#define MTL_STATE_SIZE 19 300 301#define VAP_CMD_0 0 302#define VAP_SE_VAP_CNTL 1 303#define VAP_STATE_SIZE 2 304 305/* Replaces a lot of packet info from radeon 306 */ 307#define VTX_CMD_0 0 308#define VTX_VTXFMT_0 1 309#define VTX_VTXFMT_1 2 310#define VTX_TCL_OUTPUT_VTXFMT_0 3 311#define VTX_TCL_OUTPUT_VTXFMT_1 4 312#define VTX_CMD_1 5 313#define VTX_TCL_OUTPUT_COMPSEL 6 314#define VTX_CMD_2 7 315#define VTX_STATE_CNTL 8 316#define VTX_STATE_SIZE 9 317 318/* SPR - point sprite state 319 */ 320#define SPR_CMD_0 0 321#define SPR_POINT_SPRITE_CNTL 1 322#define SPR_STATE_SIZE 2 323 324#define PTP_CMD_0 0 325#define PTP_VPORT_SCALE_0 1 326#define PTP_VPORT_SCALE_1 2 327#define PTP_VPORT_SCALE_PTSIZE 3 328#define PTP_VPORT_SCALE_3 4 329#define PTP_CMD_1 5 330#define PTP_ATT_CONST_QUAD 6 331#define PTP_ATT_CONST_LIN 7 332#define PTP_ATT_CONST_CON 8 333#define PTP_ATT_CONST_3 9 334#define PTP_EYE_X 10 335#define PTP_EYE_Y 11 336#define PTP_EYE_Z 12 337#define PTP_EYE_3 13 338#define PTP_CLAMP_MIN 14 339#define PTP_CLAMP_MAX 15 340#define PTP_CLAMP_2 16 341#define PTP_CLAMP_3 17 342#define PTP_STATE_SIZE 18 343 344#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 345 R200_VTX_COLOR_MASK) 346 347/** 348 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 349 * how many components are in texture coordinate \c n. 350 */ 351#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 352 353#define MAT_CMD_0 0 354#define MAT_ELT_0 1 355#define MAT_STATE_SIZE 17 356 357#define GRD_CMD_0 0 358#define GRD_VERT_GUARD_CLIP_ADJ 1 359#define GRD_VERT_GUARD_DISCARD_ADJ 2 360#define GRD_HORZ_GUARD_CLIP_ADJ 3 361#define GRD_HORZ_GUARD_DISCARD_ADJ 4 362#define GRD_STATE_SIZE 5 363 364/* position changes frequently when lighting in modelpos - separate 365 * out to new state item? 366 */ 367#define LIT_CMD_0 0 368#define LIT_AMBIENT_RED 1 369#define LIT_AMBIENT_GREEN 2 370#define LIT_AMBIENT_BLUE 3 371#define LIT_AMBIENT_ALPHA 4 372#define LIT_DIFFUSE_RED 5 373#define LIT_DIFFUSE_GREEN 6 374#define LIT_DIFFUSE_BLUE 7 375#define LIT_DIFFUSE_ALPHA 8 376#define LIT_SPECULAR_RED 9 377#define LIT_SPECULAR_GREEN 10 378#define LIT_SPECULAR_BLUE 11 379#define LIT_SPECULAR_ALPHA 12 380#define LIT_POSITION_X 13 381#define LIT_POSITION_Y 14 382#define LIT_POSITION_Z 15 383#define LIT_POSITION_W 16 384#define LIT_DIRECTION_X 17 385#define LIT_DIRECTION_Y 18 386#define LIT_DIRECTION_Z 19 387#define LIT_DIRECTION_W 20 388#define LIT_ATTEN_QUADRATIC 21 389#define LIT_ATTEN_LINEAR 22 390#define LIT_ATTEN_CONST 23 391#define LIT_ATTEN_XXX 24 392#define LIT_CMD_1 25 393#define LIT_SPOT_DCD 26 394#define LIT_SPOT_DCM 27 395#define LIT_SPOT_EXPONENT 28 396#define LIT_SPOT_CUTOFF 29 397#define LIT_SPECULAR_THRESH 30 398#define LIT_RANGE_CUTOFF 31 /* ? */ 399#define LIT_ATTEN_CONST_INV 32 400#define LIT_STATE_SIZE 33 401 402/* Fog 403 */ 404#define FOG_CMD_0 0 405#define FOG_R 1 406#define FOG_C 2 407#define FOG_D 3 408#define FOG_PAD 4 409#define FOG_STATE_SIZE 5 410 411/* UCP 412 */ 413#define UCP_CMD_0 0 414#define UCP_X 1 415#define UCP_Y 2 416#define UCP_Z 3 417#define UCP_W 4 418#define UCP_STATE_SIZE 5 419 420/* GLT - Global ambient 421 */ 422#define GLT_CMD_0 0 423#define GLT_RED 1 424#define GLT_GREEN 2 425#define GLT_BLUE 3 426#define GLT_ALPHA 4 427#define GLT_STATE_SIZE 5 428 429/* EYE 430 */ 431#define EYE_CMD_0 0 432#define EYE_X 1 433#define EYE_Y 2 434#define EYE_Z 3 435#define EYE_RESCALE_FACTOR 4 436#define EYE_STATE_SIZE 5 437 438/* CST - constant state 439 */ 440#define CST_CMD_0 0 441#define CST_PP_CNTL_X 1 442#define CST_CMD_1 2 443#define CST_RB3D_DEPTHXY_OFFSET 3 444#define CST_CMD_2 4 445#define CST_RE_AUX_SCISSOR_CNTL 5 446#define CST_CMD_3 6 447#define CST_RE_SCISSOR_TL_0 7 448#define CST_RE_SCISSOR_BR_0 8 449#define CST_CMD_4 9 450#define CST_SE_VAP_CNTL_STATUS 10 451#define CST_CMD_5 11 452#define CST_RE_POINTSIZE 12 453#define CST_CMD_6 13 454#define CST_SE_TCL_INPUT_VTX_0 14 455#define CST_SE_TCL_INPUT_VTX_1 15 456#define CST_SE_TCL_INPUT_VTX_2 16 457#define CST_SE_TCL_INPUT_VTX_3 17 458#define CST_STATE_SIZE 18 459 460#define PRF_CMD_0 0 461#define PRF_PP_TRI_PERF 1 462#define PRF_PP_PERF_CNTL 2 463#define PRF_STATE_SIZE 3 464 465 466#define SCI_CMD_0 0 467#define SCI_RE_AUX 1 468#define SCI_CMD_1 2 469#define SCI_XY_1 3 470#define SCI_CMD_2 4 471#define SCI_XY_2 5 472#define SCI_STATE_SIZE 6 473 474#define R200_QUERYOBJ_CMD_0 0 475#define R200_QUERYOBJ_DATA_0 1 476#define R200_QUERYOBJ_CMDSIZE 2 477 478#define STP_CMD_0 0 479#define STP_DATA_0 1 480#define STP_CMD_1 2 481#define STP_STATE_SIZE 35 482 483struct r200_hw_state { 484 /* Hardware state, stored as cmdbuf commands: 485 * -- Need to doublebuffer for 486 * - reviving state after loss of context 487 * - eliding noop statechange loops? (except line stipple count) 488 */ 489 struct radeon_state_atom ctx; 490 struct radeon_state_atom set; 491 struct radeon_state_atom sci; 492 struct radeon_state_atom vte; 493 struct radeon_state_atom lin; 494 struct radeon_state_atom msk; 495 struct radeon_state_atom vpt; 496 struct radeon_state_atom vap; 497 struct radeon_state_atom vtx; 498 struct radeon_state_atom tcl; 499 struct radeon_state_atom msl; 500 struct radeon_state_atom tcg; 501 struct radeon_state_atom msc; 502 struct radeon_state_atom cst; 503 struct radeon_state_atom tam; 504 struct radeon_state_atom tf; 505 struct radeon_state_atom tex[6]; 506 struct radeon_state_atom cube[6]; 507 struct radeon_state_atom zbs; 508 struct radeon_state_atom mtl[2]; 509 struct radeon_state_atom mat[9]; 510 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 511 struct radeon_state_atom ucp[6]; 512 struct radeon_state_atom pix[6]; /* pixshader stages */ 513 struct radeon_state_atom eye; /* eye pos */ 514 struct radeon_state_atom grd; /* guard band clipping */ 515 struct radeon_state_atom fog; 516 struct radeon_state_atom glt; 517 struct radeon_state_atom prf; 518 struct radeon_state_atom afs[2]; 519 struct radeon_state_atom pvs; 520 struct radeon_state_atom vpi[2]; 521 struct radeon_state_atom vpp[2]; 522 struct radeon_state_atom atf; 523 struct radeon_state_atom spr; 524 struct radeon_state_atom ptp; 525 struct radeon_state_atom stp; 526}; 527 528struct r200_state { 529 /* Derived state for internal purposes: 530 */ 531 struct r200_texture_state texture; 532 GLuint envneeded; 533}; 534 535#define R200_CMD_BUF_SZ (16*1024) 536 537#define R200_ELT_BUF_SZ (16*1024) 538/* r200_tcl.c 539 */ 540struct r200_tcl_info { 541 GLuint hw_primitive; 542 543 int elt_used; 544 545}; 546 547 548/* r200_swtcl.c 549 */ 550struct r200_swtcl_info { 551 552 553 radeon_point_func draw_point; 554 radeon_line_func draw_line; 555 radeon_tri_func draw_tri; 556 557 /** 558 * Offset of the 4UB color data within a hardware (swtcl) vertex. 559 */ 560 GLuint coloroffset; 561 562 /** 563 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 564 */ 565 GLuint specoffset; 566 567 /** 568 * Should Mesa project vertex data or will the hardware do it? 569 */ 570 GLboolean needproj; 571}; 572 573 574 575 576 /* A maximum total of 29 elements per vertex: 3 floats for position, 3 577 * floats for normal, 4 floats for color, 4 bytes for secondary color, 578 * 3 floats for each texture unit (18 floats total). 579 * 580 * we maybe need add. 4 to prevent segfault if someone specifies 581 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 582 * 583 * The position data is never actually stored here, so 3 elements could be 584 * trimmed out of the buffer. 585 */ 586 587#define R200_MAX_VERTEX_SIZE ((3*6)+11) 588 589struct r200_context { 590 struct radeon_context radeon; 591 592 /* Driver and hardware state management 593 */ 594 struct r200_hw_state hw; 595 struct r200_state state; 596 struct r200_vertex_program *curr_vp_hw; 597 598 /* Vertex buffers 599 */ 600 struct radeon_ioctl ioctl; 601 struct radeon_store store; 602 603 /* Clientdata textures; 604 */ 605 GLuint prefer_gart_client_texturing; 606 607 /* TCL stuff 608 */ 609 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 610 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 611 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 612 GLuint TexMatEnabled; 613 GLuint TexMatCompSel; 614 GLuint TexGenEnabled; 615 GLuint TexGenCompSel; 616 GLmatrix tmpmat; 617 618 /* r200_tcl.c 619 */ 620 struct r200_tcl_info tcl; 621 622 /* r200_swtcl.c 623 */ 624 struct r200_swtcl_info swtcl; 625 626 GLboolean using_hyperz; 627 GLboolean texmicrotile; 628 629 struct ati_fragment_shader *afs_loaded; 630}; 631 632#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 633 634 635extern void r200DestroyContext( __DRIcontext *driContextPriv ); 636extern GLboolean r200CreateContext( gl_api api, 637 const struct gl_config *glVisual, 638 __DRIcontext *driContextPriv, 639 void *sharedContextPrivate); 640extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv, 641 __DRIdrawable *driDrawPriv, 642 __DRIdrawable *driReadPriv ); 643extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv ); 644 645extern void r200_init_texcopy_functions(struct dd_function_table *table); 646 647/* ================================================================ 648 * Debugging: 649 */ 650 651#define R200_DEBUG RADEON_DEBUG 652 653 654 655#endif /* __R200_CONTEXT_H__ */ 656