r200_context.h revision 692ca82116485a9c6191e5265c5b369d5b4f82f3
1/* 2Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4The Weather Channel (TM) funded Tungsten Graphics to develop the 5initial release of the Radeon 8500 driver under the XFree86 license. 6This notice must be preserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35#ifndef __R200_CONTEXT_H__ 36#define __R200_CONTEXT_H__ 37 38#include "tnl/t_vertex.h" 39#include "drm.h" 40#include "radeon_drm.h" 41#include "dri_util.h" 42#include "texmem.h" 43 44#include "main/macros.h" 45#include "main/mtypes.h" 46#include "main/colormac.h" 47#include "r200_reg.h" 48#include "r200_vertprog.h" 49 50#define ENABLE_HW_3D_TEXTURE 1 /* XXX this is temporary! */ 51 52#ifndef R200_EMIT_VAP_PVS_CNTL 53#error This driver requires a newer libdrm to compile 54#endif 55 56#include "common_context.h" 57 58struct r200_context; 59typedef struct r200_context r200ContextRec; 60typedef struct r200_context *r200ContextPtr; 61 62#include "r200_lock.h" 63#include "radeon_screen.h" 64#include "main/mm.h" 65 66typedef void (*r200_tri_func)( r200ContextPtr, 67 radeonVertex *, 68 radeonVertex *, 69 radeonVertex * ); 70 71typedef void (*r200_line_func)( r200ContextPtr, 72 radeonVertex *, 73 radeonVertex * ); 74 75typedef void (*r200_point_func)( r200ContextPtr, 76 radeonVertex * ); 77 78 79struct r200_vertex_program { 80 struct gl_vertex_program mesa_program; /* Must be first */ 81 int translated; 82 /* need excess instr: 1 for late loop checking, 2 for 83 additional instr due to instr/attr, 3 for fog */ 84 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 85 int pos_end; 86 int inputs[VERT_ATTRIB_MAX]; 87 GLubyte inputmap_rev[16]; 88 int native; 89 int fogpidx; 90 int fogmode; 91}; 92 93#define R200_TEX_ALL 0x3f 94 95 96struct r200_texture_env_state { 97 radeonTexObjPtr texobj; 98 GLuint outputreg; 99 GLuint unitneeded; 100}; 101 102#define R200_MAX_TEXTURE_UNITS 6 103 104struct r200_texture_state { 105 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 106}; 107 108 109struct r200_state_atom { 110 struct r200_state_atom *next, *prev; 111 const char *name; /* for debug */ 112 int cmd_size; /* size in bytes */ 113 GLuint is_tcl; 114 GLuint idx; 115 int *cmd; /* one or more cmd's */ 116 int *lastcmd; /* one or more cmd's */ 117 GLboolean dirty; 118 GLboolean (*check)( GLcontext *, int ); /* is this state active? */ 119}; 120 121/* Trying to keep these relatively short as the variables are becoming 122 * extravagently long. Drop the driver name prefix off the front of 123 * everything - I think we know which driver we're in by now, and keep the 124 * prefix to 3 letters unless absolutely impossible. 125 */ 126 127#define CTX_CMD_0 0 128#define CTX_PP_MISC 1 129#define CTX_PP_FOG_COLOR 2 130#define CTX_RE_SOLID_COLOR 3 131#define CTX_RB3D_BLENDCNTL 4 132#define CTX_RB3D_DEPTHOFFSET 5 133#define CTX_RB3D_DEPTHPITCH 6 134#define CTX_RB3D_ZSTENCILCNTL 7 135#define CTX_CMD_1 8 136#define CTX_PP_CNTL 9 137#define CTX_RB3D_CNTL 10 138#define CTX_RB3D_COLOROFFSET 11 139#define CTX_CMD_2 12 /* why */ 140#define CTX_RB3D_COLORPITCH 13 /* why */ 141#define CTX_STATE_SIZE_OLDDRM 14 142#define CTX_CMD_3 14 143#define CTX_RB3D_BLENDCOLOR 15 144#define CTX_RB3D_ABLENDCNTL 16 145#define CTX_RB3D_CBLENDCNTL 17 146#define CTX_STATE_SIZE_NEWDRM 18 147 148#define SET_CMD_0 0 149#define SET_SE_CNTL 1 150#define SET_RE_CNTL 2 /* replace se_coord_fmt */ 151#define SET_STATE_SIZE 3 152 153#define VTE_CMD_0 0 154#define VTE_SE_VTE_CNTL 1 155#define VTE_STATE_SIZE 2 156 157#define LIN_CMD_0 0 158#define LIN_RE_LINE_PATTERN 1 159#define LIN_RE_LINE_STATE 2 160#define LIN_CMD_1 3 161#define LIN_SE_LINE_WIDTH 4 162#define LIN_STATE_SIZE 5 163 164#define MSK_CMD_0 0 165#define MSK_RB3D_STENCILREFMASK 1 166#define MSK_RB3D_ROPCNTL 2 167#define MSK_RB3D_PLANEMASK 3 168#define MSK_STATE_SIZE 4 169 170#define VPT_CMD_0 0 171#define VPT_SE_VPORT_XSCALE 1 172#define VPT_SE_VPORT_XOFFSET 2 173#define VPT_SE_VPORT_YSCALE 3 174#define VPT_SE_VPORT_YOFFSET 4 175#define VPT_SE_VPORT_ZSCALE 5 176#define VPT_SE_VPORT_ZOFFSET 6 177#define VPT_STATE_SIZE 7 178 179#define ZBS_CMD_0 0 180#define ZBS_SE_ZBIAS_FACTOR 1 181#define ZBS_SE_ZBIAS_CONSTANT 2 182#define ZBS_STATE_SIZE 3 183 184#define MSC_CMD_0 0 185#define MSC_RE_MISC 1 186#define MSC_STATE_SIZE 2 187 188#define TAM_CMD_0 0 189#define TAM_DEBUG3 1 190#define TAM_STATE_SIZE 2 191 192#define TEX_CMD_0 0 193#define TEX_PP_TXFILTER 1 /*2c00*/ 194#define TEX_PP_TXFORMAT 2 /*2c04*/ 195#define TEX_PP_TXFORMAT_X 3 /*2c08*/ 196#define TEX_PP_TXSIZE 4 /*2c0c*/ 197#define TEX_PP_TXPITCH 5 /*2c10*/ 198#define TEX_PP_BORDER_COLOR 6 /*2c14*/ 199#define TEX_CMD_1_OLDDRM 7 200#define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 201#define TEX_STATE_SIZE_OLDDRM 9 202#define TEX_PP_CUBIC_FACES 7 203#define TEX_PP_TXMULTI_CTL 8 204#define TEX_CMD_1_NEWDRM 9 205#define TEX_PP_TXOFFSET_NEWDRM 10 206#define TEX_STATE_SIZE_NEWDRM 11 207 208#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 209#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 210#define CUBE_CMD_1 2 /* 5 registers follow */ 211#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 212#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 213#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 214#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 215#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 216#define CUBE_STATE_SIZE 8 217 218#define PIX_CMD_0 0 219#define PIX_PP_TXCBLEND 1 220#define PIX_PP_TXCBLEND2 2 221#define PIX_PP_TXABLEND 3 222#define PIX_PP_TXABLEND2 4 223#define PIX_STATE_SIZE 5 224 225#define TF_CMD_0 0 226#define TF_TFACTOR_0 1 227#define TF_TFACTOR_1 2 228#define TF_TFACTOR_2 3 229#define TF_TFACTOR_3 4 230#define TF_TFACTOR_4 5 231#define TF_TFACTOR_5 6 232#define TF_STATE_SIZE 7 233 234#define ATF_CMD_0 0 235#define ATF_TFACTOR_0 1 236#define ATF_TFACTOR_1 2 237#define ATF_TFACTOR_2 3 238#define ATF_TFACTOR_3 4 239#define ATF_TFACTOR_4 5 240#define ATF_TFACTOR_5 6 241#define ATF_TFACTOR_6 7 242#define ATF_TFACTOR_7 8 243#define ATF_STATE_SIZE 9 244 245/* ATI_FRAGMENT_SHADER */ 246#define AFS_CMD_0 0 247#define AFS_IC0 1 /* 2f00 */ 248#define AFS_IC1 2 /* 2f04 */ 249#define AFS_IA0 3 /* 2f08 */ 250#define AFS_IA1 4 /* 2f0c */ 251#define AFS_STATE_SIZE 33 252 253#define PVS_CMD_0 0 254#define PVS_CNTL_1 1 255#define PVS_CNTL_2 2 256#define PVS_STATE_SIZE 3 257 258/* those are quite big... */ 259#define VPI_CMD_0 0 260#define VPI_OPDST_0 1 261#define VPI_SRC0_0 2 262#define VPI_SRC1_0 3 263#define VPI_SRC2_0 4 264#define VPI_OPDST_63 253 265#define VPI_SRC0_63 254 266#define VPI_SRC1_63 255 267#define VPI_SRC2_63 256 268#define VPI_STATE_SIZE 257 269 270#define VPP_CMD_0 0 271#define VPP_PARAM0_0 1 272#define VPP_PARAM1_0 2 273#define VPP_PARAM2_0 3 274#define VPP_PARAM3_0 4 275#define VPP_PARAM0_95 381 276#define VPP_PARAM1_95 382 277#define VPP_PARAM2_95 383 278#define VPP_PARAM3_95 384 279#define VPP_STATE_SIZE 385 280 281#define TCL_CMD_0 0 282#define TCL_LIGHT_MODEL_CTL_0 1 283#define TCL_LIGHT_MODEL_CTL_1 2 284#define TCL_PER_LIGHT_CTL_0 3 285#define TCL_PER_LIGHT_CTL_1 4 286#define TCL_PER_LIGHT_CTL_2 5 287#define TCL_PER_LIGHT_CTL_3 6 288#define TCL_CMD_1 7 289#define TCL_UCP_VERT_BLEND_CTL 8 290#define TCL_STATE_SIZE 9 291 292#define MSL_CMD_0 0 293#define MSL_MATRIX_SELECT_0 1 294#define MSL_MATRIX_SELECT_1 2 295#define MSL_MATRIX_SELECT_2 3 296#define MSL_MATRIX_SELECT_3 4 297#define MSL_MATRIX_SELECT_4 5 298#define MSL_STATE_SIZE 6 299 300#define TCG_CMD_0 0 301#define TCG_TEX_PROC_CTL_2 1 302#define TCG_TEX_PROC_CTL_3 2 303#define TCG_TEX_PROC_CTL_0 3 304#define TCG_TEX_PROC_CTL_1 4 305#define TCG_TEX_CYL_WRAP_CTL 5 306#define TCG_STATE_SIZE 6 307 308#define MTL_CMD_0 0 309#define MTL_EMMISSIVE_RED 1 310#define MTL_EMMISSIVE_GREEN 2 311#define MTL_EMMISSIVE_BLUE 3 312#define MTL_EMMISSIVE_ALPHA 4 313#define MTL_AMBIENT_RED 5 314#define MTL_AMBIENT_GREEN 6 315#define MTL_AMBIENT_BLUE 7 316#define MTL_AMBIENT_ALPHA 8 317#define MTL_DIFFUSE_RED 9 318#define MTL_DIFFUSE_GREEN 10 319#define MTL_DIFFUSE_BLUE 11 320#define MTL_DIFFUSE_ALPHA 12 321#define MTL_SPECULAR_RED 13 322#define MTL_SPECULAR_GREEN 14 323#define MTL_SPECULAR_BLUE 15 324#define MTL_SPECULAR_ALPHA 16 325#define MTL_CMD_1 17 326#define MTL_SHININESS 18 327#define MTL_STATE_SIZE 19 328 329#define VAP_CMD_0 0 330#define VAP_SE_VAP_CNTL 1 331#define VAP_STATE_SIZE 2 332 333/* Replaces a lot of packet info from radeon 334 */ 335#define VTX_CMD_0 0 336#define VTX_VTXFMT_0 1 337#define VTX_VTXFMT_1 2 338#define VTX_TCL_OUTPUT_VTXFMT_0 3 339#define VTX_TCL_OUTPUT_VTXFMT_1 4 340#define VTX_CMD_1 5 341#define VTX_TCL_OUTPUT_COMPSEL 6 342#define VTX_CMD_2 7 343#define VTX_STATE_CNTL 8 344#define VTX_STATE_SIZE 9 345 346/* SPR - point sprite state 347 */ 348#define SPR_CMD_0 0 349#define SPR_POINT_SPRITE_CNTL 1 350#define SPR_STATE_SIZE 2 351 352#define PTP_CMD_0 0 353#define PTP_VPORT_SCALE_0 1 354#define PTP_VPORT_SCALE_1 2 355#define PTP_VPORT_SCALE_PTSIZE 3 356#define PTP_VPORT_SCALE_3 4 357#define PTP_CMD_1 5 358#define PTP_ATT_CONST_QUAD 6 359#define PTP_ATT_CONST_LIN 7 360#define PTP_ATT_CONST_CON 8 361#define PTP_ATT_CONST_3 9 362#define PTP_EYE_X 10 363#define PTP_EYE_Y 11 364#define PTP_EYE_Z 12 365#define PTP_EYE_3 13 366#define PTP_CLAMP_MIN 14 367#define PTP_CLAMP_MAX 15 368#define PTP_CLAMP_2 16 369#define PTP_CLAMP_3 17 370#define PTP_STATE_SIZE 18 371 372#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 373 R200_VTX_COLOR_MASK) 374 375/** 376 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 377 * how many components are in texture coordinate \c n. 378 */ 379#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 380 381#define MAT_CMD_0 0 382#define MAT_ELT_0 1 383#define MAT_STATE_SIZE 17 384 385#define GRD_CMD_0 0 386#define GRD_VERT_GUARD_CLIP_ADJ 1 387#define GRD_VERT_GUARD_DISCARD_ADJ 2 388#define GRD_HORZ_GUARD_CLIP_ADJ 3 389#define GRD_HORZ_GUARD_DISCARD_ADJ 4 390#define GRD_STATE_SIZE 5 391 392/* position changes frequently when lighting in modelpos - separate 393 * out to new state item? 394 */ 395#define LIT_CMD_0 0 396#define LIT_AMBIENT_RED 1 397#define LIT_AMBIENT_GREEN 2 398#define LIT_AMBIENT_BLUE 3 399#define LIT_AMBIENT_ALPHA 4 400#define LIT_DIFFUSE_RED 5 401#define LIT_DIFFUSE_GREEN 6 402#define LIT_DIFFUSE_BLUE 7 403#define LIT_DIFFUSE_ALPHA 8 404#define LIT_SPECULAR_RED 9 405#define LIT_SPECULAR_GREEN 10 406#define LIT_SPECULAR_BLUE 11 407#define LIT_SPECULAR_ALPHA 12 408#define LIT_POSITION_X 13 409#define LIT_POSITION_Y 14 410#define LIT_POSITION_Z 15 411#define LIT_POSITION_W 16 412#define LIT_DIRECTION_X 17 413#define LIT_DIRECTION_Y 18 414#define LIT_DIRECTION_Z 19 415#define LIT_DIRECTION_W 20 416#define LIT_ATTEN_QUADRATIC 21 417#define LIT_ATTEN_LINEAR 22 418#define LIT_ATTEN_CONST 23 419#define LIT_ATTEN_XXX 24 420#define LIT_CMD_1 25 421#define LIT_SPOT_DCD 26 422#define LIT_SPOT_DCM 27 423#define LIT_SPOT_EXPONENT 28 424#define LIT_SPOT_CUTOFF 29 425#define LIT_SPECULAR_THRESH 30 426#define LIT_RANGE_CUTOFF 31 /* ? */ 427#define LIT_ATTEN_CONST_INV 32 428#define LIT_STATE_SIZE 33 429 430/* Fog 431 */ 432#define FOG_CMD_0 0 433#define FOG_R 1 434#define FOG_C 2 435#define FOG_D 3 436#define FOG_PAD 4 437#define FOG_STATE_SIZE 5 438 439/* UCP 440 */ 441#define UCP_CMD_0 0 442#define UCP_X 1 443#define UCP_Y 2 444#define UCP_Z 3 445#define UCP_W 4 446#define UCP_STATE_SIZE 5 447 448/* GLT - Global ambient 449 */ 450#define GLT_CMD_0 0 451#define GLT_RED 1 452#define GLT_GREEN 2 453#define GLT_BLUE 3 454#define GLT_ALPHA 4 455#define GLT_STATE_SIZE 5 456 457/* EYE 458 */ 459#define EYE_CMD_0 0 460#define EYE_X 1 461#define EYE_Y 2 462#define EYE_Z 3 463#define EYE_RESCALE_FACTOR 4 464#define EYE_STATE_SIZE 5 465 466/* CST - constant state 467 */ 468#define CST_CMD_0 0 469#define CST_PP_CNTL_X 1 470#define CST_CMD_1 2 471#define CST_RB3D_DEPTHXY_OFFSET 3 472#define CST_CMD_2 4 473#define CST_RE_AUX_SCISSOR_CNTL 5 474#define CST_CMD_3 6 475#define CST_RE_SCISSOR_TL_0 7 476#define CST_RE_SCISSOR_BR_0 8 477#define CST_CMD_4 9 478#define CST_SE_VAP_CNTL_STATUS 10 479#define CST_CMD_5 11 480#define CST_RE_POINTSIZE 12 481#define CST_CMD_6 13 482#define CST_SE_TCL_INPUT_VTX_0 14 483#define CST_SE_TCL_INPUT_VTX_1 15 484#define CST_SE_TCL_INPUT_VTX_2 16 485#define CST_SE_TCL_INPUT_VTX_3 17 486#define CST_STATE_SIZE 18 487 488#define PRF_CMD_0 0 489#define PRF_PP_TRI_PERF 1 490#define PRF_PP_PERF_CNTL 2 491#define PRF_STATE_SIZE 3 492 493 494struct r200_hw_state { 495 /* Head of the linked list of state atoms. */ 496 struct r200_state_atom atomlist; 497 498 /* Hardware state, stored as cmdbuf commands: 499 * -- Need to doublebuffer for 500 * - reviving state after loss of context 501 * - eliding noop statechange loops? (except line stipple count) 502 */ 503 struct r200_state_atom ctx; 504 struct r200_state_atom set; 505 struct r200_state_atom vte; 506 struct r200_state_atom lin; 507 struct r200_state_atom msk; 508 struct r200_state_atom vpt; 509 struct r200_state_atom vap; 510 struct r200_state_atom vtx; 511 struct r200_state_atom tcl; 512 struct r200_state_atom msl; 513 struct r200_state_atom tcg; 514 struct r200_state_atom msc; 515 struct r200_state_atom cst; 516 struct r200_state_atom tam; 517 struct r200_state_atom tf; 518 struct r200_state_atom tex[6]; 519 struct r200_state_atom cube[6]; 520 struct r200_state_atom zbs; 521 struct r200_state_atom mtl[2]; 522 struct r200_state_atom mat[9]; 523 struct r200_state_atom lit[8]; /* includes vec, scl commands */ 524 struct r200_state_atom ucp[6]; 525 struct r200_state_atom pix[6]; /* pixshader stages */ 526 struct r200_state_atom eye; /* eye pos */ 527 struct r200_state_atom grd; /* guard band clipping */ 528 struct r200_state_atom fog; 529 struct r200_state_atom glt; 530 struct r200_state_atom prf; 531 struct r200_state_atom afs[2]; 532 struct r200_state_atom pvs; 533 struct r200_state_atom vpi[2]; 534 struct r200_state_atom vpp[2]; 535 struct r200_state_atom atf; 536 struct r200_state_atom spr; 537 struct r200_state_atom ptp; 538 539 int max_state_size; /* Number of bytes necessary for a full state emit. */ 540 GLboolean is_dirty, all_dirty; 541}; 542 543struct r200_state { 544 /* Derived state for internal purposes: 545 */ 546 struct radeon_colorbuffer_state color; 547 struct radeon_depthbuffer_state depth; 548#if 00 549 struct r200_pixel_state pixel; 550#endif 551 struct radeon_scissor_state scissor; 552 struct radeon_stencilbuffer_state stencil; 553 struct radeon_stipple_state stipple; 554 struct r200_texture_state texture; 555 GLuint envneeded; 556}; 557 558#define GET_START(rvb) (rmesa->r200Screen->gart_buffer_offset + \ 559 (rvb)->address - rmesa->dma.buf0_address + \ 560 (rvb)->start) 561 562struct r200_dri_mirror { 563 __DRIcontextPrivate *context; /* DRI context */ 564 __DRIscreenPrivate *screen; /* DRI screen */ 565 __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */ 566 __DRIdrawablePrivate *readable; /* DRI readable bound to this ctx */ 567 568 drm_context_t hwContext; 569 drm_hw_lock_t *hwLock; 570 int fd; 571 int drmMinor; 572}; 573 574 575#define R200_CMD_BUF_SZ (16*1024) 576 577struct r200_store { 578 GLuint statenr; 579 GLuint primnr; 580 char cmd_buf[R200_CMD_BUF_SZ]; 581 int cmd_used; 582 int elts_start; 583}; 584 585 586/* r200_tcl.c 587 */ 588struct r200_tcl_info { 589 GLuint hw_primitive; 590 591/* hw can handle 12 components max */ 592 struct radeon_dma_region *aos_components[12]; 593 GLuint nr_aos_components; 594 595 GLuint *Elts; 596 597 struct radeon_dma_region indexed_verts; 598 struct radeon_dma_region vertex_data[15]; 599}; 600 601 602/* r200_swtcl.c 603 */ 604struct r200_swtcl_info { 605 GLuint RenderIndex; 606 607 /** 608 * Size of a hardware vertex. This is calculated when \c ::vertex_attrs is 609 * installed in the Mesa state vector. 610 */ 611 GLuint vertex_size; 612 613 /** 614 * Attributes instructing the Mesa TCL pipeline where / how to put vertex 615 * data in the hardware buffer. 616 */ 617 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 618 619 /** 620 * Number of elements of \c ::vertex_attrs that are actually used. 621 */ 622 GLuint vertex_attr_count; 623 624 /** 625 * Cached pointer to the buffer where Mesa will store vertex data. 626 */ 627 GLubyte *verts; 628 629 /* Fallback rasterization functions 630 */ 631 r200_point_func draw_point; 632 r200_line_func draw_line; 633 r200_tri_func draw_tri; 634 635 GLuint hw_primitive; 636 GLenum render_primitive; 637 GLuint numverts; 638 639 /** 640 * Offset of the 4UB color data within a hardware (swtcl) vertex. 641 */ 642 GLuint coloroffset; 643 644 /** 645 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 646 */ 647 GLuint specoffset; 648 649 /** 650 * Should Mesa project vertex data or will the hardware do it? 651 */ 652 GLboolean needproj; 653 654 struct radeon_dma_region indexed_verts; 655}; 656 657 658 659 660 /* A maximum total of 29 elements per vertex: 3 floats for position, 3 661 * floats for normal, 4 floats for color, 4 bytes for secondary color, 662 * 3 floats for each texture unit (18 floats total). 663 * 664 * we maybe need add. 4 to prevent segfault if someone specifies 665 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 666 * 667 * The position data is never actually stored here, so 3 elements could be 668 * trimmed out of the buffer. 669 */ 670 671#define R200_MAX_VERTEX_SIZE ((3*6)+11) 672 673 674struct r200_context { 675 GLcontext *glCtx; /* Mesa context */ 676 677 /* Driver and hardware state management 678 */ 679 struct r200_hw_state hw; 680 struct r200_state state; 681 struct r200_vertex_program *curr_vp_hw; 682 683 /* Texture object bookkeeping 684 */ 685 unsigned nr_heaps; 686 driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 687 driTextureObject swapped; 688 int texture_depth; 689 float initialMaxAnisotropy; 690 691 /* Rasterization and vertex state: 692 */ 693 GLuint TclFallback; 694 GLuint Fallback; 695 GLuint NewGLState; 696 DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ 697 698 /* Vertex buffers 699 */ 700 struct radeon_ioctl ioctl; 701 struct radeon_dma dma; 702 struct r200_store store; 703 /* A full state emit as of the first state emit in the main store, in case 704 * the context is lost. 705 */ 706 struct r200_store backup_store; 707 708 /* Page flipping 709 */ 710 GLuint doPageFlip; 711 712 /* Busy waiting 713 */ 714 GLuint do_usleeps; 715 GLuint do_irqs; 716 GLuint irqsEmitted; 717 drm_radeon_irq_wait_t iw; 718 719 /* Clientdata textures; 720 */ 721 GLuint prefer_gart_client_texturing; 722 723 /* Drawable, cliprect and scissor information 724 */ 725 GLuint numClipRects; /* Cliprects for the draw buffer */ 726 drm_clip_rect_t *pClipRects; 727 unsigned int lastStamp; 728 GLboolean lost_context; 729 GLboolean save_on_next_emit; 730 radeonScreenPtr r200Screen; /* Screen private DRI data */ 731 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 732 733 /* TCL stuff 734 */ 735 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 736 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 737 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 738 GLuint TexMatEnabled; 739 GLuint TexMatCompSel; 740 GLuint TexGenEnabled; 741 GLuint TexGenCompSel; 742 GLmatrix tmpmat; 743 744 /* buffer swap 745 */ 746 int64_t swap_ust; 747 int64_t swap_missed_ust; 748 749 GLuint swap_count; 750 GLuint swap_missed_count; 751 752 753 /* r200_tcl.c 754 */ 755 struct r200_tcl_info tcl; 756 757 /* r200_swtcl.c 758 */ 759 struct r200_swtcl_info swtcl; 760 761 /* Mirrors of some DRI state 762 */ 763 struct r200_dri_mirror dri; 764 765 /* Configuration cache 766 */ 767 driOptionCache optionCache; 768 769 GLboolean using_hyperz; 770 GLboolean texmicrotile; 771 772 struct ati_fragment_shader *afs_loaded; 773}; 774 775#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 776 777 778extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); 779extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, 780 __DRIcontextPrivate *driContextPriv, 781 void *sharedContextPrivate); 782extern void r200SwapBuffers( __DRIdrawablePrivate *dPriv ); 783extern void r200CopySubBuffer( __DRIdrawablePrivate * dPriv, 784 int x, int y, int w, int h ); 785extern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, 786 __DRIdrawablePrivate *driDrawPriv, 787 __DRIdrawablePrivate *driReadPriv ); 788extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); 789 790/* ================================================================ 791 * Debugging: 792 */ 793#define DO_DEBUG 1 794 795#if DO_DEBUG 796extern int R200_DEBUG; 797#else 798#define R200_DEBUG 0 799#endif 800 801#define DEBUG_TEXTURE 0x001 802#define DEBUG_STATE 0x002 803#define DEBUG_IOCTL 0x004 804#define DEBUG_PRIMS 0x008 805#define DEBUG_VERTS 0x010 806#define DEBUG_FALLBACKS 0x020 807#define DEBUG_VFMT 0x040 808#define DEBUG_CODEGEN 0x080 809#define DEBUG_VERBOSE 0x100 810#define DEBUG_DRI 0x200 811#define DEBUG_DMA 0x400 812#define DEBUG_SANITY 0x800 813#define DEBUG_SYNC 0x1000 814#define DEBUG_PIXEL 0x2000 815#define DEBUG_MEMORY 0x4000 816 817#endif /* __R200_CONTEXT_H__ */ 818