r200_sanity.c revision c53d2d0ca81f4335c3b3bf9870635ba5ec2b3b52
1/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_sanity.c,v 1.1 2002/10/30 12:51:52 alanh Exp $ */ 2/************************************************************************** 3 4Copyright 2002 ATI Technologies Inc., Ontario, Canada, and 5 Tungsten Graphics Inc, Cedar Park, TX. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining a 10copy of this software and associated documentation files (the "Software"), 11to deal in the Software without restriction, including without limitation 12on the rights to use, copy, modify, merge, publish, distribute, sub 13license, and/or sell copies of the Software, and to permit persons to whom 14the Software is furnished to do so, subject to the following conditions: 15 16The above copyright notice and this permission notice (including the next 17paragraph) shall be included in all copies or substantial portions of the 18Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 23ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 24DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 25OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 26USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 * 34 */ 35 36#include <errno.h> 37 38#include "glheader.h" 39#include "imports.h" 40 41#include "r200_context.h" 42#include "r200_ioctl.h" 43#include "r200_sanity.h" 44#include "radeon_reg.h" 45#include "r200_reg.h" 46 47/* Set this '1' to get more verbiage. 48 */ 49#define MORE_VERBOSE 1 50 51#if MORE_VERBOSE 52#define VERBOSE (R200_DEBUG & DEBUG_VERBOSE) 53#define NORMAL (1) 54#else 55#define VERBOSE 0 56#define NORMAL (R200_DEBUG & DEBUG_VERBOSE) 57#endif 58 59 60/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 61 * 1.3 cmdbuffers allow all previous state to be updated as well as 62 * the tcl scalar and vector areas. 63 */ 64static struct { 65 int start; 66 int len; 67 const char *name; 68} packet[RADEON_MAX_STATE_PACKETS] = { 69 { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, 70 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, 71 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, 72 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, 73 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, 74 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, 75 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, 76 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, 77 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, 78 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, 79 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, 80 { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, 81 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, 82 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, 83 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, 84 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, 85 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, 86 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, 87 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, 88 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, 89 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, 90 { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" }, 91 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, 92 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, 93 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, 94 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, 95 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, 96 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, 97 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, 98 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 99 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, 100 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, 101 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, 102 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, 103 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, 104 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 105 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, 106 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, 107 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, 108 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, 109 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, 110 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, 111 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, 112 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, 113 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, 114 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, 115 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, 116 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, 117 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, 118 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 119 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, 120 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, 121 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, 122 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, 123 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, 124 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, 125 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, 126 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, 127 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, 128 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, 129 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 130 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ 131 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ 132 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, 133 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, 134 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, 135 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, 136 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, 137 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, 138 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, 139 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, 140 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, 141 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, 142 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, 143 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, 144 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, 145 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, 146 { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 147 { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" }, 148 { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" }, 149 { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" }, 150 { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" }, 151 { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" }, 152 { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" }, 153 { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" }, 154 { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 155 { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 156 { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 157 { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 158 { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 159 { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 160 { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 161 { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 162 { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 163}; 164 165struct reg_names { 166 int idx; 167 const char *name; 168}; 169 170static struct reg_names reg_names[] = { 171 { R200_PP_MISC, "R200_PP_MISC" }, 172 { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" }, 173 { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" }, 174 { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" }, 175 { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" }, 176 { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" }, 177 { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" }, 178 { R200_PP_CNTL, "R200_PP_CNTL" }, 179 { R200_RB3D_CNTL, "R200_RB3D_CNTL" }, 180 { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" }, 181 { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" }, 182 { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" }, 183 { R200_SE_CNTL, "R200_SE_CNTL" }, 184 { R200_RE_CNTL, "R200_RE_CNTL" }, 185 { R200_RE_MISC, "R200_RE_MISC" }, 186 { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" }, 187 { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" }, 188 { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" }, 189 { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" }, 190 { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" }, 191 { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" }, 192 { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" }, 193 { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" }, 194 { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" }, 195 { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" }, 196 { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" }, 197 { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" }, 198 { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" }, 199 { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" }, 200 { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" }, 201 { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" }, 202 { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" }, 203 { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" }, 204 { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" }, 205 { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" }, 206 { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" }, 207 { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" }, 208 { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" }, 209 { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" }, 210 { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" }, 211 { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" }, 212 { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" }, 213 { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" }, 214 { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" }, 215 { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" }, 216 { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" }, 217 { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" }, 218 { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" }, 219 { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" }, 220 { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" }, 221 { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" }, 222 { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" }, 223 { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" }, 224 { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" }, 225 { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" }, 226 { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" }, 227 { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" }, 228 { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" }, 229 { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" }, 230 { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" }, 231 { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" }, 232 { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" }, 233 { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" }, 234 { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" }, 235 { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" }, 236 { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" }, 237 { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" }, 238 { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" }, 239 { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" }, 240 { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" }, 241 { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" }, 242 { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" }, 243 { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" }, 244 { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" }, 245 { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" }, 246 { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" }, 247 { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, 248 { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" }, 249 { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" }, 250 { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" }, 251 { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" }, 252 { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" }, 253 { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" }, 254 { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" }, 255 { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" }, 256 { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" }, 257 { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" }, 258 { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, 259 { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" }, 260 { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" }, 261 { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" }, 262 { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" }, 263 { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" }, 264 { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" }, 265 { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" }, 266 { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" }, 267 { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" }, 268 { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" }, 269 { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" }, 270 { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" }, 271 { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" }, 272 { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" }, 273 { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" }, 274 { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" }, 275 { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" }, 276 { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" }, 277 { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" }, 278 { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" }, 279 { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" }, 280 { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" }, 281 { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" }, 282 { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" }, 283 { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" }, 284 { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" }, 285 { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" }, 286 { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" }, 287 { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" }, 288 { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" }, 289 { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" }, 290 { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" }, 291 { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" }, 292 { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" }, 293 { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" }, 294 { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" }, 295 { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" }, 296 { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" }, 297 { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" }, 298 { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" }, 299 { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" }, 300 { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" }, 301 { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" }, 302 { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" }, 303 { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" }, 304 { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" }, 305 { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" }, 306 { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" }, 307 { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" }, 308 { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" }, 309 { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" }, 310 { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" }, 311 { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" }, 312 { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" }, 313 { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" }, 314 { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" }, 315 { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" }, 316 { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" }, 317 { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" }, 318 { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" }, 319 { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" }, 320 { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" }, 321 { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" }, 322 { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" }, 323 { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" }, 324 { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" }, 325 { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" }, 326 { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" }, 327 { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" }, 328 { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" }, 329 { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" }, 330 { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" }, 331 { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" }, 332 { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" }, 333 { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" }, 334 { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" }, 335 { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" }, 336 { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" }, 337 { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" }, 338 { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" }, 339 { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" }, 340 { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" }, 341 { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" }, 342 { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" }, 343 { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" }, 344 { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" }, 345 { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" }, 346 { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" }, 347 { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" }, 348 { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" }, 349 { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" }, 350 { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" }, 351 { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" }, 352 { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" }, 353 { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" }, 354 { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" }, 355 { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" }, 356 { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" }, 357 { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" }, 358 { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" }, 359 { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" }, 360 { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" }, 361 { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" }, 362 { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" }, 363 { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" }, 364 { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" }, 365 { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" }, 366 { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" }, 367 { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" }, 368 { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" }, 369 { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" }, 370 { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" }, 371 { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" }, 372 { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" }, 373 { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" }, 374 { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" }, 375 { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" }, 376 { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" }, 377 { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" }, 378 { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" }, 379 { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" }, 380 { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" }, 381 { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" }, 382 { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" }, 383 { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" }, 384 { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" }, 385 { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" }, 386 { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" }, 387 { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" }, 388 { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" }, 389 { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" }, 390 { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" }, 391 { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" }, 392 { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" }, 393 { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" }, 394 { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" }, 395 { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" }, 396 { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" }, 397 { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" }, 398 { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" }, 399 { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" }, 400 { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" }, 401 { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" }, 402 { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" }, 403 { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" }, 404 { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" }, 405 { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" }, 406 { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" }, 407 { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" }, 408 { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" }, 409 { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" }, 410 { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" }, 411 { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" }, 412 { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" }, 413 { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" }, 414 { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" }, 415 { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" }, 416 { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" }, 417 { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" }, 418 { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" }, 419 { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" }, 420 { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" }, 421 { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" }, 422 { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" }, 423 { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" }, 424 { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" }, 425 { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" }, 426 { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" }, 427 { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" }, 428 { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" }, 429 { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" }, 430 { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" }, 431 { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" }, 432 { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" }, 433 { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" }, 434 { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" }, 435 { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" }, 436 { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" }, 437 { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" }, 438 { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" }, 439 { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" }, 440 { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" }, 441 { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" }, 442 { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" }, 443 { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" }, 444 { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" }, 445 { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" }, 446 { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" }, 447 { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" }, 448 { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" }, 449 { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" }, 450 { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" }, 451 { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" }, 452 { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" }, 453 { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" }, 454 { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" }, 455 { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" }, 456 { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" }, 457 { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" }, 458 { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" }, 459 { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" }, 460 { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" }, 461 { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" }, 462 { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" }, 463 { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" }, 464 { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" }, 465 { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" }, 466 { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" }, 467 { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" }, 468 { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" }, 469 { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" }, 470 { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" }, 471 { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" }, 472 { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" }, 473 { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" }, 474 { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" }, 475 { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" }, 476 { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" }, 477 { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" }, 478 { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" }, 479 { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" }, 480 { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" }, 481 { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" }, 482 { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" }, 483 { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" }, 484 { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" }, 485 { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" }, 486 { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" }, 487 { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" }, 488 { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" }, 489 { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" }, 490 { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" }, 491 { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" }, 492 { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" }, 493 { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" }, 494 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, 495 { R200_PP_CNTL_X, "R200_PP_CNTL_X" }, 496 { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" }, 497 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, 498 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" }, 499 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" }, 500 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" }, 501 { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" }, 502 { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" }, 503 { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" }, 504 { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" }, 505 { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" }, 506 { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" }, 507 { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" }, 508 { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" }, 509 { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" }, 510 { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" }, 511 { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" }, 512 { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" }, 513 { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" }, 514 { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" }, 515 { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" }, 516 { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" }, 517 { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" }, 518 { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" }, 519 { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" }, 520 { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" }, 521 { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" }, 522 { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" }, 523 { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" }, 524 { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" }, 525 { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" }, 526 { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" }, 527 { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" }, 528 { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" }, 529 { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" }, 530 { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" }, 531 { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" }, 532 { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" }, 533 { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" }, 534 { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" }, 535}; 536 537static struct reg_names scalar_names[] = { 538 { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" }, 539 { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" }, 540 { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" }, 541 { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" }, 542 { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" }, 543 { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" }, 544 { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" }, 545 { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" }, 546 { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" }, 547 { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" }, 548 { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" }, 549 { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" }, 550 { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" }, 551 { 1000, "" }, 552}; 553 554/* Puff these out to make them look like normal (dword) registers. 555 */ 556static struct reg_names vector_names[] = { 557 { 0, "start" }, 558 { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" }, 559 { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" }, 560 { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" }, 561 { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" }, 562 { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" }, 563 { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" }, 564 { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" }, 565 { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" }, 566 { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" }, 567 { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" }, 568 { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" }, 569 { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" }, 570 { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" }, 571 { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" }, 572 { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" }, 573 { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" }, 574 { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" }, 575 { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" }, 576 { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" }, 577 { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" }, 578 { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" }, 579 { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" }, 580 { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" }, 581 { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" }, 582 { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" }, 583 { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" }, 584 { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" }, 585 { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" }, 586 { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" }, 587 { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" }, 588 { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" }, 589 { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" }, 590 { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" }, 591 { R200_VS_MAX, "R200_VS_MAX" }, 592 { 1000, "" }, 593}; 594 595union fi { float f; int i; }; 596 597#define ISVEC 1 598#define ISFLOAT 2 599#define TOUCHED 4 600 601struct reg { 602 int idx; 603 struct reg_names *closest; 604 int flags; 605 union fi current; 606 union fi *values; 607 int nvalues; 608 int nalloc; 609 float vmin, vmax; 610}; 611 612 613static struct reg regs[Elements(reg_names)+1]; 614static struct reg scalars[512+1]; 615static struct reg vectors[512*4+1]; 616 617static int total, total_changed, bufs; 618 619static void init_regs( void ) 620{ 621 struct reg_names *tmp; 622 int i; 623 624 for (i = 0 ; i < Elements(regs) ; i++) { 625 regs[i].idx = reg_names[i].idx; 626 regs[i].closest = ®_names[i]; 627 regs[i].flags = 0; 628 } 629 630 for (i = 0, tmp = scalar_names ; i < Elements(scalars) ; i++) { 631 if (tmp[1].idx == i) tmp++; 632 scalars[i].idx = i; 633 scalars[i].closest = tmp; 634 scalars[i].flags = ISFLOAT; 635 } 636 637 for (i = 0, tmp = vector_names ; i < Elements(vectors) ; i++) { 638 if (tmp[1].idx*4 == i) tmp++; 639 vectors[i].idx = i; 640 vectors[i].closest = tmp; 641 vectors[i].flags = ISFLOAT|ISVEC; 642 } 643 644 regs[Elements(regs)-1].idx = -1; 645 scalars[Elements(scalars)-1].idx = -1; 646 vectors[Elements(vectors)-1].idx = -1; 647} 648 649static int find_or_add_value( struct reg *reg, int val ) 650{ 651 int j; 652 653 for ( j = 0 ; j < reg->nvalues ; j++) 654 if ( val == reg->values[j].i ) 655 return 1; 656 657 if (j == reg->nalloc) { 658 reg->nalloc += 5; 659 reg->nalloc *= 2; 660 reg->values = (union fi *) realloc( reg->values, 661 reg->nalloc * sizeof(union fi) ); 662 } 663 664 reg->values[reg->nvalues++].i = val; 665 return 0; 666} 667 668static struct reg *lookup_reg( struct reg *tab, int reg ) 669{ 670 int i; 671 672 for (i = 0 ; tab[i].idx != -1 ; i++) { 673 if (tab[i].idx == reg) 674 return &tab[i]; 675 } 676 677 fprintf(stderr, "*** unknown reg 0x%x\n", reg); 678 return NULL; 679} 680 681 682static const char *get_reg_name( struct reg *reg ) 683{ 684 static char tmp[80]; 685 686 if (reg->idx == reg->closest->idx) 687 return reg->closest->name; 688 689 690 if (reg->flags & ISVEC) { 691 if (reg->idx/4 != reg->closest->idx) 692 sprintf(tmp, "%s+%d[%d]", 693 reg->closest->name, 694 (reg->idx/4) - reg->closest->idx, 695 reg->idx%4); 696 else 697 sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4); 698 } 699 else { 700 if (reg->idx != reg->closest->idx) 701 sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx); 702 else 703 sprintf(tmp, "%s", reg->closest->name); 704 } 705 706 return tmp; 707} 708 709static int print_int_reg_assignment( struct reg *reg, int data ) 710{ 711 int changed = (reg->current.i != data); 712 int ever_seen = find_or_add_value( reg, data ); 713 714 if (VERBOSE || (NORMAL && (changed || !ever_seen))) 715 fprintf(stderr, " %s <-- 0x%x", get_reg_name(reg), data); 716 717 if (NORMAL) { 718 if (!ever_seen) 719 fprintf(stderr, " *** BRAND NEW VALUE"); 720 else if (changed) 721 fprintf(stderr, " *** CHANGED"); 722 } 723 724 reg->current.i = data; 725 726 if (VERBOSE || (NORMAL && (changed || !ever_seen))) 727 fprintf(stderr, "\n"); 728 729 return changed; 730} 731 732 733static int print_float_reg_assignment( struct reg *reg, float data ) 734{ 735 int changed = (reg->current.f != data); 736 int newmin = (data < reg->vmin); 737 int newmax = (data > reg->vmax); 738 739 if (VERBOSE || (NORMAL && (newmin || newmax || changed))) 740 fprintf(stderr, " %s <-- %.3f", get_reg_name(reg), data); 741 742 if (NORMAL) { 743 if (newmin) { 744 fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin); 745 reg->vmin = data; 746 } 747 else if (newmax) { 748 fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax); 749 reg->vmax = data; 750 } 751 else if (changed) { 752 fprintf(stderr, " *** CHANGED"); 753 } 754 } 755 756 reg->current.f = data; 757 758 if (VERBOSE || (NORMAL && (newmin || newmax || changed))) 759 fprintf(stderr, "\n"); 760 761 return changed; 762} 763 764static int print_reg_assignment( struct reg *reg, int data ) 765{ 766 reg->flags |= TOUCHED; 767 if (reg->flags & ISFLOAT) 768 return print_float_reg_assignment( reg, *(float *)&data ); 769 else 770 return print_int_reg_assignment( reg, data ); 771} 772 773static void print_reg( struct reg *reg ) 774{ 775 if (reg->flags & TOUCHED) { 776 if (reg->flags & ISFLOAT) { 777 fprintf(stderr, " %s == %f\n", get_reg_name(reg), reg->current.f); 778 } else { 779 fprintf(stderr, " %s == 0x%x\n", get_reg_name(reg), reg->current.i); 780 } 781 } 782} 783 784 785static void dump_state( void ) 786{ 787 int i; 788 789 for (i = 0 ; i < Elements(regs) ; i++) 790 print_reg( ®s[i] ); 791 792 for (i = 0 ; i < Elements(scalars) ; i++) 793 print_reg( &scalars[i] ); 794 795 for (i = 0 ; i < Elements(vectors) ; i++) 796 print_reg( &vectors[i] ); 797} 798 799 800 801static int radeon_emit_packets( 802 drm_radeon_cmd_header_t header, 803 drm_radeon_cmd_buffer_t *cmdbuf ) 804{ 805 int id = (int)header.packet.packet_id; 806 int sz = packet[id].len; 807 int *data = (int *)cmdbuf->buf; 808 int i; 809 810 if (sz * sizeof(int) > cmdbuf->bufsz) { 811 fprintf(stderr, "Packet overflows cmdbuf\n"); 812 return -EINVAL; 813 } 814 815 if (!packet[id].name) { 816 fprintf(stderr, "*** Unknown packet 0 nr %d\n", id ); 817 return -EINVAL; 818 } 819 820 821 if (VERBOSE) 822 fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz ); 823 824 for ( i = 0 ; i < sz ; i++) { 825 struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); 826 if (print_reg_assignment( reg, data[i] )) 827 total_changed++; 828 total++; 829 } 830 831 cmdbuf->buf += sz * sizeof(int); 832 cmdbuf->bufsz -= sz * sizeof(int); 833 return 0; 834} 835 836 837static int radeon_emit_scalars( 838 drm_radeon_cmd_header_t header, 839 drm_radeon_cmd_buffer_t *cmdbuf ) 840{ 841 int sz = header.scalars.count; 842 int *data = (int *)cmdbuf->buf; 843 int start = header.scalars.offset; 844 int stride = header.scalars.stride; 845 int i; 846 847 if (VERBOSE) 848 fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n", 849 start, stride, sz, start + stride * sz); 850 851 852 for (i = 0 ; i < sz ; i++, start += stride) { 853 struct reg *reg = lookup_reg( scalars, start ); 854 if (print_reg_assignment( reg, data[i] )) 855 total_changed++; 856 total++; 857 } 858 859 cmdbuf->buf += sz * sizeof(int); 860 cmdbuf->bufsz -= sz * sizeof(int); 861 return 0; 862} 863 864 865static int radeon_emit_scalars2( 866 drm_radeon_cmd_header_t header, 867 drm_radeon_cmd_buffer_t *cmdbuf ) 868{ 869 int sz = header.scalars.count; 870 int *data = (int *)cmdbuf->buf; 871 int start = header.scalars.offset + 0x100; 872 int stride = header.scalars.stride; 873 int i; 874 875 if (VERBOSE) 876 fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n", 877 start, stride, sz, start + stride * sz); 878 879 if (start + stride * sz > 258) { 880 fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz); 881 return -1; 882 } 883 884 for (i = 0 ; i < sz ; i++, start += stride) { 885 struct reg *reg = lookup_reg( scalars, start ); 886 if (print_reg_assignment( reg, data[i] )) 887 total_changed++; 888 total++; 889 } 890 891 cmdbuf->buf += sz * sizeof(int); 892 cmdbuf->bufsz -= sz * sizeof(int); 893 return 0; 894} 895 896/* Check: inf/nan/extreme-size? 897 * Check: table start, end, nr, etc. 898 */ 899static int radeon_emit_vectors( 900 drm_radeon_cmd_header_t header, 901 drm_radeon_cmd_buffer_t *cmdbuf ) 902{ 903 int sz = header.vectors.count; 904 int *data = (int *)cmdbuf->buf; 905 int start = header.vectors.offset; 906 int stride = header.vectors.stride; 907 int i,j; 908 909 if (VERBOSE) 910 fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n", 911 start, stride, sz, start + stride * sz, header.i); 912 913/* if (start + stride * (sz/4) > 128) { */ 914/* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */ 915/* return -1; */ 916/* } */ 917 918 for (i = 0 ; i < sz ; start += stride) { 919 int changed = 0; 920 for (j = 0 ; j < 4 ; i++,j++) { 921 struct reg *reg = lookup_reg( vectors, start*4+j ); 922 if (print_reg_assignment( reg, data[i] )) 923 changed = 1; 924 } 925 if (changed) 926 total_changed += 4; 927 total += 4; 928 } 929 930 931 cmdbuf->buf += sz * sizeof(int); 932 cmdbuf->bufsz -= sz * sizeof(int); 933 return 0; 934} 935 936#if 0 937static int print_vertex_format( int vfmt ) 938{ 939 if (NORMAL) { 940 fprintf(stderr, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 941 "vertex format", 942 vfmt, 943 "xy,", 944 (vfmt & R200_VTX_Z0) ? "z," : "", 945 (vfmt & R200_VTX_W0) ? "w0," : "", 946 (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "", 947 (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "", 948 (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "", 949 (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "", 950 (vfmt & R200_VTX_FPFOG) ? "fpfog," : "", 951 (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "", 952 (vfmt & R200_VTX_ST0) ? "st0," : "", 953 (vfmt & R200_VTX_ST1) ? "st1," : "", 954 (vfmt & R200_VTX_Q1) ? "q1," : "", 955 (vfmt & R200_VTX_ST2) ? "st2," : "", 956 (vfmt & R200_VTX_Q2) ? "q2," : "", 957 (vfmt & R200_VTX_ST3) ? "st3," : "", 958 (vfmt & R200_VTX_Q3) ? "q3," : "", 959 (vfmt & R200_VTX_Q0) ? "q0," : "", 960 (vfmt & R200_VTX_N0) ? "n0," : "", 961 (vfmt & R200_VTX_XY1) ? "xy1," : "", 962 (vfmt & R200_VTX_Z1) ? "z1," : "", 963 (vfmt & R200_VTX_W1) ? "w1," : "", 964 (vfmt & R200_VTX_N1) ? "n1," : ""); 965 966 967 if (!find_or_add_value( &others[V_VTXFMT], vfmt )) 968 fprintf(stderr, " *** NEW VALUE"); 969 970 fprintf(stderr, "\n"); 971 } 972 973 return 0; 974} 975#endif 976 977static char *primname[0x10] = { 978 "NONE", 979 "POINTS", 980 "LINES", 981 "LINE_STRIP", 982 "TRIANGLES", 983 "TRIANGLE_FAN", 984 "TRIANGLE_STRIP", 985 "RECT_LIST", 986 NULL, 987 "3VRT_POINTS", 988 "3VRT_LINES", 989 "POINT_SPRITES", 990 "LINE_LOOP", 991 "QUADS", 992 "QUAD_STRIP", 993 "POLYGON", 994}; 995 996static int print_prim_and_flags( int prim ) 997{ 998 int numverts; 999 1000 if (NORMAL) 1001 fprintf(stderr, " %s(%x): %s%s%s%s%s%s\n", 1002 "prim flags", 1003 prim, 1004 ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "", 1005 ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "", 1006 ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "", 1007 (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ", 1008 (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "", 1009 (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : ""); 1010 1011 numverts = prim>>16; 1012 1013 if (NORMAL) 1014 fprintf(stderr, " prim: %s numverts %d\n", primname[prim&0xf], numverts); 1015 1016 switch (prim & 0xf) { 1017 case R200_VF_PRIM_NONE: 1018 case R200_VF_PRIM_POINTS: 1019 if (numverts < 1) { 1020 fprintf(stderr, "Bad nr verts for line %d\n", numverts); 1021 return -1; 1022 } 1023 break; 1024 case R200_VF_PRIM_LINES: 1025 case R200_VF_PRIM_POINT_SPRITES: 1026 if ((numverts & 1) || numverts == 0) { 1027 fprintf(stderr, "Bad nr verts for line %d\n", numverts); 1028 return -1; 1029 } 1030 break; 1031 case R200_VF_PRIM_LINE_STRIP: 1032 case R200_VF_PRIM_LINE_LOOP: 1033 if (numverts < 2) { 1034 fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts); 1035 return -1; 1036 } 1037 break; 1038 case R200_VF_PRIM_TRIANGLES: 1039 case R200_VF_PRIM_3VRT_POINTS: 1040 case R200_VF_PRIM_3VRT_LINES: 1041 case R200_VF_PRIM_RECT_LIST: 1042 if (numverts % 3 || numverts == 0) { 1043 fprintf(stderr, "Bad nr verts for tri %d\n", numverts); 1044 return -1; 1045 } 1046 break; 1047 case R200_VF_PRIM_TRIANGLE_FAN: 1048 case R200_VF_PRIM_TRIANGLE_STRIP: 1049 case R200_VF_PRIM_POLYGON: 1050 if (numverts < 3) { 1051 fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts); 1052 return -1; 1053 } 1054 break; 1055 case R200_VF_PRIM_QUADS: 1056 if (numverts % 4 || numverts == 0) { 1057 fprintf(stderr, "Bad nr verts for quad %d\n", numverts); 1058 return -1; 1059 } 1060 break; 1061 case R200_VF_PRIM_QUAD_STRIP: 1062 if (numverts % 2 || numverts < 4) { 1063 fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts); 1064 return -1; 1065 } 1066 break; 1067 default: 1068 fprintf(stderr, "Bad primitive\n"); 1069 return -1; 1070 } 1071 return 0; 1072} 1073 1074/* build in knowledge about each packet type 1075 */ 1076static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) 1077{ 1078 int cmdsz; 1079 int *cmd = (int *)cmdbuf->buf; 1080 int *tmp; 1081 int i, stride, size, start; 1082 1083 cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); 1084 1085 if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 || 1086 cmdsz * 4 > cmdbuf->bufsz || 1087 cmdsz > RADEON_CP_PACKET_MAX_DWORDS) { 1088 fprintf(stderr, "Bad packet\n"); 1089 return -EINVAL; 1090 } 1091 1092 switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) { 1093 case R200_CP_CMD_NOP: 1094 if (NORMAL) 1095 fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz); 1096 break; 1097 case R200_CP_CMD_NEXT_CHAR: 1098 if (NORMAL) 1099 fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz); 1100 break; 1101 case R200_CP_CMD_PLY_NEXTSCAN: 1102 if (NORMAL) 1103 fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz); 1104 break; 1105 case R200_CP_CMD_SET_SCISSORS: 1106 if (NORMAL) 1107 fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz); 1108 break; 1109 case R200_CP_CMD_LOAD_MICROCODE: 1110 if (NORMAL) 1111 fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz); 1112 break; 1113 case R200_CP_CMD_WAIT_FOR_IDLE: 1114 if (NORMAL) 1115 fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz); 1116 break; 1117 1118 case R200_CP_CMD_3D_DRAW_VBUF: 1119 if (NORMAL) 1120 fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz); 1121/* print_vertex_format(cmd[1]); */ 1122 if (print_prim_and_flags(cmd[2])) 1123 return -EINVAL; 1124 break; 1125 1126 case R200_CP_CMD_3D_DRAW_IMMD: 1127 if (NORMAL) 1128 fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz); 1129 break; 1130 case R200_CP_CMD_3D_DRAW_INDX: { 1131 int neltdwords; 1132 if (NORMAL) 1133 fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz); 1134/* print_vertex_format(cmd[1]); */ 1135 if (print_prim_and_flags(cmd[2])) 1136 return -EINVAL; 1137 neltdwords = cmd[2]>>16; 1138 neltdwords += neltdwords & 1; 1139 neltdwords /= 2; 1140 if (neltdwords + 3 != cmdsz) 1141 fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n", 1142 neltdwords, cmdsz); 1143 break; 1144 } 1145 case R200_CP_CMD_LOAD_PALETTE: 1146 if (NORMAL) 1147 fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz); 1148 break; 1149 case R200_CP_CMD_3D_LOAD_VBPNTR: 1150 if (NORMAL) { 1151 fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz); 1152 fprintf(stderr, " nr arrays: %d\n", cmd[1]); 1153 } 1154 1155 if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) { 1156 fprintf(stderr, " ****** MISMATCH %d/%d *******\n", 1157 ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz); 1158 return -EINVAL; 1159 } 1160 1161 if (NORMAL) { 1162 tmp = cmd+2; 1163 for (i = 0 ; i < cmd[1] ; i++) { 1164 if (i & 1) { 1165 stride = (tmp[0]>>24) & 0xff; 1166 size = (tmp[0]>>16) & 0xff; 1167 start = tmp[2]; 1168 tmp += 3; 1169 } 1170 else { 1171 stride = (tmp[0]>>8) & 0xff; 1172 size = (tmp[0]) & 0xff; 1173 start = tmp[1]; 1174 } 1175 fprintf(stderr, " array %d: start 0x%x vsize %d vstride %d\n", 1176 i, start, size, stride ); 1177 } 1178 } 1179 break; 1180 case R200_CP_CMD_PAINT: 1181 if (NORMAL) 1182 fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz); 1183 break; 1184 case R200_CP_CMD_BITBLT: 1185 if (NORMAL) 1186 fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz); 1187 break; 1188 case R200_CP_CMD_SMALLTEXT: 1189 if (NORMAL) 1190 fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz); 1191 break; 1192 case R200_CP_CMD_HOSTDATA_BLT: 1193 if (NORMAL) 1194 fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n", 1195 cmdsz); 1196 break; 1197 case R200_CP_CMD_POLYLINE: 1198 if (NORMAL) 1199 fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz); 1200 break; 1201 case R200_CP_CMD_POLYSCANLINES: 1202 if (NORMAL) 1203 fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n", 1204 cmdsz); 1205 break; 1206 case R200_CP_CMD_PAINT_MULTI: 1207 if (NORMAL) 1208 fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n", 1209 cmdsz); 1210 break; 1211 case R200_CP_CMD_BITBLT_MULTI: 1212 if (NORMAL) 1213 fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n", 1214 cmdsz); 1215 break; 1216 case R200_CP_CMD_TRANS_BITBLT: 1217 if (NORMAL) 1218 fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n", 1219 cmdsz); 1220 break; 1221 case R200_CP_CMD_3D_DRAW_VBUF_2: 1222 if (NORMAL) 1223 fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n", 1224 cmdsz); 1225 if (print_prim_and_flags(cmd[1])) 1226 return -EINVAL; 1227 break; 1228 case R200_CP_CMD_3D_DRAW_IMMD_2: 1229 if (NORMAL) 1230 fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n", 1231 cmdsz); 1232 if (print_prim_and_flags(cmd[1])) 1233 return -EINVAL; 1234 break; 1235 case R200_CP_CMD_3D_DRAW_INDX_2: 1236 if (NORMAL) 1237 fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n", 1238 cmdsz); 1239 if (print_prim_and_flags(cmd[1])) 1240 return -EINVAL; 1241 break; 1242 default: 1243 fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz); 1244 break; 1245 } 1246 1247 cmdbuf->buf += cmdsz * 4; 1248 cmdbuf->bufsz -= cmdsz * 4; 1249 return 0; 1250} 1251 1252 1253/* Check cliprects for bounds, then pass on to above: 1254 */ 1255static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf ) 1256{ 1257 drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes; 1258 int i = 0; 1259 1260 if (VERBOSE && total_changed) { 1261 dump_state(); 1262 total_changed = 0; 1263 } 1264 1265 if (NORMAL) { 1266 do { 1267 if ( i < cmdbuf->nbox ) { 1268 fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n", 1269 i, cmdbuf->nbox, 1270 boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2); 1271 } 1272 } while ( ++i < cmdbuf->nbox ); 1273 } 1274 1275 if (cmdbuf->nbox == 1) 1276 cmdbuf->nbox = 0; 1277 1278 return radeon_emit_packet3( cmdbuf ); 1279} 1280 1281 1282int r200SanityCmdBuffer( r200ContextPtr rmesa, 1283 int nbox, 1284 drm_clip_rect_t *boxes ) 1285{ 1286 int idx; 1287 drm_radeon_cmd_buffer_t cmdbuf; 1288 drm_radeon_cmd_header_t header; 1289 static int inited = 0; 1290 1291 if (!inited) { 1292 init_regs(); 1293 inited = 1; 1294 } 1295 1296 1297 cmdbuf.buf = rmesa->store.cmd_buf; 1298 cmdbuf.bufsz = rmesa->store.cmd_used; 1299 cmdbuf.boxes = (drm_clip_rect_t *)boxes; 1300 cmdbuf.nbox = nbox; 1301 1302 while ( cmdbuf.bufsz >= sizeof(header) ) { 1303 1304 header.i = *(int *)cmdbuf.buf; 1305 cmdbuf.buf += sizeof(header); 1306 cmdbuf.bufsz -= sizeof(header); 1307 1308 switch (header.header.cmd_type) { 1309 case RADEON_CMD_PACKET: 1310 if (radeon_emit_packets( header, &cmdbuf )) { 1311 fprintf(stderr,"radeon_emit_packets failed\n"); 1312 return -EINVAL; 1313 } 1314 break; 1315 1316 case RADEON_CMD_SCALARS: 1317 if (radeon_emit_scalars( header, &cmdbuf )) { 1318 fprintf(stderr,"radeon_emit_scalars failed\n"); 1319 return -EINVAL; 1320 } 1321 break; 1322 1323 case RADEON_CMD_SCALARS2: 1324 if (radeon_emit_scalars2( header, &cmdbuf )) { 1325 fprintf(stderr,"radeon_emit_scalars failed\n"); 1326 return -EINVAL; 1327 } 1328 break; 1329 1330 case RADEON_CMD_VECTORS: 1331 if (radeon_emit_vectors( header, &cmdbuf )) { 1332 fprintf(stderr,"radeon_emit_vectors failed\n"); 1333 return -EINVAL; 1334 } 1335 break; 1336 1337 case RADEON_CMD_DMA_DISCARD: 1338 idx = header.dma.buf_idx; 1339 if (NORMAL) 1340 fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx); 1341 bufs++; 1342 break; 1343 1344 case RADEON_CMD_PACKET3: 1345 if (radeon_emit_packet3( &cmdbuf )) { 1346 fprintf(stderr,"radeon_emit_packet3 failed\n"); 1347 return -EINVAL; 1348 } 1349 break; 1350 1351 case RADEON_CMD_PACKET3_CLIP: 1352 if (radeon_emit_packet3_cliprect( &cmdbuf )) { 1353 fprintf(stderr,"radeon_emit_packet3_clip failed\n"); 1354 return -EINVAL; 1355 } 1356 break; 1357 1358 case RADEON_CMD_WAIT: 1359 break; 1360 1361 default: 1362 fprintf(stderr,"bad cmd_type %d at %p\n", 1363 header.header.cmd_type, 1364 cmdbuf.buf - sizeof(header)); 1365 return -EINVAL; 1366 } 1367 } 1368 1369 if (0) 1370 { 1371 static int n = 0; 1372 n++; 1373 if (n == 10) { 1374 fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n", 1375 bufs, 1376 total, total_changed, 1377 ((float)total_changed/(float)total*100.0)); 1378 fprintf(stderr, "Total emitted per buf: %.2f\n", 1379 (float)total/(float)bufs); 1380 fprintf(stderr, "Real changes per buf: %.2f\n", 1381 (float)total_changed/(float)bufs); 1382 1383 bufs = n = total = total_changed = 0; 1384 } 1385 } 1386 1387 fprintf(stderr, "leaving %s\n\n\n", __FUNCTION__); 1388 1389 return 0; 1390} 1391