r200_state_init.c revision 76a9831b2b20d59c49b5f25ba5275f17b4e2067b
1/* 2Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4The Weather Channel (TM) funded Tungsten Graphics to develop the 5initial release of the Radeon 8500 driver under the XFree86 license. 6This notice must be preserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27*/ 28 29/* 30 * Authors: 31 * Keith Whitwell <keith@tungstengraphics.com> 32 */ 33 34#include "main/glheader.h" 35#include "main/imports.h" 36#include "main/enums.h" 37#include "main/colormac.h" 38#include "main/api_arrayelt.h" 39 40#include "swrast/swrast.h" 41#include "vbo/vbo.h" 42#include "tnl/t_pipeline.h" 43#include "swrast_setup/swrast_setup.h" 44 45#include "radeon_common.h" 46#include "radeon_mipmap_tree.h" 47#include "r200_context.h" 48#include "r200_ioctl.h" 49#include "r200_state.h" 50#include "radeon_queryobj.h" 51 52#include "xmlpool.h" 53 54/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in 55 * 1.3 cmdbuffers allow all previous state to be updated as well as 56 * the tcl scalar and vector areas. 57 */ 58static struct { 59 int start; 60 int len; 61 const char *name; 62} packet[RADEON_MAX_STATE_PACKETS] = { 63 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, 64 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, 65 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, 66 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, 67 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, 68 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, 69 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, 70 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, 71 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, 72 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, 73 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, 74 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, 75 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, 76 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, 77 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, 78 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, 79 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, 80 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, 81 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, 82 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, 83 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, 84 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, 85 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, 86 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, 87 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, 88 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, 89 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, 90 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, 91 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, 92 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, 93 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, 94 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, 95 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, 96 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, 97 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, 98 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, 99 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, 100 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, 101 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, 102 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, 103 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, 104 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, 105 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, 106 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, 107 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, 108 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, 109 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, 110 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, 111 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, 112 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, 113 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, 114 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, 115 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, 116 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, 117 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, 118 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, 119 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, 120 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, 121 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, 122 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, 123 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, 124 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, 125 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, 126 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, 127 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ 128 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ 129 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, 130 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, 131 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, 132 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, 133 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, 134 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, 135 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, 136 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, 137 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, 138 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, 139 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, 140 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, 141 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, 142 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, 143 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, 144 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, 145 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, 146 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, 147 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, 148 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, 149 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, 150 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, 151 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ 152 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, 153 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, 154 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, 155 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, 156 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, 157 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, 158 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, 159 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, 160 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, 161}; 162 163/* ============================================================= 164 * State initialization 165 */ 166static int cmdpkt( r200ContextPtr rmesa, int id ) 167{ 168 drm_radeon_cmd_header_t h; 169 170 if (rmesa->radeon.radeonScreen->kernel_mm) { 171 return CP_PACKET0(packet[id].start, packet[id].len - 1); 172 } else { 173 h.i = 0; 174 h.packet.cmd_type = RADEON_CMD_PACKET; 175 h.packet.packet_id = id; 176 } 177 return h.i; 178} 179 180static int cmdvec( int offset, int stride, int count ) 181{ 182 drm_radeon_cmd_header_t h; 183 h.i = 0; 184 h.vectors.cmd_type = RADEON_CMD_VECTORS; 185 h.vectors.offset = offset; 186 h.vectors.stride = stride; 187 h.vectors.count = count; 188 return h.i; 189} 190 191/* warning: the count here is divided by 4 compared to other cmds 192 (so it doesn't exceed the char size)! */ 193static int cmdveclinear( int offset, int count ) 194{ 195 drm_radeon_cmd_header_t h; 196 h.i = 0; 197 h.veclinear.cmd_type = RADEON_CMD_VECLINEAR; 198 h.veclinear.addr_lo = offset & 0xff; 199 h.veclinear.addr_hi = (offset & 0xff00) >> 8; 200 h.veclinear.count = count; 201 return h.i; 202} 203 204static int cmdscl( int offset, int stride, int count ) 205{ 206 drm_radeon_cmd_header_t h; 207 h.i = 0; 208 h.scalars.cmd_type = RADEON_CMD_SCALARS; 209 h.scalars.offset = offset; 210 h.scalars.stride = stride; 211 h.scalars.count = count; 212 return h.i; 213} 214 215static int cmdscl2( int offset, int stride, int count ) 216{ 217 drm_radeon_cmd_header_t h; 218 h.i = 0; 219 h.scalars.cmd_type = RADEON_CMD_SCALARS2; 220 h.scalars.offset = offset - 0x100; 221 h.scalars.stride = stride; 222 h.scalars.count = count; 223 return h.i; 224} 225 226/** 227 * Check functions are used to check if state is active. 228 * If it is active check function returns maximum emit size. 229 */ 230#define CHECK( NM, FLAG, ADD ) \ 231static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ 232{ \ 233 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 234 (void) rmesa; \ 235 return (FLAG) ? atom->cmd_size + (ADD) : 0; \ 236} 237 238#define TCL_CHECK( NM, FLAG, ADD ) \ 239static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom) \ 240{ \ 241 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 242 return (!rmesa->radeon.TclFallback && !ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 243} 244 245#define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \ 246static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ 247{ \ 248 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 249 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 250} 251 252#define VP_CHECK( NM, FLAG, ADD ) \ 253static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \ 254{ \ 255 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 256 (void) atom; \ 257 return (!rmesa->radeon.TclFallback && ctx->VertexProgram._Enabled && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ 258} 259 260CHECK( always, GL_TRUE, 0 ) 261CHECK( always_add4, GL_TRUE, 4 ) 262CHECK( never, GL_FALSE, 0 ) 263CHECK( tex_any, ctx->Texture._EnabledUnits, 0 ) 264CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled), 0 ); 265CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled, 0 ) 266 CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !ctx->ATIFragmentShader._Enabled), 0 ) 267CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 ) 268CHECK( afs, ctx->ATIFragmentShader._Enabled, 0 ) 269CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE ) 270CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE ) 271TCL_CHECK( tcl_fog, ctx->Fog.Enabled, 0 ) 272TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 ) 273TCL_CHECK( tcl, GL_TRUE, 0 ) 274TCL_CHECK( tcl_add8, GL_TRUE, 8 ) 275TCL_CHECK( tcl_add4, GL_TRUE, 4 ) 276TCL_CHECK( tcl_tex, rmesa->state.texture.unit[atom->idx].unitneeded, 0 ) 277TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 ) 278TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 0 ) 279TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 ) 280TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) 281TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 ) 282TCL_CHECK( tcl_light_add8, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 8 ) 283TCL_OR_VP_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 0 ) 284TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 ) 285TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 ) 286TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 ) 287VP_CHECK( tcl_vp, GL_TRUE, 0 ) 288VP_CHECK( tcl_vp_add4, GL_TRUE, 4 ) 289VP_CHECK( tcl_vp_size, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 0 ) 290VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 0 ) 291VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->Base.NumNativeInstructions > 64, 4 ) 292VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->Base.NumNativeParameters > 96, 4 ) 293 294#define OUT_VEC(hdr, data) do { \ 295 drm_radeon_cmd_header_t h; \ 296 h.i = hdr; \ 297 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 298 OUT_BATCH(0); \ 299 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 300 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 301 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ 302 OUT_BATCH_TABLE((data), h.vectors.count); \ 303 } while(0) 304 305#define OUT_VECLINEAR(hdr, data) do { \ 306 drm_radeon_cmd_header_t h; \ 307 uint32_t _start, _sz; \ 308 h.i = hdr; \ 309 _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ 310 _sz = h.veclinear.count * 4; \ 311 if (r200->radeon.radeonScreen->kernel_mm && _sz) { \ 312 BEGIN_BATCH_NO_AUTOSTATE(dwords); \ 313 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ 314 OUT_BATCH(0); \ 315 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ 316 OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ 317 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \ 318 OUT_BATCH_TABLE((data), _sz); \ 319 END_BATCH(); \ 320 } \ 321 } while(0) 322 323#define OUT_SCL(hdr, data) do { \ 324 drm_radeon_cmd_header_t h; \ 325 h.i = hdr; \ 326 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 327 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 328 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 329 OUT_BATCH_TABLE((data), h.scalars.count); \ 330 } while(0) 331 332#define OUT_SCL2(hdr, data) do { \ 333 drm_radeon_cmd_header_t h; \ 334 h.i = hdr; \ 335 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ 336 OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ 337 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ 338 OUT_BATCH_TABLE((data), h.scalars.count); \ 339 } while(0) 340static int check_rrb(GLcontext *ctx, struct radeon_state_atom *atom) 341{ 342 r200ContextPtr r200 = R200_CONTEXT(ctx); 343 struct radeon_renderbuffer *rrb; 344 rrb = radeon_get_colorbuffer(&r200->radeon); 345 if (!rrb || !rrb->bo) 346 return 0; 347 return atom->cmd_size; 348} 349 350static int check_polygon_stipple(GLcontext *ctx, 351 struct radeon_state_atom *atom) 352{ 353 r200ContextPtr r200 = R200_CONTEXT(ctx); 354 if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) 355 return atom->cmd_size; 356 return 0; 357} 358 359static void mtl_emit(GLcontext *ctx, struct radeon_state_atom *atom) 360{ 361 r200ContextPtr r200 = R200_CONTEXT(ctx); 362 BATCH_LOCALS(&r200->radeon); 363 uint32_t dwords = atom->check(ctx, atom); 364 365 BEGIN_BATCH_NO_AUTOSTATE(dwords); 366 OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); 367 OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); 368 END_BATCH(); 369} 370 371static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom) 372{ 373 r200ContextPtr r200 = R200_CONTEXT(ctx); 374 BATCH_LOCALS(&r200->radeon); 375 uint32_t dwords = atom->check(ctx, atom); 376 377 BEGIN_BATCH_NO_AUTOSTATE(dwords); 378 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); 379 OUT_VEC(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); 380 END_BATCH(); 381} 382 383static void ptp_emit(GLcontext *ctx, struct radeon_state_atom *atom) 384{ 385 r200ContextPtr r200 = R200_CONTEXT(ctx); 386 BATCH_LOCALS(&r200->radeon); 387 uint32_t dwords = atom->check(ctx, atom); 388 389 BEGIN_BATCH_NO_AUTOSTATE(dwords); 390 OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); 391 OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); 392 END_BATCH(); 393} 394 395static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) 396{ 397 r200ContextPtr r200 = R200_CONTEXT(ctx); 398 BATCH_LOCALS(&r200->radeon); 399 uint32_t dwords = atom->check(ctx, atom); 400 401 OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); 402} 403 404static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) 405{ 406 r200ContextPtr r200 = R200_CONTEXT(ctx); 407 BATCH_LOCALS(&r200->radeon); 408 uint32_t dwords = atom->check(ctx, atom); 409 410 BEGIN_BATCH_NO_AUTOSTATE(dwords); 411 OUT_SCL(atom->cmd[0], atom->cmd+1); 412 END_BATCH(); 413} 414 415 416static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom) 417{ 418 r200ContextPtr r200 = R200_CONTEXT(ctx); 419 BATCH_LOCALS(&r200->radeon); 420 uint32_t dwords = atom->check(ctx, atom); 421 422 BEGIN_BATCH_NO_AUTOSTATE(dwords); 423 OUT_VEC(atom->cmd[0], atom->cmd+1); 424 END_BATCH(); 425} 426 427static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom) 428{ 429 r200ContextPtr r200 = R200_CONTEXT(ctx); 430 BATCH_LOCALS(&r200->radeon); 431 struct radeon_renderbuffer *rrb; 432 uint32_t cbpitch; 433 uint32_t zbpitch, depth_fmt; 434 uint32_t dwords = atom->check(ctx, atom); 435 436 /* output the first 7 bytes of context */ 437 BEGIN_BATCH_NO_AUTOSTATE(dwords); 438 OUT_BATCH_TABLE(atom->cmd, 5); 439 440 rrb = radeon_get_depthbuffer(&r200->radeon); 441 if (!rrb) { 442 OUT_BATCH(0); 443 OUT_BATCH(0); 444 } else { 445 zbpitch = (rrb->pitch / rrb->cpp); 446 if (r200->using_hyperz) 447 zbpitch |= RADEON_DEPTH_HYPERZ; 448 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 449 OUT_BATCH(zbpitch); 450 if (rrb->cpp == 4) 451 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 452 else 453 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 454 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 455 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 456 } 457 458 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 459 OUT_BATCH(atom->cmd[CTX_CMD_1]); 460 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 461 462 rrb = radeon_get_colorbuffer(&r200->radeon); 463 if (!rrb || !rrb->bo) { 464 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 465 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]); 466 } else { 467 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 468 if (rrb->cpp == 4) 469 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 470 else 471 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 472 473 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 474 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 475 } 476 477 OUT_BATCH(atom->cmd[CTX_CMD_2]); 478 479 if (!rrb || !rrb->bo) { 480 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]); 481 } else { 482 cbpitch = (rrb->pitch / rrb->cpp); 483 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 484 cbpitch |= R200_COLOR_TILE_ENABLE; 485 OUT_BATCH(cbpitch); 486 } 487 488 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) 489 OUT_BATCH_TABLE((atom->cmd + 14), 4); 490 491 END_BATCH(); 492} 493 494static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom) 495{ 496 r200ContextPtr r200 = R200_CONTEXT(ctx); 497 struct radeon_renderbuffer *rrb, *drb; 498 uint32_t dwords; 499 500 rrb = radeon_get_colorbuffer(&r200->radeon); 501 if (!rrb || !rrb->bo) { 502 return 0; 503 } 504 505 drb = radeon_get_depthbuffer(&r200->radeon); 506 507 dwords = 10; 508 if (drb) 509 dwords += 6; 510 if (rrb) 511 dwords += 8; 512 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) 513 dwords += 4; 514 515 516 return dwords; 517} 518 519static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) 520{ 521 r200ContextPtr r200 = R200_CONTEXT(ctx); 522 BATCH_LOCALS(&r200->radeon); 523 struct radeon_renderbuffer *rrb, *drb; 524 uint32_t cbpitch = 0; 525 uint32_t zbpitch = 0; 526 uint32_t dwords = atom->check(ctx, atom); 527 uint32_t depth_fmt; 528 529 rrb = radeon_get_colorbuffer(&r200->radeon); 530 if (!rrb || !rrb->bo) { 531 return; 532 } 533 534 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); 535 if (rrb->cpp == 4) 536 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; 537 else switch (rrb->base.Format) { 538 case MESA_FORMAT_RGB565: 539 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; 540 break; 541 case MESA_FORMAT_ARGB4444: 542 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; 543 break; 544 case MESA_FORMAT_ARGB1555: 545 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; 546 break; 547 default: 548 _mesa_problem(ctx, "Unexpected format in ctx_emit_cs"); 549 } 550 551 cbpitch = (rrb->pitch / rrb->cpp); 552 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 553 cbpitch |= R200_COLOR_TILE_ENABLE; 554 555 drb = radeon_get_depthbuffer(&r200->radeon); 556 if (drb) { 557 zbpitch = (drb->pitch / drb->cpp); 558 if (drb->cpp == 4) 559 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 560 else 561 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 562 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; 563 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; 564 } 565 566 /* output the first 7 bytes of context */ 567 BEGIN_BATCH_NO_AUTOSTATE(dwords); 568 569 /* In the CS case we need to split this up */ 570 OUT_BATCH(CP_PACKET0(packet[0].start, 3)); 571 OUT_BATCH_TABLE((atom->cmd + 1), 4); 572 573 if (drb) { 574 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); 575 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 576 577 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); 578 OUT_BATCH(zbpitch); 579 } 580 581 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); 582 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); 583 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); 584 OUT_BATCH(atom->cmd[CTX_PP_CNTL]); 585 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); 586 587 588 if (rrb) { 589 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); 590 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); 591 592 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); 593 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); 594 } 595 596 if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { 597 OUT_BATCH_TABLE((atom->cmd + 14), 4); 598 } 599 600 END_BATCH(); 601} 602 603static int get_tex_size(GLcontext* ctx, struct radeon_state_atom *atom) 604{ 605 r200ContextPtr r200 = R200_CONTEXT(ctx); 606 uint32_t dwords = atom->cmd_size + 2; 607 int i = atom->idx; 608 radeonTexObj *t = r200->state.texture.unit[i].texobj; 609 if (!(t && t->mt && !t->image_override)) 610 dwords -= 2; 611 612 return dwords; 613} 614 615static int check_tex_pair(GLcontext* ctx, struct radeon_state_atom *atom) 616{ 617 r200ContextPtr r200 = R200_CONTEXT(ctx); 618 /** XOR is bit flip operation so use it for finding pair */ 619 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded)) 620 return 0; 621 622 return get_tex_size(ctx, atom); 623} 624 625static int check_tex(GLcontext* ctx, struct radeon_state_atom *atom) 626{ 627 r200ContextPtr r200 = R200_CONTEXT(ctx); 628 if (!(r200->state.texture.unit[atom->idx].unitneeded)) 629 return 0; 630 631 return get_tex_size(ctx, atom); 632} 633 634 635static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom) 636{ 637 r200ContextPtr r200 = R200_CONTEXT(ctx); 638 BATCH_LOCALS(&r200->radeon); 639 uint32_t dwords = atom->check(ctx, atom); 640 int i = atom->idx; 641 radeonTexObj *t = r200->state.texture.unit[i].texobj; 642 643 BEGIN_BATCH_NO_AUTOSTATE(dwords); 644 /* is this ok even with drm older than 1.18? */ 645 OUT_BATCH_TABLE(atom->cmd, 10); 646 647 if (t && t->mt && !t->image_override) { 648 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t), 649 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 650 } else if (!t) { 651 /* workaround for old CS mechanism */ 652 OUT_BATCH(r200->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]); 653 } else { 654 OUT_BATCH(t->override_offset); 655 } 656 657 END_BATCH(); 658} 659 660static int get_tex_mm_size(GLcontext* ctx, struct radeon_state_atom *atom) 661{ 662 r200ContextPtr r200 = R200_CONTEXT(ctx); 663 uint32_t dwords = atom->cmd_size + 2; 664 int hastexture = 1; 665 int i = atom->idx; 666 radeonTexObj *t = r200->state.texture.unit[i].texobj; 667 if (!t) 668 hastexture = 0; 669 else { 670 if (!t->mt && !t->bo) 671 hastexture = 0; 672 } 673 674 if (!hastexture) 675 dwords -= 4; 676 return dwords; 677} 678 679static int check_tex_pair_mm(GLcontext* ctx, struct radeon_state_atom *atom) 680{ 681 r200ContextPtr r200 = R200_CONTEXT(ctx); 682 /** XOR is bit flip operation so use it for finding pair */ 683 if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded)) 684 return 0; 685 686 return get_tex_mm_size(ctx, atom); 687} 688 689static int check_tex_mm(GLcontext* ctx, struct radeon_state_atom *atom) 690{ 691 r200ContextPtr r200 = R200_CONTEXT(ctx); 692 if (!(r200->state.texture.unit[atom->idx].unitneeded)) 693 return 0; 694 695 return get_tex_mm_size(ctx, atom); 696} 697 698 699static void tex_emit_mm(GLcontext *ctx, struct radeon_state_atom *atom) 700{ 701 r200ContextPtr r200 = R200_CONTEXT(ctx); 702 BATCH_LOCALS(&r200->radeon); 703 uint32_t dwords = atom->check(ctx, atom); 704 int i = atom->idx; 705 radeonTexObj *t = r200->state.texture.unit[i].texobj; 706 707 if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size)) 708 dwords -= 4; 709 BEGIN_BATCH_NO_AUTOSTATE(dwords); 710 711 OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7)); 712 OUT_BATCH_TABLE((atom->cmd + 1), 8); 713 714 if (dwords > atom->cmd_size) { 715 OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); 716 if (t->mt && !t->image_override) { 717 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0, 718 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 719 } else { 720 if (t->bo) 721 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0, 722 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 723 } 724 } 725 END_BATCH(); 726} 727 728 729static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom) 730{ 731 r200ContextPtr r200 = R200_CONTEXT(ctx); 732 BATCH_LOCALS(&r200->radeon); 733 uint32_t dwords = atom->check(ctx, atom); 734 int i = atom->idx, j; 735 radeonTexObj *t = r200->state.texture.unit[i].texobj; 736 radeon_mipmap_level *lvl; 737 738 if (!(t && !t->image_override)) 739 dwords = 2; 740 741 BEGIN_BATCH_NO_AUTOSTATE(dwords); 742 /* XXX that size won't really match with image_override... */ 743 OUT_BATCH_TABLE(atom->cmd, 2); 744 745 if (t && !t->image_override) { 746 lvl = &t->mt->levels[0]; 747 OUT_BATCH_TABLE((atom->cmd + 2), 1); 748 for (j = 1; j <= 5; j++) { 749 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 750 RADEON_GEM_DOMAIN_VRAM, 0, 0); 751 } 752 } 753 END_BATCH(); 754} 755 756static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom) 757{ 758 r200ContextPtr r200 = R200_CONTEXT(ctx); 759 BATCH_LOCALS(&r200->radeon); 760 uint32_t dwords = atom->check(ctx, atom); 761 int i = atom->idx, j; 762 radeonTexObj *t = r200->state.texture.unit[i].texobj; 763 radeon_mipmap_level *lvl; 764 if (!(t && !t->image_override)) 765 dwords = 2; 766 767 BEGIN_BATCH_NO_AUTOSTATE(dwords); 768 OUT_BATCH_TABLE(atom->cmd, 2); 769 770 if (t && !t->image_override) { 771 lvl = &t->mt->levels[0]; 772 for (j = 1; j <= 5; j++) { 773 OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0)); 774 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset, 775 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 776 } 777 } 778 END_BATCH(); 779} 780 781/* Initialize the context's hardware state. 782 */ 783void r200InitState( r200ContextPtr rmesa ) 784{ 785 GLcontext *ctx = rmesa->radeon.glCtx; 786 GLuint i; 787 788 rmesa->radeon.state.color.clear = 0x00000000; 789 790 switch ( ctx->Visual.depthBits ) { 791 case 16: 792 rmesa->radeon.state.depth.clear = 0x0000ffff; 793 rmesa->radeon.state.stencil.clear = 0x00000000; 794 break; 795 case 24: 796 default: 797 rmesa->radeon.state.depth.clear = 0x00ffffff; 798 rmesa->radeon.state.stencil.clear = 0xffff0000; 799 break; 800 } 801 802 rmesa->radeon.Fallback = 0; 803 804 rmesa->radeon.hw.max_state_size = 0; 805 806#define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ 807 do { \ 808 rmesa->hw.ATOM.cmd_size = SZ; \ 809 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 810 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \ 811 rmesa->hw.ATOM.name = NM; \ 812 rmesa->hw.ATOM.idx = IDX; \ 813 if (check_##CHK != check_never) { \ 814 rmesa->hw.ATOM.check = check_##CHK; \ 815 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ 816 } else { \ 817 rmesa->hw.ATOM.check = NULL; \ 818 } \ 819 rmesa->hw.ATOM.dirty = GL_FALSE; \ 820 } while (0) 821 822 823 /* Allocate state buffers: 824 */ 825 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) 826 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); 827 else 828 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); 829 830 if (rmesa->radeon.radeonScreen->kernel_mm) 831 { 832 rmesa->hw.ctx.emit = ctx_emit_cs; 833 rmesa->hw.ctx.check = check_always_ctx; 834 } 835 else 836 { 837 rmesa->hw.ctx.emit = ctx_emit; 838 } 839 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 840 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 841 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 842 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 843 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 ); 844 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 ); 845 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 ); 846 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 847 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); 848 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 849 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); 850 { 851 int state_size = TEX_STATE_SIZE_NEWDRM; 852 if (!rmesa->radeon.radeonScreen->drmSupportsFragShader) { 853 state_size = TEX_STATE_SIZE_OLDDRM; 854 } 855 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { 856 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { 857 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ 858 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 ); 859 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 ); 860 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); 861 } 862 else { 863 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 ); 864 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 ); 865 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); 866 } 867 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 ); 868 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 ); 869 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 ); 870 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 ); 871 if (!rmesa->radeon.radeonScreen->kernel_mm) 872 { 873 if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { 874 rmesa->hw.tex[0].check = check_tex_pair; 875 rmesa->hw.tex[1].check = check_tex_pair; 876 } else { 877 rmesa->hw.tex[0].check = check_tex; 878 rmesa->hw.tex[1].check = check_tex; 879 } 880 rmesa->hw.tex[2].check = check_tex; 881 rmesa->hw.tex[3].check = check_tex; 882 rmesa->hw.tex[4].check = check_tex; 883 rmesa->hw.tex[5].check = check_tex; 884 } 885 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { 886 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 ); 887 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); 888 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); 889 } else { 890 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "ATF/tfactor", 0 ); 891 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); 892 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); 893 } 894 } 895 } 896 897 ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 ); 898 899 for (i = 0; i < 6; i++) 900 if (rmesa->radeon.radeonScreen->kernel_mm) 901 rmesa->hw.tex[i].emit = tex_emit_mm; 902 else 903 rmesa->hw.tex[i].emit = tex_emit; 904 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR200) { 905 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); 906 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); 907 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); 908 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); 909 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); 910 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); 911 for (i = 0; i < 6; i++) 912 if (rmesa->radeon.radeonScreen->kernel_mm) { 913 rmesa->hw.cube[i].emit = cube_emit_cs; 914 rmesa->hw.cube[i].check = check_tex_cube_cs; 915 } else 916 rmesa->hw.cube[i].emit = cube_emit; 917 } 918 else { 919 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); 920 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); 921 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); 922 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); 923 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); 924 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); 925 } 926 927 if (rmesa->radeon.radeonScreen->drmSupportsVertexProgram) { 928 ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); 929 if (rmesa->radeon.radeonScreen->kernel_mm) { 930 ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); 931 ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); 932 ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); 933 ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); 934 } else { 935 ALLOC_STATE( vpi[0], tcl_vp, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); 936 ALLOC_STATE( vpi[1], tcl_vp_size, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); 937 ALLOC_STATE( vpp[0], tcl_vp, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); 938 ALLOC_STATE( vpp[1], tcl_vpp_size, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); 939 } 940 } 941 else { 942 ALLOC_STATE( pvs, never, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); 943 ALLOC_STATE( vpi[0], never, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); 944 ALLOC_STATE( vpi[1], never, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); 945 ALLOC_STATE( vpp[0], never, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); 946 ALLOC_STATE( vpp[1], never, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); 947 } 948 /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */ 949 ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 ); 950 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 ); 951 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); 952 if (rmesa->radeon.radeonScreen->kernel_mm) { 953 ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 ); 954 ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 ); 955 ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 ); 956 ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 ); 957 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 ); 958 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); 959 ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 ); 960 ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); 961 ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 ); 962 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 ); 963 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 964 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 ); 965 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 ); 966 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 ); 967 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 ); 968 ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); 969 ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 970 ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); 971 ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); 972 ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); 973 ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); 974 ALLOC_STATE( lit[0], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-0", 0 ); 975 ALLOC_STATE( lit[1], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-1", 1 ); 976 ALLOC_STATE( lit[2], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-2", 2 ); 977 ALLOC_STATE( lit[3], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-3", 3 ); 978 ALLOC_STATE( lit[4], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-4", 4 ); 979 ALLOC_STATE( lit[5], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-5", 5 ); 980 ALLOC_STATE( lit[6], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-6", 6 ); 981 ALLOC_STATE( lit[7], tcl_light_add8, LIT_STATE_SIZE, "LIT/light-7", 7 ); 982 ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 ); 983 } else { 984 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 ); 985 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 ); 986 ALLOC_STATE( grd, tcl_or_vp, GRD_STATE_SIZE, "GRD/guard-band", 0 ); 987 ALLOC_STATE( fog, tcl_fog, FOG_STATE_SIZE, "FOG/fog", 0 ); 988 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 ); 989 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); 990 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 ); 991 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); 992 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 ); 993 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 ); 994 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 995 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 ); 996 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 ); 997 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 ); 998 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 ); 999 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); 1000 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 1001 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); 1002 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); 1003 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); 1004 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); 1005 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 ); 1006 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 ); 1007 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 ); 1008 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 ); 1009 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 ); 1010 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 ); 1011 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 ); 1012 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 ); 1013 ALLOC_STATE( sci, never, SCI_STATE_SIZE, "SCI/scissor", 0 ); 1014 } 1015 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 ); 1016 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 ); 1017 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 ); 1018 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); 1019 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); 1020 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); 1021 if (rmesa->radeon.radeonScreen->drmSupportsTriPerf) { 1022 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); 1023 } 1024 else { 1025 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); 1026 } 1027 if (rmesa->radeon.radeonScreen->drmSupportsPointSprites) { 1028 ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); 1029 if (rmesa->radeon.radeonScreen->kernel_mm) 1030 ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 ); 1031 else 1032 ALLOC_STATE( ptp, tcl, PTP_STATE_SIZE, "PTP/pointparams", 0 ); 1033 } 1034 else { 1035 ALLOC_STATE (spr, never, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); 1036 ALLOC_STATE (ptp, never, PTP_STATE_SIZE, "PTP/pointparams", 0 ); 1037 } 1038 1039 r200SetUpAtomList( rmesa ); 1040 1041 /* Fill in the packet headers: 1042 */ 1043 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); 1044 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); 1045 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); 1046 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) 1047 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR); 1048 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); 1049 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); 1050 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); 1051 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); 1052 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); 1053 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); 1054 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X); 1055 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET); 1056 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL); 1057 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(rmesa, R200_EMIT_RE_SCISSOR_TL_0); 1058 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS); 1059 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE); 1060 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); 1061 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3); 1062 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0); 1063 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { 1064 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR); 1065 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0); 1066 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); 1067 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1); 1068 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); 1069 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2); 1070 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); 1071 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3); 1072 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); 1073 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4); 1074 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); 1075 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5); 1076 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); 1077 } else { 1078 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_0); 1079 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); 1080 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_1); 1081 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); 1082 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_2); 1083 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); 1084 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_3); 1085 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); 1086 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_4); 1087 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); 1088 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXFILTER_5); 1089 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); 1090 } 1091 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0); 1092 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1); 1093 rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL); 1094 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0); 1095 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0); 1096 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1); 1097 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1); 1098 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2); 1099 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2); 1100 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3); 1101 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3); 1102 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4); 1103 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4); 1104 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5); 1105 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5); 1106 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0); 1107 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1); 1108 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2); 1109 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3); 1110 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4); 1111 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5); 1112 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); 1113 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0); 1114 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL); 1115 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2); 1116 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0); 1117 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL); 1118 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0); 1119 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL); 1120 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL); 1121 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL); 1122 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL); 1123 rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); 1124 1125 rmesa->hw.sci.cmd[SCI_CMD_0] = CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0); 1126 rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0); 1127 rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0); 1128 1129 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); 1130 rmesa->hw.stp.cmd[STP_DATA_0] = 0; 1131 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); 1132 1133 if (rmesa->radeon.radeonScreen->kernel_mm) { 1134 rmesa->hw.mtl[0].emit = mtl_emit; 1135 rmesa->hw.mtl[1].emit = mtl_emit; 1136 1137 rmesa->hw.vpi[0].emit = veclinear_emit; 1138 rmesa->hw.vpi[1].emit = veclinear_emit; 1139 rmesa->hw.vpp[0].emit = veclinear_emit; 1140 rmesa->hw.vpp[1].emit = veclinear_emit; 1141 1142 rmesa->hw.grd.emit = scl_emit; 1143 rmesa->hw.fog.emit = vec_emit; 1144 rmesa->hw.glt.emit = vec_emit; 1145 rmesa->hw.eye.emit = vec_emit; 1146 1147 for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) 1148 rmesa->hw.mat[i].emit = vec_emit; 1149 1150 for (i = 0; i < 8; i++) 1151 rmesa->hw.lit[i].emit = lit_emit; 1152 1153 for (i = 0; i < 6; i++) 1154 rmesa->hw.ucp[i].emit = vec_emit; 1155 1156 rmesa->hw.ptp.emit = ptp_emit; 1157 } 1158 1159 1160 1161 rmesa->hw.mtl[0].cmd[MTL_CMD_0] = 1162 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); 1163 rmesa->hw.mtl[0].cmd[MTL_CMD_1] = 1164 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 ); 1165 rmesa->hw.mtl[1].cmd[MTL_CMD_0] = 1166 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 ); 1167 rmesa->hw.mtl[1].cmd[MTL_CMD_1] = 1168 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 ); 1169 1170 rmesa->hw.vpi[0].cmd[VPI_CMD_0] = 1171 cmdveclinear( R200_PVS_PROG0, 64 ); 1172 rmesa->hw.vpi[1].cmd[VPI_CMD_0] = 1173 cmdveclinear( R200_PVS_PROG1, 64 ); 1174 rmesa->hw.vpp[0].cmd[VPP_CMD_0] = 1175 cmdveclinear( R200_PVS_PARAM0, 96 ); 1176 rmesa->hw.vpp[1].cmd[VPP_CMD_0] = 1177 cmdveclinear( R200_PVS_PARAM1, 96 ); 1178 1179 rmesa->hw.grd.cmd[GRD_CMD_0] = 1180 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 1181 rmesa->hw.fog.cmd[FOG_CMD_0] = 1182 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 ); 1183 rmesa->hw.glt.cmd[GLT_CMD_0] = 1184 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 1185 rmesa->hw.eye.cmd[EYE_CMD_0] = 1186 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 ); 1187 1188 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] = 1189 cmdvec( R200_VS_MATRIX_0_MV, 1, 16); 1190 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] = 1191 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16); 1192 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] = 1193 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16); 1194 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] = 1195 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16); 1196 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] = 1197 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16); 1198 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] = 1199 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16); 1200 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] = 1201 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16); 1202 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] = 1203 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16); 1204 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] = 1205 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16); 1206 1207 for (i = 0 ; i < 8; i++) { 1208 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 1209 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 1210 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 1211 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 ); 1212 } 1213 1214 for (i = 0 ; i < 6; i++) { 1215 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 1216 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 ); 1217 } 1218 1219 rmesa->hw.ptp.cmd[PTP_CMD_0] = 1220 cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 ); 1221 rmesa->hw.ptp.cmd[PTP_CMD_1] = 1222 cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 ); 1223 1224 /* Initial Harware state: 1225 */ 1226 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS 1227 /* | R200_RIGHT_HAND_CUBE_OGL*/); 1228 1229 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX | 1230 R200_FOG_USE_SPEC_ALPHA); 1231 1232 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 1233 1234 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 1235 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 1236 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 1237 1238 if (rmesa->radeon.radeonScreen->drmSupportsBlendColor) { 1239 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; 1240 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 1241 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 1242 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 1243 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 1244 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 1245 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 1246 } 1247 1248 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = 1249 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; 1250 1251 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 1252 ((rmesa->radeon.radeonScreen->depthPitch & 1253 R200_DEPTHPITCH_MASK) | 1254 R200_DEPTH_ENDIAN_NO_SWAP); 1255 1256 if (rmesa->using_hyperz) 1257 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; 1258 1259 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS | 1260 R200_STENCIL_TEST_ALWAYS | 1261 R200_STENCIL_FAIL_KEEP | 1262 R200_STENCIL_ZPASS_KEEP | 1263 R200_STENCIL_ZFAIL_KEEP | 1264 R200_Z_WRITE_ENABLE); 1265 1266 if (rmesa->using_hyperz) { 1267 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | 1268 R200_Z_DECOMPRESSION_ENABLE; 1269/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) 1270 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 1271 } 1272 1273 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE 1274 | R200_TEX_BLEND_0_ENABLE); 1275 1276 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { 1277 case DRI_CONF_DITHER_XERRORDIFFRESET: 1278 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; 1279 break; 1280 case DRI_CONF_DITHER_ORDERED: 1281 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; 1282 break; 1283 } 1284 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == 1285 DRI_CONF_ROUND_ROUND ) 1286 rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE; 1287 else 1288 rmesa->radeon.state.color.roundEnable = 0; 1289 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == 1290 DRI_CONF_COLOR_REDUCTION_DITHER ) 1291 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; 1292 else 1293 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; 1294 1295 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * 1296 driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality"); 1297 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; 1298 1299 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | 1300 R200_BFACE_SOLID | 1301 R200_FFACE_SOLID | 1302 R200_FLAT_SHADE_VTX_LAST | 1303 R200_DIFFUSE_SHADE_GOURAUD | 1304 R200_ALPHA_SHADE_GOURAUD | 1305 R200_SPECULAR_SHADE_GOURAUD | 1306 R200_FOG_SHADE_GOURAUD | 1307 R200_DISC_FOG_SHADE_GOURAUD | 1308 R200_VTX_PIX_CENTER_OGL | 1309 R200_ROUND_MODE_TRUNC | 1310 R200_ROUND_PREC_8TH_PIX); 1311 1312 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE | 1313 R200_SCISSOR_ENABLE); 1314 1315 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 1316 1317 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 1318 ((0 << R200_LINE_CURRENT_PTR_SHIFT) | 1319 (1 << R200_LINE_CURRENT_COUNT_SHIFT)); 1320 1321 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 1322 1323 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 1324 ((0x00 << R200_STENCIL_REF_SHIFT) | 1325 (0xff << R200_STENCIL_MASK_SHIFT) | 1326 (0xff << R200_STENCIL_WRITEMASK_SHIFT)); 1327 1328 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY; 1329 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 1330 1331 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0; 1332 1333 rmesa->hw.msc.cmd[MSC_RE_MISC] = 1334 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) | 1335 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) | 1336 R200_STIPPLE_BIG_BIT_ORDER); 1337 1338 1339 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; 1340 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0; 1341 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0; 1342 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0; 1343 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0; 1344 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] = 1345#ifdef MESA_BIG_ENDIAN 1346 R200_VC_32BIT_SWAP; 1347#else 1348 R200_VC_NO_SWAP; 1349#endif 1350 1351 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 1352 /* Bypass TCL */ 1353 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); 1354 } 1355 1356 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 1357 (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10; 1358 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] = 1359 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT); 1360 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] = 1361 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) | 1362 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT); 1363 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] = 1364 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) | 1365 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) | 1366 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) | 1367 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT); 1368 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] = 1369 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) | 1370 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT); 1371 1372 1373 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 1374 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 1375 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 1376 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 1377 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 1378 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 1379 1380 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 1381 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL; 1382 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 1383 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */ 1384 (2 << R200_TXFORMAT_WIDTH_SHIFT) | 1385 (2 << R200_TXFORMAT_HEIGHT_SHIFT)); 1386 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 1387 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = 1388 (/* R200_TEXCOORD_PROJ | */ 1389 R200_LOD_BIAS_CORRECTION); /* Small default bias */ 1390 if (rmesa->radeon.radeonScreen->drmSupportsFragShader) { 1391 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = 1392 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1393 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; 1394 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; 1395 } 1396 else { 1397 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] = 1398 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1399 } 1400 1401 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 1402 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = 1403 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1404 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = 1405 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1406 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = 1407 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1408 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = 1409 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1410 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = 1411 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; 1412 1413 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = 1414 (R200_TXC_ARG_A_ZERO | 1415 R200_TXC_ARG_B_ZERO | 1416 R200_TXC_ARG_C_DIFFUSE_COLOR | 1417 R200_TXC_OP_MADD); 1418 1419 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] = 1420 ((i << R200_TXC_TFACTOR_SEL_SHIFT) | 1421 R200_TXC_SCALE_1X | 1422 R200_TXC_CLAMP_0_1 | 1423 R200_TXC_OUTPUT_REG_R0); 1424 1425 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] = 1426 (R200_TXA_ARG_A_ZERO | 1427 R200_TXA_ARG_B_ZERO | 1428 R200_TXA_ARG_C_DIFFUSE_ALPHA | 1429 R200_TXA_OP_MADD); 1430 1431 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] = 1432 ((i << R200_TXA_TFACTOR_SEL_SHIFT) | 1433 R200_TXA_SCALE_1X | 1434 R200_TXA_CLAMP_0_1 | 1435 R200_TXA_OUTPUT_REG_R0); 1436 } 1437 1438 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0; 1439 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0; 1440 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0; 1441 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0; 1442 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0; 1443 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0; 1444 1445 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = 1446 (R200_VAP_TCL_ENABLE | 1447 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)); 1448 1449 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = 1450 (R200_VPORT_X_SCALE_ENA | 1451 R200_VPORT_Y_SCALE_ENA | 1452 R200_VPORT_Z_SCALE_ENA | 1453 R200_VPORT_X_OFFSET_ENA | 1454 R200_VPORT_Y_OFFSET_ENA | 1455 R200_VPORT_Z_OFFSET_ENA | 1456/* FIXME: Turn on for tex rect only */ 1457 R200_VTX_ST_DENORMALIZED | 1458 R200_VTX_W0_FMT); 1459 1460 1461 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0; 1462 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0; 1463 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = 1464 ((R200_VTX_Z0 | R200_VTX_W0 | 1465 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT))); 1466 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0; 1467 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW); 1468 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE; 1469 1470 1471 /* Matrix selection */ 1472 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] = 1473 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT); 1474 1475 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] = 1476 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT); 1477 1478 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] = 1479 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT); 1480 1481 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] = 1482 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) | 1483 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) | 1484 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) | 1485 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT)); 1486 1487 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] = 1488 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) | 1489 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT)); 1490 1491 1492 /* General TCL state */ 1493 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = 1494 (R200_SPECULAR_LIGHTS | 1495 R200_DIFFUSE_SPECULAR_COMBINE | 1496 R200_LOCAL_LIGHT_VEC_GL | 1497 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT | 1498 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT); 1499 1500 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = 1501 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | 1502 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) | 1503 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | 1504 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) | 1505 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) | 1506 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) | 1507 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) | 1508 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT)); 1509 1510 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */ 1511 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0; 1512 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0; 1513 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0; 1514 1515 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 1516 (R200_UCP_IN_CLIP_SPACE | 1517 R200_CULL_FRONT_IS_CCW); 1518 1519 /* Texgen/Texmat state */ 1520 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; 1521 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = 1522 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) | 1523 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) | 1524 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) | 1525 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) | 1526 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) | 1527 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT)); 1528 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; 1529 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = 1530 ((0 << R200_TEXGEN_0_INPUT_SHIFT) | 1531 (1 << R200_TEXGEN_1_INPUT_SHIFT) | 1532 (2 << R200_TEXGEN_2_INPUT_SHIFT) | 1533 (3 << R200_TEXGEN_3_INPUT_SHIFT) | 1534 (4 << R200_TEXGEN_4_INPUT_SHIFT) | 1535 (5 << R200_TEXGEN_5_INPUT_SHIFT)); 1536 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0; 1537 1538 1539 for (i = 0 ; i < 8; i++) { 1540 struct gl_light *l = &ctx->Light.Light[i]; 1541 GLenum p = GL_LIGHT0 + i; 1542 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 1543 1544 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 1545 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 1546 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 1547 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 1548 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 1549 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 1550 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 1551 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 1552 &l->ConstantAttenuation ); 1553 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 1554 &l->LinearAttenuation ); 1555 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 1556 &l->QuadraticAttenuation ); 1557 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 1558 } 1559 1560 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 1561 ctx->Light.Model.Ambient ); 1562 1563 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 1564 1565 for (i = 0 ; i < 6; i++) { 1566 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 1567 } 1568 1569 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 1570 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 1571 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 1572 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 1573 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 1574 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 1575 1576 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 1577 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 1578 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 1579 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 1580 1581 rmesa->hw.eye.cmd[EYE_X] = 0; 1582 rmesa->hw.eye.cmd[EYE_Y] = 0; 1583 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 1584 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 1585 1586 rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] = 1587 R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST; 1588 1589 /* ptp_eye is presumably used to calculate the attenuation wrt a different 1590 location? In any case, since point attenuation triggers _needeyecoords, 1591 it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC 1592 isn't set */ 1593 rmesa->hw.ptp.cmd[PTP_EYE_X] = 0; 1594 rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0; 1595 rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */ 1596 rmesa->hw.ptp.cmd[PTP_EYE_3] = 0; 1597 /* no idea what the ptp_vport_scale values are good for, except the 1598 PTSIZE one - hopefully doesn't matter */ 1599 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE; 1600 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE; 1601 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE; 1602 rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE; 1603 rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0; 1604 rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0; 1605 rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE; 1606 rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0; 1607 rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE; 1608 rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */ 1609 rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0; 1610 rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0; 1611 1612 r200LightingSpaceChange( ctx ); 1613 1614 if (rmesa->radeon.radeonScreen->kernel_mm) { 1615 radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE); 1616 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); 1617 rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0; 1618 } 1619 1620 rmesa->radeon.hw.all_dirty = GL_TRUE; 1621 1622 rcommonInitCmdBuf(&rmesa->radeon); 1623} 1624