r200_state_init.c revision f20917de5bd2b1fc152e74304d3649a1f6042422
1/* $XFree86: xc/lib/GL/mesa/src/drv/r200/r200_state_init.c,v 1.4 2003/02/22 06:21:11 dawes Exp $ */ 2/* 3Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 4 5The Weather Channel (TM) funded Tungsten Graphics to develop the 6initial release of the Radeon 8500 driver under the XFree86 license. 7This notice must be preserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28*/ 29 30/* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35#include "glheader.h" 36#include "imports.h" 37#include "enums.h" 38#include "colormac.h" 39#include "api_arrayelt.h" 40 41#include "swrast/swrast.h" 42#include "array_cache/acache.h" 43#include "tnl/tnl.h" 44#include "tnl/t_pipeline.h" 45#include "swrast_setup/swrast_setup.h" 46 47#include "r200_context.h" 48#include "r200_ioctl.h" 49#include "r200_state.h" 50#include "r200_tcl.h" 51#include "r200_tex.h" 52#include "r200_swtcl.h" 53#include "r200_vtxfmt.h" 54 55#include "xmlpool.h" 56 57/* ============================================================= 58 * State initialization 59 */ 60 61void r200PrintDirty( r200ContextPtr rmesa, const char *msg ) 62{ 63 struct r200_state_atom *l; 64 65 fprintf(stderr, msg); 66 fprintf(stderr, ": "); 67 68 foreach(l, &rmesa->hw.atomlist) { 69 if (l->dirty || rmesa->hw.all_dirty) 70 fprintf(stderr, "%s, ", l->name); 71 } 72 73 fprintf(stderr, "\n"); 74} 75 76static int cmdpkt( int id ) 77{ 78 drm_radeon_cmd_header_t h; 79 h.i = 0; 80 h.packet.cmd_type = RADEON_CMD_PACKET; 81 h.packet.packet_id = id; 82 return h.i; 83} 84 85static int cmdvec( int offset, int stride, int count ) 86{ 87 drm_radeon_cmd_header_t h; 88 h.i = 0; 89 h.vectors.cmd_type = RADEON_CMD_VECTORS; 90 h.vectors.offset = offset; 91 h.vectors.stride = stride; 92 h.vectors.count = count; 93 return h.i; 94} 95 96static int cmdscl( int offset, int stride, int count ) 97{ 98 drm_radeon_cmd_header_t h; 99 h.i = 0; 100 h.scalars.cmd_type = RADEON_CMD_SCALARS; 101 h.scalars.offset = offset; 102 h.scalars.stride = stride; 103 h.scalars.count = count; 104 return h.i; 105} 106 107static int cmdscl2( int offset, int stride, int count ) 108{ 109 drm_radeon_cmd_header_t h; 110 h.i = 0; 111 h.scalars.cmd_type = RADEON_CMD_SCALARS2; 112 h.scalars.offset = offset - 0x100; 113 h.scalars.stride = stride; 114 h.scalars.count = count; 115 return h.i; 116} 117 118#define CHECK( NM, FLAG ) \ 119static GLboolean check_##NM( GLcontext *ctx, int idx ) \ 120{ \ 121 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 122 (void) idx; \ 123 (void) rmesa; \ 124 return FLAG; \ 125} 126 127#define TCL_CHECK( NM, FLAG ) \ 128static GLboolean check_##NM( GLcontext *ctx, int idx ) \ 129{ \ 130 r200ContextPtr rmesa = R200_CONTEXT(ctx); \ 131 (void) idx; \ 132 return !rmesa->TclFallback && (FLAG); \ 133} 134 135 136 137CHECK( always, GL_TRUE ) 138CHECK( never, GL_FALSE ) 139CHECK( tex_any, ctx->Texture._EnabledUnits ) 140CHECK( tf, (ctx->Texture._EnabledUnits && !ctx->ATIFragmentShader._Enabled) ); 141CHECK( tex_pair, (rmesa->state.texture.unit[idx].unitneeded | rmesa->state.texture.unit[idx & ~1].unitneeded) ) 142CHECK( tex, rmesa->state.texture.unit[idx].unitneeded ) 143CHECK( pix_zero, !ctx->ATIFragmentShader._Enabled ) 144CHECK( texenv, (rmesa->state.envneeded & (1 << idx) && !ctx->ATIFragmentShader._Enabled) ) 145CHECK( afs_pass1, (ctx->ATIFragmentShader._Enabled && (ctx->ATIFragmentShader.Current->NumPasses > 1)) ) 146CHECK( afs, ctx->ATIFragmentShader._Enabled ) 147CHECK( tex_cube, rmesa->state.texture.unit[idx].unitneeded & TEXTURE_CUBE_BIT ) 148CHECK( fog, ctx->Fog.Enabled ) 149TCL_CHECK( tcl, GL_TRUE ) 150TCL_CHECK( tcl_tex, rmesa->state.texture.unit[idx].unitneeded ) 151TCL_CHECK( tcl_lighting, ctx->Light.Enabled ) 152TCL_CHECK( tcl_light, ctx->Light.Enabled && ctx->Light.Light[idx].Enabled ) 153TCL_CHECK( tcl_ucp, (ctx->Transform.ClipPlanesEnabled & (1 << idx)) ) 154 155 156/* Initialize the context's hardware state. 157 */ 158void r200InitState( r200ContextPtr rmesa ) 159{ 160 GLcontext *ctx = rmesa->glCtx; 161 GLuint color_fmt, depth_fmt, i; 162 GLint drawPitch, drawOffset; 163 164 switch ( rmesa->r200Screen->cpp ) { 165 case 2: 166 color_fmt = R200_COLOR_FORMAT_RGB565; 167 break; 168 case 4: 169 color_fmt = R200_COLOR_FORMAT_ARGB8888; 170 break; 171 default: 172 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" ); 173 exit( -1 ); 174 } 175 176 rmesa->state.color.clear = 0x00000000; 177 178 switch ( ctx->Visual.depthBits ) { 179 case 16: 180 rmesa->state.depth.clear = 0x0000ffff; 181 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff; 182 depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z; 183 rmesa->state.stencil.clear = 0x00000000; 184 break; 185 case 24: 186 rmesa->state.depth.clear = 0x00ffffff; 187 rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff; 188 depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z; 189 rmesa->state.stencil.clear = 0xffff0000; 190 break; 191 default: 192 fprintf( stderr, "Error: Unsupported depth %d... exiting\n", 193 ctx->Visual.depthBits ); 194 exit( -1 ); 195 } 196 197 /* Only have hw stencil when depth buffer is 24 bits deep */ 198 rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 && 199 ctx->Visual.depthBits == 24 ); 200 201 rmesa->Fallback = 0; 202 203 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { 204 drawOffset = rmesa->r200Screen->backOffset; 205 drawPitch = rmesa->r200Screen->backPitch; 206 } else { 207 drawOffset = rmesa->r200Screen->frontOffset; 208 drawPitch = rmesa->r200Screen->frontPitch; 209 } 210#if 000 211 if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) { 212 rmesa->state.color.drawOffset = rmesa->r200Screen->backOffset; 213 rmesa->state.color.drawPitch = rmesa->r200Screen->backPitch; 214 } else { 215 rmesa->state.color.drawOffset = rmesa->r200Screen->frontOffset; 216 rmesa->state.color.drawPitch = rmesa->r200Screen->frontPitch; 217 } 218 219 rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset; 220 rmesa->state.pixel.readPitch = rmesa->state.color.drawPitch; 221#endif 222 223 rmesa->hw.max_state_size = 0; 224 225#define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ 226 do { \ 227 rmesa->hw.ATOM.cmd_size = SZ; \ 228 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \ 229 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \ 230 rmesa->hw.ATOM.name = NM; \ 231 rmesa->hw.ATOM.idx = IDX; \ 232 rmesa->hw.ATOM.check = check_##CHK; \ 233 rmesa->hw.ATOM.dirty = GL_FALSE; \ 234 rmesa->hw.max_state_size += SZ * sizeof(int); \ 235 } while (0) 236 237 238 /* Allocate state buffers: 239 */ 240 if (rmesa->r200Screen->drmSupportsBlendColor) 241 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); 242 else 243 ALLOC_STATE( ctx, always, CTX_STATE_SIZE_OLDDRM, "CTX/context", 0 ); 244 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); 245 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); 246 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); 247 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); 248 ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 ); 249 ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 ); 250 ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 ); 251 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); 252 ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); 253 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); 254 ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); 255 if (rmesa->r200Screen->drmSupportsFragShader) { 256 if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) { 257 /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ 258 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); 259 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); 260 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); 261 } 262 else { 263 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-0", 0 ); 264 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-1", 1 ); 265 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); 266 } 267 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-2", 2 ); 268 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-3", 3 ); 269 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-4", 4 ); 270 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_NEWDRM, "TEX/tex-5", 5 ); 271 ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 ); 272 ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); 273 ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); 274 } 275 else { 276 if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) { 277 ALLOC_STATE( tex[0], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); 278 ALLOC_STATE( tex[1], tex_pair, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); 279 ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); 280 } 281 else { 282 ALLOC_STATE( tex[0], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-0", 0 ); 283 ALLOC_STATE( tex[1], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-1", 1 ); 284 ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); 285 } 286 ALLOC_STATE( tex[2], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-2", 2 ); 287 ALLOC_STATE( tex[3], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-3", 3 ); 288 ALLOC_STATE( tex[4], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-4", 4 ); 289 ALLOC_STATE( tex[5], tex, TEX_STATE_SIZE_OLDDRM, "TEX/tex-5", 5 ); 290 ALLOC_STATE( atf, never, ATF_STATE_SIZE, "TF/tfactor", 0 ); 291 ALLOC_STATE( afs[0], never, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); 292 ALLOC_STATE( afs[1], never, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); 293 } 294 if (rmesa->r200Screen->drmSupportsCubeMaps) { 295 ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); 296 ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); 297 ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); 298 ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); 299 ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); 300 ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); 301 } 302 else { 303 ALLOC_STATE( cube[0], never, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); 304 ALLOC_STATE( cube[1], never, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); 305 ALLOC_STATE( cube[2], never, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); 306 ALLOC_STATE( cube[3], never, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); 307 ALLOC_STATE( cube[4], never, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); 308 ALLOC_STATE( cube[5], never, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); 309 } 310 311 ALLOC_STATE( tcl, tcl, TCL_STATE_SIZE, "TCL/tcl", 0 ); 312 ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 ); 313 ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); 314 ALLOC_STATE( mtl[0], tcl_lighting, MTL_STATE_SIZE, "MTL0/material0", 0 ); 315 ALLOC_STATE( mtl[1], tcl_lighting, MTL_STATE_SIZE, "MTL1/material1", 1 ); 316 ALLOC_STATE( grd, tcl, GRD_STATE_SIZE, "GRD/guard-band", 0 ); 317 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 0 ); 318 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 0 ); 319 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); 320 ALLOC_STATE( mat[R200_MTX_MV], tcl, MAT_STATE_SIZE, "MAT/modelview", 0 ); 321 ALLOC_STATE( mat[R200_MTX_IMV], tcl, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); 322 ALLOC_STATE( mat[R200_MTX_MVP], tcl, MAT_STATE_SIZE, "MAT/modelproject", 0 ); 323 ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex, MAT_STATE_SIZE, "MAT/texmat0", 0 ); 324 ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex, MAT_STATE_SIZE, "MAT/texmat1", 1 ); 325 ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex, MAT_STATE_SIZE, "MAT/texmat2", 2 ); 326 ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex, MAT_STATE_SIZE, "MAT/texmat3", 3 ); 327 ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex, MAT_STATE_SIZE, "MAT/texmat4", 4 ); 328 ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex, MAT_STATE_SIZE, "MAT/texmat5", 5 ); 329 ALLOC_STATE( ucp[0], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); 330 ALLOC_STATE( ucp[1], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); 331 ALLOC_STATE( ucp[2], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); 332 ALLOC_STATE( ucp[3], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); 333 ALLOC_STATE( ucp[4], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); 334 ALLOC_STATE( ucp[5], tcl_ucp, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); 335 ALLOC_STATE( lit[0], tcl_light, LIT_STATE_SIZE, "LIT/light-0", 0 ); 336 ALLOC_STATE( lit[1], tcl_light, LIT_STATE_SIZE, "LIT/light-1", 1 ); 337 ALLOC_STATE( lit[2], tcl_light, LIT_STATE_SIZE, "LIT/light-2", 2 ); 338 ALLOC_STATE( lit[3], tcl_light, LIT_STATE_SIZE, "LIT/light-3", 3 ); 339 ALLOC_STATE( lit[4], tcl_light, LIT_STATE_SIZE, "LIT/light-4", 4 ); 340 ALLOC_STATE( lit[5], tcl_light, LIT_STATE_SIZE, "LIT/light-5", 5 ); 341 ALLOC_STATE( lit[6], tcl_light, LIT_STATE_SIZE, "LIT/light-6", 6 ); 342 ALLOC_STATE( lit[7], tcl_light, LIT_STATE_SIZE, "LIT/light-7", 7 ); 343 ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 ); 344 ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 ); 345 ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 ); 346 ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); 347 ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); 348 ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); 349 if (rmesa->r200Screen->drmSupportsTriPerf) { 350 ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); 351 } 352 else { 353 ALLOC_STATE( prf, never, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); 354 } 355 356 r200SetUpAtomList( rmesa ); 357 358 /* Fill in the packet headers: 359 */ 360 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC); 361 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL); 362 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH); 363 if (rmesa->r200Screen->drmSupportsBlendColor) 364 rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(R200_EMIT_RB3D_BLENDCOLOR); 365 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN); 366 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH); 367 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK); 368 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE); 369 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL); 370 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC); 371 rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(R200_EMIT_PP_CNTL_X); 372 rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(R200_EMIT_RB3D_DEPTHXY_OFFSET); 373 rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(R200_EMIT_RE_AUX_SCISSOR_CNTL); 374 rmesa->hw.cst.cmd[CST_CMD_3] = cmdpkt(R200_EMIT_RE_SCISSOR_TL_0); 375 rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(R200_EMIT_SE_VAP_CNTL_STATUS); 376 rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(R200_EMIT_RE_POINTSIZE); 377 rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); 378 rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(R200_EMIT_PP_TAM_DEBUG3); 379 rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(R200_EMIT_TFACTOR_0); 380 if (rmesa->r200Screen->drmSupportsFragShader) { 381 rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(R200_EMIT_ATF_TFACTOR); 382 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_0); 383 rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0); 384 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_1); 385 rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1); 386 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_2); 387 rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2); 388 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_3); 389 rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3); 390 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_4); 391 rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4); 392 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCTLALL_5); 393 rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5); 394 } else { 395 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_0); 396 rmesa->hw.tex[0].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_0); 397 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_1); 398 rmesa->hw.tex[1].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_1); 399 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_2); 400 rmesa->hw.tex[2].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_2); 401 rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_3); 402 rmesa->hw.tex[3].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_3); 403 rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_4); 404 rmesa->hw.tex[4].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_4); 405 rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(R200_EMIT_PP_TXFILTER_5); 406 rmesa->hw.tex[5].cmd[TEX_CMD_1_OLDDRM] = cmdpkt(R200_EMIT_PP_TXOFFSET_5); 407 } 408 rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_0); 409 rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(R200_EMIT_PP_AFS_1); 410 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_0); 411 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_0); 412 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_1); 413 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_1); 414 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_2); 415 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_2); 416 rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_3); 417 rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_3); 418 rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_4); 419 rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_4); 420 rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(R200_EMIT_PP_CUBIC_FACES_5); 421 rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(R200_EMIT_PP_CUBIC_OFFSETS_5); 422 rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_0); 423 rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_1); 424 rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_2); 425 rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_3); 426 rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_4); 427 rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(R200_EMIT_PP_TXCBLEND_5); 428 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR); 429 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(R200_EMIT_TCL_LIGHT_MODEL_CTL_0); 430 rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(R200_EMIT_TCL_UCP_VERT_BLEND_CTL); 431 rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(R200_EMIT_TEX_PROC_CTL_2); 432 rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(R200_EMIT_MATRIX_SELECT_0); 433 rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(R200_EMIT_VAP_CTL); 434 rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(R200_EMIT_VTX_FMT_0); 435 rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(R200_EMIT_OUTPUT_VTX_COMP_SEL); 436 rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(R200_EMIT_SE_VTX_STATE_CNTL); 437 rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(R200_EMIT_VTE_CNTL); 438 rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(R200_EMIT_PP_TRI_PERF_CNTL); 439 rmesa->hw.mtl[0].cmd[MTL_CMD_0] = 440 cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); 441 rmesa->hw.mtl[0].cmd[MTL_CMD_1] = 442 cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 ); 443 rmesa->hw.mtl[1].cmd[MTL_CMD_0] = 444 cmdvec( R200_VS_MAT_1_EMISS, 1, 16 ); 445 rmesa->hw.mtl[1].cmd[MTL_CMD_1] = 446 cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 ); 447 448 rmesa->hw.grd.cmd[GRD_CMD_0] = 449 cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); 450 rmesa->hw.fog.cmd[FOG_CMD_0] = 451 cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 ); 452 rmesa->hw.glt.cmd[GLT_CMD_0] = 453 cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); 454 rmesa->hw.eye.cmd[EYE_CMD_0] = 455 cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 ); 456 457 rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] = 458 cmdvec( R200_VS_MATRIX_0_MV, 1, 16); 459 rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] = 460 cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16); 461 rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] = 462 cmdvec( R200_VS_MATRIX_2_MVP, 1, 16); 463 rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] = 464 cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16); 465 rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] = 466 cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16); 467 rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] = 468 cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16); 469 rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] = 470 cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16); 471 rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] = 472 cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16); 473 rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] = 474 cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16); 475 476 for (i = 0 ; i < 8; i++) { 477 rmesa->hw.lit[i].cmd[LIT_CMD_0] = 478 cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); 479 rmesa->hw.lit[i].cmd[LIT_CMD_1] = 480 cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 ); 481 } 482 483 for (i = 0 ; i < 6; i++) { 484 rmesa->hw.ucp[i].cmd[UCP_CMD_0] = 485 cmdvec( R200_VS_UCP_ADDR + i, 1, 4 ); 486 } 487 488 /* Initial Harware state: 489 */ 490 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS 491 /* | R200_RIGHT_HAND_CUBE_OGL*/); 492 493 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX | 494 R200_FOG_USE_SPEC_ALPHA); 495 496 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; 497 498 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 499 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 500 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 501 502 if (rmesa->r200Screen->drmSupportsBlendColor) { 503 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; 504 rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 505 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 506 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 507 rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | 508 (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | 509 (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); 510 } 511 512 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = 513 rmesa->r200Screen->depthOffset + rmesa->r200Screen->fbLocation; 514 515 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = 516 ((rmesa->r200Screen->depthPitch & 517 R200_DEPTHPITCH_MASK) | 518 R200_DEPTH_ENDIAN_NO_SWAP); 519 520 if (rmesa->using_hyperz) 521 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; 522 523 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt | 524 R200_Z_TEST_LESS | 525 R200_STENCIL_TEST_ALWAYS | 526 R200_STENCIL_FAIL_KEEP | 527 R200_STENCIL_ZPASS_KEEP | 528 R200_STENCIL_ZFAIL_KEEP | 529 R200_Z_WRITE_ENABLE); 530 531 if (rmesa->using_hyperz) { 532 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | 533 R200_Z_DECOMPRESSION_ENABLE; 534/* if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200) 535 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ 536 } 537 538 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE 539 | R200_TEX_BLEND_0_ENABLE); 540 541 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = color_fmt; 542 switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) { 543 case DRI_CONF_DITHER_XERRORDIFFRESET: 544 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; 545 break; 546 case DRI_CONF_DITHER_ORDERED: 547 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; 548 break; 549 } 550 if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) == 551 DRI_CONF_ROUND_ROUND ) 552 rmesa->state.color.roundEnable = R200_ROUND_ENABLE; 553 else 554 rmesa->state.color.roundEnable = 0; 555 if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) == 556 DRI_CONF_COLOR_REDUCTION_DITHER ) 557 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; 558 else 559 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; 560 561#if 000 562 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + 563 rmesa->r200Screen->fbLocation) 564 & R200_COLOROFFSET_MASK); 565 566 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & 567 R200_COLORPITCH_MASK) | 568 R200_COLOR_ENDIAN_NO_SWAP); 569#else 570 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset + 571 rmesa->r200Screen->fbLocation) 572 & R200_COLOROFFSET_MASK); 573 574 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch & 575 R200_COLORPITCH_MASK) | 576 R200_COLOR_ENDIAN_NO_SWAP); 577#endif 578 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */ 579 if (rmesa->sarea->tiling_enabled) { 580 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= R200_COLOR_TILE_ENABLE; 581 } 582 583 rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * 584 driQueryOptionf (&rmesa->optionCache,"texture_blend_quality"); 585 rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; 586 587 rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | 588 R200_BFACE_SOLID | 589 R200_FFACE_SOLID | 590 R200_FLAT_SHADE_VTX_LAST | 591 R200_DIFFUSE_SHADE_GOURAUD | 592 R200_ALPHA_SHADE_GOURAUD | 593 R200_SPECULAR_SHADE_GOURAUD | 594 R200_FOG_SHADE_GOURAUD | 595 R200_VTX_PIX_CENTER_OGL | 596 R200_ROUND_MODE_TRUNC | 597 R200_ROUND_PREC_8TH_PIX); 598 599 rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE | 600 R200_SCISSOR_ENABLE); 601 602 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); 603 604 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = 605 ((0 << R200_LINE_CURRENT_PTR_SHIFT) | 606 (1 << R200_LINE_CURRENT_COUNT_SHIFT)); 607 608 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); 609 610 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = 611 ((0x00 << R200_STENCIL_REF_SHIFT) | 612 (0xff << R200_STENCIL_MASK_SHIFT) | 613 (0xff << R200_STENCIL_WRITEMASK_SHIFT)); 614 615 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY; 616 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; 617 618 rmesa->hw.tam.cmd[TAM_DEBUG3] = 0; 619 620 rmesa->hw.msc.cmd[MSC_RE_MISC] = 621 ((0 << R200_STIPPLE_X_OFFSET_SHIFT) | 622 (0 << R200_STIPPLE_Y_OFFSET_SHIFT) | 623 R200_STIPPLE_BIG_BIT_ORDER); 624 625 626 rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; 627 rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0; 628 rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0; 629 rmesa->hw.cst.cmd[CST_RE_SCISSOR_TL_0] = 0; 630 rmesa->hw.cst.cmd[CST_RE_SCISSOR_BR_0] = 0; 631 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] = 632#ifdef MESA_BIG_ENDIAN 633 R200_VC_32BIT_SWAP; 634#else 635 R200_VC_NO_SWAP; 636#endif 637 638 if (!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) { 639 /* Bypass TCL */ 640 rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); 641 } 642 643 rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 0x100010; 644 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] = 645 (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT); 646 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] = 647 (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) | 648 (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT); 649 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] = 650 (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) | 651 (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) | 652 (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) | 653 (0x09 << R200_VTX_TEX_3_ADDR__SHIFT); 654 rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] = 655 (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) | 656 (0x0B << R200_VTX_TEX_5_ADDR__SHIFT); 657 658 659 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; 660 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; 661 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; 662 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; 663 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; 664 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; 665 666 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { 667 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL; 668 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = 669 ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */ 670 (2 << R200_TXFORMAT_WIDTH_SHIFT) | 671 (2 << R200_TXFORMAT_HEIGHT_SHIFT)); 672 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; 673 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = 674 (/* R200_TEXCOORD_PROJ | */ 675 0x100000); /* Small default bias */ 676 if (rmesa->r200Screen->drmSupportsFragShader) { 677 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = 678 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 679 rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; 680 rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; 681 } 682 else { 683 rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_OLDDRM] = 684 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 685 } 686 687 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; 688 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = 689 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 690 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = 691 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 692 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = 693 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 694 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = 695 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 696 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = 697 rmesa->r200Screen->texOffset[RADEON_LOCAL_TEX_HEAP]; 698 699 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = 700 (R200_TXC_ARG_A_ZERO | 701 R200_TXC_ARG_B_ZERO | 702 R200_TXC_ARG_C_DIFFUSE_COLOR | 703 R200_TXC_OP_MADD); 704 705 rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] = 706 ((i << R200_TXC_TFACTOR_SEL_SHIFT) | 707 R200_TXC_SCALE_1X | 708 R200_TXC_CLAMP_0_1 | 709 R200_TXC_OUTPUT_REG_R0); 710 711 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] = 712 (R200_TXA_ARG_A_ZERO | 713 R200_TXA_ARG_B_ZERO | 714 R200_TXA_ARG_C_DIFFUSE_ALPHA | 715 R200_TXA_OP_MADD); 716 717 rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] = 718 ((i << R200_TXA_TFACTOR_SEL_SHIFT) | 719 R200_TXA_SCALE_1X | 720 R200_TXA_CLAMP_0_1 | 721 R200_TXA_OUTPUT_REG_R0); 722 } 723 724 rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0; 725 rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0; 726 rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0; 727 rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0; 728 rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0; 729 rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0; 730 731 rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = 732 (R200_VAP_TCL_ENABLE | 733 (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)); 734 735 rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = 736 (R200_VPORT_X_SCALE_ENA | 737 R200_VPORT_Y_SCALE_ENA | 738 R200_VPORT_Z_SCALE_ENA | 739 R200_VPORT_X_OFFSET_ENA | 740 R200_VPORT_Y_OFFSET_ENA | 741 R200_VPORT_Z_OFFSET_ENA | 742/* FIXME: Turn on for tex rect only */ 743 R200_VTX_ST_DENORMALIZED | 744 R200_VTX_W0_FMT); 745 746 747 rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0; 748 rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0; 749 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = 750 ((R200_VTX_Z0 | R200_VTX_W0 | 751 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT))); 752 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0; 753 rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW); 754 rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE; 755 756 757 /* Matrix selection */ 758 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] = 759 (R200_MTX_MV << R200_MODELVIEW_0_SHIFT); 760 761 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] = 762 (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT); 763 764 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] = 765 (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT); 766 767 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] = 768 ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) | 769 (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) | 770 (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) | 771 (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT)); 772 773 rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] = 774 ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) | 775 (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT)); 776 777 778 /* General TCL state */ 779 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = 780 (R200_SPECULAR_LIGHTS | 781 R200_DIFFUSE_SPECULAR_COMBINE | 782 R200_LOCAL_LIGHT_VEC_GL | 783 R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT | 784 R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT); 785 786 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = 787 ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | 788 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) | 789 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | 790 (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) | 791 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) | 792 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) | 793 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) | 794 (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT)); 795 796 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */ 797 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0; 798 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0; 799 rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0; 800 801 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = 802 (R200_UCP_IN_CLIP_SPACE | 803 R200_CULL_FRONT_IS_CCW); 804 805 /* Texgen/Texmat state */ 806 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; 807 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = 808 ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) | 809 (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) | 810 (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) | 811 (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) | 812 (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) | 813 (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT)); 814 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; 815 rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = 816 ((0 << R200_TEXGEN_0_INPUT_SHIFT) | 817 (1 << R200_TEXGEN_1_INPUT_SHIFT) | 818 (2 << R200_TEXGEN_2_INPUT_SHIFT) | 819 (3 << R200_TEXGEN_3_INPUT_SHIFT) | 820 (4 << R200_TEXGEN_4_INPUT_SHIFT) | 821 (5 << R200_TEXGEN_5_INPUT_SHIFT)); 822 rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0; 823 824 825 for (i = 0 ; i < 8; i++) { 826 struct gl_light *l = &ctx->Light.Light[i]; 827 GLenum p = GL_LIGHT0 + i; 828 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; 829 830 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient ); 831 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse ); 832 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular ); 833 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); 834 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); 835 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent ); 836 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff ); 837 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, 838 &l->ConstantAttenuation ); 839 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, 840 &l->LinearAttenuation ); 841 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, 842 &l->QuadraticAttenuation ); 843 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; 844 } 845 846 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, 847 ctx->Light.Model.Ambient ); 848 849 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); 850 851 for (i = 0 ; i < 6; i++) { 852 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); 853 } 854 855 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); 856 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); 857 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); 858 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); 859 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); 860 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); 861 862 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; 863 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; 864 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; 865 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; 866 867 rmesa->hw.eye.cmd[EYE_X] = 0; 868 rmesa->hw.eye.cmd[EYE_Y] = 0; 869 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; 870 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; 871 872 r200LightingSpaceChange( ctx ); 873 874 rmesa->hw.all_dirty = GL_TRUE; 875} 876