radeon_screen.c revision 0f04a1d3f8989b0a391e6dad80abf06ce151d1f1
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include "main/glheader.h" 39#include "main/imports.h" 40#include "main/mtypes.h" 41#include "main/framebuffer.h" 42#include "main/renderbuffer.h" 43 44#define STANDALONE_MMIO 45#include "radeon_chipset.h" 46#include "radeon_macros.h" 47#include "radeon_screen.h" 48#if !RADEON_COMMON 49#include "radeon_context.h" 50#include "radeon_span.h" 51#include "radeon_tex.h" 52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 53#include "r200_context.h" 54#include "r200_ioctl.h" 55#include "r200_span.h" 56#include "r200_tex.h" 57#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 58#include "r300_context.h" 59#include "r300_fragprog.h" 60#include "r300_tex.h" 61#include "radeon_span.h" 62#endif 63 64#include "utils.h" 65#include "vblank.h" 66#include "drirenderbuffer.h" 67 68#include "GL/internal/dri_interface.h" 69 70/* Radeon configuration 71 */ 72#include "xmlpool.h" 73 74#if !RADEON_COMMON /* R100 */ 75PUBLIC const char __driConfigOptions[] = 76DRI_CONF_BEGIN 77 DRI_CONF_SECTION_PERFORMANCE 78 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 79 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 80 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 81 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 82 DRI_CONF_HYPERZ(false) 83 DRI_CONF_SECTION_END 84 DRI_CONF_SECTION_QUALITY 85 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 86 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 87 DRI_CONF_NO_NEG_LOD_BIAS(false) 88 DRI_CONF_FORCE_S3TC_ENABLE(false) 89 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 90 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 91 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 92 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 93 DRI_CONF_SECTION_END 94 DRI_CONF_SECTION_DEBUG 95 DRI_CONF_NO_RAST(false) 96 DRI_CONF_SECTION_END 97DRI_CONF_END; 98static const GLuint __driNConfigOptions = 14; 99 100#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 101 102PUBLIC const char __driConfigOptions[] = 103DRI_CONF_BEGIN 104 DRI_CONF_SECTION_PERFORMANCE 105 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 106 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 107 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 108 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 109 DRI_CONF_HYPERZ(false) 110 DRI_CONF_SECTION_END 111 DRI_CONF_SECTION_QUALITY 112 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 113 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 114 DRI_CONF_NO_NEG_LOD_BIAS(false) 115 DRI_CONF_FORCE_S3TC_ENABLE(false) 116 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 117 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 118 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 119 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 120 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 121 DRI_CONF_SECTION_END 122 DRI_CONF_SECTION_DEBUG 123 DRI_CONF_NO_RAST(false) 124 DRI_CONF_SECTION_END 125 DRI_CONF_SECTION_SOFTWARE 126 DRI_CONF_NV_VERTEX_PROGRAM(false) 127 DRI_CONF_SECTION_END 128DRI_CONF_END; 129static const GLuint __driNConfigOptions = 16; 130 131extern const struct dri_extension blend_extensions[]; 132extern const struct dri_extension ARB_vp_extension[]; 133extern const struct dri_extension NV_vp_extension[]; 134extern const struct dri_extension ATI_fs_extension[]; 135extern const struct dri_extension point_extensions[]; 136 137#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 138 139/* TODO: integrate these into xmlpool.h! */ 140#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 141DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 142 DRI_CONF_DESC(en,"Number of texture image units") \ 143 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 144DRI_CONF_OPT_END 145 146#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 147DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 148 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 149 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 150DRI_CONF_OPT_END 151 152#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 153DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 154 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 155 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 156DRI_CONF_OPT_END 157 158#define DRI_CONF_DISABLE_S3TC(def) \ 159DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 160 DRI_CONF_DESC(en,"Disable S3TC compression") \ 161DRI_CONF_OPT_END 162 163#define DRI_CONF_DISABLE_FALLBACK(def) \ 164DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 165 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 166DRI_CONF_OPT_END 167 168#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 169DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 170 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 171DRI_CONF_OPT_END 172 173#define DRI_CONF_FP_OPTIMIZATION(def) \ 174DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 175 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 176 DRI_CONF_ENUM(0,"Optimize for Speed") \ 177 DRI_CONF_ENUM(1,"Optimize for Quality") \ 178 DRI_CONF_DESC_END \ 179DRI_CONF_OPT_END 180 181PUBLIC const char __driConfigOptions[] = 182DRI_CONF_BEGIN 183 DRI_CONF_SECTION_PERFORMANCE 184 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 185 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 186 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 187 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 188 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 189 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 190 DRI_CONF_DISABLE_FALLBACK(true) 191 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 192 DRI_CONF_SECTION_END 193 DRI_CONF_SECTION_QUALITY 194 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 195 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 196 DRI_CONF_FORCE_S3TC_ENABLE(false) 197 DRI_CONF_DISABLE_S3TC(false) 198 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 199 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 200 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 201 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 202 DRI_CONF_SECTION_END 203 DRI_CONF_SECTION_DEBUG 204 DRI_CONF_NO_RAST(false) 205 DRI_CONF_SECTION_END 206DRI_CONF_END; 207static const GLuint __driNConfigOptions = 17; 208 209extern const struct dri_extension gl_20_extension[]; 210 211#ifndef RADEON_DEBUG 212int RADEON_DEBUG = 0; 213 214static const struct dri_debug_control debug_control[] = { 215 {"fall", DEBUG_FALLBACKS}, 216 {"tex", DEBUG_TEXTURE}, 217 {"ioctl", DEBUG_IOCTL}, 218 {"prim", DEBUG_PRIMS}, 219 {"vert", DEBUG_VERTS}, 220 {"state", DEBUG_STATE}, 221 {"code", DEBUG_CODEGEN}, 222 {"vfmt", DEBUG_VFMT}, 223 {"vtxf", DEBUG_VFMT}, 224 {"verb", DEBUG_VERBOSE}, 225 {"dri", DEBUG_DRI}, 226 {"dma", DEBUG_DMA}, 227 {"san", DEBUG_SANITY}, 228 {"sync", DEBUG_SYNC}, 229 {"pix", DEBUG_PIXEL}, 230 {"mem", DEBUG_MEMORY}, 231 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 232 {NULL, 0} 233}; 234#endif /* RADEON_DEBUG */ 235 236#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 237 238extern const struct dri_extension card_extensions[]; 239 240static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 241 242static int 243radeonGetParam(int fd, int param, void *value) 244{ 245 int ret; 246 drm_radeon_getparam_t gp; 247 248 gp.param = param; 249 gp.value = value; 250 251 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 252 return ret; 253} 254 255static const __DRIconfig ** 256radeonFillInModes( __DRIscreenPrivate *psp, 257 unsigned pixel_bits, unsigned depth_bits, 258 unsigned stencil_bits, GLboolean have_back_buffer ) 259{ 260 __DRIconfig **configs; 261 __GLcontextModes *m; 262 unsigned depth_buffer_factor; 263 unsigned back_buffer_factor; 264 GLenum fb_format; 265 GLenum fb_type; 266 int i; 267 268 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 269 * enough to add support. Basically, if a context is created with an 270 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 271 * will never be used. 272 */ 273 static const GLenum back_buffer_modes[] = { 274 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 275 }; 276 277 uint8_t depth_bits_array[2]; 278 uint8_t stencil_bits_array[2]; 279 uint8_t msaa_samples_array[1]; 280 281 depth_bits_array[0] = depth_bits; 282 depth_bits_array[1] = depth_bits; 283 284 /* Just like with the accumulation buffer, always provide some modes 285 * with a stencil buffer. It will be a sw fallback, but some apps won't 286 * care about that. 287 */ 288 stencil_bits_array[0] = 0; 289 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 290 291 msaa_samples_array[0] = 0; 292 293 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 294 back_buffer_factor = (have_back_buffer) ? 2 : 1; 295 296 if ( pixel_bits == 16 ) { 297 fb_format = GL_RGB; 298 fb_type = GL_UNSIGNED_SHORT_5_6_5; 299 } 300 else { 301 fb_format = GL_BGRA; 302 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 303 } 304 305 configs = driCreateConfigs(fb_format, fb_type, 306 depth_bits_array, stencil_bits_array, 307 depth_buffer_factor, 308 back_buffer_modes, back_buffer_factor, 309 msaa_samples_array, 1); 310 if (configs == NULL) { 311 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 312 __func__, __LINE__ ); 313 return NULL; 314 } 315 316 /* Mark the visual as slow if there are "fake" stencil bits. 317 */ 318 for (i = 0; configs[i]; i++) { 319 m = &configs[i]->modes; 320 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 321 m->visualRating = GLX_SLOW_CONFIG; 322 } 323 } 324 325 return (const __DRIconfig **) configs; 326} 327 328#if !RADEON_COMMON 329static const __DRItexOffsetExtension radeonTexOffsetExtension = { 330 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 331 radeonSetTexOffset, 332}; 333#endif 334 335#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 336static const __DRIallocateExtension r200AllocateExtension = { 337 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 338 r200AllocateMemoryMESA, 339 r200FreeMemoryMESA, 340 r200GetMemoryOffsetMESA 341}; 342 343static const __DRItexOffsetExtension r200texOffsetExtension = { 344 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 345 r200SetTexOffset, 346}; 347#endif 348 349#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 350static const __DRItexOffsetExtension r300texOffsetExtension = { 351 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 352 r300SetTexOffset, 353}; 354#endif 355 356/* Create the device specific screen private data struct. 357 */ 358static radeonScreenPtr 359radeonCreateScreen( __DRIscreenPrivate *sPriv ) 360{ 361 radeonScreenPtr screen; 362 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 363 unsigned char *RADEONMMIO; 364 int i; 365 int ret; 366 uint32_t temp = 0; 367 368 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 369 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 370 return GL_FALSE; 371 } 372 373 /* Allocate the private area */ 374 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 375 if ( !screen ) { 376 __driUtilMessage("%s: Could not allocate memory for screen structure", 377 __FUNCTION__); 378 return NULL; 379 } 380 381#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 382 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 383#endif 384 385 /* parse information in __driConfigOptions */ 386 driParseOptionInfo (&screen->optionCache, 387 __driConfigOptions, __driNConfigOptions); 388 389 /* This is first since which regions we map depends on whether or 390 * not we are using a PCI card. 391 */ 392 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 393 { 394 int ret; 395 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 396 &screen->gart_buffer_offset); 397 398 if (ret) { 399 FREE( screen ); 400 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 401 return NULL; 402 } 403 404 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 405 &screen->gart_base); 406 if (ret) { 407 FREE( screen ); 408 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 409 return NULL; 410 } 411 412 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 413 &screen->irq); 414 if (ret) { 415 FREE( screen ); 416 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 417 return NULL; 418 } 419 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 420 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 421 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 422 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 423 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 424 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 425 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 426 } 427 428 screen->mmio.handle = dri_priv->registerHandle; 429 screen->mmio.size = dri_priv->registerSize; 430 if ( drmMap( sPriv->fd, 431 screen->mmio.handle, 432 screen->mmio.size, 433 &screen->mmio.map ) ) { 434 FREE( screen ); 435 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 436 return NULL; 437 } 438 439 RADEONMMIO = screen->mmio.map; 440 441 screen->status.handle = dri_priv->statusHandle; 442 screen->status.size = dri_priv->statusSize; 443 if ( drmMap( sPriv->fd, 444 screen->status.handle, 445 screen->status.size, 446 &screen->status.map ) ) { 447 drmUnmap( screen->mmio.map, screen->mmio.size ); 448 FREE( screen ); 449 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 450 return NULL; 451 } 452 screen->scratch = (__volatile__ uint32_t *) 453 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 454 455 screen->buffers = drmMapBufs( sPriv->fd ); 456 if ( !screen->buffers ) { 457 drmUnmap( screen->status.map, screen->status.size ); 458 drmUnmap( screen->mmio.map, screen->mmio.size ); 459 FREE( screen ); 460 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 461 return NULL; 462 } 463 464 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 465 screen->gartTextures.handle = dri_priv->gartTexHandle; 466 screen->gartTextures.size = dri_priv->gartTexMapSize; 467 if ( drmMap( sPriv->fd, 468 screen->gartTextures.handle, 469 screen->gartTextures.size, 470 (drmAddressPtr)&screen->gartTextures.map ) ) { 471 drmUnmapBufs( screen->buffers ); 472 drmUnmap( screen->status.map, screen->status.size ); 473 drmUnmap( screen->mmio.map, screen->mmio.size ); 474 FREE( screen ); 475 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 476 return NULL; 477 } 478 479 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 480 } 481 482 screen->chip_flags = 0; 483 /* XXX: add more chipsets */ 484 switch ( dri_priv->deviceID ) { 485 case PCI_CHIP_RADEON_LY: 486 case PCI_CHIP_RADEON_LZ: 487 case PCI_CHIP_RADEON_QY: 488 case PCI_CHIP_RADEON_QZ: 489 case PCI_CHIP_RN50_515E: 490 case PCI_CHIP_RN50_5969: 491 screen->chip_family = CHIP_FAMILY_RV100; 492 break; 493 494 case PCI_CHIP_RS100_4136: 495 case PCI_CHIP_RS100_4336: 496 screen->chip_family = CHIP_FAMILY_RS100; 497 break; 498 499 case PCI_CHIP_RS200_4137: 500 case PCI_CHIP_RS200_4337: 501 case PCI_CHIP_RS250_4237: 502 case PCI_CHIP_RS250_4437: 503 screen->chip_family = CHIP_FAMILY_RS200; 504 break; 505 506 case PCI_CHIP_RADEON_QD: 507 case PCI_CHIP_RADEON_QE: 508 case PCI_CHIP_RADEON_QF: 509 case PCI_CHIP_RADEON_QG: 510 /* all original radeons (7200) presumably have a stencil op bug */ 511 screen->chip_family = CHIP_FAMILY_R100; 512 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 513 break; 514 515 case PCI_CHIP_RV200_QW: 516 case PCI_CHIP_RV200_QX: 517 case PCI_CHIP_RADEON_LW: 518 case PCI_CHIP_RADEON_LX: 519 screen->chip_family = CHIP_FAMILY_RV200; 520 screen->chip_flags = RADEON_CHIPSET_TCL; 521 break; 522 523 case PCI_CHIP_R200_BB: 524 case PCI_CHIP_R200_BC: 525 case PCI_CHIP_R200_QH: 526 case PCI_CHIP_R200_QL: 527 case PCI_CHIP_R200_QM: 528 screen->chip_family = CHIP_FAMILY_R200; 529 screen->chip_flags = RADEON_CHIPSET_TCL; 530 break; 531 532 case PCI_CHIP_RV250_If: 533 case PCI_CHIP_RV250_Ig: 534 case PCI_CHIP_RV250_Ld: 535 case PCI_CHIP_RV250_Lf: 536 case PCI_CHIP_RV250_Lg: 537 screen->chip_family = CHIP_FAMILY_RV250; 538 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 539 break; 540 541 case PCI_CHIP_RV280_5960: 542 case PCI_CHIP_RV280_5961: 543 case PCI_CHIP_RV280_5962: 544 case PCI_CHIP_RV280_5964: 545 case PCI_CHIP_RV280_5965: 546 case PCI_CHIP_RV280_5C61: 547 case PCI_CHIP_RV280_5C63: 548 screen->chip_family = CHIP_FAMILY_RV280; 549 screen->chip_flags = RADEON_CHIPSET_TCL; 550 break; 551 552 case PCI_CHIP_RS300_5834: 553 case PCI_CHIP_RS300_5835: 554 case PCI_CHIP_RS350_7834: 555 case PCI_CHIP_RS350_7835: 556 screen->chip_family = CHIP_FAMILY_RS300; 557 break; 558 559 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 560 case PCI_CHIP_R300_AD: 561 screen->chip_family = CHIP_FAMILY_RV350; 562 screen->chip_flags = RADEON_CHIPSET_TCL; 563 break; 564 case PCI_CHIP_R300_AE: 565 case PCI_CHIP_R300_AF: 566 case PCI_CHIP_R300_AG: 567 case PCI_CHIP_R300_ND: 568 case PCI_CHIP_R300_NE: 569 case PCI_CHIP_R300_NF: 570 case PCI_CHIP_R300_NG: 571 screen->chip_family = CHIP_FAMILY_R300; 572 screen->chip_flags = RADEON_CHIPSET_TCL; 573 break; 574 575 case PCI_CHIP_RV350_AP: 576 case PCI_CHIP_RV350_AQ: 577 case PCI_CHIP_RV350_AR: 578 case PCI_CHIP_RV350_AS: 579 case PCI_CHIP_RV350_AT: 580 case PCI_CHIP_RV350_AV: 581 case PCI_CHIP_RV350_AU: 582 case PCI_CHIP_RV350_NP: 583 case PCI_CHIP_RV350_NQ: 584 case PCI_CHIP_RV350_NR: 585 case PCI_CHIP_RV350_NS: 586 case PCI_CHIP_RV350_NT: 587 case PCI_CHIP_RV350_NV: 588 screen->chip_family = CHIP_FAMILY_RV350; 589 screen->chip_flags = RADEON_CHIPSET_TCL; 590 break; 591 592 case PCI_CHIP_R350_AH: 593 case PCI_CHIP_R350_AI: 594 case PCI_CHIP_R350_AJ: 595 case PCI_CHIP_R350_AK: 596 case PCI_CHIP_R350_NH: 597 case PCI_CHIP_R350_NI: 598 case PCI_CHIP_R360_NJ: 599 case PCI_CHIP_R350_NK: 600 screen->chip_family = CHIP_FAMILY_R350; 601 screen->chip_flags = RADEON_CHIPSET_TCL; 602 break; 603 604 case PCI_CHIP_RV370_5460: 605 case PCI_CHIP_RV370_5462: 606 case PCI_CHIP_RV370_5464: 607 case PCI_CHIP_RV370_5B60: 608 case PCI_CHIP_RV370_5B62: 609 case PCI_CHIP_RV370_5B63: 610 case PCI_CHIP_RV370_5B64: 611 case PCI_CHIP_RV370_5B65: 612 case PCI_CHIP_RV380_3150: 613 case PCI_CHIP_RV380_3152: 614 case PCI_CHIP_RV380_3154: 615 case PCI_CHIP_RV380_3E50: 616 case PCI_CHIP_RV380_3E54: 617 screen->chip_family = CHIP_FAMILY_RV380; 618 screen->chip_flags = RADEON_CHIPSET_TCL; 619 break; 620 621 case PCI_CHIP_R420_JN: 622 case PCI_CHIP_R420_JH: 623 case PCI_CHIP_R420_JI: 624 case PCI_CHIP_R420_JJ: 625 case PCI_CHIP_R420_JK: 626 case PCI_CHIP_R420_JL: 627 case PCI_CHIP_R420_JM: 628 case PCI_CHIP_R420_JO: 629 case PCI_CHIP_R420_JP: 630 case PCI_CHIP_R420_JT: 631 case PCI_CHIP_R481_4B49: 632 case PCI_CHIP_R481_4B4A: 633 case PCI_CHIP_R481_4B4B: 634 case PCI_CHIP_R481_4B4C: 635 case PCI_CHIP_R423_UH: 636 case PCI_CHIP_R423_UI: 637 case PCI_CHIP_R423_UJ: 638 case PCI_CHIP_R423_UK: 639 case PCI_CHIP_R430_554C: 640 case PCI_CHIP_R430_554D: 641 case PCI_CHIP_R430_554E: 642 case PCI_CHIP_R430_554F: 643 case PCI_CHIP_R423_5550: 644 case PCI_CHIP_R423_UQ: 645 case PCI_CHIP_R423_UR: 646 case PCI_CHIP_R423_UT: 647 case PCI_CHIP_R430_5D48: 648 case PCI_CHIP_R430_5D49: 649 case PCI_CHIP_R430_5D4A: 650 case PCI_CHIP_R480_5D4C: 651 case PCI_CHIP_R480_5D4D: 652 case PCI_CHIP_R480_5D4E: 653 case PCI_CHIP_R480_5D4F: 654 case PCI_CHIP_R480_5D50: 655 case PCI_CHIP_R480_5D52: 656 case PCI_CHIP_R423_5D57: 657 screen->chip_family = CHIP_FAMILY_R420; 658 screen->chip_flags = RADEON_CHIPSET_TCL; 659 break; 660 661 case PCI_CHIP_RV410_5E4C: 662 case PCI_CHIP_RV410_5E4F: 663 case PCI_CHIP_RV410_564A: 664 case PCI_CHIP_RV410_564B: 665 case PCI_CHIP_RV410_564F: 666 case PCI_CHIP_RV410_5652: 667 case PCI_CHIP_RV410_5653: 668 case PCI_CHIP_RV410_5657: 669 case PCI_CHIP_RV410_5E48: 670 case PCI_CHIP_RV410_5E4A: 671 case PCI_CHIP_RV410_5E4B: 672 case PCI_CHIP_RV410_5E4D: 673 screen->chip_family = CHIP_FAMILY_RV410; 674 screen->chip_flags = RADEON_CHIPSET_TCL; 675 break; 676 677 case PCI_CHIP_RS480_5954: 678 case PCI_CHIP_RS480_5955: 679 case PCI_CHIP_RS482_5974: 680 case PCI_CHIP_RS482_5975: 681 case PCI_CHIP_RS400_5A41: 682 case PCI_CHIP_RS400_5A42: 683 case PCI_CHIP_RC410_5A61: 684 case PCI_CHIP_RC410_5A62: 685 screen->chip_family = CHIP_FAMILY_RS400; 686 break; 687 688 case PCI_CHIP_RS600_793F: 689 case PCI_CHIP_RS600_7941: 690 case PCI_CHIP_RS600_7942: 691 screen->chip_family = CHIP_FAMILY_RS600; 692 break; 693 694 case PCI_CHIP_RS690_791E: 695 case PCI_CHIP_RS690_791F: 696 screen->chip_family = CHIP_FAMILY_RS690; 697 break; 698 case PCI_CHIP_RS740_796C: 699 case PCI_CHIP_RS740_796D: 700 case PCI_CHIP_RS740_796E: 701 case PCI_CHIP_RS740_796F: 702 screen->chip_family = CHIP_FAMILY_RS740; 703 break; 704 705 case PCI_CHIP_R520_7100: 706 case PCI_CHIP_R520_7101: 707 case PCI_CHIP_R520_7102: 708 case PCI_CHIP_R520_7103: 709 case PCI_CHIP_R520_7104: 710 case PCI_CHIP_R520_7105: 711 case PCI_CHIP_R520_7106: 712 case PCI_CHIP_R520_7108: 713 case PCI_CHIP_R520_7109: 714 case PCI_CHIP_R520_710A: 715 case PCI_CHIP_R520_710B: 716 case PCI_CHIP_R520_710C: 717 case PCI_CHIP_R520_710E: 718 case PCI_CHIP_R520_710F: 719 screen->chip_family = CHIP_FAMILY_R520; 720 screen->chip_flags = RADEON_CHIPSET_TCL; 721 break; 722 723 case PCI_CHIP_RV515_7140: 724 case PCI_CHIP_RV515_7141: 725 case PCI_CHIP_RV515_7142: 726 case PCI_CHIP_RV515_7143: 727 case PCI_CHIP_RV515_7144: 728 case PCI_CHIP_RV515_7145: 729 case PCI_CHIP_RV515_7146: 730 case PCI_CHIP_RV515_7147: 731 case PCI_CHIP_RV515_7149: 732 case PCI_CHIP_RV515_714A: 733 case PCI_CHIP_RV515_714B: 734 case PCI_CHIP_RV515_714C: 735 case PCI_CHIP_RV515_714D: 736 case PCI_CHIP_RV515_714E: 737 case PCI_CHIP_RV515_714F: 738 case PCI_CHIP_RV515_7151: 739 case PCI_CHIP_RV515_7152: 740 case PCI_CHIP_RV515_7153: 741 case PCI_CHIP_RV515_715E: 742 case PCI_CHIP_RV515_715F: 743 case PCI_CHIP_RV515_7180: 744 case PCI_CHIP_RV515_7181: 745 case PCI_CHIP_RV515_7183: 746 case PCI_CHIP_RV515_7186: 747 case PCI_CHIP_RV515_7187: 748 case PCI_CHIP_RV515_7188: 749 case PCI_CHIP_RV515_718A: 750 case PCI_CHIP_RV515_718B: 751 case PCI_CHIP_RV515_718C: 752 case PCI_CHIP_RV515_718D: 753 case PCI_CHIP_RV515_718F: 754 case PCI_CHIP_RV515_7193: 755 case PCI_CHIP_RV515_7196: 756 case PCI_CHIP_RV515_719B: 757 case PCI_CHIP_RV515_719F: 758 case PCI_CHIP_RV515_7200: 759 case PCI_CHIP_RV515_7210: 760 case PCI_CHIP_RV515_7211: 761 screen->chip_family = CHIP_FAMILY_RV515; 762 screen->chip_flags = RADEON_CHIPSET_TCL; 763 break; 764 765 case PCI_CHIP_RV530_71C0: 766 case PCI_CHIP_RV530_71C1: 767 case PCI_CHIP_RV530_71C2: 768 case PCI_CHIP_RV530_71C3: 769 case PCI_CHIP_RV530_71C4: 770 case PCI_CHIP_RV530_71C5: 771 case PCI_CHIP_RV530_71C6: 772 case PCI_CHIP_RV530_71C7: 773 case PCI_CHIP_RV530_71CD: 774 case PCI_CHIP_RV530_71CE: 775 case PCI_CHIP_RV530_71D2: 776 case PCI_CHIP_RV530_71D4: 777 case PCI_CHIP_RV530_71D5: 778 case PCI_CHIP_RV530_71D6: 779 case PCI_CHIP_RV530_71DA: 780 case PCI_CHIP_RV530_71DE: 781 screen->chip_family = CHIP_FAMILY_RV530; 782 screen->chip_flags = RADEON_CHIPSET_TCL; 783 break; 784 785 case PCI_CHIP_R580_7240: 786 case PCI_CHIP_R580_7243: 787 case PCI_CHIP_R580_7244: 788 case PCI_CHIP_R580_7245: 789 case PCI_CHIP_R580_7246: 790 case PCI_CHIP_R580_7247: 791 case PCI_CHIP_R580_7248: 792 case PCI_CHIP_R580_7249: 793 case PCI_CHIP_R580_724A: 794 case PCI_CHIP_R580_724B: 795 case PCI_CHIP_R580_724C: 796 case PCI_CHIP_R580_724D: 797 case PCI_CHIP_R580_724E: 798 case PCI_CHIP_R580_724F: 799 case PCI_CHIP_R580_7284: 800 screen->chip_family = CHIP_FAMILY_R580; 801 screen->chip_flags = RADEON_CHIPSET_TCL; 802 break; 803 804 case PCI_CHIP_RV570_7280: 805 case PCI_CHIP_RV560_7281: 806 case PCI_CHIP_RV560_7283: 807 case PCI_CHIP_RV560_7287: 808 case PCI_CHIP_RV570_7288: 809 case PCI_CHIP_RV570_7289: 810 case PCI_CHIP_RV570_728B: 811 case PCI_CHIP_RV570_728C: 812 case PCI_CHIP_RV560_7290: 813 case PCI_CHIP_RV560_7291: 814 case PCI_CHIP_RV560_7293: 815 case PCI_CHIP_RV560_7297: 816 screen->chip_family = CHIP_FAMILY_RV560; 817 screen->chip_flags = RADEON_CHIPSET_TCL; 818 break; 819 820 default: 821 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 822 dri_priv->deviceID); 823 return NULL; 824 } 825 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 826 sPriv->ddx_version.minor < 2) { 827 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 828 return NULL; 829 } 830 831 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 832 fprintf(stderr, "R500 support requires a newer drm.\n"); 833 return NULL; 834 } 835 836 if (getenv("R300_NO_TCL")) 837 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 838 839 if (screen->chip_family <= CHIP_FAMILY_RS200) 840 screen->chip_flags |= RADEON_CLASS_R100; 841 else if (screen->chip_family <= CHIP_FAMILY_RV280) 842 screen->chip_flags |= RADEON_CLASS_R200; 843 else 844 screen->chip_flags |= RADEON_CLASS_R300; 845 846 screen->cpp = dri_priv->bpp / 8; 847 screen->AGPMode = dri_priv->AGPMode; 848 849 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 850 &temp); 851 if (ret) { 852 if (screen->chip_family < CHIP_FAMILY_RS600) 853 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 854 else { 855 FREE( screen ); 856 fprintf(stderr, "Unable to get fb location need newer drm\n"); 857 return NULL; 858 } 859 } else { 860 screen->fbLocation = (temp & 0xffff) << 16; 861 } 862 863 if (screen->chip_family >= CHIP_FAMILY_R300) { 864 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 865 &temp); 866 if (ret) { 867 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 868 switch (screen->chip_family) { 869 case CHIP_FAMILY_R300: 870 case CHIP_FAMILY_R350: 871 screen->num_gb_pipes = 2; 872 break; 873 case CHIP_FAMILY_R420: 874 case CHIP_FAMILY_R520: 875 case CHIP_FAMILY_R580: 876 case CHIP_FAMILY_RV560: 877 case CHIP_FAMILY_RV570: 878 screen->num_gb_pipes = 4; 879 break; 880 case CHIP_FAMILY_RV350: 881 case CHIP_FAMILY_RV515: 882 case CHIP_FAMILY_RV530: 883 case CHIP_FAMILY_RV410: 884 default: 885 screen->num_gb_pipes = 1; 886 break; 887 } 888 } else { 889 screen->num_gb_pipes = temp; 890 } 891 } 892 893 if ( sPriv->drm_version.minor >= 10 ) { 894 drm_radeon_setparam_t sp; 895 896 sp.param = RADEON_SETPARAM_FB_LOCATION; 897 sp.value = screen->fbLocation; 898 899 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 900 &sp, sizeof( sp ) ); 901 } 902 903 screen->frontOffset = dri_priv->frontOffset; 904 screen->frontPitch = dri_priv->frontPitch; 905 screen->backOffset = dri_priv->backOffset; 906 screen->backPitch = dri_priv->backPitch; 907 screen->depthOffset = dri_priv->depthOffset; 908 screen->depthPitch = dri_priv->depthPitch; 909 910 /* Check if ddx has set up a surface reg to cover depth buffer */ 911 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 912 /* these chips don't use tiled z without hyperz. So always pretend 913 we have set up a surface which will cause linear reads/writes */ 914 (IS_R100_CLASS(screen) && 915 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 916 917 if ( dri_priv->textureSize == 0 ) { 918 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 919 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 920 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 921 dri_priv->log2GARTTexGran; 922 } else { 923 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 924 + screen->fbLocation; 925 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 926 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 927 dri_priv->log2TexGran; 928 } 929 930 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 931 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 932 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 933 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 934 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 935 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 936 } else { 937 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 938 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 939 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 940 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 941 dri_priv->log2GARTTexGran; 942 } 943 944 i = 0; 945 screen->extensions[i++] = &driCopySubBufferExtension.base; 946 screen->extensions[i++] = &driFrameTrackingExtension.base; 947 screen->extensions[i++] = &driReadDrawableExtension; 948 949 if ( screen->irq != 0 ) { 950 screen->extensions[i++] = &driSwapControlExtension.base; 951 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 952 } 953 954#if !RADEON_COMMON 955 screen->extensions[i++] = &radeonTexOffsetExtension.base; 956#endif 957 958#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 959 if (IS_R200_CLASS(screen)) 960 screen->extensions[i++] = &r200AllocateExtension.base; 961 962 screen->extensions[i++] = &r200texOffsetExtension.base; 963#endif 964 965#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 966 screen->extensions[i++] = &r300texOffsetExtension.base; 967#endif 968 969 screen->extensions[i++] = NULL; 970 sPriv->extensions = screen->extensions; 971 972 screen->driScreen = sPriv; 973 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 974 return screen; 975} 976 977/* Destroy the device specific screen private data struct. 978 */ 979static void 980radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 981{ 982 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 983 984 if (!screen) 985 return; 986 987 if ( screen->gartTextures.map ) { 988 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 989 } 990 drmUnmapBufs( screen->buffers ); 991 drmUnmap( screen->status.map, screen->status.size ); 992 drmUnmap( screen->mmio.map, screen->mmio.size ); 993 994 /* free all option information */ 995 driDestroyOptionInfo (&screen->optionCache); 996 997 FREE( screen ); 998 sPriv->private = NULL; 999} 1000 1001 1002/* Initialize the driver specific screen private data. 1003 */ 1004static GLboolean 1005radeonInitDriver( __DRIscreenPrivate *sPriv ) 1006{ 1007 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1008 if ( !sPriv->private ) { 1009 radeonDestroyScreen( sPriv ); 1010 return GL_FALSE; 1011 } 1012 1013 return GL_TRUE; 1014} 1015 1016 1017/** 1018 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1019 * 1020 * \todo This function (and its interface) will need to be updated to support 1021 * pbuffers. 1022 */ 1023static GLboolean 1024radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1025 __DRIdrawablePrivate *driDrawPriv, 1026 const __GLcontextModes *mesaVis, 1027 GLboolean isPixmap ) 1028{ 1029 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1030 1031 if (isPixmap) { 1032 return GL_FALSE; /* not implemented */ 1033 } 1034 else { 1035 const GLboolean swDepth = GL_FALSE; 1036 const GLboolean swAlpha = GL_FALSE; 1037 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1038 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1039 mesaVis->depthBits != 24; 1040 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1041 1042 /* front color renderbuffer */ 1043 { 1044 driRenderbuffer *frontRb 1045 = driNewRenderbuffer(GL_RGBA, 1046 driScrnPriv->pFB + screen->frontOffset, 1047 screen->cpp, 1048 screen->frontOffset, screen->frontPitch, 1049 driDrawPriv); 1050 radeonSetSpanFunctions(frontRb, mesaVis); 1051 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); 1052 } 1053 1054 /* back color renderbuffer */ 1055 if (mesaVis->doubleBufferMode) { 1056 driRenderbuffer *backRb 1057 = driNewRenderbuffer(GL_RGBA, 1058 driScrnPriv->pFB + screen->backOffset, 1059 screen->cpp, 1060 screen->backOffset, screen->backPitch, 1061 driDrawPriv); 1062 radeonSetSpanFunctions(backRb, mesaVis); 1063 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); 1064 } 1065 1066 /* depth renderbuffer */ 1067 if (mesaVis->depthBits == 16) { 1068 driRenderbuffer *depthRb 1069 = driNewRenderbuffer(GL_DEPTH_COMPONENT16, 1070 driScrnPriv->pFB + screen->depthOffset, 1071 screen->cpp, 1072 screen->depthOffset, screen->depthPitch, 1073 driDrawPriv); 1074 radeonSetSpanFunctions(depthRb, mesaVis); 1075 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 1076 depthRb->depthHasSurface = screen->depthHasSurface; 1077 } 1078 else if (mesaVis->depthBits == 24) { 1079 driRenderbuffer *depthRb 1080 = driNewRenderbuffer(GL_DEPTH_COMPONENT24, 1081 driScrnPriv->pFB + screen->depthOffset, 1082 screen->cpp, 1083 screen->depthOffset, screen->depthPitch, 1084 driDrawPriv); 1085 radeonSetSpanFunctions(depthRb, mesaVis); 1086 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 1087 depthRb->depthHasSurface = screen->depthHasSurface; 1088 } 1089 1090 /* stencil renderbuffer */ 1091 if (mesaVis->stencilBits > 0 && !swStencil) { 1092 driRenderbuffer *stencilRb 1093 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, 1094 driScrnPriv->pFB + screen->depthOffset, 1095 screen->cpp, 1096 screen->depthOffset, screen->depthPitch, 1097 driDrawPriv); 1098 radeonSetSpanFunctions(stencilRb, mesaVis); 1099 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); 1100 stencilRb->depthHasSurface = screen->depthHasSurface; 1101 } 1102 1103 _mesa_add_soft_renderbuffers(fb, 1104 GL_FALSE, /* color */ 1105 swDepth, 1106 swStencil, 1107 swAccum, 1108 swAlpha, 1109 GL_FALSE /* aux */); 1110 driDrawPriv->driverPrivate = (void *) fb; 1111 1112 return (driDrawPriv->driverPrivate != NULL); 1113 } 1114} 1115 1116 1117static void 1118radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1119{ 1120 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1121} 1122 1123#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1124/** 1125 * Choose the appropriate CreateContext function based on the chipset. 1126 * Eventually, all drivers will go through this process. 1127 */ 1128static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1129 __DRIcontextPrivate * driContextPriv, 1130 void *sharedContextPriv) 1131{ 1132 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1133 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1134 1135 if (IS_R300_CLASS(screen)) 1136 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1137 return GL_FALSE; 1138} 1139 1140/** 1141 * Choose the appropriate DestroyContext function based on the chipset. 1142 */ 1143static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1144{ 1145 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1146 1147 if (IS_R300_CLASS(radeon->radeonScreen)) 1148 return r300DestroyContext(driContextPriv); 1149} 1150 1151 1152#endif 1153 1154 1155/** 1156 * This is the driver specific part of the createNewScreen entry point. 1157 * 1158 * \todo maybe fold this into intelInitDriver 1159 * 1160 * \return the __GLcontextModes supported by this driver 1161 */ 1162static const __DRIconfig ** 1163radeonInitScreen(__DRIscreenPrivate *psp) 1164{ 1165#if !RADEON_COMMON 1166 static const char *driver_name = "Radeon"; 1167 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1168 static const __DRIversion dri_expected = { 4, 0, 0 }; 1169 static const __DRIversion drm_expected = { 1, 6, 0 }; 1170#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1171 static const char *driver_name = "R200"; 1172 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1173 static const __DRIversion dri_expected = { 4, 0, 0 }; 1174 static const __DRIversion drm_expected = { 1, 6, 0 }; 1175#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1176 static const char *driver_name = "R300"; 1177 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1178 static const __DRIversion dri_expected = { 4, 0, 0 }; 1179 static const __DRIversion drm_expected = { 1, 24, 0 }; 1180#endif 1181 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1182 1183 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1184 &psp->dri_version, & dri_expected, 1185 &psp->ddx_version, & ddx_expected, 1186 &psp->drm_version, & drm_expected ) ) { 1187 return NULL; 1188 } 1189 1190 /* Calling driInitExtensions here, with a NULL context pointer, 1191 * does not actually enable the extensions. It just makes sure 1192 * that all the dispatch offsets for all the extensions that 1193 * *might* be enables are known. This is needed because the 1194 * dispatch offsets need to be known when _mesa_context_create 1195 * is called, but we can't enable the extensions until we have a 1196 * context pointer. 1197 * 1198 * Hello chicken. Hello egg. How are you two today? 1199 */ 1200 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1201#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1202 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1203 driInitSingleExtension( NULL, ARB_vp_extension ); 1204 driInitSingleExtension( NULL, NV_vp_extension ); 1205 driInitSingleExtension( NULL, ATI_fs_extension ); 1206 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1207#elif defined(RADEON_COMMON_FOR_R300) 1208 driInitSingleExtension( NULL, gl_20_extension ); 1209#endif 1210 1211 if (!radeonInitDriver(psp)) 1212 return NULL; 1213 1214 return radeonFillInModes( psp, 1215 dri_priv->bpp, 1216 (dri_priv->bpp == 16) ? 16 : 24, 1217 (dri_priv->bpp == 16) ? 0 : 8, 1218 (dri_priv->backOffset != dri_priv->depthOffset) ); 1219} 1220 1221 1222/** 1223 * Get information about previous buffer swaps. 1224 */ 1225static int 1226getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1227{ 1228#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1229 radeonContextPtr rmesa; 1230#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1231 r200ContextPtr rmesa; 1232#endif 1233 1234 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1235 || (dPriv->driContextPriv->driverPrivate == NULL) 1236 || (sInfo == NULL) ) { 1237 return -1; 1238 } 1239 1240 rmesa = dPriv->driContextPriv->driverPrivate; 1241 sInfo->swap_count = rmesa->swap_count; 1242 sInfo->swap_ust = rmesa->swap_ust; 1243 sInfo->swap_missed_count = rmesa->swap_missed_count; 1244 1245 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1246 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1247 : 0.0; 1248 1249 return 0; 1250} 1251 1252#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1253const struct __DriverAPIRec driDriverAPI = { 1254 .InitScreen = radeonInitScreen, 1255 .DestroyScreen = radeonDestroyScreen, 1256 .CreateContext = radeonCreateContext, 1257 .DestroyContext = radeonDestroyContext, 1258 .CreateBuffer = radeonCreateBuffer, 1259 .DestroyBuffer = radeonDestroyBuffer, 1260 .SwapBuffers = radeonSwapBuffers, 1261 .MakeCurrent = radeonMakeCurrent, 1262 .UnbindContext = radeonUnbindContext, 1263 .GetSwapInfo = getSwapInfo, 1264 .GetDrawableMSC = driDrawableGetMSC32, 1265 .WaitForMSC = driWaitForMSC32, 1266 .WaitForSBC = NULL, 1267 .SwapBuffersMSC = NULL, 1268 .CopySubBuffer = radeonCopySubBuffer, 1269}; 1270#else 1271const struct __DriverAPIRec driDriverAPI = { 1272 .InitScreen = radeonInitScreen, 1273 .DestroyScreen = radeonDestroyScreen, 1274 .CreateContext = r200CreateContext, 1275 .DestroyContext = r200DestroyContext, 1276 .CreateBuffer = radeonCreateBuffer, 1277 .DestroyBuffer = radeonDestroyBuffer, 1278 .SwapBuffers = r200SwapBuffers, 1279 .MakeCurrent = r200MakeCurrent, 1280 .UnbindContext = r200UnbindContext, 1281 .GetSwapInfo = getSwapInfo, 1282 .GetDrawableMSC = driDrawableGetMSC32, 1283 .WaitForMSC = driWaitForMSC32, 1284 .WaitForSBC = NULL, 1285 .SwapBuffersMSC = NULL, 1286 .CopySubBuffer = r200CopySubBuffer, 1287}; 1288#endif 1289