radeon_screen.c revision 234286c0f8b7d30ed49223c648d4c73c1a517ab3
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#if defined(RADEON_R100) 51#include "radeon_context.h" 52#include "radeon_tex.h" 53#elif defined(RADEON_R200) 54#include "r200_context.h" 55#include "r200_ioctl.h" 56#include "r200_tex.h" 57#elif defined(RADEON_R300) 58#include "r300_context.h" 59#include "r300_tex.h" 60#elif defined(RADEON_R600) 61#include "r600_context.h" 62#include "r700_driconf.h" /* +r6/r7 */ 63#include "r600_tex.h" /* +r6/r7 */ 64#endif 65 66#include "utils.h" 67#include "vblank.h" 68 69#include "radeon_bocs_wrapper.h" 70 71#include "GL/internal/dri_interface.h" 72 73/* Radeon configuration 74 */ 75#include "xmlpool.h" 76 77#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 78DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 79 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 80 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 81DRI_CONF_OPT_END 82 83#if defined(RADEON_R100) /* R100 */ 84PUBLIC const char __driConfigOptions[] = 85DRI_CONF_BEGIN 86 DRI_CONF_SECTION_PERFORMANCE 87 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 88 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 89 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 90 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 91 DRI_CONF_HYPERZ(false) 92 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 93 DRI_CONF_SECTION_END 94 DRI_CONF_SECTION_QUALITY 95 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 96 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 97 DRI_CONF_NO_NEG_LOD_BIAS(false) 98 DRI_CONF_FORCE_S3TC_ENABLE(false) 99 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 100 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 101 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 102 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 103 DRI_CONF_SECTION_END 104 DRI_CONF_SECTION_DEBUG 105 DRI_CONF_NO_RAST(false) 106 DRI_CONF_SECTION_END 107DRI_CONF_END; 108static const GLuint __driNConfigOptions = 15; 109 110#elif defined(RADEON_R200) 111 112PUBLIC const char __driConfigOptions[] = 113DRI_CONF_BEGIN 114 DRI_CONF_SECTION_PERFORMANCE 115 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 116 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 117 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 118 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 119 DRI_CONF_HYPERZ(false) 120 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 121 DRI_CONF_SECTION_END 122 DRI_CONF_SECTION_QUALITY 123 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 124 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 125 DRI_CONF_NO_NEG_LOD_BIAS(false) 126 DRI_CONF_FORCE_S3TC_ENABLE(false) 127 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 128 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 129 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 130 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 131 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 132 DRI_CONF_SECTION_END 133 DRI_CONF_SECTION_DEBUG 134 DRI_CONF_NO_RAST(false) 135 DRI_CONF_SECTION_END 136 DRI_CONF_SECTION_SOFTWARE 137 DRI_CONF_NV_VERTEX_PROGRAM(false) 138 DRI_CONF_SECTION_END 139DRI_CONF_END; 140static const GLuint __driNConfigOptions = 17; 141 142#elif defined(RADEON_R300) || defined(RADEON_R600) 143 144#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 145#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 146 147/* TODO: integrate these into xmlpool.h! */ 148#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 149DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 150 DRI_CONF_DESC(en,"Number of texture image units") \ 151 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 152DRI_CONF_OPT_END 153 154#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 155DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 156 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 157 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 158DRI_CONF_OPT_END 159 160 161 162#define DRI_CONF_DISABLE_S3TC(def) \ 163DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 164 DRI_CONF_DESC(en,"Disable S3TC compression") \ 165DRI_CONF_OPT_END 166 167#define DRI_CONF_DISABLE_FALLBACK(def) \ 168DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 169 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 170DRI_CONF_OPT_END 171 172#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 173DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 174 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 175DRI_CONF_OPT_END 176 177#define DRI_CONF_FP_OPTIMIZATION(def) \ 178DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 179 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 180 DRI_CONF_ENUM(0,"Optimize for Speed") \ 181 DRI_CONF_ENUM(1,"Optimize for Quality") \ 182 DRI_CONF_DESC_END \ 183DRI_CONF_OPT_END 184 185PUBLIC const char __driConfigOptions[] = 186DRI_CONF_BEGIN 187 DRI_CONF_SECTION_PERFORMANCE 188 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 189 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 190 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 191 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 192 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 193 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 194 DRI_CONF_DISABLE_FALLBACK(true) 195 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 196 DRI_CONF_SECTION_END 197 DRI_CONF_SECTION_QUALITY 198 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 199 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 200 DRI_CONF_FORCE_S3TC_ENABLE(false) 201 DRI_CONF_DISABLE_S3TC(false) 202 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 203 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 204 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 205 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 206 DRI_CONF_SECTION_END 207 DRI_CONF_SECTION_DEBUG 208 DRI_CONF_NO_RAST(false) 209 DRI_CONF_SECTION_END 210DRI_CONF_END; 211static const GLuint __driNConfigOptions = 17; 212 213#endif 214 215static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ); 216 217static int 218radeonGetParam(__DRIscreen *sPriv, int param, void *value) 219{ 220 int ret; 221 drm_radeon_getparam_t gp = { 0 }; 222 struct drm_radeon_info info = { 0 }; 223 224 if (sPriv->drm_version.major >= 2) { 225 info.value = (uint64_t)(uintptr_t)value; 226 switch (param) { 227 case RADEON_PARAM_DEVICE_ID: 228 info.request = RADEON_INFO_DEVICE_ID; 229 break; 230 case RADEON_PARAM_NUM_GB_PIPES: 231 info.request = RADEON_INFO_NUM_GB_PIPES; 232 break; 233 case RADEON_PARAM_NUM_Z_PIPES: 234 info.request = RADEON_INFO_NUM_Z_PIPES; 235 break; 236 default: 237 return -EINVAL; 238 } 239 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 240 } else { 241 gp.param = param; 242 gp.value = value; 243 244 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 245 } 246 return ret; 247} 248 249static const __DRIconfig ** 250radeonFillInModes( __DRIscreen *psp, 251 unsigned pixel_bits, unsigned depth_bits, 252 unsigned stencil_bits, GLboolean have_back_buffer ) 253{ 254 __DRIconfig **configs; 255 __GLcontextModes *m; 256 unsigned depth_buffer_factor; 257 unsigned back_buffer_factor; 258 int i; 259 260 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 261 * enough to add support. Basically, if a context is created with an 262 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 263 * will never be used. 264 */ 265 static const GLenum back_buffer_modes[] = { 266 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 267 }; 268 269 uint8_t depth_bits_array[2]; 270 uint8_t stencil_bits_array[2]; 271 uint8_t msaa_samples_array[1]; 272 273 depth_bits_array[0] = depth_bits; 274 depth_bits_array[1] = depth_bits; 275 276 /* Just like with the accumulation buffer, always provide some modes 277 * with a stencil buffer. It will be a sw fallback, but some apps won't 278 * care about that. 279 */ 280 stencil_bits_array[0] = stencil_bits; 281 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 282 283 msaa_samples_array[0] = 0; 284 285 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1; 286 back_buffer_factor = (have_back_buffer) ? 2 : 1; 287 288 if (pixel_bits == 16) { 289 __DRIconfig **configs_a8r8g8b8; 290 __DRIconfig **configs_r5g6b5; 291 292 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 293 depth_bits_array, stencil_bits_array, 294 depth_buffer_factor, back_buffer_modes, 295 back_buffer_factor, msaa_samples_array, 296 1, GL_TRUE); 297 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 298 depth_bits_array, stencil_bits_array, 299 1, back_buffer_modes, 1, 300 msaa_samples_array, 1, GL_TRUE); 301 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 302 } else 303 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 304 depth_bits_array, stencil_bits_array, 305 depth_buffer_factor, 306 back_buffer_modes, back_buffer_factor, 307 msaa_samples_array, 1, GL_TRUE); 308 309 if (configs == NULL) { 310 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 311 __func__, __LINE__ ); 312 return NULL; 313 } 314 315 /* Mark the visual as slow if there are "fake" stencil bits. 316 */ 317 for (i = 0; configs[i]; i++) { 318 m = &configs[i]->modes; 319 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 320 m->visualRating = GLX_SLOW_CONFIG; 321 } 322 } 323 324 return (const __DRIconfig **) configs; 325} 326 327#if defined(RADEON_R100) 328static const __DRItexOffsetExtension radeonTexOffsetExtension = { 329 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 330 radeonSetTexOffset, 331}; 332 333static const __DRItexBufferExtension radeonTexBufferExtension = { 334 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 335 radeonSetTexBuffer, 336 radeonSetTexBuffer2, 337}; 338#endif 339 340#if defined(RADEON_R200) 341static const __DRIallocateExtension r200AllocateExtension = { 342 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 343 r200AllocateMemoryMESA, 344 r200FreeMemoryMESA, 345 r200GetMemoryOffsetMESA 346}; 347 348static const __DRItexOffsetExtension r200texOffsetExtension = { 349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 350 r200SetTexOffset, 351}; 352 353static const __DRItexBufferExtension r200TexBufferExtension = { 354 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 355 r200SetTexBuffer, 356 r200SetTexBuffer2, 357}; 358#endif 359 360#if defined(RADEON_R300) 361static const __DRItexOffsetExtension r300texOffsetExtension = { 362 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 363 r300SetTexOffset, 364}; 365 366static const __DRItexBufferExtension r300TexBufferExtension = { 367 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 368 r300SetTexBuffer, 369 r300SetTexBuffer2, 370}; 371#endif 372 373#if defined(RADEON_R600) 374static const __DRItexOffsetExtension r600texOffsetExtension = { 375 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 376 r600SetTexOffset, /* +r6/r7 */ 377}; 378 379static const __DRItexBufferExtension r600TexBufferExtension = { 380 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 381 r600SetTexBuffer, /* +r6/r7 */ 382 r600SetTexBuffer2, /* +r6/r7 */ 383}; 384#endif 385 386static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 387{ 388 screen->device_id = device_id; 389 screen->chip_flags = 0; 390 switch ( device_id ) { 391 case PCI_CHIP_RN50_515E: 392 case PCI_CHIP_RN50_5969: 393 return -1; 394 395 case PCI_CHIP_RADEON_LY: 396 case PCI_CHIP_RADEON_LZ: 397 case PCI_CHIP_RADEON_QY: 398 case PCI_CHIP_RADEON_QZ: 399 screen->chip_family = CHIP_FAMILY_RV100; 400 break; 401 402 case PCI_CHIP_RS100_4136: 403 case PCI_CHIP_RS100_4336: 404 screen->chip_family = CHIP_FAMILY_RS100; 405 break; 406 407 case PCI_CHIP_RS200_4137: 408 case PCI_CHIP_RS200_4337: 409 case PCI_CHIP_RS250_4237: 410 case PCI_CHIP_RS250_4437: 411 screen->chip_family = CHIP_FAMILY_RS200; 412 break; 413 414 case PCI_CHIP_RADEON_QD: 415 case PCI_CHIP_RADEON_QE: 416 case PCI_CHIP_RADEON_QF: 417 case PCI_CHIP_RADEON_QG: 418 /* all original radeons (7200) presumably have a stencil op bug */ 419 screen->chip_family = CHIP_FAMILY_R100; 420 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 421 break; 422 423 case PCI_CHIP_RV200_QW: 424 case PCI_CHIP_RV200_QX: 425 case PCI_CHIP_RADEON_LW: 426 case PCI_CHIP_RADEON_LX: 427 screen->chip_family = CHIP_FAMILY_RV200; 428 screen->chip_flags = RADEON_CHIPSET_TCL; 429 break; 430 431 case PCI_CHIP_R200_BB: 432 case PCI_CHIP_R200_BC: 433 case PCI_CHIP_R200_QH: 434 case PCI_CHIP_R200_QL: 435 case PCI_CHIP_R200_QM: 436 screen->chip_family = CHIP_FAMILY_R200; 437 screen->chip_flags = RADEON_CHIPSET_TCL; 438 break; 439 440 case PCI_CHIP_RV250_If: 441 case PCI_CHIP_RV250_Ig: 442 case PCI_CHIP_RV250_Ld: 443 case PCI_CHIP_RV250_Lf: 444 case PCI_CHIP_RV250_Lg: 445 screen->chip_family = CHIP_FAMILY_RV250; 446 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 447 break; 448 449 case PCI_CHIP_RV280_5960: 450 case PCI_CHIP_RV280_5961: 451 case PCI_CHIP_RV280_5962: 452 case PCI_CHIP_RV280_5964: 453 case PCI_CHIP_RV280_5965: 454 case PCI_CHIP_RV280_5C61: 455 case PCI_CHIP_RV280_5C63: 456 screen->chip_family = CHIP_FAMILY_RV280; 457 screen->chip_flags = RADEON_CHIPSET_TCL; 458 break; 459 460 case PCI_CHIP_RS300_5834: 461 case PCI_CHIP_RS300_5835: 462 case PCI_CHIP_RS350_7834: 463 case PCI_CHIP_RS350_7835: 464 screen->chip_family = CHIP_FAMILY_RS300; 465 break; 466 467 case PCI_CHIP_R300_AD: 468 case PCI_CHIP_R300_AE: 469 case PCI_CHIP_R300_AF: 470 case PCI_CHIP_R300_AG: 471 case PCI_CHIP_R300_ND: 472 case PCI_CHIP_R300_NE: 473 case PCI_CHIP_R300_NF: 474 case PCI_CHIP_R300_NG: 475 screen->chip_family = CHIP_FAMILY_R300; 476 screen->chip_flags = RADEON_CHIPSET_TCL; 477 break; 478 479 case PCI_CHIP_RV350_AP: 480 case PCI_CHIP_RV350_AQ: 481 case PCI_CHIP_RV350_AR: 482 case PCI_CHIP_RV350_AS: 483 case PCI_CHIP_RV350_AT: 484 case PCI_CHIP_RV350_AV: 485 case PCI_CHIP_RV350_AU: 486 case PCI_CHIP_RV350_NP: 487 case PCI_CHIP_RV350_NQ: 488 case PCI_CHIP_RV350_NR: 489 case PCI_CHIP_RV350_NS: 490 case PCI_CHIP_RV350_NT: 491 case PCI_CHIP_RV350_NV: 492 screen->chip_family = CHIP_FAMILY_RV350; 493 screen->chip_flags = RADEON_CHIPSET_TCL; 494 break; 495 496 case PCI_CHIP_R350_AH: 497 case PCI_CHIP_R350_AI: 498 case PCI_CHIP_R350_AJ: 499 case PCI_CHIP_R350_AK: 500 case PCI_CHIP_R350_NH: 501 case PCI_CHIP_R350_NI: 502 case PCI_CHIP_R360_NJ: 503 case PCI_CHIP_R350_NK: 504 screen->chip_family = CHIP_FAMILY_R350; 505 screen->chip_flags = RADEON_CHIPSET_TCL; 506 break; 507 508 case PCI_CHIP_RV370_5460: 509 case PCI_CHIP_RV370_5462: 510 case PCI_CHIP_RV370_5464: 511 case PCI_CHIP_RV370_5B60: 512 case PCI_CHIP_RV370_5B62: 513 case PCI_CHIP_RV370_5B63: 514 case PCI_CHIP_RV370_5B64: 515 case PCI_CHIP_RV370_5B65: 516 case PCI_CHIP_RV380_3150: 517 case PCI_CHIP_RV380_3152: 518 case PCI_CHIP_RV380_3154: 519 case PCI_CHIP_RV380_3155: 520 case PCI_CHIP_RV380_3E50: 521 case PCI_CHIP_RV380_3E54: 522 screen->chip_family = CHIP_FAMILY_RV380; 523 screen->chip_flags = RADEON_CHIPSET_TCL; 524 break; 525 526 case PCI_CHIP_R420_JN: 527 case PCI_CHIP_R420_JH: 528 case PCI_CHIP_R420_JI: 529 case PCI_CHIP_R420_JJ: 530 case PCI_CHIP_R420_JK: 531 case PCI_CHIP_R420_JL: 532 case PCI_CHIP_R420_JM: 533 case PCI_CHIP_R420_JO: 534 case PCI_CHIP_R420_JP: 535 case PCI_CHIP_R420_JT: 536 case PCI_CHIP_R481_4B49: 537 case PCI_CHIP_R481_4B4A: 538 case PCI_CHIP_R481_4B4B: 539 case PCI_CHIP_R481_4B4C: 540 case PCI_CHIP_R423_UH: 541 case PCI_CHIP_R423_UI: 542 case PCI_CHIP_R423_UJ: 543 case PCI_CHIP_R423_UK: 544 case PCI_CHIP_R430_554C: 545 case PCI_CHIP_R430_554D: 546 case PCI_CHIP_R430_554E: 547 case PCI_CHIP_R430_554F: 548 case PCI_CHIP_R423_5550: 549 case PCI_CHIP_R423_UQ: 550 case PCI_CHIP_R423_UR: 551 case PCI_CHIP_R423_UT: 552 case PCI_CHIP_R430_5D48: 553 case PCI_CHIP_R430_5D49: 554 case PCI_CHIP_R430_5D4A: 555 case PCI_CHIP_R480_5D4C: 556 case PCI_CHIP_R480_5D4D: 557 case PCI_CHIP_R480_5D4E: 558 case PCI_CHIP_R480_5D4F: 559 case PCI_CHIP_R480_5D50: 560 case PCI_CHIP_R480_5D52: 561 case PCI_CHIP_R423_5D57: 562 screen->chip_family = CHIP_FAMILY_R420; 563 screen->chip_flags = RADEON_CHIPSET_TCL; 564 break; 565 566 case PCI_CHIP_RV410_5E4C: 567 case PCI_CHIP_RV410_5E4F: 568 case PCI_CHIP_RV410_564A: 569 case PCI_CHIP_RV410_564B: 570 case PCI_CHIP_RV410_564F: 571 case PCI_CHIP_RV410_5652: 572 case PCI_CHIP_RV410_5653: 573 case PCI_CHIP_RV410_5657: 574 case PCI_CHIP_RV410_5E48: 575 case PCI_CHIP_RV410_5E4A: 576 case PCI_CHIP_RV410_5E4B: 577 case PCI_CHIP_RV410_5E4D: 578 screen->chip_family = CHIP_FAMILY_RV410; 579 screen->chip_flags = RADEON_CHIPSET_TCL; 580 break; 581 582 case PCI_CHIP_RS480_5954: 583 case PCI_CHIP_RS480_5955: 584 case PCI_CHIP_RS482_5974: 585 case PCI_CHIP_RS482_5975: 586 case PCI_CHIP_RS400_5A41: 587 case PCI_CHIP_RS400_5A42: 588 case PCI_CHIP_RC410_5A61: 589 case PCI_CHIP_RC410_5A62: 590 screen->chip_family = CHIP_FAMILY_RS400; 591 break; 592 593 case PCI_CHIP_RS600_793F: 594 case PCI_CHIP_RS600_7941: 595 case PCI_CHIP_RS600_7942: 596 screen->chip_family = CHIP_FAMILY_RS600; 597 break; 598 599 case PCI_CHIP_RS690_791E: 600 case PCI_CHIP_RS690_791F: 601 screen->chip_family = CHIP_FAMILY_RS690; 602 break; 603 case PCI_CHIP_RS740_796C: 604 case PCI_CHIP_RS740_796D: 605 case PCI_CHIP_RS740_796E: 606 case PCI_CHIP_RS740_796F: 607 screen->chip_family = CHIP_FAMILY_RS740; 608 break; 609 610 case PCI_CHIP_R520_7100: 611 case PCI_CHIP_R520_7101: 612 case PCI_CHIP_R520_7102: 613 case PCI_CHIP_R520_7103: 614 case PCI_CHIP_R520_7104: 615 case PCI_CHIP_R520_7105: 616 case PCI_CHIP_R520_7106: 617 case PCI_CHIP_R520_7108: 618 case PCI_CHIP_R520_7109: 619 case PCI_CHIP_R520_710A: 620 case PCI_CHIP_R520_710B: 621 case PCI_CHIP_R520_710C: 622 case PCI_CHIP_R520_710E: 623 case PCI_CHIP_R520_710F: 624 screen->chip_family = CHIP_FAMILY_R520; 625 screen->chip_flags = RADEON_CHIPSET_TCL; 626 break; 627 628 case PCI_CHIP_RV515_7140: 629 case PCI_CHIP_RV515_7141: 630 case PCI_CHIP_RV515_7142: 631 case PCI_CHIP_RV515_7143: 632 case PCI_CHIP_RV515_7144: 633 case PCI_CHIP_RV515_7145: 634 case PCI_CHIP_RV515_7146: 635 case PCI_CHIP_RV515_7147: 636 case PCI_CHIP_RV515_7149: 637 case PCI_CHIP_RV515_714A: 638 case PCI_CHIP_RV515_714B: 639 case PCI_CHIP_RV515_714C: 640 case PCI_CHIP_RV515_714D: 641 case PCI_CHIP_RV515_714E: 642 case PCI_CHIP_RV515_714F: 643 case PCI_CHIP_RV515_7151: 644 case PCI_CHIP_RV515_7152: 645 case PCI_CHIP_RV515_7153: 646 case PCI_CHIP_RV515_715E: 647 case PCI_CHIP_RV515_715F: 648 case PCI_CHIP_RV515_7180: 649 case PCI_CHIP_RV515_7181: 650 case PCI_CHIP_RV515_7183: 651 case PCI_CHIP_RV515_7186: 652 case PCI_CHIP_RV515_7187: 653 case PCI_CHIP_RV515_7188: 654 case PCI_CHIP_RV515_718A: 655 case PCI_CHIP_RV515_718B: 656 case PCI_CHIP_RV515_718C: 657 case PCI_CHIP_RV515_718D: 658 case PCI_CHIP_RV515_718F: 659 case PCI_CHIP_RV515_7193: 660 case PCI_CHIP_RV515_7196: 661 case PCI_CHIP_RV515_719B: 662 case PCI_CHIP_RV515_719F: 663 case PCI_CHIP_RV515_7200: 664 case PCI_CHIP_RV515_7210: 665 case PCI_CHIP_RV515_7211: 666 screen->chip_family = CHIP_FAMILY_RV515; 667 screen->chip_flags = RADEON_CHIPSET_TCL; 668 break; 669 670 case PCI_CHIP_RV530_71C0: 671 case PCI_CHIP_RV530_71C1: 672 case PCI_CHIP_RV530_71C2: 673 case PCI_CHIP_RV530_71C3: 674 case PCI_CHIP_RV530_71C4: 675 case PCI_CHIP_RV530_71C5: 676 case PCI_CHIP_RV530_71C6: 677 case PCI_CHIP_RV530_71C7: 678 case PCI_CHIP_RV530_71CD: 679 case PCI_CHIP_RV530_71CE: 680 case PCI_CHIP_RV530_71D2: 681 case PCI_CHIP_RV530_71D4: 682 case PCI_CHIP_RV530_71D5: 683 case PCI_CHIP_RV530_71D6: 684 case PCI_CHIP_RV530_71DA: 685 case PCI_CHIP_RV530_71DE: 686 screen->chip_family = CHIP_FAMILY_RV530; 687 screen->chip_flags = RADEON_CHIPSET_TCL; 688 break; 689 690 case PCI_CHIP_R580_7240: 691 case PCI_CHIP_R580_7243: 692 case PCI_CHIP_R580_7244: 693 case PCI_CHIP_R580_7245: 694 case PCI_CHIP_R580_7246: 695 case PCI_CHIP_R580_7247: 696 case PCI_CHIP_R580_7248: 697 case PCI_CHIP_R580_7249: 698 case PCI_CHIP_R580_724A: 699 case PCI_CHIP_R580_724B: 700 case PCI_CHIP_R580_724C: 701 case PCI_CHIP_R580_724D: 702 case PCI_CHIP_R580_724E: 703 case PCI_CHIP_R580_724F: 704 case PCI_CHIP_R580_7284: 705 screen->chip_family = CHIP_FAMILY_R580; 706 screen->chip_flags = RADEON_CHIPSET_TCL; 707 break; 708 709 case PCI_CHIP_RV570_7280: 710 case PCI_CHIP_RV560_7281: 711 case PCI_CHIP_RV560_7283: 712 case PCI_CHIP_RV560_7287: 713 case PCI_CHIP_RV570_7288: 714 case PCI_CHIP_RV570_7289: 715 case PCI_CHIP_RV570_728B: 716 case PCI_CHIP_RV570_728C: 717 case PCI_CHIP_RV560_7290: 718 case PCI_CHIP_RV560_7291: 719 case PCI_CHIP_RV560_7293: 720 case PCI_CHIP_RV560_7297: 721 screen->chip_family = CHIP_FAMILY_RV560; 722 screen->chip_flags = RADEON_CHIPSET_TCL; 723 break; 724 725 case PCI_CHIP_R600_9400: 726 case PCI_CHIP_R600_9401: 727 case PCI_CHIP_R600_9402: 728 case PCI_CHIP_R600_9403: 729 case PCI_CHIP_R600_9405: 730 case PCI_CHIP_R600_940A: 731 case PCI_CHIP_R600_940B: 732 case PCI_CHIP_R600_940F: 733 screen->chip_family = CHIP_FAMILY_R600; 734 screen->chip_flags = RADEON_CHIPSET_TCL; 735 break; 736 737 case PCI_CHIP_RV610_94C0: 738 case PCI_CHIP_RV610_94C1: 739 case PCI_CHIP_RV610_94C3: 740 case PCI_CHIP_RV610_94C4: 741 case PCI_CHIP_RV610_94C5: 742 case PCI_CHIP_RV610_94C6: 743 case PCI_CHIP_RV610_94C7: 744 case PCI_CHIP_RV610_94C8: 745 case PCI_CHIP_RV610_94C9: 746 case PCI_CHIP_RV610_94CB: 747 case PCI_CHIP_RV610_94CC: 748 case PCI_CHIP_RV610_94CD: 749 screen->chip_family = CHIP_FAMILY_RV610; 750 screen->chip_flags = RADEON_CHIPSET_TCL; 751 break; 752 753 case PCI_CHIP_RV630_9580: 754 case PCI_CHIP_RV630_9581: 755 case PCI_CHIP_RV630_9583: 756 case PCI_CHIP_RV630_9586: 757 case PCI_CHIP_RV630_9587: 758 case PCI_CHIP_RV630_9588: 759 case PCI_CHIP_RV630_9589: 760 case PCI_CHIP_RV630_958A: 761 case PCI_CHIP_RV630_958B: 762 case PCI_CHIP_RV630_958C: 763 case PCI_CHIP_RV630_958D: 764 case PCI_CHIP_RV630_958E: 765 case PCI_CHIP_RV630_958F: 766 screen->chip_family = CHIP_FAMILY_RV630; 767 screen->chip_flags = RADEON_CHIPSET_TCL; 768 break; 769 770 case PCI_CHIP_RV670_9500: 771 case PCI_CHIP_RV670_9501: 772 case PCI_CHIP_RV670_9504: 773 case PCI_CHIP_RV670_9505: 774 case PCI_CHIP_RV670_9506: 775 case PCI_CHIP_RV670_9507: 776 case PCI_CHIP_RV670_9508: 777 case PCI_CHIP_RV670_9509: 778 case PCI_CHIP_RV670_950F: 779 case PCI_CHIP_RV670_9511: 780 case PCI_CHIP_RV670_9515: 781 case PCI_CHIP_RV670_9517: 782 case PCI_CHIP_RV670_9519: 783 screen->chip_family = CHIP_FAMILY_RV670; 784 screen->chip_flags = RADEON_CHIPSET_TCL; 785 break; 786 787 case PCI_CHIP_RV620_95C0: 788 case PCI_CHIP_RV620_95C2: 789 case PCI_CHIP_RV620_95C4: 790 case PCI_CHIP_RV620_95C5: 791 case PCI_CHIP_RV620_95C6: 792 case PCI_CHIP_RV620_95C7: 793 case PCI_CHIP_RV620_95C9: 794 case PCI_CHIP_RV620_95CC: 795 case PCI_CHIP_RV620_95CD: 796 case PCI_CHIP_RV620_95CE: 797 case PCI_CHIP_RV620_95CF: 798 screen->chip_family = CHIP_FAMILY_RV620; 799 screen->chip_flags = RADEON_CHIPSET_TCL; 800 break; 801 802 case PCI_CHIP_RV635_9590: 803 case PCI_CHIP_RV635_9591: 804 case PCI_CHIP_RV635_9593: 805 case PCI_CHIP_RV635_9595: 806 case PCI_CHIP_RV635_9596: 807 case PCI_CHIP_RV635_9597: 808 case PCI_CHIP_RV635_9598: 809 case PCI_CHIP_RV635_9599: 810 case PCI_CHIP_RV635_959B: 811 screen->chip_family = CHIP_FAMILY_RV635; 812 screen->chip_flags = RADEON_CHIPSET_TCL; 813 break; 814 815 case PCI_CHIP_RS780_9610: 816 case PCI_CHIP_RS780_9611: 817 case PCI_CHIP_RS780_9612: 818 case PCI_CHIP_RS780_9613: 819 case PCI_CHIP_RS780_9614: 820 case PCI_CHIP_RS780_9615: 821 case PCI_CHIP_RS780_9616: 822 screen->chip_family = CHIP_FAMILY_RS780; 823 screen->chip_flags = RADEON_CHIPSET_TCL; 824 break; 825 case PCI_CHIP_RS880_9710: 826 case PCI_CHIP_RS880_9711: 827 case PCI_CHIP_RS880_9712: 828 case PCI_CHIP_RS880_9713: 829 case PCI_CHIP_RS880_9714: 830 case PCI_CHIP_RS880_9715: 831 screen->chip_family = CHIP_FAMILY_RS880; 832 screen->chip_flags = RADEON_CHIPSET_TCL; 833 break; 834 835 case PCI_CHIP_RV770_9440: 836 case PCI_CHIP_RV770_9441: 837 case PCI_CHIP_RV770_9442: 838 case PCI_CHIP_RV770_9443: 839 case PCI_CHIP_RV770_9444: 840 case PCI_CHIP_RV770_9446: 841 case PCI_CHIP_RV770_944A: 842 case PCI_CHIP_RV770_944B: 843 case PCI_CHIP_RV770_944C: 844 case PCI_CHIP_RV770_944E: 845 case PCI_CHIP_RV770_9450: 846 case PCI_CHIP_RV770_9452: 847 case PCI_CHIP_RV770_9456: 848 case PCI_CHIP_RV770_945A: 849 case PCI_CHIP_RV770_945B: 850 case PCI_CHIP_RV770_945E: 851 case PCI_CHIP_RV790_9460: 852 case PCI_CHIP_RV790_9462: 853 case PCI_CHIP_RV770_946A: 854 case PCI_CHIP_RV770_946B: 855 case PCI_CHIP_RV770_947A: 856 case PCI_CHIP_RV770_947B: 857 screen->chip_family = CHIP_FAMILY_RV770; 858 screen->chip_flags = RADEON_CHIPSET_TCL; 859 break; 860 861 case PCI_CHIP_RV730_9480: 862 case PCI_CHIP_RV730_9487: 863 case PCI_CHIP_RV730_9488: 864 case PCI_CHIP_RV730_9489: 865 case PCI_CHIP_RV730_948A: 866 case PCI_CHIP_RV730_948F: 867 case PCI_CHIP_RV730_9490: 868 case PCI_CHIP_RV730_9491: 869 case PCI_CHIP_RV730_9495: 870 case PCI_CHIP_RV730_9498: 871 case PCI_CHIP_RV730_949C: 872 case PCI_CHIP_RV730_949E: 873 case PCI_CHIP_RV730_949F: 874 screen->chip_family = CHIP_FAMILY_RV730; 875 screen->chip_flags = RADEON_CHIPSET_TCL; 876 break; 877 878 case PCI_CHIP_RV710_9540: 879 case PCI_CHIP_RV710_9541: 880 case PCI_CHIP_RV710_9542: 881 case PCI_CHIP_RV710_954E: 882 case PCI_CHIP_RV710_954F: 883 case PCI_CHIP_RV710_9552: 884 case PCI_CHIP_RV710_9553: 885 case PCI_CHIP_RV710_9555: 886 case PCI_CHIP_RV710_9557: 887 case PCI_CHIP_RV710_955F: 888 screen->chip_family = CHIP_FAMILY_RV710; 889 screen->chip_flags = RADEON_CHIPSET_TCL; 890 break; 891 892 case PCI_CHIP_RV740_94A0: 893 case PCI_CHIP_RV740_94A1: 894 case PCI_CHIP_RV740_94A3: 895 case PCI_CHIP_RV740_94B1: 896 case PCI_CHIP_RV740_94B3: 897 case PCI_CHIP_RV740_94B4: 898 case PCI_CHIP_RV740_94B5: 899 case PCI_CHIP_RV740_94B9: 900 screen->chip_family = CHIP_FAMILY_RV740; 901 screen->chip_flags = RADEON_CHIPSET_TCL; 902 break; 903 904 default: 905 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 906 device_id); 907 return -1; 908 } 909 910 return 0; 911} 912 913 914/* Create the device specific screen private data struct. 915 */ 916static radeonScreenPtr 917radeonCreateScreen( __DRIscreen *sPriv ) 918{ 919 radeonScreenPtr screen; 920 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 921 unsigned char *RADEONMMIO = NULL; 922 int i; 923 int ret; 924 uint32_t temp = 0; 925 926 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 927 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 928 return GL_FALSE; 929 } 930 931 /* Allocate the private area */ 932 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 933 if ( !screen ) { 934 __driUtilMessage("%s: Could not allocate memory for screen structure", 935 __FUNCTION__); 936 return NULL; 937 } 938 939 radeon_init_debug(); 940 941 /* parse information in __driConfigOptions */ 942 driParseOptionInfo (&screen->optionCache, 943 __driConfigOptions, __driNConfigOptions); 944 945 /* This is first since which regions we map depends on whether or 946 * not we are using a PCI card. 947 */ 948 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 949 { 950 int ret; 951 952 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 953 &screen->gart_buffer_offset); 954 955 if (ret) { 956 FREE( screen ); 957 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 958 return NULL; 959 } 960 961 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 962 &screen->gart_base); 963 if (ret) { 964 FREE( screen ); 965 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 966 return NULL; 967 } 968 969 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 970 &screen->irq); 971 if (ret) { 972 FREE( screen ); 973 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 974 return NULL; 975 } 976 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 977 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 978 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 979 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 980 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 981 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 982 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 983 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30); 984 } 985 986 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 987 if (ret == -1) 988 return NULL; 989 990 screen->mmio.handle = dri_priv->registerHandle; 991 screen->mmio.size = dri_priv->registerSize; 992 if ( drmMap( sPriv->fd, 993 screen->mmio.handle, 994 screen->mmio.size, 995 &screen->mmio.map ) ) { 996 FREE( screen ); 997 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 998 return NULL; 999 } 1000 1001 RADEONMMIO = screen->mmio.map; 1002 1003 screen->status.handle = dri_priv->statusHandle; 1004 screen->status.size = dri_priv->statusSize; 1005 if ( drmMap( sPriv->fd, 1006 screen->status.handle, 1007 screen->status.size, 1008 &screen->status.map ) ) { 1009 drmUnmap( screen->mmio.map, screen->mmio.size ); 1010 FREE( screen ); 1011 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1012 return NULL; 1013 } 1014 if (screen->chip_family < CHIP_FAMILY_R600) 1015 screen->scratch = (__volatile__ uint32_t *) 1016 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1017 else 1018 screen->scratch = (__volatile__ uint32_t *) 1019 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET); 1020 1021 screen->buffers = drmMapBufs( sPriv->fd ); 1022 if ( !screen->buffers ) { 1023 drmUnmap( screen->status.map, screen->status.size ); 1024 drmUnmap( screen->mmio.map, screen->mmio.size ); 1025 FREE( screen ); 1026 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1027 return NULL; 1028 } 1029 1030 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1031 screen->gartTextures.handle = dri_priv->gartTexHandle; 1032 screen->gartTextures.size = dri_priv->gartTexMapSize; 1033 if ( drmMap( sPriv->fd, 1034 screen->gartTextures.handle, 1035 screen->gartTextures.size, 1036 (drmAddressPtr)&screen->gartTextures.map ) ) { 1037 drmUnmapBufs( screen->buffers ); 1038 drmUnmap( screen->status.map, screen->status.size ); 1039 drmUnmap( screen->mmio.map, screen->mmio.size ); 1040 FREE( screen ); 1041 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1042 return NULL; 1043 } 1044 1045 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1046 } 1047 1048 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1049 sPriv->ddx_version.minor < 2) { 1050 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1051 return NULL; 1052 } 1053 1054 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1055 fprintf(stderr, "R500 support requires a newer drm.\n"); 1056 return NULL; 1057 } 1058 1059 if (getenv("R300_NO_TCL")) 1060 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1061 1062 if (screen->chip_family <= CHIP_FAMILY_RS200) 1063 screen->chip_flags |= RADEON_CLASS_R100; 1064 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1065 screen->chip_flags |= RADEON_CLASS_R200; 1066 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1067 screen->chip_flags |= RADEON_CLASS_R300; 1068 else 1069 screen->chip_flags |= RADEON_CLASS_R600; 1070 1071 screen->cpp = dri_priv->bpp / 8; 1072 screen->AGPMode = dri_priv->AGPMode; 1073 1074 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1075 1076 /* +r6/r7 */ 1077 if(screen->chip_family >= CHIP_FAMILY_R600) 1078 { 1079 if (ret) 1080 { 1081 FREE( screen ); 1082 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1083 return NULL; 1084 } 1085 else 1086 { 1087 screen->fbLocation = (temp & 0xffff) << 24; 1088 } 1089 } 1090 else 1091 { 1092 if (ret) 1093 { 1094 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1095 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1096 else 1097 { 1098 FREE( screen ); 1099 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1100 return NULL; 1101 } 1102 } 1103 else 1104 { 1105 screen->fbLocation = (temp & 0xffff) << 16; 1106 } 1107 } 1108 1109 if (IS_R300_CLASS(screen)) { 1110 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1111 if (ret) { 1112 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1113 switch (screen->chip_family) { 1114 case CHIP_FAMILY_R300: 1115 case CHIP_FAMILY_R350: 1116 screen->num_gb_pipes = 2; 1117 break; 1118 case CHIP_FAMILY_R420: 1119 case CHIP_FAMILY_R520: 1120 case CHIP_FAMILY_R580: 1121 case CHIP_FAMILY_RV560: 1122 case CHIP_FAMILY_RV570: 1123 screen->num_gb_pipes = 4; 1124 break; 1125 case CHIP_FAMILY_RV350: 1126 case CHIP_FAMILY_RV515: 1127 case CHIP_FAMILY_RV530: 1128 case CHIP_FAMILY_RV410: 1129 default: 1130 screen->num_gb_pipes = 1; 1131 break; 1132 } 1133 } else { 1134 screen->num_gb_pipes = temp; 1135 } 1136 1137 /* pipe overrides */ 1138 switch (dri_priv->deviceID) { 1139 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1140 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1141 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1142 screen->num_gb_pipes = 1; 1143 break; 1144 default: 1145 break; 1146 } 1147 1148 if ( sPriv->drm_version.minor >= 31 ) { 1149 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1150 if (ret) 1151 screen->num_z_pipes = 2; 1152 else 1153 screen->num_z_pipes = temp; 1154 } else 1155 screen->num_z_pipes = 2; 1156 } 1157 1158 if ( sPriv->drm_version.minor >= 10 ) { 1159 drm_radeon_setparam_t sp; 1160 1161 sp.param = RADEON_SETPARAM_FB_LOCATION; 1162 sp.value = screen->fbLocation; 1163 1164 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1165 &sp, sizeof( sp ) ); 1166 } 1167 1168 screen->frontOffset = dri_priv->frontOffset; 1169 screen->frontPitch = dri_priv->frontPitch; 1170 screen->backOffset = dri_priv->backOffset; 1171 screen->backPitch = dri_priv->backPitch; 1172 screen->depthOffset = dri_priv->depthOffset; 1173 screen->depthPitch = dri_priv->depthPitch; 1174 1175 /* Check if ddx has set up a surface reg to cover depth buffer */ 1176 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1177 /* these chips don't use tiled z without hyperz. So always pretend 1178 we have set up a surface which will cause linear reads/writes */ 1179 (IS_R100_CLASS(screen) && 1180 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1181 1182 if ( dri_priv->textureSize == 0 ) { 1183 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1184 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1185 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1186 dri_priv->log2GARTTexGran; 1187 } else { 1188 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1189 + screen->fbLocation; 1190 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1191 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1192 dri_priv->log2TexGran; 1193 } 1194 1195 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1196 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1197 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1198 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1199 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1200 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1201 } else { 1202 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1203 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1204 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1205 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1206 dri_priv->log2GARTTexGran; 1207 } 1208 1209 i = 0; 1210 screen->extensions[i++] = &driCopySubBufferExtension.base; 1211 screen->extensions[i++] = &driFrameTrackingExtension.base; 1212 screen->extensions[i++] = &driReadDrawableExtension; 1213 1214 if ( screen->irq != 0 ) { 1215 screen->extensions[i++] = &driSwapControlExtension.base; 1216 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1217 } 1218 1219#if defined(RADEON_R100) 1220 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1221#endif 1222 1223#if defined(RADEON_R200) 1224 if (IS_R200_CLASS(screen)) 1225 screen->extensions[i++] = &r200AllocateExtension.base; 1226 1227 screen->extensions[i++] = &r200texOffsetExtension.base; 1228#endif 1229 1230#if defined(RADEON_R300) 1231 screen->extensions[i++] = &r300texOffsetExtension.base; 1232#endif 1233 1234#if defined(RADEON_R600) 1235 screen->extensions[i++] = &r600texOffsetExtension.base; 1236#endif 1237 1238 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1239 1240 screen->extensions[i++] = NULL; 1241 sPriv->extensions = screen->extensions; 1242 1243 screen->driScreen = sPriv; 1244 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1245 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1246 screen->sarea_priv_offset); 1247 1248 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1249 if (screen->bom == NULL) { 1250 free(screen); 1251 return NULL; 1252 } 1253 1254 return screen; 1255} 1256 1257static radeonScreenPtr 1258radeonCreateScreen2(__DRIscreen *sPriv) 1259{ 1260 radeonScreenPtr screen; 1261 int i; 1262 int ret; 1263 uint32_t device_id = 0; 1264 uint32_t temp = 0; 1265 1266 /* Allocate the private area */ 1267 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1268 if ( !screen ) { 1269 __driUtilMessage("%s: Could not allocate memory for screen structure", 1270 __FUNCTION__); 1271 fprintf(stderr, "leaving here\n"); 1272 return NULL; 1273 } 1274 1275 radeon_init_debug(); 1276 1277 /* parse information in __driConfigOptions */ 1278 driParseOptionInfo (&screen->optionCache, 1279 __driConfigOptions, __driNConfigOptions); 1280 1281 screen->kernel_mm = 1; 1282 screen->chip_flags = 0; 1283 1284 /* if we have kms we can support all of these */ 1285 screen->drmSupportsCubeMapsR200 = 1; 1286 screen->drmSupportsBlendColor = 1; 1287 screen->drmSupportsTriPerf = 1; 1288 screen->drmSupportsFragShader = 1; 1289 screen->drmSupportsPointSprites = 1; 1290 screen->drmSupportsCubeMapsR100 = 1; 1291 screen->drmSupportsVertexProgram = 1; 1292 screen->drmSupportsOcclusionQueries = 1; 1293 screen->irq = 1; 1294 1295 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1296 if (ret) { 1297 FREE( screen ); 1298 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1299 return NULL; 1300 } 1301 1302 ret = radeon_set_screen_flags(screen, device_id); 1303 if (ret == -1) 1304 return NULL; 1305 1306 if (getenv("R300_NO_TCL")) 1307 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1308 1309 if (screen->chip_family <= CHIP_FAMILY_RS200) 1310 screen->chip_flags |= RADEON_CLASS_R100; 1311 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1312 screen->chip_flags |= RADEON_CLASS_R200; 1313 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1314 screen->chip_flags |= RADEON_CLASS_R300; 1315 else 1316 screen->chip_flags |= RADEON_CLASS_R600; 1317 1318 if (IS_R300_CLASS(screen)) { 1319 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1320 if (ret) { 1321 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1322 switch (screen->chip_family) { 1323 case CHIP_FAMILY_R300: 1324 case CHIP_FAMILY_R350: 1325 screen->num_gb_pipes = 2; 1326 break; 1327 case CHIP_FAMILY_R420: 1328 case CHIP_FAMILY_R520: 1329 case CHIP_FAMILY_R580: 1330 case CHIP_FAMILY_RV560: 1331 case CHIP_FAMILY_RV570: 1332 screen->num_gb_pipes = 4; 1333 break; 1334 case CHIP_FAMILY_RV350: 1335 case CHIP_FAMILY_RV515: 1336 case CHIP_FAMILY_RV530: 1337 case CHIP_FAMILY_RV410: 1338 default: 1339 screen->num_gb_pipes = 1; 1340 break; 1341 } 1342 } else { 1343 screen->num_gb_pipes = temp; 1344 } 1345 1346 /* pipe overrides */ 1347 switch (device_id) { 1348 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1349 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1350 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1351 screen->num_gb_pipes = 1; 1352 break; 1353 default: 1354 break; 1355 } 1356 1357 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1358 if (ret) 1359 screen->num_z_pipes = 2; 1360 else 1361 screen->num_z_pipes = temp; 1362 1363 } 1364 1365 i = 0; 1366 screen->extensions[i++] = &driCopySubBufferExtension.base; 1367 screen->extensions[i++] = &driFrameTrackingExtension.base; 1368 screen->extensions[i++] = &driReadDrawableExtension; 1369 1370 if ( screen->irq != 0 ) { 1371 screen->extensions[i++] = &driSwapControlExtension.base; 1372 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1373 } 1374 1375#if defined(RADEON_R100) 1376 screen->extensions[i++] = &radeonTexBufferExtension.base; 1377#endif 1378 1379#if defined(RADEON_R200) 1380 if (IS_R200_CLASS(screen)) 1381 screen->extensions[i++] = &r200AllocateExtension.base; 1382 1383 screen->extensions[i++] = &r200TexBufferExtension.base; 1384#endif 1385 1386#if defined(RADEON_R300) 1387 screen->extensions[i++] = &r300TexBufferExtension.base; 1388#endif 1389 1390#if defined(RADEON_R600) 1391 screen->extensions[i++] = &r600TexBufferExtension.base; 1392#endif 1393 1394 screen->extensions[i++] = NULL; 1395 sPriv->extensions = screen->extensions; 1396 1397 screen->driScreen = sPriv; 1398 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1399 if (screen->bom == NULL) { 1400 free(screen); 1401 return NULL; 1402 } 1403 return screen; 1404} 1405 1406/* Destroy the device specific screen private data struct. 1407 */ 1408static void 1409radeonDestroyScreen( __DRIscreen *sPriv ) 1410{ 1411 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1412 1413 if (!screen) 1414 return; 1415 1416 if (screen->kernel_mm) { 1417#ifdef RADEON_BO_TRACK 1418 radeon_tracker_print(&screen->bom->tracker, stderr); 1419#endif 1420 radeon_bo_manager_gem_dtor(screen->bom); 1421 } else { 1422 radeon_bo_manager_legacy_dtor(screen->bom); 1423 1424 if ( screen->gartTextures.map ) { 1425 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1426 } 1427 drmUnmapBufs( screen->buffers ); 1428 drmUnmap( screen->status.map, screen->status.size ); 1429 drmUnmap( screen->mmio.map, screen->mmio.size ); 1430 } 1431 1432 /* free all option information */ 1433 driDestroyOptionInfo (&screen->optionCache); 1434 1435 FREE( screen ); 1436 sPriv->private = NULL; 1437} 1438 1439 1440/* Initialize the driver specific screen private data. 1441 */ 1442static GLboolean 1443radeonInitDriver( __DRIscreen *sPriv ) 1444{ 1445 if (sPriv->dri2.enabled) { 1446 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1447 } else { 1448 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1449 } 1450 if ( !sPriv->private ) { 1451 radeonDestroyScreen( sPriv ); 1452 return GL_FALSE; 1453 } 1454 1455 return GL_TRUE; 1456} 1457 1458 1459 1460/** 1461 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1462 * 1463 * \todo This function (and its interface) will need to be updated to support 1464 * pbuffers. 1465 */ 1466static GLboolean 1467radeonCreateBuffer( __DRIscreen *driScrnPriv, 1468 __DRIdrawable *driDrawPriv, 1469 const __GLcontextModes *mesaVis, 1470 GLboolean isPixmap ) 1471{ 1472 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1473 1474 const GLboolean swDepth = GL_FALSE; 1475 const GLboolean swAlpha = GL_FALSE; 1476 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1477 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1478 mesaVis->depthBits != 24; 1479 gl_format rgbFormat; 1480 struct radeon_framebuffer *rfb; 1481 1482 if (isPixmap) 1483 return GL_FALSE; /* not implemented */ 1484 1485 rfb = CALLOC_STRUCT(radeon_framebuffer); 1486 if (!rfb) 1487 return GL_FALSE; 1488 1489 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis); 1490 1491 if (mesaVis->redBits == 5) 1492 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV; 1493 else if (mesaVis->alphaBits == 0) 1494 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV; 1495 else 1496 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV; 1497 1498 /* front color renderbuffer */ 1499 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1500 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1501 rfb->color_rb[0]->has_surface = 1; 1502 1503 /* back color renderbuffer */ 1504 if (mesaVis->doubleBufferMode) { 1505 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1506 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1507 rfb->color_rb[1]->has_surface = 1; 1508 } 1509 1510 if (mesaVis->depthBits == 24) { 1511 if (mesaVis->stencilBits == 8) { 1512 struct radeon_renderbuffer *depthStencilRb = 1513 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); 1514 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1515 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1516 depthStencilRb->has_surface = screen->depthHasSurface; 1517 } else { 1518 /* depth renderbuffer */ 1519 struct radeon_renderbuffer *depth = 1520 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); 1521 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1522 depth->has_surface = screen->depthHasSurface; 1523 } 1524 } else if (mesaVis->depthBits == 16) { 1525 /* just 16-bit depth buffer, no hw stencil */ 1526 struct radeon_renderbuffer *depth = 1527 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); 1528 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1529 depth->has_surface = screen->depthHasSurface; 1530 } 1531 1532 _mesa_add_soft_renderbuffers(&rfb->base, 1533 GL_FALSE, /* color */ 1534 swDepth, 1535 swStencil, 1536 swAccum, 1537 swAlpha, 1538 GL_FALSE /* aux */); 1539 driDrawPriv->driverPrivate = (void *) rfb; 1540 1541 return (driDrawPriv->driverPrivate != NULL); 1542} 1543 1544 1545static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1546{ 1547 struct radeon_renderbuffer *rb; 1548 1549 rb = rfb->color_rb[0]; 1550 if (rb && rb->bo) { 1551 radeon_bo_unref(rb->bo); 1552 rb->bo = NULL; 1553 } 1554 rb = rfb->color_rb[1]; 1555 if (rb && rb->bo) { 1556 radeon_bo_unref(rb->bo); 1557 rb->bo = NULL; 1558 } 1559 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1560 if (rb && rb->bo) { 1561 radeon_bo_unref(rb->bo); 1562 rb->bo = NULL; 1563 } 1564} 1565 1566void 1567radeonDestroyBuffer(__DRIdrawable *driDrawPriv) 1568{ 1569 struct radeon_framebuffer *rfb; 1570 if (!driDrawPriv) 1571 return; 1572 1573 rfb = (void*)driDrawPriv->driverPrivate; 1574 if (!rfb) 1575 return; 1576 radeon_cleanup_renderbuffers(rfb); 1577 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1578} 1579 1580 1581/** 1582 * This is the driver specific part of the createNewScreen entry point. 1583 * 1584 * \todo maybe fold this into intelInitDriver 1585 * 1586 * \return the __GLcontextModes supported by this driver 1587 */ 1588static const __DRIconfig ** 1589radeonInitScreen(__DRIscreen *psp) 1590{ 1591#if defined(RADEON_R100) 1592 static const char *driver_name = "Radeon"; 1593 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1594 static const __DRIversion dri_expected = { 4, 0, 0 }; 1595 static const __DRIversion drm_expected = { 1, 6, 0 }; 1596#elif defined(RADEON_R200) 1597 static const char *driver_name = "R200"; 1598 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1599 static const __DRIversion dri_expected = { 4, 0, 0 }; 1600 static const __DRIversion drm_expected = { 1, 6, 0 }; 1601#elif defined(RADEON_R300) 1602 static const char *driver_name = "R300"; 1603 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1604 static const __DRIversion dri_expected = { 4, 0, 0 }; 1605 static const __DRIversion drm_expected = { 1, 24, 0 }; 1606#elif defined(RADEON_R600) 1607 static const char *driver_name = "R600"; 1608 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1609 static const __DRIversion dri_expected = { 4, 0, 0 }; 1610 static const __DRIversion drm_expected = { 1, 24, 0 }; 1611#endif 1612 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1613 1614 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1615 &psp->dri_version, & dri_expected, 1616 &psp->ddx_version, & ddx_expected, 1617 &psp->drm_version, & drm_expected ) ) { 1618 return NULL; 1619 } 1620 1621 if (!radeonInitDriver(psp)) 1622 return NULL; 1623 1624 /* for now fill in all modes */ 1625 return radeonFillInModes( psp, 1626 dri_priv->bpp, 1627 (dri_priv->bpp == 16) ? 16 : 24, 1628 (dri_priv->bpp == 16) ? 0 : 8, 1); 1629} 1630#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1631 1632/** 1633 * This is the driver specific part of the createNewScreen entry point. 1634 * Called when using DRI2. 1635 * 1636 * \return the __GLcontextModes supported by this driver 1637 */ 1638static const 1639__DRIconfig **radeonInitScreen2(__DRIscreen *psp) 1640{ 1641 GLenum fb_format[3]; 1642 GLenum fb_type[3]; 1643 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1644 * support pageflipping at all. 1645 */ 1646 static const GLenum back_buffer_modes[] = { 1647 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1648 }; 1649 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1650 int color; 1651 __DRIconfig **configs = NULL; 1652 1653 if (!radeonInitDriver(psp)) { 1654 return NULL; 1655 } 1656 depth_bits[0] = 0; 1657 stencil_bits[0] = 0; 1658 depth_bits[1] = 16; 1659 stencil_bits[1] = 0; 1660 depth_bits[2] = 24; 1661 stencil_bits[2] = 0; 1662 depth_bits[3] = 24; 1663 stencil_bits[3] = 8; 1664 1665 msaa_samples_array[0] = 0; 1666 1667 fb_format[0] = GL_RGB; 1668 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1669 1670 fb_format[1] = GL_BGR; 1671 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1672 1673 fb_format[2] = GL_BGRA; 1674 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1675 1676 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1677 __DRIconfig **new_configs; 1678 1679 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1680 depth_bits, 1681 stencil_bits, 1682 ARRAY_SIZE(depth_bits), 1683 back_buffer_modes, 1684 ARRAY_SIZE(back_buffer_modes), 1685 msaa_samples_array, 1686 ARRAY_SIZE(msaa_samples_array), 1687 GL_TRUE); 1688 if (configs == NULL) 1689 configs = new_configs; 1690 else 1691 configs = driConcatConfigs(configs, new_configs); 1692 } 1693 1694 if (configs == NULL) { 1695 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1696 __LINE__); 1697 return NULL; 1698 } 1699 1700 return (const __DRIconfig **)configs; 1701} 1702 1703/** 1704 * Get information about previous buffer swaps. 1705 */ 1706static int 1707getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ) 1708{ 1709 struct radeon_framebuffer *rfb; 1710 1711 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1712 || (dPriv->driContextPriv->driverPrivate == NULL) 1713 || (sInfo == NULL) ) { 1714 return -1; 1715 } 1716 1717 rfb = dPriv->driverPrivate; 1718 sInfo->swap_count = rfb->swap_count; 1719 sInfo->swap_ust = rfb->swap_ust; 1720 sInfo->swap_missed_count = rfb->swap_missed_count; 1721 1722 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1723 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1724 : 0.0; 1725 1726 return 0; 1727} 1728 1729const struct __DriverAPIRec driDriverAPI = { 1730 .InitScreen = radeonInitScreen, 1731 .DestroyScreen = radeonDestroyScreen, 1732#if defined(RADEON_R200) 1733 .CreateContext = r200CreateContext, 1734 .DestroyContext = r200DestroyContext, 1735#elif defined(RADEON_R600) 1736 .CreateContext = r600CreateContext, 1737 .DestroyContext = radeonDestroyContext, 1738#elif defined(RADEON_R300) 1739 .CreateContext = r300CreateContext, 1740 .DestroyContext = radeonDestroyContext, 1741#else 1742 .CreateContext = r100CreateContext, 1743 .DestroyContext = radeonDestroyContext, 1744#endif 1745 .CreateBuffer = radeonCreateBuffer, 1746 .DestroyBuffer = radeonDestroyBuffer, 1747 .SwapBuffers = radeonSwapBuffers, 1748 .MakeCurrent = radeonMakeCurrent, 1749 .UnbindContext = radeonUnbindContext, 1750 .GetSwapInfo = getSwapInfo, 1751 .GetDrawableMSC = driDrawableGetMSC32, 1752 .WaitForMSC = driWaitForMSC32, 1753 .WaitForSBC = NULL, 1754 .SwapBuffersMSC = NULL, 1755 .CopySubBuffer = radeonCopySubBuffer, 1756 /* DRI2 */ 1757 .InitScreen2 = radeonInitScreen2, 1758}; 1759 1760/* This is the table of extensions that the loader will dlsym() for. */ 1761PUBLIC const __DRIextension *__driDriverExtensions[] = { 1762 &driCoreExtension.base, 1763 &driLegacyExtension.base, 1764 &driDRI2Extension.base, 1765 NULL 1766}; 1767