radeon_screen.c revision 5b15b5f4a8fffa07d8051e6cd4cd0a6c9288fc9f
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#if defined(RADEON_R100) 51#include "radeon_context.h" 52#include "radeon_tex.h" 53#elif defined(RADEON_R200) 54#include "r200_context.h" 55#include "r200_tex.h" 56#elif defined(RADEON_R300) 57#include "r300_context.h" 58#include "r300_tex.h" 59#elif defined(RADEON_R600) 60#include "r600_context.h" 61#include "r700_driconf.h" /* +r6/r7 */ 62#include "r600_tex.h" /* +r6/r7 */ 63#endif 64 65#include "utils.h" 66#include "vblank.h" 67 68#include "radeon_bocs_wrapper.h" 69 70#include "GL/internal/dri_interface.h" 71 72/* Radeon configuration 73 */ 74#include "xmlpool.h" 75 76#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 77DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 80DRI_CONF_OPT_END 81 82#if defined(RADEON_R100) /* R100 */ 83PUBLIC const char __driConfigOptions[] = 84DRI_CONF_BEGIN 85 DRI_CONF_SECTION_PERFORMANCE 86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 90 DRI_CONF_HYPERZ(false) 91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 92 DRI_CONF_SECTION_END 93 DRI_CONF_SECTION_QUALITY 94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 96 DRI_CONF_NO_NEG_LOD_BIAS(false) 97 DRI_CONF_FORCE_S3TC_ENABLE(false) 98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 101 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 102 DRI_CONF_SECTION_END 103 DRI_CONF_SECTION_DEBUG 104 DRI_CONF_NO_RAST(false) 105 DRI_CONF_SECTION_END 106DRI_CONF_END; 107static const GLuint __driNConfigOptions = 15; 108 109#elif defined(RADEON_R200) 110 111PUBLIC const char __driConfigOptions[] = 112DRI_CONF_BEGIN 113 DRI_CONF_SECTION_PERFORMANCE 114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 118 DRI_CONF_HYPERZ(false) 119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 120 DRI_CONF_SECTION_END 121 DRI_CONF_SECTION_QUALITY 122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 124 DRI_CONF_NO_NEG_LOD_BIAS(false) 125 DRI_CONF_FORCE_S3TC_ENABLE(false) 126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 129 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 131 DRI_CONF_SECTION_END 132 DRI_CONF_SECTION_DEBUG 133 DRI_CONF_NO_RAST(false) 134 DRI_CONF_SECTION_END 135 DRI_CONF_SECTION_SOFTWARE 136 DRI_CONF_NV_VERTEX_PROGRAM(false) 137 DRI_CONF_SECTION_END 138DRI_CONF_END; 139static const GLuint __driNConfigOptions = 17; 140 141#elif defined(RADEON_R300) || defined(RADEON_R600) 142 143#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 144#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 145 146/* TODO: integrate these into xmlpool.h! */ 147#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 148DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 149 DRI_CONF_DESC(en,"Number of texture image units") \ 150 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 151DRI_CONF_OPT_END 152 153#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 154DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 155 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 156 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 157DRI_CONF_OPT_END 158 159 160 161#define DRI_CONF_DISABLE_S3TC(def) \ 162DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 163 DRI_CONF_DESC(en,"Disable S3TC compression") \ 164DRI_CONF_OPT_END 165 166#define DRI_CONF_DISABLE_FALLBACK(def) \ 167DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 168 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 169DRI_CONF_OPT_END 170 171#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 172DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 173 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 174DRI_CONF_OPT_END 175 176#define DRI_CONF_FP_OPTIMIZATION(def) \ 177DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 178 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 179 DRI_CONF_ENUM(0,"Optimize for Speed") \ 180 DRI_CONF_ENUM(1,"Optimize for Quality") \ 181 DRI_CONF_DESC_END \ 182DRI_CONF_OPT_END 183 184PUBLIC const char __driConfigOptions[] = 185DRI_CONF_BEGIN 186 DRI_CONF_SECTION_PERFORMANCE 187 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 188 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 189 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 190 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 191 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 192 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 193 DRI_CONF_DISABLE_FALLBACK(true) 194 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 195 DRI_CONF_SECTION_END 196 DRI_CONF_SECTION_QUALITY 197 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 198 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 199 DRI_CONF_FORCE_S3TC_ENABLE(false) 200 DRI_CONF_DISABLE_S3TC(false) 201 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 202 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 203 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 204 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 205 DRI_CONF_SECTION_END 206 DRI_CONF_SECTION_DEBUG 207 DRI_CONF_NO_RAST(false) 208 DRI_CONF_SECTION_END 209DRI_CONF_END; 210static const GLuint __driNConfigOptions = 17; 211 212#endif 213 214static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ); 215 216#ifndef RADEON_INFO_TILE_CONFIG 217#define RADEON_INFO_TILE_CONFIG 0x6 218#endif 219 220static int 221radeonGetParam(__DRIscreen *sPriv, int param, void *value) 222{ 223 int ret; 224 drm_radeon_getparam_t gp = { 0 }; 225 struct drm_radeon_info info = { 0 }; 226 227 if (sPriv->drm_version.major >= 2) { 228 info.value = (uint64_t)(uintptr_t)value; 229 switch (param) { 230 case RADEON_PARAM_DEVICE_ID: 231 info.request = RADEON_INFO_DEVICE_ID; 232 break; 233 case RADEON_PARAM_NUM_GB_PIPES: 234 info.request = RADEON_INFO_NUM_GB_PIPES; 235 break; 236 case RADEON_PARAM_NUM_Z_PIPES: 237 info.request = RADEON_INFO_NUM_Z_PIPES; 238 break; 239 case RADEON_INFO_TILE_CONFIG: 240 info.request = RADEON_INFO_TILE_CONFIG; 241 break; 242 default: 243 return -EINVAL; 244 } 245 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 246 } else { 247 gp.param = param; 248 gp.value = value; 249 250 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 251 } 252 return ret; 253} 254 255static const __DRIconfig ** 256radeonFillInModes( __DRIscreen *psp, 257 unsigned pixel_bits, unsigned depth_bits, 258 unsigned stencil_bits, GLboolean have_back_buffer ) 259{ 260 __DRIconfig **configs; 261 struct gl_config *m; 262 unsigned depth_buffer_factor; 263 unsigned back_buffer_factor; 264 int i; 265 266 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 267 * enough to add support. Basically, if a context is created with an 268 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 269 * will never be used. 270 */ 271 static const GLenum back_buffer_modes[] = { 272 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 273 }; 274 275 uint8_t depth_bits_array[2]; 276 uint8_t stencil_bits_array[2]; 277 uint8_t msaa_samples_array[1]; 278 279 depth_bits_array[0] = depth_bits; 280 depth_bits_array[1] = depth_bits; 281 282 /* Just like with the accumulation buffer, always provide some modes 283 * with a stencil buffer. It will be a sw fallback, but some apps won't 284 * care about that. 285 */ 286 stencil_bits_array[0] = stencil_bits; 287 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 288 289 msaa_samples_array[0] = 0; 290 291 depth_buffer_factor = (stencil_bits == 0) ? 2 : 1; 292 back_buffer_factor = (have_back_buffer) ? 2 : 1; 293 294 if (pixel_bits == 16) { 295 __DRIconfig **configs_a8r8g8b8; 296 __DRIconfig **configs_r5g6b5; 297 298 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 299 depth_bits_array, stencil_bits_array, 300 depth_buffer_factor, back_buffer_modes, 301 back_buffer_factor, msaa_samples_array, 302 1, GL_TRUE); 303 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 304 depth_bits_array, stencil_bits_array, 305 1, back_buffer_modes, 1, 306 msaa_samples_array, 1, GL_TRUE); 307 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 308 } else 309 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 310 depth_bits_array, stencil_bits_array, 311 depth_buffer_factor, 312 back_buffer_modes, back_buffer_factor, 313 msaa_samples_array, 1, GL_TRUE); 314 315 if (configs == NULL) { 316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 317 __func__, __LINE__ ); 318 return NULL; 319 } 320 321 /* Mark the visual as slow if there are "fake" stencil bits. 322 */ 323 for (i = 0; configs[i]; i++) { 324 m = &configs[i]->modes; 325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 326 m->visualRating = GLX_SLOW_CONFIG; 327 } 328 } 329 330 return (const __DRIconfig **) configs; 331} 332 333#if defined(RADEON_R100) 334static const __DRItexOffsetExtension radeonTexOffsetExtension = { 335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 336 radeonSetTexOffset, 337}; 338 339static const __DRItexBufferExtension radeonTexBufferExtension = { 340 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 341 radeonSetTexBuffer, 342 radeonSetTexBuffer2, 343}; 344#endif 345 346#if defined(RADEON_R200) 347 348static const __DRItexOffsetExtension r200texOffsetExtension = { 349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 350 r200SetTexOffset, 351}; 352 353static const __DRItexBufferExtension r200TexBufferExtension = { 354 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 355 r200SetTexBuffer, 356 r200SetTexBuffer2, 357}; 358#endif 359 360#if defined(RADEON_R300) 361static const __DRItexOffsetExtension r300texOffsetExtension = { 362 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 363 r300SetTexOffset, 364}; 365 366static const __DRItexBufferExtension r300TexBufferExtension = { 367 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 368 r300SetTexBuffer, 369 r300SetTexBuffer2, 370}; 371#endif 372 373#if defined(RADEON_R600) 374static const __DRItexOffsetExtension r600texOffsetExtension = { 375 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 376 r600SetTexOffset, /* +r6/r7 */ 377}; 378 379static const __DRItexBufferExtension r600TexBufferExtension = { 380 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 381 r600SetTexBuffer, /* +r6/r7 */ 382 r600SetTexBuffer2, /* +r6/r7 */ 383}; 384#endif 385 386static void 387radeonDRI2Flush(__DRIdrawable *drawable) 388{ 389 radeonContextPtr rmesa; 390 391 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; 392 radeonFlush(rmesa->glCtx); 393} 394 395static const struct __DRI2flushExtensionRec radeonFlushExtension = { 396 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION }, 397 radeonDRI2Flush, 398 dri2InvalidateDrawable, 399}; 400 401static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 402{ 403 screen->device_id = device_id; 404 screen->chip_flags = 0; 405 switch ( device_id ) { 406 case PCI_CHIP_RN50_515E: 407 case PCI_CHIP_RN50_5969: 408 return -1; 409 410 case PCI_CHIP_RADEON_LY: 411 case PCI_CHIP_RADEON_LZ: 412 case PCI_CHIP_RADEON_QY: 413 case PCI_CHIP_RADEON_QZ: 414 screen->chip_family = CHIP_FAMILY_RV100; 415 break; 416 417 case PCI_CHIP_RS100_4136: 418 case PCI_CHIP_RS100_4336: 419 screen->chip_family = CHIP_FAMILY_RS100; 420 break; 421 422 case PCI_CHIP_RS200_4137: 423 case PCI_CHIP_RS200_4337: 424 case PCI_CHIP_RS250_4237: 425 case PCI_CHIP_RS250_4437: 426 screen->chip_family = CHIP_FAMILY_RS200; 427 break; 428 429 case PCI_CHIP_RADEON_QD: 430 case PCI_CHIP_RADEON_QE: 431 case PCI_CHIP_RADEON_QF: 432 case PCI_CHIP_RADEON_QG: 433 /* all original radeons (7200) presumably have a stencil op bug */ 434 screen->chip_family = CHIP_FAMILY_R100; 435 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 436 break; 437 438 case PCI_CHIP_RV200_QW: 439 case PCI_CHIP_RV200_QX: 440 case PCI_CHIP_RADEON_LW: 441 case PCI_CHIP_RADEON_LX: 442 screen->chip_family = CHIP_FAMILY_RV200; 443 screen->chip_flags = RADEON_CHIPSET_TCL; 444 break; 445 446 case PCI_CHIP_R200_BB: 447 case PCI_CHIP_R200_BC: 448 case PCI_CHIP_R200_QH: 449 case PCI_CHIP_R200_QL: 450 case PCI_CHIP_R200_QM: 451 screen->chip_family = CHIP_FAMILY_R200; 452 screen->chip_flags = RADEON_CHIPSET_TCL; 453 break; 454 455 case PCI_CHIP_RV250_If: 456 case PCI_CHIP_RV250_Ig: 457 case PCI_CHIP_RV250_Ld: 458 case PCI_CHIP_RV250_Lf: 459 case PCI_CHIP_RV250_Lg: 460 screen->chip_family = CHIP_FAMILY_RV250; 461 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 462 break; 463 464 case PCI_CHIP_RV280_5960: 465 case PCI_CHIP_RV280_5961: 466 case PCI_CHIP_RV280_5962: 467 case PCI_CHIP_RV280_5964: 468 case PCI_CHIP_RV280_5965: 469 case PCI_CHIP_RV280_5C61: 470 case PCI_CHIP_RV280_5C63: 471 screen->chip_family = CHIP_FAMILY_RV280; 472 screen->chip_flags = RADEON_CHIPSET_TCL; 473 break; 474 475 case PCI_CHIP_RS300_5834: 476 case PCI_CHIP_RS300_5835: 477 case PCI_CHIP_RS350_7834: 478 case PCI_CHIP_RS350_7835: 479 screen->chip_family = CHIP_FAMILY_RS300; 480 break; 481 482 case PCI_CHIP_R300_AD: 483 case PCI_CHIP_R300_AE: 484 case PCI_CHIP_R300_AF: 485 case PCI_CHIP_R300_AG: 486 case PCI_CHIP_R300_ND: 487 case PCI_CHIP_R300_NE: 488 case PCI_CHIP_R300_NF: 489 case PCI_CHIP_R300_NG: 490 screen->chip_family = CHIP_FAMILY_R300; 491 screen->chip_flags = RADEON_CHIPSET_TCL; 492 break; 493 494 case PCI_CHIP_RV350_AP: 495 case PCI_CHIP_RV350_AQ: 496 case PCI_CHIP_RV350_AR: 497 case PCI_CHIP_RV350_AS: 498 case PCI_CHIP_RV350_AT: 499 case PCI_CHIP_RV350_AV: 500 case PCI_CHIP_RV350_AU: 501 case PCI_CHIP_RV350_NP: 502 case PCI_CHIP_RV350_NQ: 503 case PCI_CHIP_RV350_NR: 504 case PCI_CHIP_RV350_NS: 505 case PCI_CHIP_RV350_NT: 506 case PCI_CHIP_RV350_NV: 507 screen->chip_family = CHIP_FAMILY_RV350; 508 screen->chip_flags = RADEON_CHIPSET_TCL; 509 break; 510 511 case PCI_CHIP_R350_AH: 512 case PCI_CHIP_R350_AI: 513 case PCI_CHIP_R350_AJ: 514 case PCI_CHIP_R350_AK: 515 case PCI_CHIP_R350_NH: 516 case PCI_CHIP_R350_NI: 517 case PCI_CHIP_R360_NJ: 518 case PCI_CHIP_R350_NK: 519 screen->chip_family = CHIP_FAMILY_R350; 520 screen->chip_flags = RADEON_CHIPSET_TCL; 521 break; 522 523 case PCI_CHIP_RV370_5460: 524 case PCI_CHIP_RV370_5462: 525 case PCI_CHIP_RV370_5464: 526 case PCI_CHIP_RV370_5B60: 527 case PCI_CHIP_RV370_5B62: 528 case PCI_CHIP_RV370_5B63: 529 case PCI_CHIP_RV370_5B64: 530 case PCI_CHIP_RV370_5B65: 531 case PCI_CHIP_RV380_3150: 532 case PCI_CHIP_RV380_3152: 533 case PCI_CHIP_RV380_3154: 534 case PCI_CHIP_RV380_3155: 535 case PCI_CHIP_RV380_3E50: 536 case PCI_CHIP_RV380_3E54: 537 screen->chip_family = CHIP_FAMILY_RV380; 538 screen->chip_flags = RADEON_CHIPSET_TCL; 539 break; 540 541 case PCI_CHIP_R420_JN: 542 case PCI_CHIP_R420_JH: 543 case PCI_CHIP_R420_JI: 544 case PCI_CHIP_R420_JJ: 545 case PCI_CHIP_R420_JK: 546 case PCI_CHIP_R420_JL: 547 case PCI_CHIP_R420_JM: 548 case PCI_CHIP_R420_JO: 549 case PCI_CHIP_R420_JP: 550 case PCI_CHIP_R420_JT: 551 case PCI_CHIP_R481_4B49: 552 case PCI_CHIP_R481_4B4A: 553 case PCI_CHIP_R481_4B4B: 554 case PCI_CHIP_R481_4B4C: 555 case PCI_CHIP_R423_UH: 556 case PCI_CHIP_R423_UI: 557 case PCI_CHIP_R423_UJ: 558 case PCI_CHIP_R423_UK: 559 case PCI_CHIP_R430_554C: 560 case PCI_CHIP_R430_554D: 561 case PCI_CHIP_R430_554E: 562 case PCI_CHIP_R430_554F: 563 case PCI_CHIP_R423_5550: 564 case PCI_CHIP_R423_UQ: 565 case PCI_CHIP_R423_UR: 566 case PCI_CHIP_R423_UT: 567 case PCI_CHIP_R430_5D48: 568 case PCI_CHIP_R430_5D49: 569 case PCI_CHIP_R430_5D4A: 570 case PCI_CHIP_R480_5D4C: 571 case PCI_CHIP_R480_5D4D: 572 case PCI_CHIP_R480_5D4E: 573 case PCI_CHIP_R480_5D4F: 574 case PCI_CHIP_R480_5D50: 575 case PCI_CHIP_R480_5D52: 576 case PCI_CHIP_R423_5D57: 577 screen->chip_family = CHIP_FAMILY_R420; 578 screen->chip_flags = RADEON_CHIPSET_TCL; 579 break; 580 581 case PCI_CHIP_RV410_5E4C: 582 case PCI_CHIP_RV410_5E4F: 583 case PCI_CHIP_RV410_564A: 584 case PCI_CHIP_RV410_564B: 585 case PCI_CHIP_RV410_564F: 586 case PCI_CHIP_RV410_5652: 587 case PCI_CHIP_RV410_5653: 588 case PCI_CHIP_RV410_5657: 589 case PCI_CHIP_RV410_5E48: 590 case PCI_CHIP_RV410_5E4A: 591 case PCI_CHIP_RV410_5E4B: 592 case PCI_CHIP_RV410_5E4D: 593 screen->chip_family = CHIP_FAMILY_RV410; 594 screen->chip_flags = RADEON_CHIPSET_TCL; 595 break; 596 597 case PCI_CHIP_RS480_5954: 598 case PCI_CHIP_RS480_5955: 599 case PCI_CHIP_RS482_5974: 600 case PCI_CHIP_RS482_5975: 601 case PCI_CHIP_RS400_5A41: 602 case PCI_CHIP_RS400_5A42: 603 case PCI_CHIP_RC410_5A61: 604 case PCI_CHIP_RC410_5A62: 605 screen->chip_family = CHIP_FAMILY_RS400; 606 break; 607 608 case PCI_CHIP_RS600_793F: 609 case PCI_CHIP_RS600_7941: 610 case PCI_CHIP_RS600_7942: 611 screen->chip_family = CHIP_FAMILY_RS600; 612 break; 613 614 case PCI_CHIP_RS690_791E: 615 case PCI_CHIP_RS690_791F: 616 screen->chip_family = CHIP_FAMILY_RS690; 617 break; 618 case PCI_CHIP_RS740_796C: 619 case PCI_CHIP_RS740_796D: 620 case PCI_CHIP_RS740_796E: 621 case PCI_CHIP_RS740_796F: 622 screen->chip_family = CHIP_FAMILY_RS740; 623 break; 624 625 case PCI_CHIP_R520_7100: 626 case PCI_CHIP_R520_7101: 627 case PCI_CHIP_R520_7102: 628 case PCI_CHIP_R520_7103: 629 case PCI_CHIP_R520_7104: 630 case PCI_CHIP_R520_7105: 631 case PCI_CHIP_R520_7106: 632 case PCI_CHIP_R520_7108: 633 case PCI_CHIP_R520_7109: 634 case PCI_CHIP_R520_710A: 635 case PCI_CHIP_R520_710B: 636 case PCI_CHIP_R520_710C: 637 case PCI_CHIP_R520_710E: 638 case PCI_CHIP_R520_710F: 639 screen->chip_family = CHIP_FAMILY_R520; 640 screen->chip_flags = RADEON_CHIPSET_TCL; 641 break; 642 643 case PCI_CHIP_RV515_7140: 644 case PCI_CHIP_RV515_7141: 645 case PCI_CHIP_RV515_7142: 646 case PCI_CHIP_RV515_7143: 647 case PCI_CHIP_RV515_7144: 648 case PCI_CHIP_RV515_7145: 649 case PCI_CHIP_RV515_7146: 650 case PCI_CHIP_RV515_7147: 651 case PCI_CHIP_RV515_7149: 652 case PCI_CHIP_RV515_714A: 653 case PCI_CHIP_RV515_714B: 654 case PCI_CHIP_RV515_714C: 655 case PCI_CHIP_RV515_714D: 656 case PCI_CHIP_RV515_714E: 657 case PCI_CHIP_RV515_714F: 658 case PCI_CHIP_RV515_7151: 659 case PCI_CHIP_RV515_7152: 660 case PCI_CHIP_RV515_7153: 661 case PCI_CHIP_RV515_715E: 662 case PCI_CHIP_RV515_715F: 663 case PCI_CHIP_RV515_7180: 664 case PCI_CHIP_RV515_7181: 665 case PCI_CHIP_RV515_7183: 666 case PCI_CHIP_RV515_7186: 667 case PCI_CHIP_RV515_7187: 668 case PCI_CHIP_RV515_7188: 669 case PCI_CHIP_RV515_718A: 670 case PCI_CHIP_RV515_718B: 671 case PCI_CHIP_RV515_718C: 672 case PCI_CHIP_RV515_718D: 673 case PCI_CHIP_RV515_718F: 674 case PCI_CHIP_RV515_7193: 675 case PCI_CHIP_RV515_7196: 676 case PCI_CHIP_RV515_719B: 677 case PCI_CHIP_RV515_719F: 678 case PCI_CHIP_RV515_7200: 679 case PCI_CHIP_RV515_7210: 680 case PCI_CHIP_RV515_7211: 681 screen->chip_family = CHIP_FAMILY_RV515; 682 screen->chip_flags = RADEON_CHIPSET_TCL; 683 break; 684 685 case PCI_CHIP_RV530_71C0: 686 case PCI_CHIP_RV530_71C1: 687 case PCI_CHIP_RV530_71C2: 688 case PCI_CHIP_RV530_71C3: 689 case PCI_CHIP_RV530_71C4: 690 case PCI_CHIP_RV530_71C5: 691 case PCI_CHIP_RV530_71C6: 692 case PCI_CHIP_RV530_71C7: 693 case PCI_CHIP_RV530_71CD: 694 case PCI_CHIP_RV530_71CE: 695 case PCI_CHIP_RV530_71D2: 696 case PCI_CHIP_RV530_71D4: 697 case PCI_CHIP_RV530_71D5: 698 case PCI_CHIP_RV530_71D6: 699 case PCI_CHIP_RV530_71DA: 700 case PCI_CHIP_RV530_71DE: 701 screen->chip_family = CHIP_FAMILY_RV530; 702 screen->chip_flags = RADEON_CHIPSET_TCL; 703 break; 704 705 case PCI_CHIP_R580_7240: 706 case PCI_CHIP_R580_7243: 707 case PCI_CHIP_R580_7244: 708 case PCI_CHIP_R580_7245: 709 case PCI_CHIP_R580_7246: 710 case PCI_CHIP_R580_7247: 711 case PCI_CHIP_R580_7248: 712 case PCI_CHIP_R580_7249: 713 case PCI_CHIP_R580_724A: 714 case PCI_CHIP_R580_724B: 715 case PCI_CHIP_R580_724C: 716 case PCI_CHIP_R580_724D: 717 case PCI_CHIP_R580_724E: 718 case PCI_CHIP_R580_724F: 719 case PCI_CHIP_R580_7284: 720 screen->chip_family = CHIP_FAMILY_R580; 721 screen->chip_flags = RADEON_CHIPSET_TCL; 722 break; 723 724 case PCI_CHIP_RV570_7280: 725 case PCI_CHIP_RV560_7281: 726 case PCI_CHIP_RV560_7283: 727 case PCI_CHIP_RV560_7287: 728 case PCI_CHIP_RV570_7288: 729 case PCI_CHIP_RV570_7289: 730 case PCI_CHIP_RV570_728B: 731 case PCI_CHIP_RV570_728C: 732 case PCI_CHIP_RV560_7290: 733 case PCI_CHIP_RV560_7291: 734 case PCI_CHIP_RV560_7293: 735 case PCI_CHIP_RV560_7297: 736 screen->chip_family = CHIP_FAMILY_RV560; 737 screen->chip_flags = RADEON_CHIPSET_TCL; 738 break; 739 740 case PCI_CHIP_R600_9400: 741 case PCI_CHIP_R600_9401: 742 case PCI_CHIP_R600_9402: 743 case PCI_CHIP_R600_9403: 744 case PCI_CHIP_R600_9405: 745 case PCI_CHIP_R600_940A: 746 case PCI_CHIP_R600_940B: 747 case PCI_CHIP_R600_940F: 748 screen->chip_family = CHIP_FAMILY_R600; 749 screen->chip_flags = RADEON_CHIPSET_TCL; 750 break; 751 752 case PCI_CHIP_RV610_94C0: 753 case PCI_CHIP_RV610_94C1: 754 case PCI_CHIP_RV610_94C3: 755 case PCI_CHIP_RV610_94C4: 756 case PCI_CHIP_RV610_94C5: 757 case PCI_CHIP_RV610_94C6: 758 case PCI_CHIP_RV610_94C7: 759 case PCI_CHIP_RV610_94C8: 760 case PCI_CHIP_RV610_94C9: 761 case PCI_CHIP_RV610_94CB: 762 case PCI_CHIP_RV610_94CC: 763 case PCI_CHIP_RV610_94CD: 764 screen->chip_family = CHIP_FAMILY_RV610; 765 screen->chip_flags = RADEON_CHIPSET_TCL; 766 break; 767 768 case PCI_CHIP_RV630_9580: 769 case PCI_CHIP_RV630_9581: 770 case PCI_CHIP_RV630_9583: 771 case PCI_CHIP_RV630_9586: 772 case PCI_CHIP_RV630_9587: 773 case PCI_CHIP_RV630_9588: 774 case PCI_CHIP_RV630_9589: 775 case PCI_CHIP_RV630_958A: 776 case PCI_CHIP_RV630_958B: 777 case PCI_CHIP_RV630_958C: 778 case PCI_CHIP_RV630_958D: 779 case PCI_CHIP_RV630_958E: 780 case PCI_CHIP_RV630_958F: 781 screen->chip_family = CHIP_FAMILY_RV630; 782 screen->chip_flags = RADEON_CHIPSET_TCL; 783 break; 784 785 case PCI_CHIP_RV670_9500: 786 case PCI_CHIP_RV670_9501: 787 case PCI_CHIP_RV670_9504: 788 case PCI_CHIP_RV670_9505: 789 case PCI_CHIP_RV670_9506: 790 case PCI_CHIP_RV670_9507: 791 case PCI_CHIP_RV670_9508: 792 case PCI_CHIP_RV670_9509: 793 case PCI_CHIP_RV670_950F: 794 case PCI_CHIP_RV670_9511: 795 case PCI_CHIP_RV670_9515: 796 case PCI_CHIP_RV670_9517: 797 case PCI_CHIP_RV670_9519: 798 screen->chip_family = CHIP_FAMILY_RV670; 799 screen->chip_flags = RADEON_CHIPSET_TCL; 800 break; 801 802 case PCI_CHIP_RV620_95C0: 803 case PCI_CHIP_RV620_95C2: 804 case PCI_CHIP_RV620_95C4: 805 case PCI_CHIP_RV620_95C5: 806 case PCI_CHIP_RV620_95C6: 807 case PCI_CHIP_RV620_95C7: 808 case PCI_CHIP_RV620_95C9: 809 case PCI_CHIP_RV620_95CC: 810 case PCI_CHIP_RV620_95CD: 811 case PCI_CHIP_RV620_95CE: 812 case PCI_CHIP_RV620_95CF: 813 screen->chip_family = CHIP_FAMILY_RV620; 814 screen->chip_flags = RADEON_CHIPSET_TCL; 815 break; 816 817 case PCI_CHIP_RV635_9590: 818 case PCI_CHIP_RV635_9591: 819 case PCI_CHIP_RV635_9593: 820 case PCI_CHIP_RV635_9595: 821 case PCI_CHIP_RV635_9596: 822 case PCI_CHIP_RV635_9597: 823 case PCI_CHIP_RV635_9598: 824 case PCI_CHIP_RV635_9599: 825 case PCI_CHIP_RV635_959B: 826 screen->chip_family = CHIP_FAMILY_RV635; 827 screen->chip_flags = RADEON_CHIPSET_TCL; 828 break; 829 830 case PCI_CHIP_RS780_9610: 831 case PCI_CHIP_RS780_9611: 832 case PCI_CHIP_RS780_9612: 833 case PCI_CHIP_RS780_9613: 834 case PCI_CHIP_RS780_9614: 835 case PCI_CHIP_RS780_9615: 836 case PCI_CHIP_RS780_9616: 837 screen->chip_family = CHIP_FAMILY_RS780; 838 screen->chip_flags = RADEON_CHIPSET_TCL; 839 break; 840 case PCI_CHIP_RS880_9710: 841 case PCI_CHIP_RS880_9711: 842 case PCI_CHIP_RS880_9712: 843 case PCI_CHIP_RS880_9713: 844 case PCI_CHIP_RS880_9714: 845 case PCI_CHIP_RS880_9715: 846 screen->chip_family = CHIP_FAMILY_RS880; 847 screen->chip_flags = RADEON_CHIPSET_TCL; 848 break; 849 850 case PCI_CHIP_RV770_9440: 851 case PCI_CHIP_RV770_9441: 852 case PCI_CHIP_RV770_9442: 853 case PCI_CHIP_RV770_9443: 854 case PCI_CHIP_RV770_9444: 855 case PCI_CHIP_RV770_9446: 856 case PCI_CHIP_RV770_944A: 857 case PCI_CHIP_RV770_944B: 858 case PCI_CHIP_RV770_944C: 859 case PCI_CHIP_RV770_944E: 860 case PCI_CHIP_RV770_9450: 861 case PCI_CHIP_RV770_9452: 862 case PCI_CHIP_RV770_9456: 863 case PCI_CHIP_RV770_945A: 864 case PCI_CHIP_RV770_945B: 865 case PCI_CHIP_RV770_945E: 866 case PCI_CHIP_RV790_9460: 867 case PCI_CHIP_RV790_9462: 868 case PCI_CHIP_RV770_946A: 869 case PCI_CHIP_RV770_946B: 870 case PCI_CHIP_RV770_947A: 871 case PCI_CHIP_RV770_947B: 872 screen->chip_family = CHIP_FAMILY_RV770; 873 screen->chip_flags = RADEON_CHIPSET_TCL; 874 break; 875 876 case PCI_CHIP_RV730_9480: 877 case PCI_CHIP_RV730_9487: 878 case PCI_CHIP_RV730_9488: 879 case PCI_CHIP_RV730_9489: 880 case PCI_CHIP_RV730_948A: 881 case PCI_CHIP_RV730_948F: 882 case PCI_CHIP_RV730_9490: 883 case PCI_CHIP_RV730_9491: 884 case PCI_CHIP_RV730_9495: 885 case PCI_CHIP_RV730_9498: 886 case PCI_CHIP_RV730_949C: 887 case PCI_CHIP_RV730_949E: 888 case PCI_CHIP_RV730_949F: 889 screen->chip_family = CHIP_FAMILY_RV730; 890 screen->chip_flags = RADEON_CHIPSET_TCL; 891 break; 892 893 case PCI_CHIP_RV710_9540: 894 case PCI_CHIP_RV710_9541: 895 case PCI_CHIP_RV710_9542: 896 case PCI_CHIP_RV710_954E: 897 case PCI_CHIP_RV710_954F: 898 case PCI_CHIP_RV710_9552: 899 case PCI_CHIP_RV710_9553: 900 case PCI_CHIP_RV710_9555: 901 case PCI_CHIP_RV710_9557: 902 case PCI_CHIP_RV710_955F: 903 screen->chip_family = CHIP_FAMILY_RV710; 904 screen->chip_flags = RADEON_CHIPSET_TCL; 905 break; 906 907 case PCI_CHIP_RV740_94A0: 908 case PCI_CHIP_RV740_94A1: 909 case PCI_CHIP_RV740_94A3: 910 case PCI_CHIP_RV740_94B1: 911 case PCI_CHIP_RV740_94B3: 912 case PCI_CHIP_RV740_94B4: 913 case PCI_CHIP_RV740_94B5: 914 case PCI_CHIP_RV740_94B9: 915 screen->chip_family = CHIP_FAMILY_RV740; 916 screen->chip_flags = RADEON_CHIPSET_TCL; 917 break; 918 919 case PCI_CHIP_CEDAR_68E0: 920 case PCI_CHIP_CEDAR_68E1: 921 case PCI_CHIP_CEDAR_68E4: 922 case PCI_CHIP_CEDAR_68E5: 923 case PCI_CHIP_CEDAR_68E8: 924 case PCI_CHIP_CEDAR_68E9: 925 case PCI_CHIP_CEDAR_68F1: 926 case PCI_CHIP_CEDAR_68F8: 927 case PCI_CHIP_CEDAR_68F9: 928 case PCI_CHIP_CEDAR_68FE: 929 screen->chip_family = CHIP_FAMILY_CEDAR; 930 screen->chip_flags = RADEON_CHIPSET_TCL; 931 break; 932 933 case PCI_CHIP_REDWOOD_68C0: 934 case PCI_CHIP_REDWOOD_68C1: 935 case PCI_CHIP_REDWOOD_68C8: 936 case PCI_CHIP_REDWOOD_68C9: 937 case PCI_CHIP_REDWOOD_68D8: 938 case PCI_CHIP_REDWOOD_68D9: 939 case PCI_CHIP_REDWOOD_68DA: 940 case PCI_CHIP_REDWOOD_68DE: 941 screen->chip_family = CHIP_FAMILY_REDWOOD; 942 screen->chip_flags = RADEON_CHIPSET_TCL; 943 break; 944 945 case PCI_CHIP_JUNIPER_68A0: 946 case PCI_CHIP_JUNIPER_68A1: 947 case PCI_CHIP_JUNIPER_68A8: 948 case PCI_CHIP_JUNIPER_68A9: 949 case PCI_CHIP_JUNIPER_68B0: 950 case PCI_CHIP_JUNIPER_68B8: 951 case PCI_CHIP_JUNIPER_68B9: 952 case PCI_CHIP_JUNIPER_68BE: 953 screen->chip_family = CHIP_FAMILY_JUNIPER; 954 screen->chip_flags = RADEON_CHIPSET_TCL; 955 break; 956 957 case PCI_CHIP_CYPRESS_6880: 958 case PCI_CHIP_CYPRESS_6888: 959 case PCI_CHIP_CYPRESS_6889: 960 case PCI_CHIP_CYPRESS_688A: 961 case PCI_CHIP_CYPRESS_6898: 962 case PCI_CHIP_CYPRESS_6899: 963 case PCI_CHIP_CYPRESS_689E: 964 screen->chip_family = CHIP_FAMILY_CYPRESS; 965 screen->chip_flags = RADEON_CHIPSET_TCL; 966 break; 967 968 case PCI_CHIP_HEMLOCK_689C: 969 case PCI_CHIP_HEMLOCK_689D: 970 screen->chip_family = CHIP_FAMILY_HEMLOCK; 971 screen->chip_flags = RADEON_CHIPSET_TCL; 972 break; 973 974 default: 975 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 976 device_id); 977 return -1; 978 } 979 980 return 0; 981} 982 983 984/* Create the device specific screen private data struct. 985 */ 986static radeonScreenPtr 987radeonCreateScreen( __DRIscreen *sPriv ) 988{ 989 radeonScreenPtr screen; 990 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 991 unsigned char *RADEONMMIO = NULL; 992 int i; 993 int ret; 994 uint32_t temp = 0; 995 996 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 997 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 998 return GL_FALSE; 999 } 1000 1001 /* Allocate the private area */ 1002 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1003 if ( !screen ) { 1004 __driUtilMessage("%s: Could not allocate memory for screen structure", 1005 __FUNCTION__); 1006 return NULL; 1007 } 1008 1009 radeon_init_debug(); 1010 1011 /* parse information in __driConfigOptions */ 1012 driParseOptionInfo (&screen->optionCache, 1013 __driConfigOptions, __driNConfigOptions); 1014 1015 /* This is first since which regions we map depends on whether or 1016 * not we are using a PCI card. 1017 */ 1018 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 1019 { 1020 int ret; 1021 1022 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 1023 &screen->gart_buffer_offset); 1024 1025 if (ret) { 1026 FREE( screen ); 1027 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 1028 return NULL; 1029 } 1030 1031 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 1032 &screen->gart_base); 1033 if (ret) { 1034 FREE( screen ); 1035 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 1036 return NULL; 1037 } 1038 1039 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 1040 &screen->irq); 1041 if (ret) { 1042 FREE( screen ); 1043 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 1044 return NULL; 1045 } 1046 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 1047 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 1048 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 1049 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 1050 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 1051 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 1052 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 1053 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30); 1054 } 1055 1056 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 1057 if (ret == -1) 1058 return NULL; 1059 1060 screen->mmio.handle = dri_priv->registerHandle; 1061 screen->mmio.size = dri_priv->registerSize; 1062 if ( drmMap( sPriv->fd, 1063 screen->mmio.handle, 1064 screen->mmio.size, 1065 &screen->mmio.map ) ) { 1066 FREE( screen ); 1067 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 1068 return NULL; 1069 } 1070 1071 RADEONMMIO = screen->mmio.map; 1072 1073 screen->status.handle = dri_priv->statusHandle; 1074 screen->status.size = dri_priv->statusSize; 1075 if ( drmMap( sPriv->fd, 1076 screen->status.handle, 1077 screen->status.size, 1078 &screen->status.map ) ) { 1079 drmUnmap( screen->mmio.map, screen->mmio.size ); 1080 FREE( screen ); 1081 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1082 return NULL; 1083 } 1084 if (screen->chip_family < CHIP_FAMILY_R600) 1085 screen->scratch = (__volatile__ uint32_t *) 1086 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1087 else 1088 screen->scratch = (__volatile__ uint32_t *) 1089 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET); 1090 1091 screen->buffers = drmMapBufs( sPriv->fd ); 1092 if ( !screen->buffers ) { 1093 drmUnmap( screen->status.map, screen->status.size ); 1094 drmUnmap( screen->mmio.map, screen->mmio.size ); 1095 FREE( screen ); 1096 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1097 return NULL; 1098 } 1099 1100 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1101 screen->gartTextures.handle = dri_priv->gartTexHandle; 1102 screen->gartTextures.size = dri_priv->gartTexMapSize; 1103 if ( drmMap( sPriv->fd, 1104 screen->gartTextures.handle, 1105 screen->gartTextures.size, 1106 (drmAddressPtr)&screen->gartTextures.map ) ) { 1107 drmUnmapBufs( screen->buffers ); 1108 drmUnmap( screen->status.map, screen->status.size ); 1109 drmUnmap( screen->mmio.map, screen->mmio.size ); 1110 FREE( screen ); 1111 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1112 return NULL; 1113 } 1114 1115 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1116 } 1117 1118 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1119 sPriv->ddx_version.minor < 2) { 1120 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1121 return NULL; 1122 } 1123 1124 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1125 fprintf(stderr, "R500 support requires a newer drm.\n"); 1126 return NULL; 1127 } 1128 1129 if (getenv("R300_NO_TCL")) 1130 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1131 1132 if (screen->chip_family <= CHIP_FAMILY_RS200) 1133 screen->chip_flags |= RADEON_CLASS_R100; 1134 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1135 screen->chip_flags |= RADEON_CLASS_R200; 1136 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1137 screen->chip_flags |= RADEON_CLASS_R300; 1138 else 1139 screen->chip_flags |= RADEON_CLASS_R600; 1140 1141 /* set group bytes for r6xx+ */ 1142 screen->group_bytes = 256; 1143 screen->cpp = dri_priv->bpp / 8; 1144 screen->AGPMode = dri_priv->AGPMode; 1145 1146 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1147 1148 /* +r6/r7 */ 1149 if(screen->chip_family >= CHIP_FAMILY_R600) 1150 { 1151 if (ret) 1152 { 1153 FREE( screen ); 1154 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1155 return NULL; 1156 } 1157 else 1158 { 1159 screen->fbLocation = (temp & 0xffff) << 24; 1160 } 1161 } 1162 else 1163 { 1164 if (ret) 1165 { 1166 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1167 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1168 else 1169 { 1170 FREE( screen ); 1171 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1172 return NULL; 1173 } 1174 } 1175 else 1176 { 1177 screen->fbLocation = (temp & 0xffff) << 16; 1178 } 1179 } 1180 1181 if (IS_R300_CLASS(screen)) { 1182 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1183 if (ret) { 1184 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1185 switch (screen->chip_family) { 1186 case CHIP_FAMILY_R300: 1187 case CHIP_FAMILY_R350: 1188 screen->num_gb_pipes = 2; 1189 break; 1190 case CHIP_FAMILY_R420: 1191 case CHIP_FAMILY_R520: 1192 case CHIP_FAMILY_R580: 1193 case CHIP_FAMILY_RV560: 1194 case CHIP_FAMILY_RV570: 1195 screen->num_gb_pipes = 4; 1196 break; 1197 case CHIP_FAMILY_RV350: 1198 case CHIP_FAMILY_RV515: 1199 case CHIP_FAMILY_RV530: 1200 case CHIP_FAMILY_RV410: 1201 default: 1202 screen->num_gb_pipes = 1; 1203 break; 1204 } 1205 } else { 1206 screen->num_gb_pipes = temp; 1207 } 1208 1209 /* pipe overrides */ 1210 switch (dri_priv->deviceID) { 1211 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1212 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */ 1213 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1214 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1215 screen->num_gb_pipes = 1; 1216 break; 1217 default: 1218 break; 1219 } 1220 1221 if ( sPriv->drm_version.minor >= 31 ) { 1222 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1223 if (ret) 1224 screen->num_z_pipes = 2; 1225 else 1226 screen->num_z_pipes = temp; 1227 } else 1228 screen->num_z_pipes = 2; 1229 } 1230 1231 if ( sPriv->drm_version.minor >= 10 ) { 1232 drm_radeon_setparam_t sp; 1233 1234 sp.param = RADEON_SETPARAM_FB_LOCATION; 1235 sp.value = screen->fbLocation; 1236 1237 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1238 &sp, sizeof( sp ) ); 1239 } 1240 1241 screen->frontOffset = dri_priv->frontOffset; 1242 screen->frontPitch = dri_priv->frontPitch; 1243 screen->backOffset = dri_priv->backOffset; 1244 screen->backPitch = dri_priv->backPitch; 1245 screen->depthOffset = dri_priv->depthOffset; 1246 screen->depthPitch = dri_priv->depthPitch; 1247 1248 /* Check if ddx has set up a surface reg to cover depth buffer */ 1249 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1250 /* these chips don't use tiled z without hyperz. So always pretend 1251 we have set up a surface which will cause linear reads/writes */ 1252 (IS_R100_CLASS(screen) && 1253 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1254 1255 if ( dri_priv->textureSize == 0 ) { 1256 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1257 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1258 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1259 dri_priv->log2GARTTexGran; 1260 } else { 1261 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1262 + screen->fbLocation; 1263 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1264 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1265 dri_priv->log2TexGran; 1266 } 1267 1268 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1269 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1270 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1271 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1272 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1273 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1274 } else { 1275 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1276 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1277 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1278 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1279 dri_priv->log2GARTTexGran; 1280 } 1281 1282 i = 0; 1283 screen->extensions[i++] = &driCopySubBufferExtension.base; 1284 screen->extensions[i++] = &driReadDrawableExtension; 1285 1286 if ( screen->irq != 0 ) { 1287 screen->extensions[i++] = &driSwapControlExtension.base; 1288 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1289 } 1290 1291#if defined(RADEON_R100) 1292 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1293#endif 1294 1295#if defined(RADEON_R200) 1296 screen->extensions[i++] = &r200texOffsetExtension.base; 1297#endif 1298 1299#if defined(RADEON_R300) 1300 screen->extensions[i++] = &r300texOffsetExtension.base; 1301#endif 1302 1303#if defined(RADEON_R600) 1304 screen->extensions[i++] = &r600texOffsetExtension.base; 1305#endif 1306 1307 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1308 1309 screen->extensions[i++] = NULL; 1310 sPriv->extensions = screen->extensions; 1311 1312 screen->driScreen = sPriv; 1313 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1314 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1315 screen->sarea_priv_offset); 1316 1317 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1318 if (screen->bom == NULL) { 1319 free(screen); 1320 return NULL; 1321 } 1322 1323 return screen; 1324} 1325 1326static radeonScreenPtr 1327radeonCreateScreen2(__DRIscreen *sPriv) 1328{ 1329 radeonScreenPtr screen; 1330 int i; 1331 int ret; 1332 uint32_t device_id = 0; 1333 uint32_t temp = 0; 1334 1335 /* Allocate the private area */ 1336 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1337 if ( !screen ) { 1338 __driUtilMessage("%s: Could not allocate memory for screen structure", 1339 __FUNCTION__); 1340 fprintf(stderr, "leaving here\n"); 1341 return NULL; 1342 } 1343 1344 radeon_init_debug(); 1345 1346 /* parse information in __driConfigOptions */ 1347 driParseOptionInfo (&screen->optionCache, 1348 __driConfigOptions, __driNConfigOptions); 1349 1350 screen->kernel_mm = 1; 1351 screen->chip_flags = 0; 1352 1353 /* if we have kms we can support all of these */ 1354 screen->drmSupportsCubeMapsR200 = 1; 1355 screen->drmSupportsBlendColor = 1; 1356 screen->drmSupportsTriPerf = 1; 1357 screen->drmSupportsFragShader = 1; 1358 screen->drmSupportsPointSprites = 1; 1359 screen->drmSupportsCubeMapsR100 = 1; 1360 screen->drmSupportsVertexProgram = 1; 1361 screen->drmSupportsOcclusionQueries = 1; 1362 screen->irq = 1; 1363 1364 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1365 if (ret) { 1366 FREE( screen ); 1367 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1368 return NULL; 1369 } 1370 1371 ret = radeon_set_screen_flags(screen, device_id); 1372 if (ret == -1) 1373 return NULL; 1374 1375 if (getenv("R300_NO_TCL")) 1376 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1377 1378 if (screen->chip_family <= CHIP_FAMILY_RS200) 1379 screen->chip_flags |= RADEON_CLASS_R100; 1380 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1381 screen->chip_flags |= RADEON_CLASS_R200; 1382 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1383 screen->chip_flags |= RADEON_CLASS_R300; 1384 else 1385 screen->chip_flags |= RADEON_CLASS_R600; 1386 1387 /* r6xx+ tiling, default to 256 group bytes */ 1388 screen->group_bytes = 256; 1389 if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) { 1390 ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp); 1391 if (ret) 1392 fprintf(stderr, "failed to get tiling info\n"); 1393 else { 1394 screen->tile_config = temp; 1395 screen->r7xx_bank_op = 0; 1396 switch((screen->tile_config & 0xe) >> 1) { 1397 case 0: 1398 screen->num_channels = 1; 1399 break; 1400 case 1: 1401 screen->num_channels = 2; 1402 break; 1403 case 2: 1404 screen->num_channels = 4; 1405 break; 1406 case 3: 1407 screen->num_channels = 8; 1408 break; 1409 default: 1410 fprintf(stderr, "bad channels\n"); 1411 break; 1412 } 1413 switch((screen->tile_config & 0x30) >> 4) { 1414 case 0: 1415 screen->num_banks = 4; 1416 break; 1417 case 1: 1418 screen->num_banks = 8; 1419 break; 1420 default: 1421 fprintf(stderr, "bad banks\n"); 1422 break; 1423 } 1424 switch((screen->tile_config & 0xc0) >> 6) { 1425 case 0: 1426 screen->group_bytes = 256; 1427 break; 1428 case 1: 1429 screen->group_bytes = 512; 1430 break; 1431 default: 1432 fprintf(stderr, "bad group_bytes\n"); 1433 break; 1434 } 1435 } 1436 } 1437 1438 if (IS_R300_CLASS(screen)) { 1439 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1440 if (ret) { 1441 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1442 switch (screen->chip_family) { 1443 case CHIP_FAMILY_R300: 1444 case CHIP_FAMILY_R350: 1445 screen->num_gb_pipes = 2; 1446 break; 1447 case CHIP_FAMILY_R420: 1448 case CHIP_FAMILY_R520: 1449 case CHIP_FAMILY_R580: 1450 case CHIP_FAMILY_RV560: 1451 case CHIP_FAMILY_RV570: 1452 screen->num_gb_pipes = 4; 1453 break; 1454 case CHIP_FAMILY_RV350: 1455 case CHIP_FAMILY_RV515: 1456 case CHIP_FAMILY_RV530: 1457 case CHIP_FAMILY_RV410: 1458 default: 1459 screen->num_gb_pipes = 1; 1460 break; 1461 } 1462 } else { 1463 screen->num_gb_pipes = temp; 1464 } 1465 1466 /* pipe overrides */ 1467 switch (device_id) { 1468 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1469 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */ 1470 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1471 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1472 screen->num_gb_pipes = 1; 1473 break; 1474 default: 1475 break; 1476 } 1477 1478 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1479 if (ret) 1480 screen->num_z_pipes = 2; 1481 else 1482 screen->num_z_pipes = temp; 1483 1484 } 1485 1486 i = 0; 1487 screen->extensions[i++] = &driCopySubBufferExtension.base; 1488 screen->extensions[i++] = &driReadDrawableExtension; 1489 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1490 1491 if ( screen->irq != 0 ) { 1492 screen->extensions[i++] = &driSwapControlExtension.base; 1493 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1494 } 1495 1496#if defined(RADEON_R100) 1497 screen->extensions[i++] = &radeonTexBufferExtension.base; 1498#endif 1499 1500#if defined(RADEON_R200) 1501 screen->extensions[i++] = &r200TexBufferExtension.base; 1502#endif 1503 1504#if defined(RADEON_R300) 1505 screen->extensions[i++] = &r300TexBufferExtension.base; 1506#endif 1507 1508#if defined(RADEON_R600) 1509 screen->extensions[i++] = &r600TexBufferExtension.base; 1510#endif 1511 1512 screen->extensions[i++] = &radeonFlushExtension.base; 1513 1514 screen->extensions[i++] = NULL; 1515 sPriv->extensions = screen->extensions; 1516 1517 screen->driScreen = sPriv; 1518 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1519 if (screen->bom == NULL) { 1520 free(screen); 1521 return NULL; 1522 } 1523 return screen; 1524} 1525 1526/* Destroy the device specific screen private data struct. 1527 */ 1528static void 1529radeonDestroyScreen( __DRIscreen *sPriv ) 1530{ 1531 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1532 1533 if (!screen) 1534 return; 1535 1536 if (screen->kernel_mm) { 1537#ifdef RADEON_BO_TRACK 1538 radeon_tracker_print(&screen->bom->tracker, stderr); 1539#endif 1540 radeon_bo_manager_gem_dtor(screen->bom); 1541 } else { 1542 radeon_bo_manager_legacy_dtor(screen->bom); 1543 1544 if ( screen->gartTextures.map ) { 1545 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1546 } 1547 drmUnmapBufs( screen->buffers ); 1548 drmUnmap( screen->status.map, screen->status.size ); 1549 drmUnmap( screen->mmio.map, screen->mmio.size ); 1550 } 1551 1552 /* free all option information */ 1553 driDestroyOptionInfo (&screen->optionCache); 1554 1555 FREE( screen ); 1556 sPriv->private = NULL; 1557} 1558 1559 1560/* Initialize the driver specific screen private data. 1561 */ 1562static GLboolean 1563radeonInitDriver( __DRIscreen *sPriv ) 1564{ 1565 if (sPriv->dri2.enabled) { 1566 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1567 } else { 1568 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1569 } 1570 if ( !sPriv->private ) { 1571 radeonDestroyScreen( sPriv ); 1572 return GL_FALSE; 1573 } 1574 1575 return GL_TRUE; 1576} 1577 1578 1579 1580/** 1581 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1582 * 1583 * \todo This function (and its interface) will need to be updated to support 1584 * pbuffers. 1585 */ 1586static GLboolean 1587radeonCreateBuffer( __DRIscreen *driScrnPriv, 1588 __DRIdrawable *driDrawPriv, 1589 const struct gl_config *mesaVis, 1590 GLboolean isPixmap ) 1591{ 1592 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1593 1594 const GLboolean swDepth = GL_FALSE; 1595 const GLboolean swAlpha = GL_FALSE; 1596 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1597 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1598 mesaVis->depthBits != 24; 1599 gl_format rgbFormat; 1600 struct radeon_framebuffer *rfb; 1601 1602 if (isPixmap) 1603 return GL_FALSE; /* not implemented */ 1604 1605 rfb = CALLOC_STRUCT(radeon_framebuffer); 1606 if (!rfb) 1607 return GL_FALSE; 1608 1609 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis); 1610 1611 if (mesaVis->redBits == 5) 1612 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV; 1613 else if (mesaVis->alphaBits == 0) 1614 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV; 1615 else 1616 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV; 1617 1618 /* front color renderbuffer */ 1619 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1620 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1621 rfb->color_rb[0]->has_surface = 1; 1622 1623 /* back color renderbuffer */ 1624 if (mesaVis->doubleBufferMode) { 1625 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1626 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1627 rfb->color_rb[1]->has_surface = 1; 1628 } 1629 1630 if (mesaVis->depthBits == 24) { 1631 if (mesaVis->stencilBits == 8) { 1632 struct radeon_renderbuffer *depthStencilRb = 1633 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); 1634 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1635 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1636 depthStencilRb->has_surface = screen->depthHasSurface; 1637 } else { 1638 /* depth renderbuffer */ 1639 struct radeon_renderbuffer *depth = 1640 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); 1641 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1642 depth->has_surface = screen->depthHasSurface; 1643 } 1644 } else if (mesaVis->depthBits == 16) { 1645 /* just 16-bit depth buffer, no hw stencil */ 1646 struct radeon_renderbuffer *depth = 1647 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); 1648 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1649 depth->has_surface = screen->depthHasSurface; 1650 } 1651 1652 _mesa_add_soft_renderbuffers(&rfb->base, 1653 GL_FALSE, /* color */ 1654 swDepth, 1655 swStencil, 1656 swAccum, 1657 swAlpha, 1658 GL_FALSE /* aux */); 1659 driDrawPriv->driverPrivate = (void *) rfb; 1660 1661 return (driDrawPriv->driverPrivate != NULL); 1662} 1663 1664 1665static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1666{ 1667 struct radeon_renderbuffer *rb; 1668 1669 rb = rfb->color_rb[0]; 1670 if (rb && rb->bo) { 1671 radeon_bo_unref(rb->bo); 1672 rb->bo = NULL; 1673 } 1674 rb = rfb->color_rb[1]; 1675 if (rb && rb->bo) { 1676 radeon_bo_unref(rb->bo); 1677 rb->bo = NULL; 1678 } 1679 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1680 if (rb && rb->bo) { 1681 radeon_bo_unref(rb->bo); 1682 rb->bo = NULL; 1683 } 1684} 1685 1686void 1687radeonDestroyBuffer(__DRIdrawable *driDrawPriv) 1688{ 1689 struct radeon_framebuffer *rfb; 1690 if (!driDrawPriv) 1691 return; 1692 1693 rfb = (void*)driDrawPriv->driverPrivate; 1694 if (!rfb) 1695 return; 1696 radeon_cleanup_renderbuffers(rfb); 1697 _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1698} 1699 1700 1701/** 1702 * This is the driver specific part of the createNewScreen entry point. 1703 * 1704 * \todo maybe fold this into intelInitDriver 1705 * 1706 * \return the struct gl_config supported by this driver 1707 */ 1708static const __DRIconfig ** 1709radeonInitScreen(__DRIscreen *psp) 1710{ 1711#if defined(RADEON_R100) 1712 static const char *driver_name = "Radeon"; 1713 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1714 static const __DRIversion dri_expected = { 4, 0, 0 }; 1715 static const __DRIversion drm_expected = { 1, 6, 0 }; 1716#elif defined(RADEON_R200) 1717 static const char *driver_name = "R200"; 1718 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1719 static const __DRIversion dri_expected = { 4, 0, 0 }; 1720 static const __DRIversion drm_expected = { 1, 6, 0 }; 1721#elif defined(RADEON_R300) 1722 static const char *driver_name = "R300"; 1723 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1724 static const __DRIversion dri_expected = { 4, 0, 0 }; 1725 static const __DRIversion drm_expected = { 1, 24, 0 }; 1726#elif defined(RADEON_R600) 1727 static const char *driver_name = "R600"; 1728 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1729 static const __DRIversion dri_expected = { 4, 0, 0 }; 1730 static const __DRIversion drm_expected = { 1, 24, 0 }; 1731#endif 1732 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1733 1734 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1735 &psp->dri_version, & dri_expected, 1736 &psp->ddx_version, & ddx_expected, 1737 &psp->drm_version, & drm_expected ) ) { 1738 return NULL; 1739 } 1740 1741 if (!radeonInitDriver(psp)) 1742 return NULL; 1743 1744 /* for now fill in all modes */ 1745 return radeonFillInModes( psp, 1746 dri_priv->bpp, 1747 (dri_priv->bpp == 16) ? 16 : 24, 1748 (dri_priv->bpp == 16) ? 0 : 8, 1); 1749} 1750#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1751 1752/** 1753 * This is the driver specific part of the createNewScreen entry point. 1754 * Called when using DRI2. 1755 * 1756 * \return the struct gl_config supported by this driver 1757 */ 1758static const 1759__DRIconfig **radeonInitScreen2(__DRIscreen *psp) 1760{ 1761 GLenum fb_format[3]; 1762 GLenum fb_type[3]; 1763 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1764 * support pageflipping at all. 1765 */ 1766 static const GLenum back_buffer_modes[] = { 1767 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1768 }; 1769 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1770 int color; 1771 __DRIconfig **configs = NULL; 1772 1773 if (!radeonInitDriver(psp)) { 1774 return NULL; 1775 } 1776 depth_bits[0] = 0; 1777 stencil_bits[0] = 0; 1778 depth_bits[1] = 16; 1779 stencil_bits[1] = 0; 1780 depth_bits[2] = 24; 1781 stencil_bits[2] = 0; 1782 depth_bits[3] = 24; 1783 stencil_bits[3] = 8; 1784 1785 msaa_samples_array[0] = 0; 1786 1787 fb_format[0] = GL_RGB; 1788 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1789 1790 fb_format[1] = GL_BGR; 1791 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1792 1793 fb_format[2] = GL_BGRA; 1794 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1795 1796 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1797 __DRIconfig **new_configs; 1798 1799 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1800 depth_bits, 1801 stencil_bits, 1802 ARRAY_SIZE(depth_bits), 1803 back_buffer_modes, 1804 ARRAY_SIZE(back_buffer_modes), 1805 msaa_samples_array, 1806 ARRAY_SIZE(msaa_samples_array), 1807 GL_TRUE); 1808 if (configs == NULL) 1809 configs = new_configs; 1810 else 1811 configs = driConcatConfigs(configs, new_configs); 1812 } 1813 1814 if (configs == NULL) { 1815 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1816 __LINE__); 1817 return NULL; 1818 } 1819 1820 return (const __DRIconfig **)configs; 1821} 1822 1823/** 1824 * Get information about previous buffer swaps. 1825 */ 1826static int 1827getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ) 1828{ 1829 struct radeon_framebuffer *rfb; 1830 1831 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1832 || (dPriv->driContextPriv->driverPrivate == NULL) 1833 || (sInfo == NULL) ) { 1834 return -1; 1835 } 1836 1837 rfb = dPriv->driverPrivate; 1838 sInfo->swap_count = rfb->swap_count; 1839 sInfo->swap_ust = rfb->swap_ust; 1840 sInfo->swap_missed_count = rfb->swap_missed_count; 1841 1842 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1843 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1844 : 0.0; 1845 1846 return 0; 1847} 1848 1849const struct __DriverAPIRec driDriverAPI = { 1850 .InitScreen = radeonInitScreen, 1851 .DestroyScreen = radeonDestroyScreen, 1852#if defined(RADEON_R200) 1853 .CreateContext = r200CreateContext, 1854 .DestroyContext = r200DestroyContext, 1855#elif defined(RADEON_R600) 1856 .CreateContext = r600CreateContext, 1857 .DestroyContext = radeonDestroyContext, 1858#elif defined(RADEON_R300) 1859 .CreateContext = r300CreateContext, 1860 .DestroyContext = radeonDestroyContext, 1861#else 1862 .CreateContext = r100CreateContext, 1863 .DestroyContext = radeonDestroyContext, 1864#endif 1865 .CreateBuffer = radeonCreateBuffer, 1866 .DestroyBuffer = radeonDestroyBuffer, 1867 .SwapBuffers = radeonSwapBuffers, 1868 .MakeCurrent = radeonMakeCurrent, 1869 .UnbindContext = radeonUnbindContext, 1870 .GetSwapInfo = getSwapInfo, 1871 .GetDrawableMSC = driDrawableGetMSC32, 1872 .WaitForMSC = driWaitForMSC32, 1873 .WaitForSBC = NULL, 1874 .SwapBuffersMSC = NULL, 1875 .CopySubBuffer = radeonCopySubBuffer, 1876 /* DRI2 */ 1877 .InitScreen2 = radeonInitScreen2, 1878}; 1879 1880/* This is the table of extensions that the loader will dlsym() for. */ 1881PUBLIC const __DRIextension *__driDriverExtensions[] = { 1882 &driCoreExtension.base, 1883 &driLegacyExtension.base, 1884 &driDRI2Extension.base, 1885 NULL 1886}; 1887