radeon_screen.c revision 5ed440400573631f540701f3efd479d8c1592007 
1/**************************************************************************
2
3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4                     VA Linux Systems Inc., Fremont, California.
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining
9a copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sublicense, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial
18portions of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author  Gareth Hughes <gareth@valinux.com>
36 */
37
38#include "main/glheader.h"
39#include "main/imports.h"
40#include "main/mtypes.h"
41#include "main/framebuffer.h"
42#include "main/renderbuffer.h"
43
44#define STANDALONE_MMIO
45#include "radeon_chipset.h"
46#include "radeon_macros.h"
47#include "radeon_screen.h"
48#if !RADEON_COMMON
49#include "radeon_context.h"
50#include "radeon_span.h"
51#include "radeon_tex.h"
52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53#include "r200_context.h"
54#include "r200_ioctl.h"
55#include "r200_span.h"
56#include "r200_tex.h"
57#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58#include "r300_context.h"
59#include "r300_fragprog.h"
60#include "r300_tex.h"
61#include "radeon_span.h"
62#endif
63
64#include "utils.h"
65#include "vblank.h"
66#include "drirenderbuffer.h"
67
68#include "GL/internal/dri_interface.h"
69
70/* Radeon configuration
71 */
72#include "xmlpool.h"
73
74#if !RADEON_COMMON	/* R100 */
75PUBLIC const char __driConfigOptions[] =
76DRI_CONF_BEGIN
77    DRI_CONF_SECTION_PERFORMANCE
78        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
79        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
80        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
81        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
82        DRI_CONF_HYPERZ(false)
83    DRI_CONF_SECTION_END
84    DRI_CONF_SECTION_QUALITY
85        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
86        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
87        DRI_CONF_NO_NEG_LOD_BIAS(false)
88        DRI_CONF_FORCE_S3TC_ENABLE(false)
89        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
90        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
91        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
92        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
93    DRI_CONF_SECTION_END
94    DRI_CONF_SECTION_DEBUG
95        DRI_CONF_NO_RAST(false)
96    DRI_CONF_SECTION_END
97DRI_CONF_END;
98static const GLuint __driNConfigOptions = 14;
99
100#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
101
102PUBLIC const char __driConfigOptions[] =
103DRI_CONF_BEGIN
104    DRI_CONF_SECTION_PERFORMANCE
105        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
106        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
107        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
108        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
109        DRI_CONF_HYPERZ(false)
110    DRI_CONF_SECTION_END
111    DRI_CONF_SECTION_QUALITY
112        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
113        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
114        DRI_CONF_NO_NEG_LOD_BIAS(false)
115        DRI_CONF_FORCE_S3TC_ENABLE(false)
116        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
117        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
118        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
119        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
120        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
121    DRI_CONF_SECTION_END
122    DRI_CONF_SECTION_DEBUG
123        DRI_CONF_NO_RAST(false)
124    DRI_CONF_SECTION_END
125    DRI_CONF_SECTION_SOFTWARE
126        DRI_CONF_NV_VERTEX_PROGRAM(false)
127    DRI_CONF_SECTION_END
128DRI_CONF_END;
129static const GLuint __driNConfigOptions = 16;
130
131extern const struct dri_extension blend_extensions[];
132extern const struct dri_extension ARB_vp_extension[];
133extern const struct dri_extension NV_vp_extension[];
134extern const struct dri_extension ATI_fs_extension[];
135extern const struct dri_extension point_extensions[];
136
137#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
138
139/* TODO: integrate these into xmlpool.h! */
140#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
141DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
142        DRI_CONF_DESC(en,"Number of texture image units") \
143        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
144DRI_CONF_OPT_END
145
146#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
147DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
148        DRI_CONF_DESC(en,"Number of texture coordinate units") \
149        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
150DRI_CONF_OPT_END
151
152#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
153DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
154        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
155        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
156DRI_CONF_OPT_END
157
158#define DRI_CONF_DISABLE_S3TC(def) \
159DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
160        DRI_CONF_DESC(en,"Disable S3TC compression") \
161DRI_CONF_OPT_END
162
163#define DRI_CONF_DISABLE_FALLBACK(def) \
164DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
165        DRI_CONF_DESC(en,"Disable Low-impact fallback") \
166DRI_CONF_OPT_END
167
168#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
169DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
170        DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
171DRI_CONF_OPT_END
172
173#define DRI_CONF_FP_OPTIMIZATION(def) \
174DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
175	DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
176                DRI_CONF_ENUM(0,"Optimize for Speed") \
177                DRI_CONF_ENUM(1,"Optimize for Quality") \
178        DRI_CONF_DESC_END \
179DRI_CONF_OPT_END
180
181PUBLIC const char __driConfigOptions[] =
182DRI_CONF_BEGIN
183	DRI_CONF_SECTION_PERFORMANCE
184		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
185		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
186		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
187		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
188		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
189		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
190		DRI_CONF_DISABLE_FALLBACK(true)
191		DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
192	DRI_CONF_SECTION_END
193	DRI_CONF_SECTION_QUALITY
194		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
195		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
196		DRI_CONF_FORCE_S3TC_ENABLE(false)
197		DRI_CONF_DISABLE_S3TC(false)
198		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
199		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
200		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
201		DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
202	DRI_CONF_SECTION_END
203	DRI_CONF_SECTION_DEBUG
204		DRI_CONF_NO_RAST(false)
205	DRI_CONF_SECTION_END
206DRI_CONF_END;
207static const GLuint __driNConfigOptions = 17;
208
209extern const struct dri_extension gl_20_extension[];
210
211#ifndef RADEON_DEBUG
212int RADEON_DEBUG = 0;
213
214static const struct dri_debug_control debug_control[] = {
215	{"fall", DEBUG_FALLBACKS},
216	{"tex", DEBUG_TEXTURE},
217	{"ioctl", DEBUG_IOCTL},
218	{"prim", DEBUG_PRIMS},
219	{"vert", DEBUG_VERTS},
220	{"state", DEBUG_STATE},
221	{"code", DEBUG_CODEGEN},
222	{"vfmt", DEBUG_VFMT},
223	{"vtxf", DEBUG_VFMT},
224	{"verb", DEBUG_VERBOSE},
225	{"dri", DEBUG_DRI},
226	{"dma", DEBUG_DMA},
227	{"san", DEBUG_SANITY},
228	{"sync", DEBUG_SYNC},
229	{"pix", DEBUG_PIXEL},
230	{"mem", DEBUG_MEMORY},
231	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
232	{NULL, 0}
233};
234#endif /* RADEON_DEBUG */
235
236#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237
238extern const struct dri_extension card_extensions[];
239
240static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
241
242static int
243radeonGetParam(int fd, int param, void *value)
244{
245  int ret;
246  drm_radeon_getparam_t gp;
247
248  gp.param = param;
249  gp.value = value;
250
251  ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
252  return ret;
253}
254
255static const __DRIconfig **
256radeonFillInModes( __DRIscreenPrivate *psp,
257		   unsigned pixel_bits, unsigned depth_bits,
258		   unsigned stencil_bits, GLboolean have_back_buffer )
259{
260    __DRIconfig **configs;
261    __GLcontextModes *m;
262    unsigned depth_buffer_factor;
263    unsigned back_buffer_factor;
264    int i;
265
266    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
267     * enough to add support.  Basically, if a context is created with an
268     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
269     * will never be used.
270     */
271    static const GLenum back_buffer_modes[] = {
272	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
273    };
274
275    uint8_t depth_bits_array[2];
276    uint8_t stencil_bits_array[2];
277    uint8_t msaa_samples_array[1];
278
279    depth_bits_array[0] = depth_bits;
280    depth_bits_array[1] = depth_bits;
281
282    /* Just like with the accumulation buffer, always provide some modes
283     * with a stencil buffer.  It will be a sw fallback, but some apps won't
284     * care about that.
285     */
286    stencil_bits_array[0] = stencil_bits;
287    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
288
289    msaa_samples_array[0] = 0;
290
291    depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
292    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
293
294    if (pixel_bits == 16) {
295	__DRIconfig **configs_a8r8g8b8;
296	__DRIconfig **configs_r5g6b5;
297
298	configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
299					  depth_bits_array, stencil_bits_array,
300					  depth_buffer_factor, back_buffer_modes,
301					  back_buffer_factor, msaa_samples_array,
302					  1);
303	configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
304					    depth_bits_array, stencil_bits_array,
305					    1, back_buffer_modes, 1,
306					    msaa_samples_array, 1);
307	configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
308   } else
309	configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
310				   depth_bits_array, stencil_bits_array,
311				   depth_buffer_factor,
312				   back_buffer_modes, back_buffer_factor,
313				   msaa_samples_array, 1);
314
315    if (configs == NULL) {
316	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
317		 __func__, __LINE__ );
318	return NULL;
319    }
320
321    /* Mark the visual as slow if there are "fake" stencil bits.
322     */
323    for (i = 0; configs[i]; i++) {
324	m = &configs[i]->modes;
325	if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
326	    m->visualRating = GLX_SLOW_CONFIG;
327	}
328    }
329
330    return (const __DRIconfig **) configs;
331}
332
333#if !RADEON_COMMON
334static const __DRItexOffsetExtension radeonTexOffsetExtension = {
335    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
336    radeonSetTexOffset,
337};
338#endif
339
340#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
341static const __DRIallocateExtension r200AllocateExtension = {
342    { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
343    r200AllocateMemoryMESA,
344    r200FreeMemoryMESA,
345    r200GetMemoryOffsetMESA
346};
347
348static const __DRItexOffsetExtension r200texOffsetExtension = {
349    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
350   r200SetTexOffset,
351};
352#endif
353
354#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
355static const __DRItexOffsetExtension r300texOffsetExtension = {
356    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
357   r300SetTexOffset,
358};
359#endif
360
361/* Create the device specific screen private data struct.
362 */
363static radeonScreenPtr
364radeonCreateScreen( __DRIscreenPrivate *sPriv )
365{
366   radeonScreenPtr screen;
367   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
368   unsigned char *RADEONMMIO;
369   int i;
370   int ret;
371   uint32_t temp = 0;
372
373   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
374      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
375      return GL_FALSE;
376   }
377
378   /* Allocate the private area */
379   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
380   if ( !screen ) {
381      __driUtilMessage("%s: Could not allocate memory for screen structure",
382		       __FUNCTION__);
383      return NULL;
384   }
385
386#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
387	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
388#endif
389
390   /* parse information in __driConfigOptions */
391   driParseOptionInfo (&screen->optionCache,
392		       __driConfigOptions, __driNConfigOptions);
393
394   /* This is first since which regions we map depends on whether or
395    * not we are using a PCI card.
396    */
397   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
398   {
399      int ret;
400      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
401			    &screen->gart_buffer_offset);
402
403      if (ret) {
404	 FREE( screen );
405	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
406	 return NULL;
407      }
408
409      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
410			    &screen->gart_base);
411      if (ret) {
412	 FREE( screen );
413	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
414	 return NULL;
415      }
416
417      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
418			    &screen->irq);
419      if (ret) {
420	 FREE( screen );
421	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
422	 return NULL;
423      }
424      screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
425      screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
426      screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
427      screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
428      screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
429      screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
430      screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
431   }
432
433   screen->mmio.handle = dri_priv->registerHandle;
434   screen->mmio.size   = dri_priv->registerSize;
435   if ( drmMap( sPriv->fd,
436		screen->mmio.handle,
437		screen->mmio.size,
438		&screen->mmio.map ) ) {
439      FREE( screen );
440      __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
441      return NULL;
442   }
443
444   RADEONMMIO = screen->mmio.map;
445
446   screen->status.handle = dri_priv->statusHandle;
447   screen->status.size   = dri_priv->statusSize;
448   if ( drmMap( sPriv->fd,
449		screen->status.handle,
450		screen->status.size,
451		&screen->status.map ) ) {
452      drmUnmap( screen->mmio.map, screen->mmio.size );
453      FREE( screen );
454      __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
455      return NULL;
456   }
457   screen->scratch = (__volatile__ uint32_t *)
458      ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
459
460   screen->buffers = drmMapBufs( sPriv->fd );
461   if ( !screen->buffers ) {
462      drmUnmap( screen->status.map, screen->status.size );
463      drmUnmap( screen->mmio.map, screen->mmio.size );
464      FREE( screen );
465      __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
466      return NULL;
467   }
468
469   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
470      screen->gartTextures.handle = dri_priv->gartTexHandle;
471      screen->gartTextures.size   = dri_priv->gartTexMapSize;
472      if ( drmMap( sPriv->fd,
473		   screen->gartTextures.handle,
474		   screen->gartTextures.size,
475		   (drmAddressPtr)&screen->gartTextures.map ) ) {
476	 drmUnmapBufs( screen->buffers );
477	 drmUnmap( screen->status.map, screen->status.size );
478	 drmUnmap( screen->mmio.map, screen->mmio.size );
479	 FREE( screen );
480	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
481	 return NULL;
482      }
483
484      screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
485   }
486
487   screen->chip_flags = 0;
488   /* XXX: add more chipsets */
489   switch ( dri_priv->deviceID ) {
490   case PCI_CHIP_RADEON_LY:
491   case PCI_CHIP_RADEON_LZ:
492   case PCI_CHIP_RADEON_QY:
493   case PCI_CHIP_RADEON_QZ:
494   case PCI_CHIP_RN50_515E:
495   case PCI_CHIP_RN50_5969:
496      screen->chip_family = CHIP_FAMILY_RV100;
497      break;
498
499   case PCI_CHIP_RS100_4136:
500   case PCI_CHIP_RS100_4336:
501      screen->chip_family = CHIP_FAMILY_RS100;
502      break;
503
504   case PCI_CHIP_RS200_4137:
505   case PCI_CHIP_RS200_4337:
506   case PCI_CHIP_RS250_4237:
507   case PCI_CHIP_RS250_4437:
508      screen->chip_family = CHIP_FAMILY_RS200;
509      break;
510
511   case PCI_CHIP_RADEON_QD:
512   case PCI_CHIP_RADEON_QE:
513   case PCI_CHIP_RADEON_QF:
514   case PCI_CHIP_RADEON_QG:
515      /* all original radeons (7200) presumably have a stencil op bug */
516      screen->chip_family = CHIP_FAMILY_R100;
517      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
518      break;
519
520   case PCI_CHIP_RV200_QW:
521   case PCI_CHIP_RV200_QX:
522   case PCI_CHIP_RADEON_LW:
523   case PCI_CHIP_RADEON_LX:
524      screen->chip_family = CHIP_FAMILY_RV200;
525      screen->chip_flags = RADEON_CHIPSET_TCL;
526      break;
527
528   case PCI_CHIP_R200_BB:
529   case PCI_CHIP_R200_BC:
530   case PCI_CHIP_R200_QH:
531   case PCI_CHIP_R200_QL:
532   case PCI_CHIP_R200_QM:
533      screen->chip_family = CHIP_FAMILY_R200;
534      screen->chip_flags = RADEON_CHIPSET_TCL;
535      break;
536
537   case PCI_CHIP_RV250_If:
538   case PCI_CHIP_RV250_Ig:
539   case PCI_CHIP_RV250_Ld:
540   case PCI_CHIP_RV250_Lf:
541   case PCI_CHIP_RV250_Lg:
542      screen->chip_family = CHIP_FAMILY_RV250;
543      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
544      break;
545
546   case PCI_CHIP_RV280_5960:
547   case PCI_CHIP_RV280_5961:
548   case PCI_CHIP_RV280_5962:
549   case PCI_CHIP_RV280_5964:
550   case PCI_CHIP_RV280_5965:
551   case PCI_CHIP_RV280_5C61:
552   case PCI_CHIP_RV280_5C63:
553      screen->chip_family = CHIP_FAMILY_RV280;
554      screen->chip_flags = RADEON_CHIPSET_TCL;
555      break;
556
557   case PCI_CHIP_RS300_5834:
558   case PCI_CHIP_RS300_5835:
559   case PCI_CHIP_RS350_7834:
560   case PCI_CHIP_RS350_7835:
561      screen->chip_family = CHIP_FAMILY_RS300;
562      break;
563
564
565   case PCI_CHIP_R300_AD:
566   case PCI_CHIP_R300_AE:
567   case PCI_CHIP_R300_AF:
568   case PCI_CHIP_R300_AG:
569   case PCI_CHIP_R300_ND:
570   case PCI_CHIP_R300_NE:
571   case PCI_CHIP_R300_NF:
572   case PCI_CHIP_R300_NG:
573      screen->chip_family = CHIP_FAMILY_R300;
574      screen->chip_flags = RADEON_CHIPSET_TCL;
575      break;
576
577   case PCI_CHIP_RV350_AP:
578   case PCI_CHIP_RV350_AQ:
579   case PCI_CHIP_RV350_AR:
580   case PCI_CHIP_RV350_AS:
581   case PCI_CHIP_RV350_AT:
582   case PCI_CHIP_RV350_AV:
583   case PCI_CHIP_RV350_AU:
584   case PCI_CHIP_RV350_NP:
585   case PCI_CHIP_RV350_NQ:
586   case PCI_CHIP_RV350_NR:
587   case PCI_CHIP_RV350_NS:
588   case PCI_CHIP_RV350_NT:
589   case PCI_CHIP_RV350_NV:
590      screen->chip_family = CHIP_FAMILY_RV350;
591      screen->chip_flags = RADEON_CHIPSET_TCL;
592      break;
593
594   case PCI_CHIP_R350_AH:
595   case PCI_CHIP_R350_AI:
596   case PCI_CHIP_R350_AJ:
597   case PCI_CHIP_R350_AK:
598   case PCI_CHIP_R350_NH:
599   case PCI_CHIP_R350_NI:
600   case PCI_CHIP_R360_NJ:
601   case PCI_CHIP_R350_NK:
602      screen->chip_family = CHIP_FAMILY_R350;
603      screen->chip_flags = RADEON_CHIPSET_TCL;
604      break;
605
606   case PCI_CHIP_RV370_5460:
607   case PCI_CHIP_RV370_5462:
608   case PCI_CHIP_RV370_5464:
609   case PCI_CHIP_RV370_5B60:
610   case PCI_CHIP_RV370_5B62:
611   case PCI_CHIP_RV370_5B63:
612   case PCI_CHIP_RV370_5B64:
613   case PCI_CHIP_RV370_5B65:
614   case PCI_CHIP_RV380_3150:
615   case PCI_CHIP_RV380_3152:
616   case PCI_CHIP_RV380_3154:
617   case PCI_CHIP_RV380_3E50:
618   case PCI_CHIP_RV380_3E54:
619      screen->chip_family = CHIP_FAMILY_RV380;
620      screen->chip_flags = RADEON_CHIPSET_TCL;
621      break;
622
623   case PCI_CHIP_R420_JN:
624   case PCI_CHIP_R420_JH:
625   case PCI_CHIP_R420_JI:
626   case PCI_CHIP_R420_JJ:
627   case PCI_CHIP_R420_JK:
628   case PCI_CHIP_R420_JL:
629   case PCI_CHIP_R420_JM:
630   case PCI_CHIP_R420_JO:
631   case PCI_CHIP_R420_JP:
632   case PCI_CHIP_R420_JT:
633   case PCI_CHIP_R481_4B49:
634   case PCI_CHIP_R481_4B4A:
635   case PCI_CHIP_R481_4B4B:
636   case PCI_CHIP_R481_4B4C:
637   case PCI_CHIP_R423_UH:
638   case PCI_CHIP_R423_UI:
639   case PCI_CHIP_R423_UJ:
640   case PCI_CHIP_R423_UK:
641   case PCI_CHIP_R430_554C:
642   case PCI_CHIP_R430_554D:
643   case PCI_CHIP_R430_554E:
644   case PCI_CHIP_R430_554F:
645   case PCI_CHIP_R423_5550:
646   case PCI_CHIP_R423_UQ:
647   case PCI_CHIP_R423_UR:
648   case PCI_CHIP_R423_UT:
649   case PCI_CHIP_R430_5D48:
650   case PCI_CHIP_R430_5D49:
651   case PCI_CHIP_R430_5D4A:
652   case PCI_CHIP_R480_5D4C:
653   case PCI_CHIP_R480_5D4D:
654   case PCI_CHIP_R480_5D4E:
655   case PCI_CHIP_R480_5D4F:
656   case PCI_CHIP_R480_5D50:
657   case PCI_CHIP_R480_5D52:
658   case PCI_CHIP_R423_5D57:
659      screen->chip_family = CHIP_FAMILY_R420;
660      screen->chip_flags = RADEON_CHIPSET_TCL;
661      break;
662
663   case PCI_CHIP_RV410_5E4C:
664   case PCI_CHIP_RV410_5E4F:
665   case PCI_CHIP_RV410_564A:
666   case PCI_CHIP_RV410_564B:
667   case PCI_CHIP_RV410_564F:
668   case PCI_CHIP_RV410_5652:
669   case PCI_CHIP_RV410_5653:
670   case PCI_CHIP_RV410_5657:
671   case PCI_CHIP_RV410_5E48:
672   case PCI_CHIP_RV410_5E4A:
673   case PCI_CHIP_RV410_5E4B:
674   case PCI_CHIP_RV410_5E4D:
675      screen->chip_family = CHIP_FAMILY_RV410;
676      screen->chip_flags = RADEON_CHIPSET_TCL;
677      break;
678
679   case PCI_CHIP_RS480_5954:
680   case PCI_CHIP_RS480_5955:
681   case PCI_CHIP_RS482_5974:
682   case PCI_CHIP_RS482_5975:
683   case PCI_CHIP_RS400_5A41:
684   case PCI_CHIP_RS400_5A42:
685   case PCI_CHIP_RC410_5A61:
686   case PCI_CHIP_RC410_5A62:
687      screen->chip_family = CHIP_FAMILY_RS400;
688      break;
689
690   case PCI_CHIP_RS600_793F:
691   case PCI_CHIP_RS600_7941:
692   case PCI_CHIP_RS600_7942:
693      screen->chip_family = CHIP_FAMILY_RS600;
694      break;
695
696   case PCI_CHIP_RS690_791E:
697   case PCI_CHIP_RS690_791F:
698      screen->chip_family = CHIP_FAMILY_RS690;
699      break;
700   case PCI_CHIP_RS740_796C:
701   case PCI_CHIP_RS740_796D:
702   case PCI_CHIP_RS740_796E:
703   case PCI_CHIP_RS740_796F:
704      screen->chip_family = CHIP_FAMILY_RS740;
705      break;
706
707   case PCI_CHIP_R520_7100:
708   case PCI_CHIP_R520_7101:
709   case PCI_CHIP_R520_7102:
710   case PCI_CHIP_R520_7103:
711   case PCI_CHIP_R520_7104:
712   case PCI_CHIP_R520_7105:
713   case PCI_CHIP_R520_7106:
714   case PCI_CHIP_R520_7108:
715   case PCI_CHIP_R520_7109:
716   case PCI_CHIP_R520_710A:
717   case PCI_CHIP_R520_710B:
718   case PCI_CHIP_R520_710C:
719   case PCI_CHIP_R520_710E:
720   case PCI_CHIP_R520_710F:
721      screen->chip_family = CHIP_FAMILY_R520;
722      screen->chip_flags = RADEON_CHIPSET_TCL;
723      break;
724
725   case PCI_CHIP_RV515_7140:
726   case PCI_CHIP_RV515_7141:
727   case PCI_CHIP_RV515_7142:
728   case PCI_CHIP_RV515_7143:
729   case PCI_CHIP_RV515_7144:
730   case PCI_CHIP_RV515_7145:
731   case PCI_CHIP_RV515_7146:
732   case PCI_CHIP_RV515_7147:
733   case PCI_CHIP_RV515_7149:
734   case PCI_CHIP_RV515_714A:
735   case PCI_CHIP_RV515_714B:
736   case PCI_CHIP_RV515_714C:
737   case PCI_CHIP_RV515_714D:
738   case PCI_CHIP_RV515_714E:
739   case PCI_CHIP_RV515_714F:
740   case PCI_CHIP_RV515_7151:
741   case PCI_CHIP_RV515_7152:
742   case PCI_CHIP_RV515_7153:
743   case PCI_CHIP_RV515_715E:
744   case PCI_CHIP_RV515_715F:
745   case PCI_CHIP_RV515_7180:
746   case PCI_CHIP_RV515_7181:
747   case PCI_CHIP_RV515_7183:
748   case PCI_CHIP_RV515_7186:
749   case PCI_CHIP_RV515_7187:
750   case PCI_CHIP_RV515_7188:
751   case PCI_CHIP_RV515_718A:
752   case PCI_CHIP_RV515_718B:
753   case PCI_CHIP_RV515_718C:
754   case PCI_CHIP_RV515_718D:
755   case PCI_CHIP_RV515_718F:
756   case PCI_CHIP_RV515_7193:
757   case PCI_CHIP_RV515_7196:
758   case PCI_CHIP_RV515_719B:
759   case PCI_CHIP_RV515_719F:
760   case PCI_CHIP_RV515_7200:
761   case PCI_CHIP_RV515_7210:
762   case PCI_CHIP_RV515_7211:
763      screen->chip_family = CHIP_FAMILY_RV515;
764      screen->chip_flags = RADEON_CHIPSET_TCL;
765      break;
766
767   case PCI_CHIP_RV530_71C0:
768   case PCI_CHIP_RV530_71C1:
769   case PCI_CHIP_RV530_71C2:
770   case PCI_CHIP_RV530_71C3:
771   case PCI_CHIP_RV530_71C4:
772   case PCI_CHIP_RV530_71C5:
773   case PCI_CHIP_RV530_71C6:
774   case PCI_CHIP_RV530_71C7:
775   case PCI_CHIP_RV530_71CD:
776   case PCI_CHIP_RV530_71CE:
777   case PCI_CHIP_RV530_71D2:
778   case PCI_CHIP_RV530_71D4:
779   case PCI_CHIP_RV530_71D5:
780   case PCI_CHIP_RV530_71D6:
781   case PCI_CHIP_RV530_71DA:
782   case PCI_CHIP_RV530_71DE:
783      screen->chip_family = CHIP_FAMILY_RV530;
784      screen->chip_flags = RADEON_CHIPSET_TCL;
785      break;
786
787   case PCI_CHIP_R580_7240:
788   case PCI_CHIP_R580_7243:
789   case PCI_CHIP_R580_7244:
790   case PCI_CHIP_R580_7245:
791   case PCI_CHIP_R580_7246:
792   case PCI_CHIP_R580_7247:
793   case PCI_CHIP_R580_7248:
794   case PCI_CHIP_R580_7249:
795   case PCI_CHIP_R580_724A:
796   case PCI_CHIP_R580_724B:
797   case PCI_CHIP_R580_724C:
798   case PCI_CHIP_R580_724D:
799   case PCI_CHIP_R580_724E:
800   case PCI_CHIP_R580_724F:
801   case PCI_CHIP_R580_7284:
802      screen->chip_family = CHIP_FAMILY_R580;
803      screen->chip_flags = RADEON_CHIPSET_TCL;
804      break;
805
806   case PCI_CHIP_RV570_7280:
807   case PCI_CHIP_RV560_7281:
808   case PCI_CHIP_RV560_7283:
809   case PCI_CHIP_RV560_7287:
810   case PCI_CHIP_RV570_7288:
811   case PCI_CHIP_RV570_7289:
812   case PCI_CHIP_RV570_728B:
813   case PCI_CHIP_RV570_728C:
814   case PCI_CHIP_RV560_7290:
815   case PCI_CHIP_RV560_7291:
816   case PCI_CHIP_RV560_7293:
817   case PCI_CHIP_RV560_7297:
818      screen->chip_family = CHIP_FAMILY_RV560;
819      screen->chip_flags = RADEON_CHIPSET_TCL;
820      break;
821
822   default:
823      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
824	      dri_priv->deviceID);
825      return NULL;
826   }
827   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
828       sPriv->ddx_version.minor < 2) {
829      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
830      return NULL;
831   }
832
833   if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
834      fprintf(stderr, "R500 support requires a newer drm.\n");
835      return NULL;
836   }
837
838   if (getenv("R300_NO_TCL"))
839     screen->chip_flags &= ~RADEON_CHIPSET_TCL;
840
841   if (screen->chip_family <= CHIP_FAMILY_RS200)
842      screen->chip_flags |= RADEON_CLASS_R100;
843   else if (screen->chip_family <= CHIP_FAMILY_RV280)
844      screen->chip_flags |= RADEON_CLASS_R200;
845   else
846      screen->chip_flags |= RADEON_CLASS_R300;
847
848   screen->cpp = dri_priv->bpp / 8;
849   screen->AGPMode = dri_priv->AGPMode;
850
851   ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
852                         &temp);
853   if (ret) {
854       if (screen->chip_family < CHIP_FAMILY_RS600)
855	   screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
856       else {
857           FREE( screen );
858           fprintf(stderr, "Unable to get fb location need newer drm\n");
859           return NULL;
860       }
861   } else {
862       screen->fbLocation = (temp & 0xffff) << 16;
863   }
864
865   if (screen->chip_family >= CHIP_FAMILY_R300) {
866       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
867			     &temp);
868       if (ret) {
869	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
870	   switch (screen->chip_family) {
871	   case CHIP_FAMILY_R300:
872	   case CHIP_FAMILY_R350:
873	       screen->num_gb_pipes = 2;
874	       break;
875	   case CHIP_FAMILY_R420:
876	   case CHIP_FAMILY_R520:
877	   case CHIP_FAMILY_R580:
878	   case CHIP_FAMILY_RV560:
879	   case CHIP_FAMILY_RV570:
880	       screen->num_gb_pipes = 4;
881	       break;
882	   case CHIP_FAMILY_RV350:
883	   case CHIP_FAMILY_RV515:
884	   case CHIP_FAMILY_RV530:
885	   case CHIP_FAMILY_RV410:
886	   default:
887	       screen->num_gb_pipes = 1;
888	       break;
889	   }
890       } else {
891	   screen->num_gb_pipes = temp;
892       }
893
894       /* pipe overrides */
895       switch (dri_priv->deviceID) {
896       case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
897       case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
898       case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
899	   screen->num_gb_pipes = 1;
900	   break;
901       default:
902	   break;
903       }
904
905   }
906
907   if ( sPriv->drm_version.minor >= 10 ) {
908      drm_radeon_setparam_t sp;
909
910      sp.param = RADEON_SETPARAM_FB_LOCATION;
911      sp.value = screen->fbLocation;
912
913      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
914		       &sp, sizeof( sp ) );
915   }
916
917   screen->frontOffset	= dri_priv->frontOffset;
918   screen->frontPitch	= dri_priv->frontPitch;
919   screen->backOffset	= dri_priv->backOffset;
920   screen->backPitch	= dri_priv->backPitch;
921   screen->depthOffset	= dri_priv->depthOffset;
922   screen->depthPitch	= dri_priv->depthPitch;
923
924   /* Check if ddx has set up a surface reg to cover depth buffer */
925   screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
926      /* these chips don't use tiled z without hyperz. So always pretend
927         we have set up a surface which will cause linear reads/writes */
928      (IS_R100_CLASS(screen) &&
929      !(screen->chip_flags & RADEON_CHIPSET_TCL));
930
931   if ( dri_priv->textureSize == 0 ) {
932      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
933      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
934      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
935	 dri_priv->log2GARTTexGran;
936   } else {
937      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
938				               + screen->fbLocation;
939      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
940      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
941	 dri_priv->log2TexGran;
942   }
943
944   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
945	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
946      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
947      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
948      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
949      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
950   } else {
951      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
952      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
953      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
954      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
955	 dri_priv->log2GARTTexGran;
956   }
957
958   i = 0;
959   screen->extensions[i++] = &driCopySubBufferExtension.base;
960   screen->extensions[i++] = &driFrameTrackingExtension.base;
961   screen->extensions[i++] = &driReadDrawableExtension;
962
963   if ( screen->irq != 0 ) {
964       screen->extensions[i++] = &driSwapControlExtension.base;
965       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
966   }
967
968#if !RADEON_COMMON
969   screen->extensions[i++] = &radeonTexOffsetExtension.base;
970#endif
971
972#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
973   if (IS_R200_CLASS(screen))
974       screen->extensions[i++] = &r200AllocateExtension.base;
975
976   screen->extensions[i++] = &r200texOffsetExtension.base;
977#endif
978
979#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
980   screen->extensions[i++] = &r300texOffsetExtension.base;
981#endif
982
983   screen->extensions[i++] = NULL;
984   sPriv->extensions = screen->extensions;
985
986   screen->driScreen = sPriv;
987   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
988   return screen;
989}
990
991/* Destroy the device specific screen private data struct.
992 */
993static void
994radeonDestroyScreen( __DRIscreenPrivate *sPriv )
995{
996   radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
997
998   if (!screen)
999      return;
1000
1001   if ( screen->gartTextures.map ) {
1002      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1003   }
1004   drmUnmapBufs( screen->buffers );
1005   drmUnmap( screen->status.map, screen->status.size );
1006   drmUnmap( screen->mmio.map, screen->mmio.size );
1007
1008   /* free all option information */
1009   driDestroyOptionInfo (&screen->optionCache);
1010
1011   FREE( screen );
1012   sPriv->private = NULL;
1013}
1014
1015
1016/* Initialize the driver specific screen private data.
1017 */
1018static GLboolean
1019radeonInitDriver( __DRIscreenPrivate *sPriv )
1020{
1021   sPriv->private = (void *) radeonCreateScreen( sPriv );
1022   if ( !sPriv->private ) {
1023      radeonDestroyScreen( sPriv );
1024      return GL_FALSE;
1025   }
1026
1027   return GL_TRUE;
1028}
1029
1030
1031/**
1032 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1033 *
1034 * \todo This function (and its interface) will need to be updated to support
1035 * pbuffers.
1036 */
1037static GLboolean
1038radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1039                    __DRIdrawablePrivate *driDrawPriv,
1040                    const __GLcontextModes *mesaVis,
1041                    GLboolean isPixmap )
1042{
1043   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1044
1045   if (isPixmap) {
1046      return GL_FALSE; /* not implemented */
1047   }
1048   else {
1049      const GLboolean swDepth = GL_FALSE;
1050      const GLboolean swAlpha = GL_FALSE;
1051      const GLboolean swAccum = mesaVis->accumRedBits > 0;
1052      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1053         mesaVis->depthBits != 24;
1054      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1055
1056      /* front color renderbuffer */
1057      {
1058         driRenderbuffer *frontRb
1059            = driNewRenderbuffer(GL_RGBA,
1060                                 driScrnPriv->pFB + screen->frontOffset,
1061                                 screen->cpp,
1062                                 screen->frontOffset, screen->frontPitch,
1063                                 driDrawPriv);
1064         radeonSetSpanFunctions(frontRb, mesaVis);
1065         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1066      }
1067
1068      /* back color renderbuffer */
1069      if (mesaVis->doubleBufferMode) {
1070         driRenderbuffer *backRb
1071            = driNewRenderbuffer(GL_RGBA,
1072                                 driScrnPriv->pFB + screen->backOffset,
1073                                 screen->cpp,
1074                                 screen->backOffset, screen->backPitch,
1075                                 driDrawPriv);
1076         radeonSetSpanFunctions(backRb, mesaVis);
1077         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1078      }
1079
1080      /* depth renderbuffer */
1081      if (mesaVis->depthBits == 16) {
1082         driRenderbuffer *depthRb
1083            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1084                                 driScrnPriv->pFB + screen->depthOffset,
1085                                 screen->cpp,
1086                                 screen->depthOffset, screen->depthPitch,
1087                                 driDrawPriv);
1088         radeonSetSpanFunctions(depthRb, mesaVis);
1089         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1090	 depthRb->depthHasSurface = screen->depthHasSurface;
1091      }
1092      else if (mesaVis->depthBits == 24) {
1093         driRenderbuffer *depthRb
1094            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1095                                 driScrnPriv->pFB + screen->depthOffset,
1096                                 screen->cpp,
1097                                 screen->depthOffset, screen->depthPitch,
1098                                 driDrawPriv);
1099         radeonSetSpanFunctions(depthRb, mesaVis);
1100         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1101	 depthRb->depthHasSurface = screen->depthHasSurface;
1102      }
1103
1104      /* stencil renderbuffer */
1105      if (mesaVis->stencilBits > 0 && !swStencil) {
1106         driRenderbuffer *stencilRb
1107            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1108                                 driScrnPriv->pFB + screen->depthOffset,
1109                                 screen->cpp,
1110                                 screen->depthOffset, screen->depthPitch,
1111                                 driDrawPriv);
1112         radeonSetSpanFunctions(stencilRb, mesaVis);
1113         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1114	 stencilRb->depthHasSurface = screen->depthHasSurface;
1115      }
1116
1117      _mesa_add_soft_renderbuffers(fb,
1118                                   GL_FALSE, /* color */
1119                                   swDepth,
1120                                   swStencil,
1121                                   swAccum,
1122                                   swAlpha,
1123                                   GL_FALSE /* aux */);
1124      driDrawPriv->driverPrivate = (void *) fb;
1125
1126      return (driDrawPriv->driverPrivate != NULL);
1127   }
1128}
1129
1130
1131static void
1132radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1133{
1134   _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1135}
1136
1137#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1138/**
1139 * Choose the appropriate CreateContext function based on the chipset.
1140 * Eventually, all drivers will go through this process.
1141 */
1142static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1143				     __DRIcontextPrivate * driContextPriv,
1144				     void *sharedContextPriv)
1145{
1146	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1147	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1148
1149	if (IS_R300_CLASS(screen))
1150		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1151        return GL_FALSE;
1152}
1153
1154/**
1155 * Choose the appropriate DestroyContext function based on the chipset.
1156 */
1157static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1158{
1159	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1160
1161	if (IS_R300_CLASS(radeon->radeonScreen))
1162		return r300DestroyContext(driContextPriv);
1163}
1164
1165
1166#endif
1167
1168
1169/**
1170 * This is the driver specific part of the createNewScreen entry point.
1171 *
1172 * \todo maybe fold this into intelInitDriver
1173 *
1174 * \return the __GLcontextModes supported by this driver
1175 */
1176static const __DRIconfig **
1177radeonInitScreen(__DRIscreenPrivate *psp)
1178{
1179#if !RADEON_COMMON
1180   static const char *driver_name = "Radeon";
1181   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1182   static const __DRIversion dri_expected = { 4, 0, 0 };
1183   static const __DRIversion drm_expected = { 1, 6, 0 };
1184#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1185   static const char *driver_name = "R200";
1186   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1187   static const __DRIversion dri_expected = { 4, 0, 0 };
1188   static const __DRIversion drm_expected = { 1, 6, 0 };
1189#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1190   static const char *driver_name = "R300";
1191   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1192   static const __DRIversion dri_expected = { 4, 0, 0 };
1193   static const __DRIversion drm_expected = { 1, 24, 0 };
1194#endif
1195   RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1196
1197   if ( ! driCheckDriDdxDrmVersions3( driver_name,
1198				      &psp->dri_version, & dri_expected,
1199				      &psp->ddx_version, & ddx_expected,
1200				      &psp->drm_version, & drm_expected ) ) {
1201      return NULL;
1202   }
1203
1204   /* Calling driInitExtensions here, with a NULL context pointer,
1205    * does not actually enable the extensions.  It just makes sure
1206    * that all the dispatch offsets for all the extensions that
1207    * *might* be enables are known.  This is needed because the
1208    * dispatch offsets need to be known when _mesa_context_create
1209    * is called, but we can't enable the extensions until we have a
1210    * context pointer.
1211    *
1212    * Hello chicken.  Hello egg.  How are you two today?
1213    */
1214   driInitExtensions( NULL, card_extensions, GL_FALSE );
1215#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1216   driInitExtensions( NULL, blend_extensions, GL_FALSE );
1217   driInitSingleExtension( NULL, ARB_vp_extension );
1218   driInitSingleExtension( NULL, NV_vp_extension );
1219   driInitSingleExtension( NULL, ATI_fs_extension );
1220   driInitExtensions( NULL, point_extensions, GL_FALSE );
1221#elif defined(RADEON_COMMON_FOR_R300)
1222   driInitSingleExtension( NULL, gl_20_extension );
1223#endif
1224
1225   if (!radeonInitDriver(psp))
1226       return NULL;
1227
1228   return radeonFillInModes( psp,
1229			     dri_priv->bpp,
1230			     (dri_priv->bpp == 16) ? 16 : 24,
1231			     (dri_priv->bpp == 16) ? 0  : 8,
1232			     (dri_priv->backOffset != dri_priv->depthOffset) );
1233}
1234
1235
1236/**
1237 * Get information about previous buffer swaps.
1238 */
1239static int
1240getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1241{
1242#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1243   radeonContextPtr  rmesa;
1244#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1245   r200ContextPtr  rmesa;
1246#endif
1247
1248   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1249	|| (dPriv->driContextPriv->driverPrivate == NULL)
1250	|| (sInfo == NULL) ) {
1251      return -1;
1252   }
1253
1254   rmesa = dPriv->driContextPriv->driverPrivate;
1255   sInfo->swap_count = rmesa->swap_count;
1256   sInfo->swap_ust = rmesa->swap_ust;
1257   sInfo->swap_missed_count = rmesa->swap_missed_count;
1258
1259   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1260       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1261       : 0.0;
1262
1263   return 0;
1264}
1265
1266#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1267const struct __DriverAPIRec driDriverAPI = {
1268   .InitScreen      = radeonInitScreen,
1269   .DestroyScreen   = radeonDestroyScreen,
1270   .CreateContext   = radeonCreateContext,
1271   .DestroyContext  = radeonDestroyContext,
1272   .CreateBuffer    = radeonCreateBuffer,
1273   .DestroyBuffer   = radeonDestroyBuffer,
1274   .SwapBuffers     = radeonSwapBuffers,
1275   .MakeCurrent     = radeonMakeCurrent,
1276   .UnbindContext   = radeonUnbindContext,
1277   .GetSwapInfo     = getSwapInfo,
1278   .GetDrawableMSC  = driDrawableGetMSC32,
1279   .WaitForMSC      = driWaitForMSC32,
1280   .WaitForSBC      = NULL,
1281   .SwapBuffersMSC  = NULL,
1282   .CopySubBuffer   = radeonCopySubBuffer,
1283};
1284#else
1285const struct __DriverAPIRec driDriverAPI = {
1286   .InitScreen      = radeonInitScreen,
1287   .DestroyScreen   = radeonDestroyScreen,
1288   .CreateContext   = r200CreateContext,
1289   .DestroyContext  = r200DestroyContext,
1290   .CreateBuffer    = radeonCreateBuffer,
1291   .DestroyBuffer   = radeonDestroyBuffer,
1292   .SwapBuffers     = r200SwapBuffers,
1293   .MakeCurrent     = r200MakeCurrent,
1294   .UnbindContext   = r200UnbindContext,
1295   .GetSwapInfo     = getSwapInfo,
1296   .GetDrawableMSC  = driDrawableGetMSC32,
1297   .WaitForMSC      = driWaitForMSC32,
1298   .WaitForSBC      = NULL,
1299   .SwapBuffersMSC  = NULL,
1300   .CopySubBuffer   = r200CopySubBuffer,
1301};
1302#endif
1303