radeon_screen.c revision 6652dc8aac79265190efa0a90ebadab8831c6cca 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author  Gareth Hughes <gareth@valinux.com>
37 */
38
39#include "glheader.h"
40#include "imports.h"
41#include "mtypes.h"
42#include "framebuffer.h"
43#include "renderbuffer.h"
44
45#define STANDALONE_MMIO
46#include "radeon_chipset.h"
47#include "radeon_macros.h"
48#include "radeon_screen.h"
49#if !RADEON_COMMON
50#include "radeon_context.h"
51#include "radeon_span.h"
52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53#include "r200_context.h"
54#include "r200_ioctl.h"
55#include "r200_span.h"
56#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57#include "r300_context.h"
58#include "radeon_span.h"
59#endif
60
61#include "utils.h"
62#include "context.h"
63#include "vblank.h"
64#include "drirenderbuffer.h"
65
66#include "GL/internal/dri_interface.h"
67
68/* Radeon configuration
69 */
70#include "xmlpool.h"
71
72#if !RADEON_COMMON	/* R100 */
73PUBLIC const char __driConfigOptions[] =
74DRI_CONF_BEGIN
75    DRI_CONF_SECTION_PERFORMANCE
76        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
77        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
78        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
79        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
80        DRI_CONF_HYPERZ(false)
81    DRI_CONF_SECTION_END
82    DRI_CONF_SECTION_QUALITY
83        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
84        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
85        DRI_CONF_NO_NEG_LOD_BIAS(false)
86        DRI_CONF_FORCE_S3TC_ENABLE(false)
87        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
88        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
89        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
90        DRI_CONF_ALLOW_LARGE_TEXTURES(1)
91    DRI_CONF_SECTION_END
92    DRI_CONF_SECTION_DEBUG
93        DRI_CONF_NO_RAST(false)
94    DRI_CONF_SECTION_END
95DRI_CONF_END;
96static const GLuint __driNConfigOptions = 14;
97
98#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
99
100PUBLIC const char __driConfigOptions[] =
101DRI_CONF_BEGIN
102    DRI_CONF_SECTION_PERFORMANCE
103        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
104        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
105        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
106        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
107        DRI_CONF_HYPERZ(false)
108    DRI_CONF_SECTION_END
109    DRI_CONF_SECTION_QUALITY
110        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
111        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
112        DRI_CONF_NO_NEG_LOD_BIAS(false)
113        DRI_CONF_FORCE_S3TC_ENABLE(false)
114        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
115        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
116        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
117        DRI_CONF_ALLOW_LARGE_TEXTURES(1)
118        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
119    DRI_CONF_SECTION_END
120    DRI_CONF_SECTION_DEBUG
121        DRI_CONF_NO_RAST(false)
122    DRI_CONF_SECTION_END
123    DRI_CONF_SECTION_SOFTWARE
124        DRI_CONF_ARB_VERTEX_PROGRAM(false)
125        DRI_CONF_NV_VERTEX_PROGRAM(false)
126    DRI_CONF_SECTION_END
127DRI_CONF_END;
128static const GLuint __driNConfigOptions = 17;
129
130extern const struct dri_extension blend_extensions[];
131extern const struct dri_extension ARB_vp_extension[];
132extern const struct dri_extension NV_vp_extension[];
133extern const struct dri_extension ATI_fs_extension[];
134
135#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
136
137/* TODO: integrate these into xmlpool.h! */
138#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
139DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
140        DRI_CONF_DESC(en,"Number of texture image units") \
141        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
142DRI_CONF_OPT_END
143
144#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
145DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
146        DRI_CONF_DESC(en,"Number of texture coordinate units") \
147        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
148DRI_CONF_OPT_END
149
150#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
151DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
152        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
153        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
154DRI_CONF_OPT_END
155
156const char __driConfigOptions[] =
157DRI_CONF_BEGIN
158	DRI_CONF_SECTION_PERFORMANCE
159		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
160		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
161		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
162		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(16, 2, 16)
163		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
164		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
165	DRI_CONF_SECTION_END
166	DRI_CONF_SECTION_QUALITY
167		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
168		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
169		DRI_CONF_NO_NEG_LOD_BIAS(false)
170                DRI_CONF_FORCE_S3TC_ENABLE(false)
171		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
172		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
173		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
174	DRI_CONF_SECTION_END
175	DRI_CONF_SECTION_DEBUG
176		DRI_CONF_NO_RAST(false)
177	DRI_CONF_SECTION_END
178DRI_CONF_END;
179static const GLuint __driNConfigOptions = 14;
180
181#ifndef RADEON_DEBUG
182int RADEON_DEBUG = 0;
183
184static const struct dri_debug_control debug_control[] = {
185	{"fall", DEBUG_FALLBACKS},
186	{"tex", DEBUG_TEXTURE},
187	{"ioctl", DEBUG_IOCTL},
188	{"prim", DEBUG_PRIMS},
189	{"vert", DEBUG_VERTS},
190	{"state", DEBUG_STATE},
191	{"code", DEBUG_CODEGEN},
192	{"vfmt", DEBUG_VFMT},
193	{"vtxf", DEBUG_VFMT},
194	{"verb", DEBUG_VERBOSE},
195	{"dri", DEBUG_DRI},
196	{"dma", DEBUG_DMA},
197	{"san", DEBUG_SANITY},
198	{"sync", DEBUG_SYNC},
199	{"pix", DEBUG_PIXEL},
200	{"mem", DEBUG_MEMORY},
201	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
202	{NULL, 0}
203};
204#endif /* RADEON_DEBUG */
205
206#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
207
208extern const struct dri_extension card_extensions[];
209
210static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
211
212static __GLcontextModes *
213radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
214		 unsigned stencil_bits, GLboolean have_back_buffer )
215{
216    __GLcontextModes * modes;
217    __GLcontextModes * m;
218    unsigned num_modes;
219    unsigned depth_buffer_factor;
220    unsigned back_buffer_factor;
221    GLenum fb_format;
222    GLenum fb_type;
223
224    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
225     * enough to add support.  Basically, if a context is created with an
226     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
227     * will never be used.
228     */
229    static const GLenum back_buffer_modes[] = {
230	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
231    };
232
233    u_int8_t depth_bits_array[2];
234    u_int8_t stencil_bits_array[2];
235
236
237    depth_bits_array[0] = depth_bits;
238    depth_bits_array[1] = depth_bits;
239
240    /* Just like with the accumulation buffer, always provide some modes
241     * with a stencil buffer.  It will be a sw fallback, but some apps won't
242     * care about that.
243     */
244    stencil_bits_array[0] = 0;
245    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
246
247    depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
248    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
249
250    num_modes = depth_buffer_factor * back_buffer_factor * 4;
251
252    if ( pixel_bits == 16 ) {
253        fb_format = GL_RGB;
254        fb_type = GL_UNSIGNED_SHORT_5_6_5;
255    }
256    else {
257        fb_format = GL_BGRA;
258        fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
259    }
260
261    modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
262    m = modes;
263    if ( ! driFillInModes( & m, fb_format, fb_type,
264			   depth_bits_array, stencil_bits_array, depth_buffer_factor,
265			   back_buffer_modes, back_buffer_factor,
266			   GLX_TRUE_COLOR ) ) {
267	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
268		 __func__, __LINE__ );
269	return NULL;
270    }
271
272    if ( ! driFillInModes( & m, fb_format, fb_type,
273			   depth_bits_array, stencil_bits_array, depth_buffer_factor,
274			   back_buffer_modes, back_buffer_factor,
275			   GLX_DIRECT_COLOR ) ) {
276	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
277		 __func__, __LINE__ );
278	return NULL;
279    }
280
281    /* Mark the visual as slow if there are "fake" stencil bits.
282     */
283    for ( m = modes ; m != NULL ; m = m->next ) {
284	if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
285	    m->visualRating = GLX_SLOW_CONFIG;
286	}
287    }
288
289    return modes;
290}
291
292
293/* Create the device specific screen private data struct.
294 */
295static radeonScreenPtr
296radeonCreateScreen( __DRIscreenPrivate *sPriv )
297{
298   radeonScreenPtr screen;
299   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
300   unsigned char *RADEONMMIO;
301   PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
302     (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
303   void * const psc = sPriv->psc->screenConfigs;
304
305   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
306      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
307      return GL_FALSE;
308   }
309
310   /* Allocate the private area */
311   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
312   if ( !screen ) {
313      __driUtilMessage("%s: Could not allocate memory for screen structure",
314		       __FUNCTION__);
315      return NULL;
316   }
317
318#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
319	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
320#endif
321
322   /* parse information in __driConfigOptions */
323   driParseOptionInfo (&screen->optionCache,
324		       __driConfigOptions, __driNConfigOptions);
325
326   /* This is first since which regions we map depends on whether or
327    * not we are using a PCI card.
328    */
329   screen->IsPCI = dri_priv->IsPCI;
330
331   {
332      int ret;
333      drm_radeon_getparam_t gp;
334
335      gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
336      gp.value = &screen->gart_buffer_offset;
337
338      ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
339				 &gp, sizeof(gp));
340      if (ret) {
341	 FREE( screen );
342	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
343	 return NULL;
344      }
345
346      if (sPriv->drmMinor >= 6) {
347	 gp.param = RADEON_PARAM_GART_BASE;
348	 gp.value = &screen->gart_base;
349
350	 ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
351				    &gp, sizeof(gp));
352	 if (ret) {
353	    FREE( screen );
354	    fprintf(stderr, "drmR200GetParam (RADEON_PARAM_GART_BASE): %d\n", ret);
355	    return NULL;
356	 }
357
358	 gp.param = RADEON_PARAM_IRQ_NR;
359	 gp.value = &screen->irq;
360
361	 ret = drmCommandWriteRead( sPriv->fd, DRM_RADEON_GETPARAM,
362				    &gp, sizeof(gp));
363	 if (ret) {
364	    FREE( screen );
365	    fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
366	    return NULL;
367	 }
368	 screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7);
369	 screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
370	 screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
371	 screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
372	 screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
373	 screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15);
374      }
375   }
376
377   screen->mmio.handle = dri_priv->registerHandle;
378   screen->mmio.size   = dri_priv->registerSize;
379   if ( drmMap( sPriv->fd,
380		screen->mmio.handle,
381		screen->mmio.size,
382		&screen->mmio.map ) ) {
383      FREE( screen );
384      __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
385      return NULL;
386   }
387
388   RADEONMMIO = screen->mmio.map;
389
390   screen->status.handle = dri_priv->statusHandle;
391   screen->status.size   = dri_priv->statusSize;
392   if ( drmMap( sPriv->fd,
393		screen->status.handle,
394		screen->status.size,
395		&screen->status.map ) ) {
396      drmUnmap( screen->mmio.map, screen->mmio.size );
397      FREE( screen );
398      __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
399      return NULL;
400   }
401   screen->scratch = (__volatile__ u_int32_t *)
402      ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
403
404   screen->buffers = drmMapBufs( sPriv->fd );
405   if ( !screen->buffers ) {
406      drmUnmap( screen->status.map, screen->status.size );
407      drmUnmap( screen->mmio.map, screen->mmio.size );
408      FREE( screen );
409      __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
410      return NULL;
411   }
412
413   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
414      screen->gartTextures.handle = dri_priv->gartTexHandle;
415      screen->gartTextures.size   = dri_priv->gartTexMapSize;
416      if ( drmMap( sPriv->fd,
417		   screen->gartTextures.handle,
418		   screen->gartTextures.size,
419		   (drmAddressPtr)&screen->gartTextures.map ) ) {
420	 drmUnmapBufs( screen->buffers );
421	 drmUnmap( screen->status.map, screen->status.size );
422	 drmUnmap( screen->mmio.map, screen->mmio.size );
423	 FREE( screen );
424	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
425	 return NULL;
426      }
427
428      screen->gart_texture_offset = dri_priv->gartTexOffset + ( screen->IsPCI
429		? INREG( RADEON_AIC_LO_ADDR )
430		: ( ( INREG( RADEON_MC_AGP_LOCATION ) & 0x0ffffU ) << 16 ) );
431   }
432
433   screen->chip_flags = 0;
434   /* XXX: add more chipsets */
435   switch ( dri_priv->deviceID ) {
436   case PCI_CHIP_RADEON_LY:
437   case PCI_CHIP_RADEON_LZ:
438   case PCI_CHIP_RADEON_QY:
439   case PCI_CHIP_RADEON_QZ:
440   case PCI_CHIP_RN50_515E:
441   case PCI_CHIP_RN50_5969:
442      screen->chip_family = CHIP_FAMILY_RV100;
443      break;
444
445   case PCI_CHIP_RS100_4136:
446   case PCI_CHIP_RS100_4336:
447      screen->chip_family = CHIP_FAMILY_RS100;
448      break;
449
450   case PCI_CHIP_RS200_4137:
451   case PCI_CHIP_RS200_4337:
452   case PCI_CHIP_RS250_4237:
453   case PCI_CHIP_RS250_4437:
454      screen->chip_family = CHIP_FAMILY_RS200;
455      break;
456
457   case PCI_CHIP_RADEON_QD:
458   case PCI_CHIP_RADEON_QE:
459   case PCI_CHIP_RADEON_QF:
460   case PCI_CHIP_RADEON_QG:
461      /* all original radeons (7200) presumably have a stencil op bug */
462      screen->chip_family = CHIP_FAMILY_R100;
463      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
464      break;
465
466   case PCI_CHIP_RV200_QW:
467   case PCI_CHIP_RV200_QX:
468   case PCI_CHIP_RADEON_LW:
469   case PCI_CHIP_RADEON_LX:
470      screen->chip_family = CHIP_FAMILY_RV200;
471      screen->chip_flags = RADEON_CHIPSET_TCL;
472      break;
473
474   case PCI_CHIP_R200_BB:
475   case PCI_CHIP_R200_BC:
476   case PCI_CHIP_R200_QH:
477   case PCI_CHIP_R200_QL:
478   case PCI_CHIP_R200_QM:
479      screen->chip_family = CHIP_FAMILY_R200;
480      screen->chip_flags = RADEON_CHIPSET_TCL;
481      break;
482
483   case PCI_CHIP_RV250_If:
484   case PCI_CHIP_RV250_Ig:
485   case PCI_CHIP_RV250_Ld:
486   case PCI_CHIP_RV250_Lf:
487   case PCI_CHIP_RV250_Lg:
488      screen->chip_family = CHIP_FAMILY_RV250;
489      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
490      break;
491
492   case PCI_CHIP_RV280_5960:
493   case PCI_CHIP_RV280_5961:
494   case PCI_CHIP_RV280_5962:
495   case PCI_CHIP_RV280_5964:
496   case PCI_CHIP_RV280_5965:
497   case PCI_CHIP_RV280_5C61:
498   case PCI_CHIP_RV280_5C63:
499      screen->chip_family = CHIP_FAMILY_RV280;
500      screen->chip_flags = RADEON_CHIPSET_TCL;
501      break;
502
503   case PCI_CHIP_RS300_5834:
504   case PCI_CHIP_RS300_5835:
505   case PCI_CHIP_RS350_7834:
506   case PCI_CHIP_RS350_7835:
507      screen->chip_family = CHIP_FAMILY_RS300;
508      break;
509
510   case PCI_CHIP_R300_AD:
511   case PCI_CHIP_R300_AE:
512   case PCI_CHIP_R300_AF:
513   case PCI_CHIP_R300_AG:
514   case PCI_CHIP_R300_ND:
515   case PCI_CHIP_R300_NE:
516   case PCI_CHIP_R300_NF:
517   case PCI_CHIP_R300_NG:
518      screen->chip_family = CHIP_FAMILY_R300;
519      screen->chip_flags = RADEON_CHIPSET_TCL;
520      break;
521
522   case PCI_CHIP_RV350_AP:
523   case PCI_CHIP_RV350_AQ:
524   case PCI_CHIP_RV350_AR:
525   case PCI_CHIP_RV350_AS:
526   case PCI_CHIP_RV350_AT:
527   case PCI_CHIP_RV350_AV:
528   case PCI_CHIP_RV350_AU:
529   case PCI_CHIP_RV350_NP:
530   case PCI_CHIP_RV350_NQ:
531   case PCI_CHIP_RV350_NR:
532   case PCI_CHIP_RV350_NS:
533   case PCI_CHIP_RV350_NT:
534   case PCI_CHIP_RV350_NV:
535      screen->chip_family = CHIP_FAMILY_RV350;
536      screen->chip_flags = RADEON_CHIPSET_TCL;
537      break;
538
539   case PCI_CHIP_R350_AH:
540   case PCI_CHIP_R350_AI:
541   case PCI_CHIP_R350_AJ:
542   case PCI_CHIP_R350_AK:
543   case PCI_CHIP_R350_NH:
544   case PCI_CHIP_R350_NI:
545   case PCI_CHIP_R360_NJ:
546   case PCI_CHIP_R350_NK:
547      screen->chip_family = CHIP_FAMILY_R350;
548      screen->chip_flags = RADEON_CHIPSET_TCL;
549      break;
550
551   case PCI_CHIP_RV370_5460:
552   case PCI_CHIP_RV370_5462:
553   case PCI_CHIP_RV370_5464:
554   case PCI_CHIP_RV370_5B60:
555   case PCI_CHIP_RV370_5B62:
556   case PCI_CHIP_RV370_5B63:
557   case PCI_CHIP_RV370_5B64:
558   case PCI_CHIP_RV370_5B65:
559   case PCI_CHIP_RV380_3150:
560   case PCI_CHIP_RV380_3152:
561   case PCI_CHIP_RV380_3154:
562   case PCI_CHIP_RV380_3E50:
563   case PCI_CHIP_RV380_3E54:
564      screen->chip_family = CHIP_FAMILY_RV380;
565      screen->chip_flags = RADEON_CHIPSET_TCL;
566      break;
567
568   case PCI_CHIP_R420_JN:
569   case PCI_CHIP_R420_JH:
570   case PCI_CHIP_R420_JI:
571   case PCI_CHIP_R420_JJ:
572   case PCI_CHIP_R420_JK:
573   case PCI_CHIP_R420_JL:
574   case PCI_CHIP_R420_JM:
575   case PCI_CHIP_R420_JO:
576   case PCI_CHIP_R420_JP:
577   case PCI_CHIP_R420_JT:
578   case PCI_CHIP_R481_4B49:
579   case PCI_CHIP_R481_4B4A:
580   case PCI_CHIP_R481_4B4B:
581   case PCI_CHIP_R481_4B4C:
582   case PCI_CHIP_R423_UH:
583   case PCI_CHIP_R423_UI:
584   case PCI_CHIP_R423_UJ:
585   case PCI_CHIP_R423_UK:
586   case PCI_CHIP_R430_554C:
587   case PCI_CHIP_R430_554D:
588   case PCI_CHIP_R430_554E:
589   case PCI_CHIP_R430_554F:
590   case PCI_CHIP_R423_5550:
591   case PCI_CHIP_R423_UQ:
592   case PCI_CHIP_R423_UR:
593   case PCI_CHIP_R423_UT:
594   case PCI_CHIP_R430_5D48:
595   case PCI_CHIP_R430_5D49:
596   case PCI_CHIP_R430_5D4A:
597   case PCI_CHIP_R480_5D4C:
598   case PCI_CHIP_R480_5D4D:
599   case PCI_CHIP_R480_5D4E:
600   case PCI_CHIP_R480_5D4F:
601   case PCI_CHIP_R480_5D50:
602   case PCI_CHIP_R480_5D52:
603   case PCI_CHIP_R423_5D57:
604      screen->chip_family = CHIP_FAMILY_R420;
605      screen->chip_flags = RADEON_CHIPSET_TCL;
606      break;
607
608   case PCI_CHIP_RV410_564A:
609   case PCI_CHIP_RV410_564B:
610   case PCI_CHIP_RV410_564F:
611   case PCI_CHIP_RV410_5652:
612   case PCI_CHIP_RV410_5653:
613   case PCI_CHIP_RV410_5E48:
614   case PCI_CHIP_RV410_5E4A:
615   case PCI_CHIP_RV410_5E4B:
616   case PCI_CHIP_RV410_5E4C:
617   case PCI_CHIP_RV410_5E4D:
618   case PCI_CHIP_RV410_5E4F:
619      screen->chip_family = CHIP_FAMILY_RV410;
620      screen->chip_flags = RADEON_CHIPSET_TCL;
621      break;
622
623   case PCI_CHIP_RS480_5954:
624   case PCI_CHIP_RS480_5955:
625   case PCI_CHIP_RS482_5974:
626   case PCI_CHIP_RS482_5975:
627   case PCI_CHIP_RS400_5A41:
628   case PCI_CHIP_RS400_5A42:
629   case PCI_CHIP_RC410_5A61:
630   case PCI_CHIP_RC410_5A62:
631      screen->chip_family = CHIP_FAMILY_RS400;
632      fprintf(stderr, "Warning, xpress200 detected. Probably won't work.\n");
633      break;
634
635   default:
636      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
637	      dri_priv->deviceID);
638      return NULL;
639   }
640   if (screen->chip_family == CHIP_FAMILY_R350 ||
641       screen->chip_family == CHIP_FAMILY_R300) {
642	   if (getenv("R300_FORCE_R300") == NULL) {
643		   fprintf(stderr, "Radeon 9500/9700/9800 cards are not currently stable.\n");
644		   fprintf(stderr, "More details can be found at https://bugs.freedesktop.org/show_bug.cgi?id=6318\n");
645		   return NULL;
646	   }
647   }
648
649   if (screen->chip_family <= CHIP_FAMILY_RS200)
650      screen->chip_flags |= RADEON_CLASS_R100;
651   else if (screen->chip_family <= CHIP_FAMILY_RV280)
652      screen->chip_flags |= RADEON_CLASS_R200;
653   else
654      screen->chip_flags |= RADEON_CLASS_R300;
655
656   screen->cpp = dri_priv->bpp / 8;
657   screen->AGPMode = dri_priv->AGPMode;
658
659   screen->fbLocation	= ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
660
661   if ( sPriv->drmMinor >= 10 ) {
662      drm_radeon_setparam_t sp;
663
664      sp.param = RADEON_SETPARAM_FB_LOCATION;
665      sp.value = screen->fbLocation;
666
667      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
668		       &sp, sizeof( sp ) );
669   }
670
671   screen->frontOffset	= dri_priv->frontOffset;
672   screen->frontPitch	= dri_priv->frontPitch;
673   screen->backOffset	= dri_priv->backOffset;
674   screen->backPitch	= dri_priv->backPitch;
675   screen->depthOffset	= dri_priv->depthOffset;
676   screen->depthPitch	= dri_priv->depthPitch;
677
678   /* Check if ddx has set up a surface reg to cover depth buffer */
679   screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
680      (screen->chip_flags & RADEON_CHIPSET_TCL));
681
682   if ( dri_priv->textureSize == 0 ) {
683      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
684      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
685      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
686	 dri_priv->log2GARTTexGran;
687   } else {
688      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
689				               + screen->fbLocation;
690      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
691      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
692	 dri_priv->log2TexGran;
693   }
694
695   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
696	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
697      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
698      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
699      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
700      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
701   } else {
702      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
703      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
704      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
705      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
706	 dri_priv->log2GARTTexGran;
707   }
708
709   if ( glx_enable_extension != NULL ) {
710      if ( screen->irq != 0 ) {
711	 (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
712	 (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
713	 (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
714      }
715
716      (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
717      if (IS_R200_CLASS(screen))
718	 (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
719   }
720
721#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
722   if (IS_R200_CLASS(screen)) {
723      sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
724      sPriv->psc->freeMemory     = (void *) r200FreeMemoryMESA;
725      sPriv->psc->memoryOffset   = (void *) r200GetMemoryOffsetMESA;
726   }
727#endif
728
729   screen->driScreen = sPriv;
730   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
731   return screen;
732}
733
734/* Destroy the device specific screen private data struct.
735 */
736static void
737radeonDestroyScreen( __DRIscreenPrivate *sPriv )
738{
739   radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
740
741   if (!screen)
742      return;
743
744   if ( screen->gartTextures.map ) {
745      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
746   }
747   drmUnmapBufs( screen->buffers );
748   drmUnmap( screen->status.map, screen->status.size );
749   drmUnmap( screen->mmio.map, screen->mmio.size );
750
751   /* free all option information */
752   driDestroyOptionInfo (&screen->optionCache);
753
754   FREE( screen );
755   sPriv->private = NULL;
756}
757
758
759/* Initialize the driver specific screen private data.
760 */
761static GLboolean
762radeonInitDriver( __DRIscreenPrivate *sPriv )
763{
764   sPriv->private = (void *) radeonCreateScreen( sPriv );
765   if ( !sPriv->private ) {
766      radeonDestroyScreen( sPriv );
767      return GL_FALSE;
768   }
769
770   return GL_TRUE;
771}
772
773
774/**
775 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
776 *
777 * \todo This function (and its interface) will need to be updated to support
778 * pbuffers.
779 */
780static GLboolean
781radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
782                    __DRIdrawablePrivate *driDrawPriv,
783                    const __GLcontextModes *mesaVis,
784                    GLboolean isPixmap )
785{
786   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
787
788   if (isPixmap) {
789      return GL_FALSE; /* not implemented */
790   }
791   else {
792      const GLboolean swDepth = GL_FALSE;
793      const GLboolean swAlpha = GL_FALSE;
794      const GLboolean swAccum = mesaVis->accumRedBits > 0;
795      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
796         mesaVis->depthBits != 24;
797      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
798
799      /* front color renderbuffer */
800      {
801         driRenderbuffer *frontRb
802            = driNewRenderbuffer(GL_RGBA,
803                                 driScrnPriv->pFB + screen->frontOffset,
804                                 screen->cpp,
805                                 screen->frontOffset, screen->frontPitch,
806                                 driDrawPriv);
807         radeonSetSpanFunctions(frontRb, mesaVis);
808         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
809      }
810
811      /* back color renderbuffer */
812      if (mesaVis->doubleBufferMode) {
813         driRenderbuffer *backRb
814            = driNewRenderbuffer(GL_RGBA,
815                                 driScrnPriv->pFB + screen->backOffset,
816                                 screen->cpp,
817                                 screen->backOffset, screen->backPitch,
818                                 driDrawPriv);
819         radeonSetSpanFunctions(backRb, mesaVis);
820         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
821      }
822
823      /* depth renderbuffer */
824      if (mesaVis->depthBits == 16) {
825         driRenderbuffer *depthRb
826            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
827                                 driScrnPriv->pFB + screen->depthOffset,
828                                 screen->cpp,
829                                 screen->depthOffset, screen->depthPitch,
830                                 driDrawPriv);
831         radeonSetSpanFunctions(depthRb, mesaVis);
832         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
833	 depthRb->depthHasSurface = screen->depthHasSurface;
834      }
835      else if (mesaVis->depthBits == 24) {
836         driRenderbuffer *depthRb
837            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
838                                 driScrnPriv->pFB + screen->depthOffset,
839                                 screen->cpp,
840                                 screen->depthOffset, screen->depthPitch,
841                                 driDrawPriv);
842         radeonSetSpanFunctions(depthRb, mesaVis);
843         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
844	 depthRb->depthHasSurface = screen->depthHasSurface;
845      }
846
847      /* stencil renderbuffer */
848      if (mesaVis->stencilBits > 0 && !swStencil) {
849         driRenderbuffer *stencilRb
850            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
851                                 driScrnPriv->pFB + screen->depthOffset,
852                                 screen->cpp,
853                                 screen->depthOffset, screen->depthPitch,
854                                 driDrawPriv);
855         radeonSetSpanFunctions(stencilRb, mesaVis);
856         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
857	 stencilRb->depthHasSurface = screen->depthHasSurface;
858      }
859
860      _mesa_add_soft_renderbuffers(fb,
861                                   GL_FALSE, /* color */
862                                   swDepth,
863                                   swStencil,
864                                   swAccum,
865                                   swAlpha,
866                                   GL_FALSE /* aux */);
867      driDrawPriv->driverPrivate = (void *) fb;
868
869      return (driDrawPriv->driverPrivate != NULL);
870   }
871}
872
873
874static void
875radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
876{
877   _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
878}
879
880#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
881/**
882 * Choose the appropriate CreateContext function based on the chipset.
883 * Eventually, all drivers will go through this process.
884 */
885static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
886				     __DRIcontextPrivate * driContextPriv,
887				     void *sharedContextPriv)
888{
889	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
890	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
891
892	if (IS_R300_CLASS(screen))
893		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
894        return GL_FALSE;
895}
896
897/**
898 * Choose the appropriate DestroyContext function based on the chipset.
899 */
900static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
901{
902	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
903
904	if (IS_R300_CLASS(radeon->radeonScreen))
905		return r300DestroyContext(driContextPriv);
906}
907
908
909#endif
910
911#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
912static struct __DriverAPIRec radeonAPI = {
913   .InitDriver      = radeonInitDriver,
914   .DestroyScreen   = radeonDestroyScreen,
915   .CreateContext   = radeonCreateContext,
916   .DestroyContext  = radeonDestroyContext,
917   .CreateBuffer    = radeonCreateBuffer,
918   .DestroyBuffer   = radeonDestroyBuffer,
919   .SwapBuffers     = radeonSwapBuffers,
920   .MakeCurrent     = radeonMakeCurrent,
921   .UnbindContext   = radeonUnbindContext,
922   .GetSwapInfo     = getSwapInfo,
923   .GetMSC          = driGetMSC32,
924   .WaitForMSC      = driWaitForMSC32,
925   .WaitForSBC      = NULL,
926   .SwapBuffersMSC  = NULL
927};
928#else
929static const struct __DriverAPIRec r200API = {
930   .InitDriver      = radeonInitDriver,
931   .DestroyScreen   = radeonDestroyScreen,
932   .CreateContext   = r200CreateContext,
933   .DestroyContext  = r200DestroyContext,
934   .CreateBuffer    = radeonCreateBuffer,
935   .DestroyBuffer   = radeonDestroyBuffer,
936   .SwapBuffers     = r200SwapBuffers,
937   .MakeCurrent     = r200MakeCurrent,
938   .UnbindContext   = r200UnbindContext,
939   .GetSwapInfo     = getSwapInfo,
940   .GetMSC          = driGetMSC32,
941   .WaitForMSC      = driWaitForMSC32,
942   .WaitForSBC      = NULL,
943   .SwapBuffersMSC  = NULL
944};
945#endif
946
947/**
948 * This is the bootstrap function for the driver.  libGL supplies all of the
949 * requisite information about the system, and the driver initializes itself.
950 * This routine also fills in the linked list pointed to by \c driver_modes
951 * with the \c __GLcontextModes that the driver can support for windows or
952 * pbuffers.
953 *
954 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
955 *         failure.
956 */
957PUBLIC void *
958__driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
959                             int scrn, __DRIscreen *psc,
960			     const __GLcontextModes * modes,
961			     const __DRIversion * ddx_version,
962			     const __DRIversion * dri_version,
963			     const __DRIversion * drm_version,
964			     const __DRIframebuffer * frame_buffer,
965			     drmAddress pSAREA, int fd,
966			     int internal_api_version,
967			     const __DRIinterfaceMethods * interface,
968			     __GLcontextModes ** driver_modes )
969{
970   __DRIscreenPrivate *psp;
971#if !RADEON_COMMON
972   static const char *driver_name = "Radeon";
973   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
974   static const __DRIversion dri_expected = { 4, 0, 0 };
975   static const __DRIversion drm_expected = { 1, 3, 0 };
976#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
977   static const char *driver_name = "R200";
978   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
979   static const __DRIversion dri_expected = { 4, 0, 0 };
980   static const __DRIversion drm_expected = { 1, 5, 0 };
981#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
982   static const char *driver_name = "R300";
983   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
984   static const __DRIversion dri_expected = { 4, 0, 0 };
985   static const __DRIversion drm_expected = { 1, 24, 0 };
986#endif
987
988   dri_interface = interface;
989
990   if ( ! driCheckDriDdxDrmVersions3( driver_name,
991				      dri_version, & dri_expected,
992				      ddx_version, & ddx_expected,
993				      drm_version, & drm_expected ) ) {
994      return NULL;
995   }
996#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
997   psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
998				  ddx_version, dri_version, drm_version,
999				  frame_buffer, pSAREA, fd,
1000				  internal_api_version, &radeonAPI);
1001#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1002   psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
1003				  ddx_version, dri_version, drm_version,
1004				  frame_buffer, pSAREA, fd,
1005				  internal_api_version, &r200API);
1006#endif
1007
1008   if ( psp != NULL ) {
1009      RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1010      if (driver_modes) {
1011         *driver_modes = radeonFillInModes( dri_priv->bpp,
1012                                            (dri_priv->bpp == 16) ? 16 : 24,
1013                                            (dri_priv->bpp == 16) ? 0  : 8,
1014                                            (dri_priv->backOffset != dri_priv->depthOffset) );
1015      }
1016
1017      /* Calling driInitExtensions here, with a NULL context pointer,
1018       * does not actually enable the extensions.  It just makes sure
1019       * that all the dispatch offsets for all the extensions that
1020       * *might* be enables are known.  This is needed because the
1021       * dispatch offsets need to be known when _mesa_context_create
1022       * is called, but we can't enable the extensions until we have a
1023       * context pointer.
1024       *
1025       * Hello chicken.  Hello egg.  How are you two today?
1026       */
1027      driInitExtensions( NULL, card_extensions, GL_FALSE );
1028#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1029      driInitExtensions( NULL, blend_extensions, GL_FALSE );
1030      driInitSingleExtension( NULL, ARB_vp_extension );
1031      driInitSingleExtension( NULL, NV_vp_extension );
1032      driInitSingleExtension( NULL, ATI_fs_extension );
1033#endif
1034   }
1035
1036   return (void *) psp;
1037}
1038
1039
1040/**
1041 * Get information about previous buffer swaps.
1042 */
1043static int
1044getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1045{
1046#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1047   radeonContextPtr  rmesa;
1048#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1049   r200ContextPtr  rmesa;
1050#endif
1051
1052   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1053	|| (dPriv->driContextPriv->driverPrivate == NULL)
1054	|| (sInfo == NULL) ) {
1055      return -1;
1056   }
1057
1058   rmesa = dPriv->driContextPriv->driverPrivate;
1059   sInfo->swap_count = rmesa->swap_count;
1060   sInfo->swap_ust = rmesa->swap_ust;
1061   sInfo->swap_missed_count = rmesa->swap_missed_count;
1062
1063   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1064       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1065       : 0.0;
1066
1067   return 0;
1068}
1069