radeon_screen.c revision 73ec71cb16fbae0effcb4a92da7dc7f17cd6a62a
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44#include "main/fbobject.h" 45 46#define STANDALONE_MMIO 47#include "radeon_chipset.h" 48#include "radeon_macros.h" 49#include "radeon_screen.h" 50#include "radeon_common.h" 51#include "radeon_common_context.h" 52#if defined(RADEON_R100) 53#include "radeon_context.h" 54#include "radeon_tex.h" 55#elif defined(RADEON_R200) 56#include "r200_context.h" 57#include "r200_tex.h" 58#endif 59 60#include "utils.h" 61#include "vblank.h" 62 63#include "GL/internal/dri_interface.h" 64 65/* Radeon configuration 66 */ 67#include "xmlpool.h" 68 69#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 70DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 71 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 72 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 73DRI_CONF_OPT_END 74 75#if defined(RADEON_R100) /* R100 */ 76PUBLIC const char __driConfigOptions[] = 77DRI_CONF_BEGIN 78 DRI_CONF_SECTION_PERFORMANCE 79 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 80 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 81 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 82 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 83 DRI_CONF_HYPERZ(false) 84 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 85 DRI_CONF_SECTION_END 86 DRI_CONF_SECTION_QUALITY 87 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 88 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 89 DRI_CONF_NO_NEG_LOD_BIAS(false) 90 DRI_CONF_FORCE_S3TC_ENABLE(false) 91 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 92 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 93 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 94 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 95 DRI_CONF_SECTION_END 96 DRI_CONF_SECTION_DEBUG 97 DRI_CONF_NO_RAST(false) 98 DRI_CONF_SECTION_END 99DRI_CONF_END; 100static const GLuint __driNConfigOptions = 15; 101 102#elif defined(RADEON_R200) 103 104PUBLIC const char __driConfigOptions[] = 105DRI_CONF_BEGIN 106 DRI_CONF_SECTION_PERFORMANCE 107 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 108 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 109 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 110 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 111 DRI_CONF_HYPERZ(false) 112 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 113 DRI_CONF_SECTION_END 114 DRI_CONF_SECTION_QUALITY 115 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 116 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 117 DRI_CONF_NO_NEG_LOD_BIAS(false) 118 DRI_CONF_FORCE_S3TC_ENABLE(false) 119 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 120 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 121 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 122 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 123 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 124 DRI_CONF_SECTION_END 125 DRI_CONF_SECTION_DEBUG 126 DRI_CONF_NO_RAST(false) 127 DRI_CONF_SECTION_END 128 DRI_CONF_SECTION_SOFTWARE 129 DRI_CONF_NV_VERTEX_PROGRAM(false) 130 DRI_CONF_SECTION_END 131DRI_CONF_END; 132static const GLuint __driNConfigOptions = 17; 133 134#endif 135 136#ifndef RADEON_INFO_TILE_CONFIG 137#define RADEON_INFO_TILE_CONFIG 0x6 138#endif 139 140static int 141radeonGetParam(__DRIscreen *sPriv, int param, void *value) 142{ 143 int ret; 144 drm_radeon_getparam_t gp = { 0 }; 145 struct drm_radeon_info info = { 0 }; 146 147 if (sPriv->drm_version.major >= 2) { 148 info.value = (uint64_t)(uintptr_t)value; 149 switch (param) { 150 case RADEON_PARAM_DEVICE_ID: 151 info.request = RADEON_INFO_DEVICE_ID; 152 break; 153 case RADEON_PARAM_NUM_GB_PIPES: 154 info.request = RADEON_INFO_NUM_GB_PIPES; 155 break; 156 case RADEON_PARAM_NUM_Z_PIPES: 157 info.request = RADEON_INFO_NUM_Z_PIPES; 158 break; 159 case RADEON_INFO_TILE_CONFIG: 160 info.request = RADEON_INFO_TILE_CONFIG; 161 break; 162 default: 163 return -EINVAL; 164 } 165 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 166 } else { 167 gp.param = param; 168 gp.value = value; 169 170 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 171 } 172 return ret; 173} 174 175#if defined(RADEON_R100) 176static const __DRItexBufferExtension radeonTexBufferExtension = { 177 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 178 radeonSetTexBuffer, 179 radeonSetTexBuffer2, 180}; 181#endif 182 183#if defined(RADEON_R200) 184static const __DRItexBufferExtension r200TexBufferExtension = { 185 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 186 r200SetTexBuffer, 187 r200SetTexBuffer2, 188}; 189#endif 190 191static void 192radeonDRI2Flush(__DRIdrawable *drawable) 193{ 194 radeonContextPtr rmesa; 195 196 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; 197 radeonFlush(rmesa->glCtx); 198} 199 200static const struct __DRI2flushExtensionRec radeonFlushExtension = { 201 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION }, 202 radeonDRI2Flush, 203 dri2InvalidateDrawable, 204}; 205 206static __DRIimage * 207radeon_create_image_from_name(__DRIscreen *screen, 208 int width, int height, int format, 209 int name, int pitch, void *loaderPrivate) 210{ 211 __DRIimage *image; 212 radeonScreenPtr radeonScreen = screen->private; 213 214 if (name == 0) 215 return NULL; 216 217 image = CALLOC(sizeof *image); 218 if (image == NULL) 219 return NULL; 220 221 switch (format) { 222 case __DRI_IMAGE_FORMAT_RGB565: 223 image->format = MESA_FORMAT_RGB565; 224 image->internal_format = GL_RGB; 225 image->data_type = GL_UNSIGNED_BYTE; 226 break; 227 case __DRI_IMAGE_FORMAT_XRGB8888: 228 image->format = MESA_FORMAT_XRGB8888; 229 image->internal_format = GL_RGB; 230 image->data_type = GL_UNSIGNED_BYTE; 231 break; 232 case __DRI_IMAGE_FORMAT_ARGB8888: 233 image->format = MESA_FORMAT_ARGB8888; 234 image->internal_format = GL_RGBA; 235 image->data_type = GL_UNSIGNED_BYTE; 236 break; 237 default: 238 free(image); 239 return NULL; 240 } 241 242 image->data = loaderPrivate; 243 image->cpp = _mesa_get_format_bytes(image->format); 244 image->width = width; 245 image->pitch = pitch; 246 image->height = height; 247 248 image->bo = radeon_bo_open(radeonScreen->bom, 249 (uint32_t)name, 250 image->pitch * image->height * image->cpp, 251 0, 252 RADEON_GEM_DOMAIN_VRAM, 253 0); 254 255 if (image->bo == NULL) { 256 FREE(image); 257 return NULL; 258 } 259 260 return image; 261} 262 263static __DRIimage * 264radeon_create_image_from_renderbuffer(__DRIcontext *context, 265 int renderbuffer, void *loaderPrivate) 266{ 267 __DRIimage *image; 268 radeonContextPtr radeon = context->driverPrivate; 269 struct gl_renderbuffer *rb; 270 struct radeon_renderbuffer *rrb; 271 272 rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer); 273 if (!rb) { 274 _mesa_error(radeon->glCtx, 275 GL_INVALID_OPERATION, "glRenderbufferExternalMESA"); 276 return NULL; 277 } 278 279 rrb = radeon_renderbuffer(rb); 280 image = CALLOC(sizeof *image); 281 if (image == NULL) 282 return NULL; 283 284 image->internal_format = rb->InternalFormat; 285 image->format = rb->Format; 286 image->cpp = rrb->cpp; 287 image->data_type = rb->DataType; 288 image->data = loaderPrivate; 289 radeon_bo_ref(rrb->bo); 290 image->bo = rrb->bo; 291 292 image->width = rb->Width; 293 image->height = rb->Height; 294 image->pitch = rrb->pitch / image->cpp; 295 296 return image; 297} 298 299static void 300radeon_destroy_image(__DRIimage *image) 301{ 302 radeon_bo_unref(image->bo); 303 FREE(image); 304} 305 306static __DRIimage * 307radeon_create_image(__DRIscreen *screen, 308 int width, int height, int format, 309 unsigned int use, 310 void *loaderPrivate) 311{ 312 __DRIimage *image; 313 radeonScreenPtr radeonScreen = screen->private; 314 315 image = CALLOC(sizeof *image); 316 if (image == NULL) 317 return NULL; 318 319 switch (format) { 320 case __DRI_IMAGE_FORMAT_RGB565: 321 image->format = MESA_FORMAT_RGB565; 322 image->internal_format = GL_RGB; 323 image->data_type = GL_UNSIGNED_BYTE; 324 break; 325 case __DRI_IMAGE_FORMAT_XRGB8888: 326 image->format = MESA_FORMAT_XRGB8888; 327 image->internal_format = GL_RGB; 328 image->data_type = GL_UNSIGNED_BYTE; 329 break; 330 case __DRI_IMAGE_FORMAT_ARGB8888: 331 image->format = MESA_FORMAT_ARGB8888; 332 image->internal_format = GL_RGBA; 333 image->data_type = GL_UNSIGNED_BYTE; 334 break; 335 default: 336 free(image); 337 return NULL; 338 } 339 340 image->data = loaderPrivate; 341 image->cpp = _mesa_get_format_bytes(image->format); 342 image->width = width; 343 image->height = height; 344 image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp; 345 346 image->bo = radeon_bo_open(radeonScreen->bom, 347 0, 348 image->pitch * image->height * image->cpp, 349 0, 350 RADEON_GEM_DOMAIN_VRAM, 351 0); 352 353 if (image->bo == NULL) { 354 FREE(image); 355 return NULL; 356 } 357 358 return image; 359} 360 361static GLboolean 362radeon_query_image(__DRIimage *image, int attrib, int *value) 363{ 364 switch (attrib) { 365 case __DRI_IMAGE_ATTRIB_STRIDE: 366 *value = image->pitch * image->cpp; 367 return GL_TRUE; 368 case __DRI_IMAGE_ATTRIB_HANDLE: 369 *value = image->bo->handle; 370 return GL_TRUE; 371 case __DRI_IMAGE_ATTRIB_NAME: 372 radeon_gem_get_kernel_name(image->bo, (uint32_t *) value); 373 return GL_TRUE; 374 default: 375 return GL_FALSE; 376 } 377} 378 379static struct __DRIimageExtensionRec radeonImageExtension = { 380 { __DRI_IMAGE, __DRI_IMAGE_VERSION }, 381 radeon_create_image_from_name, 382 radeon_create_image_from_renderbuffer, 383 radeon_destroy_image, 384 radeon_create_image, 385 radeon_query_image 386}; 387 388static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 389{ 390 screen->device_id = device_id; 391 screen->chip_flags = 0; 392 switch ( device_id ) { 393 case PCI_CHIP_RN50_515E: 394 case PCI_CHIP_RN50_5969: 395 return -1; 396 397 case PCI_CHIP_RADEON_LY: 398 case PCI_CHIP_RADEON_LZ: 399 case PCI_CHIP_RADEON_QY: 400 case PCI_CHIP_RADEON_QZ: 401 screen->chip_family = CHIP_FAMILY_RV100; 402 break; 403 404 case PCI_CHIP_RS100_4136: 405 case PCI_CHIP_RS100_4336: 406 screen->chip_family = CHIP_FAMILY_RS100; 407 break; 408 409 case PCI_CHIP_RS200_4137: 410 case PCI_CHIP_RS200_4337: 411 case PCI_CHIP_RS250_4237: 412 case PCI_CHIP_RS250_4437: 413 screen->chip_family = CHIP_FAMILY_RS200; 414 break; 415 416 case PCI_CHIP_RADEON_QD: 417 case PCI_CHIP_RADEON_QE: 418 case PCI_CHIP_RADEON_QF: 419 case PCI_CHIP_RADEON_QG: 420 /* all original radeons (7200) presumably have a stencil op bug */ 421 screen->chip_family = CHIP_FAMILY_R100; 422 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 423 break; 424 425 case PCI_CHIP_RV200_QW: 426 case PCI_CHIP_RV200_QX: 427 case PCI_CHIP_RADEON_LW: 428 case PCI_CHIP_RADEON_LX: 429 screen->chip_family = CHIP_FAMILY_RV200; 430 screen->chip_flags = RADEON_CHIPSET_TCL; 431 break; 432 433 case PCI_CHIP_R200_BB: 434 case PCI_CHIP_R200_QH: 435 case PCI_CHIP_R200_QL: 436 case PCI_CHIP_R200_QM: 437 screen->chip_family = CHIP_FAMILY_R200; 438 screen->chip_flags = RADEON_CHIPSET_TCL; 439 break; 440 441 case PCI_CHIP_RV250_If: 442 case PCI_CHIP_RV250_Ig: 443 case PCI_CHIP_RV250_Ld: 444 case PCI_CHIP_RV250_Lf: 445 case PCI_CHIP_RV250_Lg: 446 screen->chip_family = CHIP_FAMILY_RV250; 447 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 448 break; 449 450 case PCI_CHIP_RV280_5960: 451 case PCI_CHIP_RV280_5961: 452 case PCI_CHIP_RV280_5962: 453 case PCI_CHIP_RV280_5964: 454 case PCI_CHIP_RV280_5965: 455 case PCI_CHIP_RV280_5C61: 456 case PCI_CHIP_RV280_5C63: 457 screen->chip_family = CHIP_FAMILY_RV280; 458 screen->chip_flags = RADEON_CHIPSET_TCL; 459 break; 460 461 case PCI_CHIP_RS300_5834: 462 case PCI_CHIP_RS300_5835: 463 case PCI_CHIP_RS350_7834: 464 case PCI_CHIP_RS350_7835: 465 screen->chip_family = CHIP_FAMILY_RS300; 466 break; 467 468 case PCI_CHIP_R300_AD: 469 case PCI_CHIP_R300_AE: 470 case PCI_CHIP_R300_AF: 471 case PCI_CHIP_R300_AG: 472 case PCI_CHIP_R300_ND: 473 case PCI_CHIP_R300_NE: 474 case PCI_CHIP_R300_NF: 475 case PCI_CHIP_R300_NG: 476 screen->chip_family = CHIP_FAMILY_R300; 477 screen->chip_flags = RADEON_CHIPSET_TCL; 478 break; 479 480 case PCI_CHIP_RV350_AP: 481 case PCI_CHIP_RV350_AQ: 482 case PCI_CHIP_RV350_AR: 483 case PCI_CHIP_RV350_AS: 484 case PCI_CHIP_RV350_AT: 485 case PCI_CHIP_RV350_AV: 486 case PCI_CHIP_RV350_AU: 487 case PCI_CHIP_RV350_NP: 488 case PCI_CHIP_RV350_NQ: 489 case PCI_CHIP_RV350_NR: 490 case PCI_CHIP_RV350_NS: 491 case PCI_CHIP_RV350_NT: 492 case PCI_CHIP_RV350_NV: 493 screen->chip_family = CHIP_FAMILY_RV350; 494 screen->chip_flags = RADEON_CHIPSET_TCL; 495 break; 496 497 case PCI_CHIP_R350_AH: 498 case PCI_CHIP_R350_AI: 499 case PCI_CHIP_R350_AJ: 500 case PCI_CHIP_R350_AK: 501 case PCI_CHIP_R350_NH: 502 case PCI_CHIP_R350_NI: 503 case PCI_CHIP_R360_NJ: 504 case PCI_CHIP_R350_NK: 505 screen->chip_family = CHIP_FAMILY_R350; 506 screen->chip_flags = RADEON_CHIPSET_TCL; 507 break; 508 509 case PCI_CHIP_RV370_5460: 510 case PCI_CHIP_RV370_5462: 511 case PCI_CHIP_RV370_5464: 512 case PCI_CHIP_RV370_5B60: 513 case PCI_CHIP_RV370_5B62: 514 case PCI_CHIP_RV370_5B63: 515 case PCI_CHIP_RV370_5B64: 516 case PCI_CHIP_RV370_5B65: 517 case PCI_CHIP_RV380_3150: 518 case PCI_CHIP_RV380_3152: 519 case PCI_CHIP_RV380_3154: 520 case PCI_CHIP_RV380_3155: 521 case PCI_CHIP_RV380_3E50: 522 case PCI_CHIP_RV380_3E54: 523 screen->chip_family = CHIP_FAMILY_RV380; 524 screen->chip_flags = RADEON_CHIPSET_TCL; 525 break; 526 527 case PCI_CHIP_R420_JN: 528 case PCI_CHIP_R420_JH: 529 case PCI_CHIP_R420_JI: 530 case PCI_CHIP_R420_JJ: 531 case PCI_CHIP_R420_JK: 532 case PCI_CHIP_R420_JL: 533 case PCI_CHIP_R420_JM: 534 case PCI_CHIP_R420_JO: 535 case PCI_CHIP_R420_JP: 536 case PCI_CHIP_R420_JT: 537 case PCI_CHIP_R481_4B49: 538 case PCI_CHIP_R481_4B4A: 539 case PCI_CHIP_R481_4B4B: 540 case PCI_CHIP_R481_4B4C: 541 case PCI_CHIP_R423_UH: 542 case PCI_CHIP_R423_UI: 543 case PCI_CHIP_R423_UJ: 544 case PCI_CHIP_R423_UK: 545 case PCI_CHIP_R430_554C: 546 case PCI_CHIP_R430_554D: 547 case PCI_CHIP_R430_554E: 548 case PCI_CHIP_R430_554F: 549 case PCI_CHIP_R423_5550: 550 case PCI_CHIP_R423_UQ: 551 case PCI_CHIP_R423_UR: 552 case PCI_CHIP_R423_UT: 553 case PCI_CHIP_R430_5D48: 554 case PCI_CHIP_R430_5D49: 555 case PCI_CHIP_R430_5D4A: 556 case PCI_CHIP_R480_5D4C: 557 case PCI_CHIP_R480_5D4D: 558 case PCI_CHIP_R480_5D4E: 559 case PCI_CHIP_R480_5D4F: 560 case PCI_CHIP_R480_5D50: 561 case PCI_CHIP_R480_5D52: 562 case PCI_CHIP_R423_5D57: 563 screen->chip_family = CHIP_FAMILY_R420; 564 screen->chip_flags = RADEON_CHIPSET_TCL; 565 break; 566 567 case PCI_CHIP_RV410_5E4C: 568 case PCI_CHIP_RV410_5E4F: 569 case PCI_CHIP_RV410_564A: 570 case PCI_CHIP_RV410_564B: 571 case PCI_CHIP_RV410_564F: 572 case PCI_CHIP_RV410_5652: 573 case PCI_CHIP_RV410_5653: 574 case PCI_CHIP_RV410_5657: 575 case PCI_CHIP_RV410_5E48: 576 case PCI_CHIP_RV410_5E4A: 577 case PCI_CHIP_RV410_5E4B: 578 case PCI_CHIP_RV410_5E4D: 579 screen->chip_family = CHIP_FAMILY_RV410; 580 screen->chip_flags = RADEON_CHIPSET_TCL; 581 break; 582 583 case PCI_CHIP_RS480_5954: 584 case PCI_CHIP_RS480_5955: 585 case PCI_CHIP_RS482_5974: 586 case PCI_CHIP_RS482_5975: 587 case PCI_CHIP_RS400_5A41: 588 case PCI_CHIP_RS400_5A42: 589 case PCI_CHIP_RC410_5A61: 590 case PCI_CHIP_RC410_5A62: 591 screen->chip_family = CHIP_FAMILY_RS400; 592 break; 593 594 case PCI_CHIP_RS600_793F: 595 case PCI_CHIP_RS600_7941: 596 case PCI_CHIP_RS600_7942: 597 screen->chip_family = CHIP_FAMILY_RS600; 598 break; 599 600 case PCI_CHIP_RS690_791E: 601 case PCI_CHIP_RS690_791F: 602 screen->chip_family = CHIP_FAMILY_RS690; 603 break; 604 case PCI_CHIP_RS740_796C: 605 case PCI_CHIP_RS740_796D: 606 case PCI_CHIP_RS740_796E: 607 case PCI_CHIP_RS740_796F: 608 screen->chip_family = CHIP_FAMILY_RS740; 609 break; 610 611 case PCI_CHIP_R520_7100: 612 case PCI_CHIP_R520_7101: 613 case PCI_CHIP_R520_7102: 614 case PCI_CHIP_R520_7103: 615 case PCI_CHIP_R520_7104: 616 case PCI_CHIP_R520_7105: 617 case PCI_CHIP_R520_7106: 618 case PCI_CHIP_R520_7108: 619 case PCI_CHIP_R520_7109: 620 case PCI_CHIP_R520_710A: 621 case PCI_CHIP_R520_710B: 622 case PCI_CHIP_R520_710C: 623 case PCI_CHIP_R520_710E: 624 case PCI_CHIP_R520_710F: 625 screen->chip_family = CHIP_FAMILY_R520; 626 screen->chip_flags = RADEON_CHIPSET_TCL; 627 break; 628 629 case PCI_CHIP_RV515_7140: 630 case PCI_CHIP_RV515_7141: 631 case PCI_CHIP_RV515_7142: 632 case PCI_CHIP_RV515_7143: 633 case PCI_CHIP_RV515_7144: 634 case PCI_CHIP_RV515_7145: 635 case PCI_CHIP_RV515_7146: 636 case PCI_CHIP_RV515_7147: 637 case PCI_CHIP_RV515_7149: 638 case PCI_CHIP_RV515_714A: 639 case PCI_CHIP_RV515_714B: 640 case PCI_CHIP_RV515_714C: 641 case PCI_CHIP_RV515_714D: 642 case PCI_CHIP_RV515_714E: 643 case PCI_CHIP_RV515_714F: 644 case PCI_CHIP_RV515_7151: 645 case PCI_CHIP_RV515_7152: 646 case PCI_CHIP_RV515_7153: 647 case PCI_CHIP_RV515_715E: 648 case PCI_CHIP_RV515_715F: 649 case PCI_CHIP_RV515_7180: 650 case PCI_CHIP_RV515_7181: 651 case PCI_CHIP_RV515_7183: 652 case PCI_CHIP_RV515_7186: 653 case PCI_CHIP_RV515_7187: 654 case PCI_CHIP_RV515_7188: 655 case PCI_CHIP_RV515_718A: 656 case PCI_CHIP_RV515_718B: 657 case PCI_CHIP_RV515_718C: 658 case PCI_CHIP_RV515_718D: 659 case PCI_CHIP_RV515_718F: 660 case PCI_CHIP_RV515_7193: 661 case PCI_CHIP_RV515_7196: 662 case PCI_CHIP_RV515_719B: 663 case PCI_CHIP_RV515_719F: 664 case PCI_CHIP_RV515_7200: 665 case PCI_CHIP_RV515_7210: 666 case PCI_CHIP_RV515_7211: 667 screen->chip_family = CHIP_FAMILY_RV515; 668 screen->chip_flags = RADEON_CHIPSET_TCL; 669 break; 670 671 case PCI_CHIP_RV530_71C0: 672 case PCI_CHIP_RV530_71C1: 673 case PCI_CHIP_RV530_71C2: 674 case PCI_CHIP_RV530_71C3: 675 case PCI_CHIP_RV530_71C4: 676 case PCI_CHIP_RV530_71C5: 677 case PCI_CHIP_RV530_71C6: 678 case PCI_CHIP_RV530_71C7: 679 case PCI_CHIP_RV530_71CD: 680 case PCI_CHIP_RV530_71CE: 681 case PCI_CHIP_RV530_71D2: 682 case PCI_CHIP_RV530_71D4: 683 case PCI_CHIP_RV530_71D5: 684 case PCI_CHIP_RV530_71D6: 685 case PCI_CHIP_RV530_71DA: 686 case PCI_CHIP_RV530_71DE: 687 screen->chip_family = CHIP_FAMILY_RV530; 688 screen->chip_flags = RADEON_CHIPSET_TCL; 689 break; 690 691 case PCI_CHIP_R580_7240: 692 case PCI_CHIP_R580_7243: 693 case PCI_CHIP_R580_7244: 694 case PCI_CHIP_R580_7245: 695 case PCI_CHIP_R580_7246: 696 case PCI_CHIP_R580_7247: 697 case PCI_CHIP_R580_7248: 698 case PCI_CHIP_R580_7249: 699 case PCI_CHIP_R580_724A: 700 case PCI_CHIP_R580_724B: 701 case PCI_CHIP_R580_724C: 702 case PCI_CHIP_R580_724D: 703 case PCI_CHIP_R580_724E: 704 case PCI_CHIP_R580_724F: 705 case PCI_CHIP_R580_7284: 706 screen->chip_family = CHIP_FAMILY_R580; 707 screen->chip_flags = RADEON_CHIPSET_TCL; 708 break; 709 710 case PCI_CHIP_RV570_7280: 711 case PCI_CHIP_RV560_7281: 712 case PCI_CHIP_RV560_7283: 713 case PCI_CHIP_RV560_7287: 714 case PCI_CHIP_RV570_7288: 715 case PCI_CHIP_RV570_7289: 716 case PCI_CHIP_RV570_728B: 717 case PCI_CHIP_RV570_728C: 718 case PCI_CHIP_RV560_7290: 719 case PCI_CHIP_RV560_7291: 720 case PCI_CHIP_RV560_7293: 721 case PCI_CHIP_RV560_7297: 722 screen->chip_family = CHIP_FAMILY_RV560; 723 screen->chip_flags = RADEON_CHIPSET_TCL; 724 break; 725 726 case PCI_CHIP_R600_9400: 727 case PCI_CHIP_R600_9401: 728 case PCI_CHIP_R600_9402: 729 case PCI_CHIP_R600_9403: 730 case PCI_CHIP_R600_9405: 731 case PCI_CHIP_R600_940A: 732 case PCI_CHIP_R600_940B: 733 case PCI_CHIP_R600_940F: 734 screen->chip_family = CHIP_FAMILY_R600; 735 screen->chip_flags = RADEON_CHIPSET_TCL; 736 break; 737 738 case PCI_CHIP_RV610_94C0: 739 case PCI_CHIP_RV610_94C1: 740 case PCI_CHIP_RV610_94C3: 741 case PCI_CHIP_RV610_94C4: 742 case PCI_CHIP_RV610_94C5: 743 case PCI_CHIP_RV610_94C6: 744 case PCI_CHIP_RV610_94C7: 745 case PCI_CHIP_RV610_94C8: 746 case PCI_CHIP_RV610_94C9: 747 case PCI_CHIP_RV610_94CB: 748 case PCI_CHIP_RV610_94CC: 749 case PCI_CHIP_RV610_94CD: 750 screen->chip_family = CHIP_FAMILY_RV610; 751 screen->chip_flags = RADEON_CHIPSET_TCL; 752 break; 753 754 case PCI_CHIP_RV630_9580: 755 case PCI_CHIP_RV630_9581: 756 case PCI_CHIP_RV630_9583: 757 case PCI_CHIP_RV630_9586: 758 case PCI_CHIP_RV630_9587: 759 case PCI_CHIP_RV630_9588: 760 case PCI_CHIP_RV630_9589: 761 case PCI_CHIP_RV630_958A: 762 case PCI_CHIP_RV630_958B: 763 case PCI_CHIP_RV630_958C: 764 case PCI_CHIP_RV630_958D: 765 case PCI_CHIP_RV630_958E: 766 case PCI_CHIP_RV630_958F: 767 screen->chip_family = CHIP_FAMILY_RV630; 768 screen->chip_flags = RADEON_CHIPSET_TCL; 769 break; 770 771 case PCI_CHIP_RV670_9500: 772 case PCI_CHIP_RV670_9501: 773 case PCI_CHIP_RV670_9504: 774 case PCI_CHIP_RV670_9505: 775 case PCI_CHIP_RV670_9506: 776 case PCI_CHIP_RV670_9507: 777 case PCI_CHIP_RV670_9508: 778 case PCI_CHIP_RV670_9509: 779 case PCI_CHIP_RV670_950F: 780 case PCI_CHIP_RV670_9511: 781 case PCI_CHIP_RV670_9515: 782 case PCI_CHIP_RV670_9517: 783 case PCI_CHIP_RV670_9519: 784 screen->chip_family = CHIP_FAMILY_RV670; 785 screen->chip_flags = RADEON_CHIPSET_TCL; 786 break; 787 788 case PCI_CHIP_RV620_95C0: 789 case PCI_CHIP_RV620_95C2: 790 case PCI_CHIP_RV620_95C4: 791 case PCI_CHIP_RV620_95C5: 792 case PCI_CHIP_RV620_95C6: 793 case PCI_CHIP_RV620_95C7: 794 case PCI_CHIP_RV620_95C9: 795 case PCI_CHIP_RV620_95CC: 796 case PCI_CHIP_RV620_95CD: 797 case PCI_CHIP_RV620_95CE: 798 case PCI_CHIP_RV620_95CF: 799 screen->chip_family = CHIP_FAMILY_RV620; 800 screen->chip_flags = RADEON_CHIPSET_TCL; 801 break; 802 803 case PCI_CHIP_RV635_9590: 804 case PCI_CHIP_RV635_9591: 805 case PCI_CHIP_RV635_9593: 806 case PCI_CHIP_RV635_9595: 807 case PCI_CHIP_RV635_9596: 808 case PCI_CHIP_RV635_9597: 809 case PCI_CHIP_RV635_9598: 810 case PCI_CHIP_RV635_9599: 811 case PCI_CHIP_RV635_959B: 812 screen->chip_family = CHIP_FAMILY_RV635; 813 screen->chip_flags = RADEON_CHIPSET_TCL; 814 break; 815 816 case PCI_CHIP_RS780_9610: 817 case PCI_CHIP_RS780_9611: 818 case PCI_CHIP_RS780_9612: 819 case PCI_CHIP_RS780_9613: 820 case PCI_CHIP_RS780_9614: 821 case PCI_CHIP_RS780_9615: 822 case PCI_CHIP_RS780_9616: 823 screen->chip_family = CHIP_FAMILY_RS780; 824 screen->chip_flags = RADEON_CHIPSET_TCL; 825 break; 826 case PCI_CHIP_RS880_9710: 827 case PCI_CHIP_RS880_9711: 828 case PCI_CHIP_RS880_9712: 829 case PCI_CHIP_RS880_9713: 830 case PCI_CHIP_RS880_9714: 831 case PCI_CHIP_RS880_9715: 832 screen->chip_family = CHIP_FAMILY_RS880; 833 screen->chip_flags = RADEON_CHIPSET_TCL; 834 break; 835 836 case PCI_CHIP_RV770_9440: 837 case PCI_CHIP_RV770_9441: 838 case PCI_CHIP_RV770_9442: 839 case PCI_CHIP_RV770_9443: 840 case PCI_CHIP_RV770_9444: 841 case PCI_CHIP_RV770_9446: 842 case PCI_CHIP_RV770_944A: 843 case PCI_CHIP_RV770_944B: 844 case PCI_CHIP_RV770_944C: 845 case PCI_CHIP_RV770_944E: 846 case PCI_CHIP_RV770_9450: 847 case PCI_CHIP_RV770_9452: 848 case PCI_CHIP_RV770_9456: 849 case PCI_CHIP_RV770_945A: 850 case PCI_CHIP_RV770_945B: 851 case PCI_CHIP_RV770_945E: 852 case PCI_CHIP_RV790_9460: 853 case PCI_CHIP_RV790_9462: 854 case PCI_CHIP_RV770_946A: 855 case PCI_CHIP_RV770_946B: 856 case PCI_CHIP_RV770_947A: 857 case PCI_CHIP_RV770_947B: 858 screen->chip_family = CHIP_FAMILY_RV770; 859 screen->chip_flags = RADEON_CHIPSET_TCL; 860 break; 861 862 case PCI_CHIP_RV730_9480: 863 case PCI_CHIP_RV730_9487: 864 case PCI_CHIP_RV730_9488: 865 case PCI_CHIP_RV730_9489: 866 case PCI_CHIP_RV730_948A: 867 case PCI_CHIP_RV730_948F: 868 case PCI_CHIP_RV730_9490: 869 case PCI_CHIP_RV730_9491: 870 case PCI_CHIP_RV730_9495: 871 case PCI_CHIP_RV730_9498: 872 case PCI_CHIP_RV730_949C: 873 case PCI_CHIP_RV730_949E: 874 case PCI_CHIP_RV730_949F: 875 screen->chip_family = CHIP_FAMILY_RV730; 876 screen->chip_flags = RADEON_CHIPSET_TCL; 877 break; 878 879 case PCI_CHIP_RV710_9540: 880 case PCI_CHIP_RV710_9541: 881 case PCI_CHIP_RV710_9542: 882 case PCI_CHIP_RV710_954E: 883 case PCI_CHIP_RV710_954F: 884 case PCI_CHIP_RV710_9552: 885 case PCI_CHIP_RV710_9553: 886 case PCI_CHIP_RV710_9555: 887 case PCI_CHIP_RV710_9557: 888 case PCI_CHIP_RV710_955F: 889 screen->chip_family = CHIP_FAMILY_RV710; 890 screen->chip_flags = RADEON_CHIPSET_TCL; 891 break; 892 893 case PCI_CHIP_RV740_94A0: 894 case PCI_CHIP_RV740_94A1: 895 case PCI_CHIP_RV740_94A3: 896 case PCI_CHIP_RV740_94B1: 897 case PCI_CHIP_RV740_94B3: 898 case PCI_CHIP_RV740_94B4: 899 case PCI_CHIP_RV740_94B5: 900 case PCI_CHIP_RV740_94B9: 901 screen->chip_family = CHIP_FAMILY_RV740; 902 screen->chip_flags = RADEON_CHIPSET_TCL; 903 break; 904 905 case PCI_CHIP_CEDAR_68E0: 906 case PCI_CHIP_CEDAR_68E1: 907 case PCI_CHIP_CEDAR_68E4: 908 case PCI_CHIP_CEDAR_68E5: 909 case PCI_CHIP_CEDAR_68E8: 910 case PCI_CHIP_CEDAR_68E9: 911 case PCI_CHIP_CEDAR_68F1: 912 case PCI_CHIP_CEDAR_68F2: 913 case PCI_CHIP_CEDAR_68F8: 914 case PCI_CHIP_CEDAR_68F9: 915 case PCI_CHIP_CEDAR_68FE: 916 screen->chip_family = CHIP_FAMILY_CEDAR; 917 screen->chip_flags = RADEON_CHIPSET_TCL; 918 break; 919 920 case PCI_CHIP_REDWOOD_68C0: 921 case PCI_CHIP_REDWOOD_68C1: 922 case PCI_CHIP_REDWOOD_68C8: 923 case PCI_CHIP_REDWOOD_68C9: 924 case PCI_CHIP_REDWOOD_68D8: 925 case PCI_CHIP_REDWOOD_68D9: 926 case PCI_CHIP_REDWOOD_68DA: 927 case PCI_CHIP_REDWOOD_68DE: 928 screen->chip_family = CHIP_FAMILY_REDWOOD; 929 screen->chip_flags = RADEON_CHIPSET_TCL; 930 break; 931 932 case PCI_CHIP_JUNIPER_68A0: 933 case PCI_CHIP_JUNIPER_68A1: 934 case PCI_CHIP_JUNIPER_68A8: 935 case PCI_CHIP_JUNIPER_68A9: 936 case PCI_CHIP_JUNIPER_68B0: 937 case PCI_CHIP_JUNIPER_68B8: 938 case PCI_CHIP_JUNIPER_68B9: 939 case PCI_CHIP_JUNIPER_68BA: 940 case PCI_CHIP_JUNIPER_68BE: 941 case PCI_CHIP_JUNIPER_68BF: 942 screen->chip_family = CHIP_FAMILY_JUNIPER; 943 screen->chip_flags = RADEON_CHIPSET_TCL; 944 break; 945 946 case PCI_CHIP_CYPRESS_6880: 947 case PCI_CHIP_CYPRESS_6888: 948 case PCI_CHIP_CYPRESS_6889: 949 case PCI_CHIP_CYPRESS_688A: 950 case PCI_CHIP_CYPRESS_6898: 951 case PCI_CHIP_CYPRESS_6899: 952 case PCI_CHIP_CYPRESS_689B: 953 case PCI_CHIP_CYPRESS_689E: 954 screen->chip_family = CHIP_FAMILY_CYPRESS; 955 screen->chip_flags = RADEON_CHIPSET_TCL; 956 break; 957 958 case PCI_CHIP_HEMLOCK_689C: 959 case PCI_CHIP_HEMLOCK_689D: 960 screen->chip_family = CHIP_FAMILY_HEMLOCK; 961 screen->chip_flags = RADEON_CHIPSET_TCL; 962 break; 963 964 case PCI_CHIP_PALM_9802: 965 case PCI_CHIP_PALM_9803: 966 case PCI_CHIP_PALM_9804: 967 case PCI_CHIP_PALM_9805: 968 case PCI_CHIP_PALM_9806: 969 case PCI_CHIP_PALM_9807: 970 screen->chip_family = CHIP_FAMILY_PALM; 971 screen->chip_flags = RADEON_CHIPSET_TCL; 972 break; 973 974 case PCI_CHIP_SUMO_9640: 975 case PCI_CHIP_SUMO_9641: 976 case PCI_CHIP_SUMO_9647: 977 case PCI_CHIP_SUMO_9648: 978 case PCI_CHIP_SUMO_964A: 979 case PCI_CHIP_SUMO_964E: 980 case PCI_CHIP_SUMO_964F: 981 screen->chip_family = CHIP_FAMILY_SUMO; 982 screen->chip_flags = RADEON_CHIPSET_TCL; 983 break; 984 985 case PCI_CHIP_SUMO2_9642: 986 case PCI_CHIP_SUMO2_9643: 987 case PCI_CHIP_SUMO2_9644: 988 case PCI_CHIP_SUMO2_9645: 989 screen->chip_family = CHIP_FAMILY_SUMO2; 990 screen->chip_flags = RADEON_CHIPSET_TCL; 991 break; 992 993 case PCI_CHIP_BARTS_6720: 994 case PCI_CHIP_BARTS_6721: 995 case PCI_CHIP_BARTS_6722: 996 case PCI_CHIP_BARTS_6723: 997 case PCI_CHIP_BARTS_6724: 998 case PCI_CHIP_BARTS_6725: 999 case PCI_CHIP_BARTS_6726: 1000 case PCI_CHIP_BARTS_6727: 1001 case PCI_CHIP_BARTS_6728: 1002 case PCI_CHIP_BARTS_6729: 1003 case PCI_CHIP_BARTS_6738: 1004 case PCI_CHIP_BARTS_6739: 1005 case PCI_CHIP_BARTS_673E: 1006 screen->chip_family = CHIP_FAMILY_BARTS; 1007 screen->chip_flags = RADEON_CHIPSET_TCL; 1008 break; 1009 1010 case PCI_CHIP_TURKS_6740: 1011 case PCI_CHIP_TURKS_6741: 1012 case PCI_CHIP_TURKS_6742: 1013 case PCI_CHIP_TURKS_6743: 1014 case PCI_CHIP_TURKS_6744: 1015 case PCI_CHIP_TURKS_6745: 1016 case PCI_CHIP_TURKS_6746: 1017 case PCI_CHIP_TURKS_6747: 1018 case PCI_CHIP_TURKS_6748: 1019 case PCI_CHIP_TURKS_6749: 1020 case PCI_CHIP_TURKS_6750: 1021 case PCI_CHIP_TURKS_6758: 1022 case PCI_CHIP_TURKS_6759: 1023 case PCI_CHIP_TURKS_675F: 1024 screen->chip_family = CHIP_FAMILY_TURKS; 1025 screen->chip_flags = RADEON_CHIPSET_TCL; 1026 break; 1027 1028 case PCI_CHIP_CAICOS_6760: 1029 case PCI_CHIP_CAICOS_6761: 1030 case PCI_CHIP_CAICOS_6762: 1031 case PCI_CHIP_CAICOS_6763: 1032 case PCI_CHIP_CAICOS_6764: 1033 case PCI_CHIP_CAICOS_6765: 1034 case PCI_CHIP_CAICOS_6766: 1035 case PCI_CHIP_CAICOS_6767: 1036 case PCI_CHIP_CAICOS_6768: 1037 case PCI_CHIP_CAICOS_6770: 1038 case PCI_CHIP_CAICOS_6778: 1039 case PCI_CHIP_CAICOS_6779: 1040 screen->chip_family = CHIP_FAMILY_CAICOS; 1041 screen->chip_flags = RADEON_CHIPSET_TCL; 1042 break; 1043 1044 default: 1045 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 1046 device_id); 1047 return -1; 1048 } 1049 1050 return 0; 1051} 1052 1053static radeonScreenPtr 1054radeonCreateScreen2(__DRIscreen *sPriv) 1055{ 1056 radeonScreenPtr screen; 1057 int i; 1058 int ret; 1059 uint32_t device_id = 0; 1060 1061 /* Allocate the private area */ 1062 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1063 if ( !screen ) { 1064 __driUtilMessage("%s: Could not allocate memory for screen structure", 1065 __FUNCTION__); 1066 fprintf(stderr, "leaving here\n"); 1067 return NULL; 1068 } 1069 1070 radeon_init_debug(); 1071 1072 /* parse information in __driConfigOptions */ 1073 driParseOptionInfo (&screen->optionCache, 1074 __driConfigOptions, __driNConfigOptions); 1075 1076 screen->chip_flags = 0; 1077 1078 screen->irq = 1; 1079 1080 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1081 if (ret) { 1082 FREE( screen ); 1083 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1084 return NULL; 1085 } 1086 1087 ret = radeon_set_screen_flags(screen, device_id); 1088 if (ret == -1) 1089 return NULL; 1090 1091 if (getenv("R300_NO_TCL")) 1092 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1093 1094 if (screen->chip_family <= CHIP_FAMILY_RS200) 1095 screen->chip_flags |= RADEON_CLASS_R100; 1096 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1097 screen->chip_flags |= RADEON_CLASS_R200; 1098 1099 i = 0; 1100 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1101 1102#if defined(RADEON_R100) 1103 screen->extensions[i++] = &radeonTexBufferExtension.base; 1104#endif 1105 1106#if defined(RADEON_R200) 1107 screen->extensions[i++] = &r200TexBufferExtension.base; 1108#endif 1109 1110 screen->extensions[i++] = &radeonFlushExtension.base; 1111 screen->extensions[i++] = &radeonImageExtension.base; 1112 1113 screen->extensions[i++] = NULL; 1114 sPriv->extensions = screen->extensions; 1115 1116 screen->driScreen = sPriv; 1117 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1118 if (screen->bom == NULL) { 1119 free(screen); 1120 return NULL; 1121 } 1122 return screen; 1123} 1124 1125/* Destroy the device specific screen private data struct. 1126 */ 1127static void 1128radeonDestroyScreen( __DRIscreen *sPriv ) 1129{ 1130 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1131 1132 if (!screen) 1133 return; 1134 1135#ifdef RADEON_BO_TRACK 1136 radeon_tracker_print(&screen->bom->tracker, stderr); 1137#endif 1138 radeon_bo_manager_gem_dtor(screen->bom); 1139 1140 /* free all option information */ 1141 driDestroyOptionInfo (&screen->optionCache); 1142 1143 FREE( screen ); 1144 sPriv->private = NULL; 1145} 1146 1147 1148/* Initialize the driver specific screen private data. 1149 */ 1150static GLboolean 1151radeonInitDriver( __DRIscreen *sPriv ) 1152{ 1153 assert(sPriv->dri2.enabled); 1154 1155 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1156 if ( !sPriv->private ) { 1157 radeonDestroyScreen( sPriv ); 1158 return GL_FALSE; 1159 } 1160 1161 return GL_TRUE; 1162} 1163 1164 1165 1166/** 1167 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1168 * 1169 * \todo This function (and its interface) will need to be updated to support 1170 * pbuffers. 1171 */ 1172static GLboolean 1173radeonCreateBuffer( __DRIscreen *driScrnPriv, 1174 __DRIdrawable *driDrawPriv, 1175 const struct gl_config *mesaVis, 1176 GLboolean isPixmap ) 1177{ 1178 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1179 1180 const GLboolean swDepth = GL_FALSE; 1181 const GLboolean swAlpha = GL_FALSE; 1182 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1183 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1184 mesaVis->depthBits != 24; 1185 gl_format rgbFormat; 1186 struct radeon_framebuffer *rfb; 1187 1188 if (isPixmap) 1189 return GL_FALSE; /* not implemented */ 1190 1191 rfb = CALLOC_STRUCT(radeon_framebuffer); 1192 if (!rfb) 1193 return GL_FALSE; 1194 1195 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis); 1196 1197 if (mesaVis->redBits == 5) 1198 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV; 1199 else if (mesaVis->alphaBits == 0) 1200 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV; 1201 else 1202 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV; 1203 1204 /* front color renderbuffer */ 1205 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1206 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1207 rfb->color_rb[0]->has_surface = 1; 1208 1209 /* back color renderbuffer */ 1210 if (mesaVis->doubleBufferMode) { 1211 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1212 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1213 rfb->color_rb[1]->has_surface = 1; 1214 } 1215 1216 if (mesaVis->depthBits == 24) { 1217 if (mesaVis->stencilBits == 8) { 1218 struct radeon_renderbuffer *depthStencilRb = 1219 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); 1220 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1221 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1222 depthStencilRb->has_surface = screen->depthHasSurface; 1223 } else { 1224 /* depth renderbuffer */ 1225 struct radeon_renderbuffer *depth = 1226 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); 1227 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1228 depth->has_surface = screen->depthHasSurface; 1229 } 1230 } else if (mesaVis->depthBits == 16) { 1231 /* just 16-bit depth buffer, no hw stencil */ 1232 struct radeon_renderbuffer *depth = 1233 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); 1234 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1235 depth->has_surface = screen->depthHasSurface; 1236 } 1237 1238 _mesa_add_soft_renderbuffers(&rfb->base, 1239 GL_FALSE, /* color */ 1240 swDepth, 1241 swStencil, 1242 swAccum, 1243 swAlpha, 1244 GL_FALSE /* aux */); 1245 driDrawPriv->driverPrivate = (void *) rfb; 1246 1247 return (driDrawPriv->driverPrivate != NULL); 1248} 1249 1250 1251static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1252{ 1253 struct radeon_renderbuffer *rb; 1254 1255 rb = rfb->color_rb[0]; 1256 if (rb && rb->bo) { 1257 radeon_bo_unref(rb->bo); 1258 rb->bo = NULL; 1259 } 1260 rb = rfb->color_rb[1]; 1261 if (rb && rb->bo) { 1262 radeon_bo_unref(rb->bo); 1263 rb->bo = NULL; 1264 } 1265 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1266 if (rb && rb->bo) { 1267 radeon_bo_unref(rb->bo); 1268 rb->bo = NULL; 1269 } 1270} 1271 1272void 1273radeonDestroyBuffer(__DRIdrawable *driDrawPriv) 1274{ 1275 struct radeon_framebuffer *rfb; 1276 if (!driDrawPriv) 1277 return; 1278 1279 rfb = (void*)driDrawPriv->driverPrivate; 1280 if (!rfb) 1281 return; 1282 radeon_cleanup_renderbuffers(rfb); 1283 _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1284} 1285 1286#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1287 1288/** 1289 * This is the driver specific part of the createNewScreen entry point. 1290 * Called when using DRI2. 1291 * 1292 * \return the struct gl_config supported by this driver 1293 */ 1294static const 1295__DRIconfig **radeonInitScreen2(__DRIscreen *psp) 1296{ 1297 GLenum fb_format[3]; 1298 GLenum fb_type[3]; 1299 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1300 * support pageflipping at all. 1301 */ 1302 static const GLenum back_buffer_modes[] = { 1303 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1304 }; 1305 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1306 int color; 1307 __DRIconfig **configs = NULL; 1308 1309 if (!radeonInitDriver(psp)) { 1310 return NULL; 1311 } 1312 depth_bits[0] = 0; 1313 stencil_bits[0] = 0; 1314 depth_bits[1] = 16; 1315 stencil_bits[1] = 0; 1316 depth_bits[2] = 24; 1317 stencil_bits[2] = 0; 1318 depth_bits[3] = 24; 1319 stencil_bits[3] = 8; 1320 1321 msaa_samples_array[0] = 0; 1322 1323 fb_format[0] = GL_RGB; 1324 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1325 1326 fb_format[1] = GL_BGR; 1327 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1328 1329 fb_format[2] = GL_BGRA; 1330 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1331 1332 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1333 __DRIconfig **new_configs; 1334 1335 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1336 depth_bits, 1337 stencil_bits, 1338 ARRAY_SIZE(depth_bits), 1339 back_buffer_modes, 1340 ARRAY_SIZE(back_buffer_modes), 1341 msaa_samples_array, 1342 ARRAY_SIZE(msaa_samples_array), 1343 GL_TRUE); 1344 if (configs == NULL) 1345 configs = new_configs; 1346 else 1347 configs = driConcatConfigs(configs, new_configs); 1348 } 1349 1350 if (configs == NULL) { 1351 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1352 __LINE__); 1353 return NULL; 1354 } 1355 1356 return (const __DRIconfig **)configs; 1357} 1358 1359const struct __DriverAPIRec driDriverAPI = { 1360 .DestroyScreen = radeonDestroyScreen, 1361#if defined(RADEON_R200) 1362 .CreateContext = r200CreateContext, 1363 .DestroyContext = r200DestroyContext, 1364#else 1365 .CreateContext = r100CreateContext, 1366 .DestroyContext = radeonDestroyContext, 1367#endif 1368 .CreateBuffer = radeonCreateBuffer, 1369 .DestroyBuffer = radeonDestroyBuffer, 1370 .MakeCurrent = radeonMakeCurrent, 1371 .UnbindContext = radeonUnbindContext, 1372 /* DRI2 */ 1373 .InitScreen2 = radeonInitScreen2, 1374}; 1375 1376/* This is the table of extensions that the loader will dlsym() for. */ 1377PUBLIC const __DRIextension *__driDriverExtensions[] = { 1378 &driCoreExtension.base, 1379 &driDRI2Extension.base, 1380 NULL 1381}; 1382