radeon_screen.c revision 7ac2f655f845a7a100939a9b1b2251535055ab84
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#include "radeon_span.h" 51#if !RADEON_COMMON 52#include "radeon_context.h" 53#include "radeon_tex.h" 54#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_tex.h" 58#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59#include "r300_context.h" 60#include "r300_fragprog.h" 61#include "r300_tex.h" 62#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 63#include "r600_context.h" 64#include "r700_driconf.h" /* +r6/r7 */ 65#include "r700_tex.h" /* +r6/r7 */ 66#endif 67 68#include "utils.h" 69#include "vblank.h" 70#include "drirenderbuffer.h" 71 72#include "radeon_bocs_wrapper.h" 73 74#include "GL/internal/dri_interface.h" 75 76/* Radeon configuration 77 */ 78#include "xmlpool.h" 79 80#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 81DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 82 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 83 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 84DRI_CONF_OPT_END 85 86#if !RADEON_COMMON /* R100 */ 87PUBLIC const char __driConfigOptions[] = 88DRI_CONF_BEGIN 89 DRI_CONF_SECTION_PERFORMANCE 90 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 91 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 92 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 93 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 94 DRI_CONF_HYPERZ(false) 95 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 96 DRI_CONF_SECTION_END 97 DRI_CONF_SECTION_QUALITY 98 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 99 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 100 DRI_CONF_NO_NEG_LOD_BIAS(false) 101 DRI_CONF_FORCE_S3TC_ENABLE(false) 102 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 103 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 104 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 105 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 106 DRI_CONF_SECTION_END 107 DRI_CONF_SECTION_DEBUG 108 DRI_CONF_NO_RAST(false) 109 DRI_CONF_SECTION_END 110DRI_CONF_END; 111static const GLuint __driNConfigOptions = 15; 112 113#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 114 115PUBLIC const char __driConfigOptions[] = 116DRI_CONF_BEGIN 117 DRI_CONF_SECTION_PERFORMANCE 118 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 119 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 120 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 121 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 122 DRI_CONF_HYPERZ(false) 123 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 124 DRI_CONF_SECTION_END 125 DRI_CONF_SECTION_QUALITY 126 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 127 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 128 DRI_CONF_NO_NEG_LOD_BIAS(false) 129 DRI_CONF_FORCE_S3TC_ENABLE(false) 130 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 131 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 132 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 133 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 134 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 135 DRI_CONF_SECTION_END 136 DRI_CONF_SECTION_DEBUG 137 DRI_CONF_NO_RAST(false) 138 DRI_CONF_SECTION_END 139 DRI_CONF_SECTION_SOFTWARE 140 DRI_CONF_NV_VERTEX_PROGRAM(false) 141 DRI_CONF_SECTION_END 142DRI_CONF_END; 143static const GLuint __driNConfigOptions = 17; 144 145extern const struct dri_extension blend_extensions[]; 146extern const struct dri_extension ARB_vp_extension[]; 147extern const struct dri_extension NV_vp_extension[]; 148extern const struct dri_extension ATI_fs_extension[]; 149extern const struct dri_extension point_extensions[]; 150 151#elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 152 153/* TODO: integrate these into xmlpool.h! */ 154#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 155DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 156 DRI_CONF_DESC(en,"Number of texture image units") \ 157 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 158DRI_CONF_OPT_END 159 160#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 161DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 162 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 163 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 164DRI_CONF_OPT_END 165 166 167 168#define DRI_CONF_DISABLE_S3TC(def) \ 169DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 170 DRI_CONF_DESC(en,"Disable S3TC compression") \ 171DRI_CONF_OPT_END 172 173#define DRI_CONF_DISABLE_FALLBACK(def) \ 174DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 175 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 176DRI_CONF_OPT_END 177 178#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 179DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 180 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 181DRI_CONF_OPT_END 182 183#define DRI_CONF_FP_OPTIMIZATION(def) \ 184DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 185 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 186 DRI_CONF_ENUM(0,"Optimize for Speed") \ 187 DRI_CONF_ENUM(1,"Optimize for Quality") \ 188 DRI_CONF_DESC_END \ 189DRI_CONF_OPT_END 190 191PUBLIC const char __driConfigOptions[] = 192DRI_CONF_BEGIN 193 DRI_CONF_SECTION_PERFORMANCE 194 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 195 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 196 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 197 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 198 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 199 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 200 DRI_CONF_DISABLE_FALLBACK(true) 201 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 202 DRI_CONF_SECTION_END 203 DRI_CONF_SECTION_QUALITY 204 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 205 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 206 DRI_CONF_FORCE_S3TC_ENABLE(false) 207 DRI_CONF_DISABLE_S3TC(false) 208 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 209 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 210 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 211 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 212 DRI_CONF_SECTION_END 213 DRI_CONF_SECTION_DEBUG 214 DRI_CONF_NO_RAST(false) 215 DRI_CONF_SECTION_END 216DRI_CONF_END; 217static const GLuint __driNConfigOptions = 17; 218 219extern const struct dri_extension gl_20_extension[]; 220 221#ifndef RADEON_DEBUG 222 223static const struct dri_debug_control debug_control[] = { 224 {"fall", DEBUG_FALLBACKS}, 225 {"tex", DEBUG_TEXTURE}, 226 {"ioctl", DEBUG_IOCTL}, 227 {"prim", DEBUG_PRIMS}, 228 {"vert", DEBUG_VERTS}, 229 {"state", DEBUG_STATE}, 230 {"code", DEBUG_CODEGEN}, 231 {"vfmt", DEBUG_VFMT}, 232 {"vtxf", DEBUG_VFMT}, 233 {"verb", DEBUG_VERBOSE}, 234 {"dri", DEBUG_DRI}, 235 {"dma", DEBUG_DMA}, 236 {"san", DEBUG_SANITY}, 237 {"sync", DEBUG_SYNC}, 238 {"pix", DEBUG_PIXEL}, 239 {"mem", DEBUG_MEMORY}, 240 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 241 {NULL, 0} 242}; 243#endif /* RADEON_DEBUG */ 244 245#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 246 247extern const struct dri_extension card_extensions[]; 248extern const struct dri_extension mm_extensions[]; 249 250static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 251 252static int 253radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) 254{ 255 int ret; 256 drm_radeon_getparam_t gp; 257 struct drm_radeon_info info; 258 259 if (sPriv->drm_version.major >= 2) { 260 info.value = (uint64_t)value; 261 switch (param) { 262 case RADEON_PARAM_DEVICE_ID: 263 info.request = RADEON_INFO_DEVICE_ID; 264 break; 265 case RADEON_PARAM_NUM_GB_PIPES: 266 info.request = RADEON_INFO_NUM_GB_PIPES; 267 break; 268 default: 269 return -EINVAL; 270 } 271 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 272 } else { 273 gp.param = param; 274 gp.value = value; 275 276 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 277 } 278 return ret; 279} 280 281static const __DRIconfig ** 282radeonFillInModes( __DRIscreenPrivate *psp, 283 unsigned pixel_bits, unsigned depth_bits, 284 unsigned stencil_bits, GLboolean have_back_buffer ) 285{ 286 __DRIconfig **configs; 287 __GLcontextModes *m; 288 unsigned depth_buffer_factor; 289 unsigned back_buffer_factor; 290 int i; 291 292 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 293 * enough to add support. Basically, if a context is created with an 294 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 295 * will never be used. 296 */ 297 static const GLenum back_buffer_modes[] = { 298 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 299 }; 300 301 uint8_t depth_bits_array[2]; 302 uint8_t stencil_bits_array[2]; 303 uint8_t msaa_samples_array[1]; 304 305 depth_bits_array[0] = depth_bits; 306 depth_bits_array[1] = depth_bits; 307 308 /* Just like with the accumulation buffer, always provide some modes 309 * with a stencil buffer. It will be a sw fallback, but some apps won't 310 * care about that. 311 */ 312 stencil_bits_array[0] = 0; 313 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 314 315 msaa_samples_array[0] = 0; 316 317 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 318 back_buffer_factor = (have_back_buffer) ? 2 : 1; 319 320 if (pixel_bits == 16) { 321 __DRIconfig **configs_a8r8g8b8; 322 __DRIconfig **configs_r5g6b5; 323 324 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 325 depth_bits_array, stencil_bits_array, 326 depth_buffer_factor, back_buffer_modes, 327 back_buffer_factor, msaa_samples_array, 328 1); 329 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 330 depth_bits_array, stencil_bits_array, 331 1, back_buffer_modes, 1, 332 msaa_samples_array, 1); 333 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 334 } else 335 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 336 depth_bits_array, stencil_bits_array, 337 depth_buffer_factor, 338 back_buffer_modes, back_buffer_factor, 339 msaa_samples_array, 1); 340 341 if (configs == NULL) { 342 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 343 __func__, __LINE__ ); 344 return NULL; 345 } 346 347 /* Mark the visual as slow if there are "fake" stencil bits. 348 */ 349 for (i = 0; configs[i]; i++) { 350 m = &configs[i]->modes; 351 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 352 m->visualRating = GLX_SLOW_CONFIG; 353 } 354 } 355 356 return (const __DRIconfig **) configs; 357} 358 359#if !RADEON_COMMON 360static const __DRItexOffsetExtension radeonTexOffsetExtension = { 361 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 362 radeonSetTexOffset, 363}; 364 365static const __DRItexBufferExtension radeonTexBufferExtension = { 366 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 367 radeonSetTexBuffer, 368 radeonSetTexBuffer2, 369}; 370#endif 371 372#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 373static const __DRIallocateExtension r200AllocateExtension = { 374 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 375 r200AllocateMemoryMESA, 376 r200FreeMemoryMESA, 377 r200GetMemoryOffsetMESA 378}; 379 380static const __DRItexOffsetExtension r200texOffsetExtension = { 381 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 382 r200SetTexOffset, 383}; 384 385static const __DRItexBufferExtension r200TexBufferExtension = { 386 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 387 r200SetTexBuffer, 388 r200SetTexBuffer2, 389}; 390#endif 391 392#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 393static const __DRItexOffsetExtension r300texOffsetExtension = { 394 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 395 r300SetTexOffset, 396}; 397 398static const __DRItexBufferExtension r300TexBufferExtension = { 399 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 400 r300SetTexBuffer, 401 r300SetTexBuffer2, 402}; 403#endif 404 405#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 406static const __DRItexOffsetExtension r600texOffsetExtension = { 407 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 408 r700SetTexOffset, /* +r6/r7 */ 409}; 410 411static const __DRItexBufferExtension r600TexBufferExtension = { 412 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 413 r700SetTexBuffer, /* +r6/r7 */ 414 r700SetTexBuffer2, /* +r6/r7 */ 415}; 416#endif 417 418static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 419{ 420 screen->chip_flags = 0; 421 switch ( device_id ) { 422 case PCI_CHIP_RADEON_LY: 423 case PCI_CHIP_RADEON_LZ: 424 case PCI_CHIP_RADEON_QY: 425 case PCI_CHIP_RADEON_QZ: 426 case PCI_CHIP_RN50_515E: 427 case PCI_CHIP_RN50_5969: 428 screen->chip_family = CHIP_FAMILY_RV100; 429 break; 430 431 case PCI_CHIP_RS100_4136: 432 case PCI_CHIP_RS100_4336: 433 screen->chip_family = CHIP_FAMILY_RS100; 434 break; 435 436 case PCI_CHIP_RS200_4137: 437 case PCI_CHIP_RS200_4337: 438 case PCI_CHIP_RS250_4237: 439 case PCI_CHIP_RS250_4437: 440 screen->chip_family = CHIP_FAMILY_RS200; 441 break; 442 443 case PCI_CHIP_RADEON_QD: 444 case PCI_CHIP_RADEON_QE: 445 case PCI_CHIP_RADEON_QF: 446 case PCI_CHIP_RADEON_QG: 447 /* all original radeons (7200) presumably have a stencil op bug */ 448 screen->chip_family = CHIP_FAMILY_R100; 449 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 450 break; 451 452 case PCI_CHIP_RV200_QW: 453 case PCI_CHIP_RV200_QX: 454 case PCI_CHIP_RADEON_LW: 455 case PCI_CHIP_RADEON_LX: 456 screen->chip_family = CHIP_FAMILY_RV200; 457 screen->chip_flags = RADEON_CHIPSET_TCL; 458 break; 459 460 case PCI_CHIP_R200_BB: 461 case PCI_CHIP_R200_BC: 462 case PCI_CHIP_R200_QH: 463 case PCI_CHIP_R200_QL: 464 case PCI_CHIP_R200_QM: 465 screen->chip_family = CHIP_FAMILY_R200; 466 screen->chip_flags = RADEON_CHIPSET_TCL; 467 break; 468 469 case PCI_CHIP_RV250_If: 470 case PCI_CHIP_RV250_Ig: 471 case PCI_CHIP_RV250_Ld: 472 case PCI_CHIP_RV250_Lf: 473 case PCI_CHIP_RV250_Lg: 474 screen->chip_family = CHIP_FAMILY_RV250; 475 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 476 break; 477 478 case PCI_CHIP_RV280_5960: 479 case PCI_CHIP_RV280_5961: 480 case PCI_CHIP_RV280_5962: 481 case PCI_CHIP_RV280_5964: 482 case PCI_CHIP_RV280_5965: 483 case PCI_CHIP_RV280_5C61: 484 case PCI_CHIP_RV280_5C63: 485 screen->chip_family = CHIP_FAMILY_RV280; 486 screen->chip_flags = RADEON_CHIPSET_TCL; 487 break; 488 489 case PCI_CHIP_RS300_5834: 490 case PCI_CHIP_RS300_5835: 491 case PCI_CHIP_RS350_7834: 492 case PCI_CHIP_RS350_7835: 493 screen->chip_family = CHIP_FAMILY_RS300; 494 break; 495 496 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 497 case PCI_CHIP_R300_AD: 498 screen->chip_family = CHIP_FAMILY_RV350; 499 screen->chip_flags = RADEON_CHIPSET_TCL; 500 break; 501 case PCI_CHIP_R300_AE: 502 case PCI_CHIP_R300_AF: 503 case PCI_CHIP_R300_AG: 504 case PCI_CHIP_R300_ND: 505 case PCI_CHIP_R300_NE: 506 case PCI_CHIP_R300_NF: 507 case PCI_CHIP_R300_NG: 508 screen->chip_family = CHIP_FAMILY_R300; 509 screen->chip_flags = RADEON_CHIPSET_TCL; 510 break; 511 512 case PCI_CHIP_RV350_AP: 513 case PCI_CHIP_RV350_AQ: 514 case PCI_CHIP_RV350_AR: 515 case PCI_CHIP_RV350_AS: 516 case PCI_CHIP_RV350_AT: 517 case PCI_CHIP_RV350_AV: 518 case PCI_CHIP_RV350_AU: 519 case PCI_CHIP_RV350_NP: 520 case PCI_CHIP_RV350_NQ: 521 case PCI_CHIP_RV350_NR: 522 case PCI_CHIP_RV350_NS: 523 case PCI_CHIP_RV350_NT: 524 case PCI_CHIP_RV350_NV: 525 screen->chip_family = CHIP_FAMILY_RV350; 526 screen->chip_flags = RADEON_CHIPSET_TCL; 527 break; 528 529 case PCI_CHIP_R350_AH: 530 case PCI_CHIP_R350_AI: 531 case PCI_CHIP_R350_AJ: 532 case PCI_CHIP_R350_AK: 533 case PCI_CHIP_R350_NH: 534 case PCI_CHIP_R350_NI: 535 case PCI_CHIP_R360_NJ: 536 case PCI_CHIP_R350_NK: 537 screen->chip_family = CHIP_FAMILY_R350; 538 screen->chip_flags = RADEON_CHIPSET_TCL; 539 break; 540 541 case PCI_CHIP_RV370_5460: 542 case PCI_CHIP_RV370_5462: 543 case PCI_CHIP_RV370_5464: 544 case PCI_CHIP_RV370_5B60: 545 case PCI_CHIP_RV370_5B62: 546 case PCI_CHIP_RV370_5B63: 547 case PCI_CHIP_RV370_5B64: 548 case PCI_CHIP_RV370_5B65: 549 case PCI_CHIP_RV380_3150: 550 case PCI_CHIP_RV380_3152: 551 case PCI_CHIP_RV380_3154: 552 case PCI_CHIP_RV380_3E50: 553 case PCI_CHIP_RV380_3E54: 554 screen->chip_family = CHIP_FAMILY_RV380; 555 screen->chip_flags = RADEON_CHIPSET_TCL; 556 break; 557 558 case PCI_CHIP_R420_JN: 559 case PCI_CHIP_R420_JH: 560 case PCI_CHIP_R420_JI: 561 case PCI_CHIP_R420_JJ: 562 case PCI_CHIP_R420_JK: 563 case PCI_CHIP_R420_JL: 564 case PCI_CHIP_R420_JM: 565 case PCI_CHIP_R420_JO: 566 case PCI_CHIP_R420_JP: 567 case PCI_CHIP_R420_JT: 568 case PCI_CHIP_R481_4B49: 569 case PCI_CHIP_R481_4B4A: 570 case PCI_CHIP_R481_4B4B: 571 case PCI_CHIP_R481_4B4C: 572 case PCI_CHIP_R423_UH: 573 case PCI_CHIP_R423_UI: 574 case PCI_CHIP_R423_UJ: 575 case PCI_CHIP_R423_UK: 576 case PCI_CHIP_R430_554C: 577 case PCI_CHIP_R430_554D: 578 case PCI_CHIP_R430_554E: 579 case PCI_CHIP_R430_554F: 580 case PCI_CHIP_R423_5550: 581 case PCI_CHIP_R423_UQ: 582 case PCI_CHIP_R423_UR: 583 case PCI_CHIP_R423_UT: 584 case PCI_CHIP_R430_5D48: 585 case PCI_CHIP_R430_5D49: 586 case PCI_CHIP_R430_5D4A: 587 case PCI_CHIP_R480_5D4C: 588 case PCI_CHIP_R480_5D4D: 589 case PCI_CHIP_R480_5D4E: 590 case PCI_CHIP_R480_5D4F: 591 case PCI_CHIP_R480_5D50: 592 case PCI_CHIP_R480_5D52: 593 case PCI_CHIP_R423_5D57: 594 screen->chip_family = CHIP_FAMILY_R420; 595 screen->chip_flags = RADEON_CHIPSET_TCL; 596 break; 597 598 case PCI_CHIP_RV410_5E4C: 599 case PCI_CHIP_RV410_5E4F: 600 case PCI_CHIP_RV410_564A: 601 case PCI_CHIP_RV410_564B: 602 case PCI_CHIP_RV410_564F: 603 case PCI_CHIP_RV410_5652: 604 case PCI_CHIP_RV410_5653: 605 case PCI_CHIP_RV410_5657: 606 case PCI_CHIP_RV410_5E48: 607 case PCI_CHIP_RV410_5E4A: 608 case PCI_CHIP_RV410_5E4B: 609 case PCI_CHIP_RV410_5E4D: 610 screen->chip_family = CHIP_FAMILY_RV410; 611 screen->chip_flags = RADEON_CHIPSET_TCL; 612 break; 613 614 case PCI_CHIP_RS480_5954: 615 case PCI_CHIP_RS480_5955: 616 case PCI_CHIP_RS482_5974: 617 case PCI_CHIP_RS482_5975: 618 case PCI_CHIP_RS400_5A41: 619 case PCI_CHIP_RS400_5A42: 620 case PCI_CHIP_RC410_5A61: 621 case PCI_CHIP_RC410_5A62: 622 screen->chip_family = CHIP_FAMILY_RS400; 623 break; 624 625 case PCI_CHIP_RS600_793F: 626 case PCI_CHIP_RS600_7941: 627 case PCI_CHIP_RS600_7942: 628 screen->chip_family = CHIP_FAMILY_RS600; 629 break; 630 631 case PCI_CHIP_RS690_791E: 632 case PCI_CHIP_RS690_791F: 633 screen->chip_family = CHIP_FAMILY_RS690; 634 break; 635 case PCI_CHIP_RS740_796C: 636 case PCI_CHIP_RS740_796D: 637 case PCI_CHIP_RS740_796E: 638 case PCI_CHIP_RS740_796F: 639 screen->chip_family = CHIP_FAMILY_RS740; 640 break; 641 642 case PCI_CHIP_R520_7100: 643 case PCI_CHIP_R520_7101: 644 case PCI_CHIP_R520_7102: 645 case PCI_CHIP_R520_7103: 646 case PCI_CHIP_R520_7104: 647 case PCI_CHIP_R520_7105: 648 case PCI_CHIP_R520_7106: 649 case PCI_CHIP_R520_7108: 650 case PCI_CHIP_R520_7109: 651 case PCI_CHIP_R520_710A: 652 case PCI_CHIP_R520_710B: 653 case PCI_CHIP_R520_710C: 654 case PCI_CHIP_R520_710E: 655 case PCI_CHIP_R520_710F: 656 screen->chip_family = CHIP_FAMILY_R520; 657 screen->chip_flags = RADEON_CHIPSET_TCL; 658 break; 659 660 case PCI_CHIP_RV515_7140: 661 case PCI_CHIP_RV515_7141: 662 case PCI_CHIP_RV515_7142: 663 case PCI_CHIP_RV515_7143: 664 case PCI_CHIP_RV515_7144: 665 case PCI_CHIP_RV515_7145: 666 case PCI_CHIP_RV515_7146: 667 case PCI_CHIP_RV515_7147: 668 case PCI_CHIP_RV515_7149: 669 case PCI_CHIP_RV515_714A: 670 case PCI_CHIP_RV515_714B: 671 case PCI_CHIP_RV515_714C: 672 case PCI_CHIP_RV515_714D: 673 case PCI_CHIP_RV515_714E: 674 case PCI_CHIP_RV515_714F: 675 case PCI_CHIP_RV515_7151: 676 case PCI_CHIP_RV515_7152: 677 case PCI_CHIP_RV515_7153: 678 case PCI_CHIP_RV515_715E: 679 case PCI_CHIP_RV515_715F: 680 case PCI_CHIP_RV515_7180: 681 case PCI_CHIP_RV515_7181: 682 case PCI_CHIP_RV515_7183: 683 case PCI_CHIP_RV515_7186: 684 case PCI_CHIP_RV515_7187: 685 case PCI_CHIP_RV515_7188: 686 case PCI_CHIP_RV515_718A: 687 case PCI_CHIP_RV515_718B: 688 case PCI_CHIP_RV515_718C: 689 case PCI_CHIP_RV515_718D: 690 case PCI_CHIP_RV515_718F: 691 case PCI_CHIP_RV515_7193: 692 case PCI_CHIP_RV515_7196: 693 case PCI_CHIP_RV515_719B: 694 case PCI_CHIP_RV515_719F: 695 case PCI_CHIP_RV515_7200: 696 case PCI_CHIP_RV515_7210: 697 case PCI_CHIP_RV515_7211: 698 screen->chip_family = CHIP_FAMILY_RV515; 699 screen->chip_flags = RADEON_CHIPSET_TCL; 700 break; 701 702 case PCI_CHIP_RV530_71C0: 703 case PCI_CHIP_RV530_71C1: 704 case PCI_CHIP_RV530_71C2: 705 case PCI_CHIP_RV530_71C3: 706 case PCI_CHIP_RV530_71C4: 707 case PCI_CHIP_RV530_71C5: 708 case PCI_CHIP_RV530_71C6: 709 case PCI_CHIP_RV530_71C7: 710 case PCI_CHIP_RV530_71CD: 711 case PCI_CHIP_RV530_71CE: 712 case PCI_CHIP_RV530_71D2: 713 case PCI_CHIP_RV530_71D4: 714 case PCI_CHIP_RV530_71D5: 715 case PCI_CHIP_RV530_71D6: 716 case PCI_CHIP_RV530_71DA: 717 case PCI_CHIP_RV530_71DE: 718 screen->chip_family = CHIP_FAMILY_RV530; 719 screen->chip_flags = RADEON_CHIPSET_TCL; 720 break; 721 722 case PCI_CHIP_R580_7240: 723 case PCI_CHIP_R580_7243: 724 case PCI_CHIP_R580_7244: 725 case PCI_CHIP_R580_7245: 726 case PCI_CHIP_R580_7246: 727 case PCI_CHIP_R580_7247: 728 case PCI_CHIP_R580_7248: 729 case PCI_CHIP_R580_7249: 730 case PCI_CHIP_R580_724A: 731 case PCI_CHIP_R580_724B: 732 case PCI_CHIP_R580_724C: 733 case PCI_CHIP_R580_724D: 734 case PCI_CHIP_R580_724E: 735 case PCI_CHIP_R580_724F: 736 case PCI_CHIP_R580_7284: 737 screen->chip_family = CHIP_FAMILY_R580; 738 screen->chip_flags = RADEON_CHIPSET_TCL; 739 break; 740 741 case PCI_CHIP_RV570_7280: 742 case PCI_CHIP_RV560_7281: 743 case PCI_CHIP_RV560_7283: 744 case PCI_CHIP_RV560_7287: 745 case PCI_CHIP_RV570_7288: 746 case PCI_CHIP_RV570_7289: 747 case PCI_CHIP_RV570_728B: 748 case PCI_CHIP_RV570_728C: 749 case PCI_CHIP_RV560_7290: 750 case PCI_CHIP_RV560_7291: 751 case PCI_CHIP_RV560_7293: 752 case PCI_CHIP_RV560_7297: 753 screen->chip_family = CHIP_FAMILY_RV560; 754 screen->chip_flags = RADEON_CHIPSET_TCL; 755 break; 756 757 case PCI_CHIP_R600_9400: 758 case PCI_CHIP_R600_9401: 759 case PCI_CHIP_R600_9402: 760 case PCI_CHIP_R600_9403: 761 case PCI_CHIP_R600_9405: 762 case PCI_CHIP_R600_940A: 763 case PCI_CHIP_R600_940B: 764 case PCI_CHIP_R600_940F: 765 screen->chip_family = CHIP_FAMILY_R600; 766 screen->chip_flags = RADEON_CHIPSET_TCL; 767 break; 768 769 case PCI_CHIP_RV610_94C0: 770 case PCI_CHIP_RV610_94C1: 771 case PCI_CHIP_RV610_94C3: 772 case PCI_CHIP_RV610_94C4: 773 case PCI_CHIP_RV610_94C5: 774 case PCI_CHIP_RV610_94C6: 775 case PCI_CHIP_RV610_94C7: 776 case PCI_CHIP_RV610_94C8: 777 case PCI_CHIP_RV610_94C9: 778 case PCI_CHIP_RV610_94CB: 779 case PCI_CHIP_RV610_94CC: 780 case PCI_CHIP_RV610_94CD: 781 screen->chip_family = CHIP_FAMILY_RV610; 782 screen->chip_flags = RADEON_CHIPSET_TCL; 783 break; 784 785 case PCI_CHIP_RV630_9580: 786 case PCI_CHIP_RV630_9581: 787 case PCI_CHIP_RV630_9583: 788 case PCI_CHIP_RV630_9586: 789 case PCI_CHIP_RV630_9587: 790 case PCI_CHIP_RV630_9588: 791 case PCI_CHIP_RV630_9589: 792 case PCI_CHIP_RV630_958A: 793 case PCI_CHIP_RV630_958B: 794 case PCI_CHIP_RV630_958C: 795 case PCI_CHIP_RV630_958D: 796 case PCI_CHIP_RV630_958E: 797 case PCI_CHIP_RV630_958F: 798 screen->chip_family = CHIP_FAMILY_RV630; 799 screen->chip_flags = RADEON_CHIPSET_TCL; 800 break; 801 802 case PCI_CHIP_RV670_9500: 803 case PCI_CHIP_RV670_9501: 804 case PCI_CHIP_RV670_9504: 805 case PCI_CHIP_RV670_9505: 806 case PCI_CHIP_RV670_9506: 807 case PCI_CHIP_RV670_9507: 808 case PCI_CHIP_RV670_9508: 809 case PCI_CHIP_RV670_9509: 810 case PCI_CHIP_RV670_950F: 811 case PCI_CHIP_RV670_9511: 812 case PCI_CHIP_RV670_9515: 813 case PCI_CHIP_RV670_9517: 814 case PCI_CHIP_RV670_9519: 815 screen->chip_family = CHIP_FAMILY_RV670; 816 screen->chip_flags = RADEON_CHIPSET_TCL; 817 break; 818 819 case PCI_CHIP_RV620_95C0: 820 case PCI_CHIP_RV620_95C2: 821 case PCI_CHIP_RV620_95C4: 822 case PCI_CHIP_RV620_95C5: 823 case PCI_CHIP_RV620_95C6: 824 case PCI_CHIP_RV620_95C7: 825 case PCI_CHIP_RV620_95C9: 826 case PCI_CHIP_RV620_95CC: 827 case PCI_CHIP_RV620_95CD: 828 case PCI_CHIP_RV620_95CE: 829 case PCI_CHIP_RV620_95CF: 830 screen->chip_family = CHIP_FAMILY_RV620; 831 screen->chip_flags = RADEON_CHIPSET_TCL; 832 break; 833 834 case PCI_CHIP_RV635_9590: 835 case PCI_CHIP_RV635_9591: 836 case PCI_CHIP_RV635_9593: 837 case PCI_CHIP_RV635_9595: 838 case PCI_CHIP_RV635_9596: 839 case PCI_CHIP_RV635_9597: 840 case PCI_CHIP_RV635_9598: 841 case PCI_CHIP_RV635_9599: 842 case PCI_CHIP_RV635_959B: 843 screen->chip_family = CHIP_FAMILY_RV635; 844 screen->chip_flags = RADEON_CHIPSET_TCL; 845 break; 846 847 case PCI_CHIP_RS780_9610: 848 case PCI_CHIP_RS780_9611: 849 case PCI_CHIP_RS780_9612: 850 case PCI_CHIP_RS780_9613: 851 case PCI_CHIP_RS780_9614: 852 case PCI_CHIP_RS780_9615: 853 case PCI_CHIP_RS780_9616: 854 screen->chip_family = CHIP_FAMILY_RS780; 855 screen->chip_flags = RADEON_CHIPSET_TCL; 856 break; 857 858 case PCI_CHIP_RV770_9440: 859 case PCI_CHIP_RV770_9441: 860 case PCI_CHIP_RV770_9442: 861 case PCI_CHIP_RV770_9444: 862 case PCI_CHIP_RV770_9446: 863 case PCI_CHIP_RV770_944A: 864 case PCI_CHIP_RV770_944B: 865 case PCI_CHIP_RV770_944C: 866 case PCI_CHIP_RV770_944E: 867 case PCI_CHIP_RV770_9450: 868 case PCI_CHIP_RV770_9452: 869 case PCI_CHIP_RV770_9456: 870 case PCI_CHIP_RV770_945A: 871 case PCI_CHIP_RV770_945B: 872 case PCI_CHIP_RV790_9460: 873 case PCI_CHIP_RV790_9462: 874 case PCI_CHIP_RV770_946A: 875 case PCI_CHIP_RV770_946B: 876 case PCI_CHIP_RV770_947A: 877 case PCI_CHIP_RV770_947B: 878 screen->chip_family = CHIP_FAMILY_RV770; 879 screen->chip_flags = RADEON_CHIPSET_TCL; 880 break; 881 882 case PCI_CHIP_RV730_9487: 883 case PCI_CHIP_RV730_9489: 884 case PCI_CHIP_RV730_948F: 885 case PCI_CHIP_RV730_9490: 886 case PCI_CHIP_RV730_9491: 887 case PCI_CHIP_RV730_9498: 888 case PCI_CHIP_RV730_949C: 889 case PCI_CHIP_RV730_949E: 890 case PCI_CHIP_RV730_949F: 891 screen->chip_family = CHIP_FAMILY_RV730; 892 screen->chip_flags = RADEON_CHIPSET_TCL; 893 break; 894 895 case PCI_CHIP_RV710_9540: 896 case PCI_CHIP_RV710_9541: 897 case PCI_CHIP_RV710_9542: 898 case PCI_CHIP_RV710_954E: 899 case PCI_CHIP_RV710_954F: 900 case PCI_CHIP_RV710_9552: 901 case PCI_CHIP_RV710_9553: 902 case PCI_CHIP_RV710_9555: 903 screen->chip_family = CHIP_FAMILY_RV710; 904 screen->chip_flags = RADEON_CHIPSET_TCL; 905 break; 906 907 default: 908 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 909 device_id); 910 return -1; 911 } 912 913 return 0; 914} 915 916 917/* Create the device specific screen private data struct. 918 */ 919static radeonScreenPtr 920radeonCreateScreen( __DRIscreenPrivate *sPriv ) 921{ 922 radeonScreenPtr screen; 923 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 924 unsigned char *RADEONMMIO = NULL; 925 int i; 926 int ret; 927 uint32_t temp = 0; 928 929 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 930 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 931 return GL_FALSE; 932 } 933 934 /* Allocate the private area */ 935 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 936 if ( !screen ) { 937 __driUtilMessage("%s: Could not allocate memory for screen structure", 938 __FUNCTION__); 939 return NULL; 940 } 941 942#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 943 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 944#endif 945 /* parse information in __driConfigOptions */ 946 driParseOptionInfo (&screen->optionCache, 947 __driConfigOptions, __driNConfigOptions); 948 949 /* This is first since which regions we map depends on whether or 950 * not we are using a PCI card. 951 */ 952 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 953 { 954 int ret; 955 956#ifdef RADEON_PARAM_KERNEL_MM 957 ret = radeonGetParam(sPriv, RADEON_PARAM_KERNEL_MM, &screen->kernel_mm); 958 959 if (ret && ret != -EINVAL) { 960 FREE( screen ); 961 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 962 return NULL; 963 } 964 965 if (ret == -EINVAL) 966 screen->kernel_mm = 0; 967#endif 968 969 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 970 &screen->gart_buffer_offset); 971 972 if (ret) { 973 FREE( screen ); 974 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 975 return NULL; 976 } 977 978 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 979 &screen->gart_base); 980 if (ret) { 981 FREE( screen ); 982 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 983 return NULL; 984 } 985 986 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 987 &screen->irq); 988 if (ret) { 989 FREE( screen ); 990 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 991 return NULL; 992 } 993 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 994 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 995 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 996 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 997 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 998 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 999 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 1000 } 1001 1002 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 1003 if (ret == -1) 1004 return NULL; 1005 1006 if (!screen->kernel_mm) { 1007 screen->mmio.handle = dri_priv->registerHandle; 1008 screen->mmio.size = dri_priv->registerSize; 1009 if ( drmMap( sPriv->fd, 1010 screen->mmio.handle, 1011 screen->mmio.size, 1012 &screen->mmio.map ) ) { 1013 FREE( screen ); 1014 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 1015 return NULL; 1016 } 1017 1018 RADEONMMIO = screen->mmio.map; 1019 1020 screen->status.handle = dri_priv->statusHandle; 1021 screen->status.size = dri_priv->statusSize; 1022 if ( drmMap( sPriv->fd, 1023 screen->status.handle, 1024 screen->status.size, 1025 &screen->status.map ) ) { 1026 drmUnmap( screen->mmio.map, screen->mmio.size ); 1027 FREE( screen ); 1028 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1029 return NULL; 1030 } 1031 if (screen->chip_family < CHIP_FAMILY_R600) 1032 screen->scratch = (__volatile__ uint32_t *) 1033 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1034 else 1035 screen->scratch = (__volatile__ uint32_t *) 1036 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET); 1037 1038 screen->buffers = drmMapBufs( sPriv->fd ); 1039 if ( !screen->buffers ) { 1040 drmUnmap( screen->status.map, screen->status.size ); 1041 drmUnmap( screen->mmio.map, screen->mmio.size ); 1042 FREE( screen ); 1043 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1044 return NULL; 1045 } 1046 1047 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1048 screen->gartTextures.handle = dri_priv->gartTexHandle; 1049 screen->gartTextures.size = dri_priv->gartTexMapSize; 1050 if ( drmMap( sPriv->fd, 1051 screen->gartTextures.handle, 1052 screen->gartTextures.size, 1053 (drmAddressPtr)&screen->gartTextures.map ) ) { 1054 drmUnmapBufs( screen->buffers ); 1055 drmUnmap( screen->status.map, screen->status.size ); 1056 drmUnmap( screen->mmio.map, screen->mmio.size ); 1057 FREE( screen ); 1058 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1059 return NULL; 1060 } 1061 1062 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1063 } 1064 } 1065 1066 1067 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1068 sPriv->ddx_version.minor < 2) { 1069 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1070 return NULL; 1071 } 1072 1073 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1074 fprintf(stderr, "R500 support requires a newer drm.\n"); 1075 return NULL; 1076 } 1077 1078 if (getenv("R300_NO_TCL")) 1079 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1080 1081 if (screen->chip_family <= CHIP_FAMILY_RS200) 1082 screen->chip_flags |= RADEON_CLASS_R100; 1083 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1084 screen->chip_flags |= RADEON_CLASS_R200; 1085 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1086 screen->chip_flags |= RADEON_CLASS_R300; 1087 else 1088 screen->chip_flags |= RADEON_CLASS_R600; 1089 1090 screen->cpp = dri_priv->bpp / 8; 1091 screen->AGPMode = dri_priv->AGPMode; 1092 1093 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1094 1095 /* +r6/r7 */ 1096 if(screen->chip_family >= CHIP_FAMILY_R600) 1097 { 1098 if (ret) 1099 { 1100 FREE( screen ); 1101 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1102 return NULL; 1103 } 1104 else 1105 { 1106 screen->fbLocation = (temp & 0xffff) << 24; 1107 } 1108 } 1109 else 1110 { 1111 if (ret) 1112 { 1113 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1114 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1115 else 1116 { 1117 FREE( screen ); 1118 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1119 return NULL; 1120 } 1121 } 1122 else 1123 { 1124 screen->fbLocation = (temp & 0xffff) << 16; 1125 } 1126 } 1127 1128 if (IS_R300_CLASS(screen)) { 1129 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1130 if (ret) { 1131 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1132 switch (screen->chip_family) { 1133 case CHIP_FAMILY_R300: 1134 case CHIP_FAMILY_R350: 1135 screen->num_gb_pipes = 2; 1136 break; 1137 case CHIP_FAMILY_R420: 1138 case CHIP_FAMILY_R520: 1139 case CHIP_FAMILY_R580: 1140 case CHIP_FAMILY_RV560: 1141 case CHIP_FAMILY_RV570: 1142 screen->num_gb_pipes = 4; 1143 break; 1144 case CHIP_FAMILY_RV350: 1145 case CHIP_FAMILY_RV515: 1146 case CHIP_FAMILY_RV530: 1147 case CHIP_FAMILY_RV410: 1148 default: 1149 screen->num_gb_pipes = 1; 1150 break; 1151 } 1152 } else { 1153 screen->num_gb_pipes = temp; 1154 } 1155 } 1156 1157 if ( sPriv->drm_version.minor >= 10 ) { 1158 drm_radeon_setparam_t sp; 1159 1160 sp.param = RADEON_SETPARAM_FB_LOCATION; 1161 sp.value = screen->fbLocation; 1162 1163 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1164 &sp, sizeof( sp ) ); 1165 } 1166 1167 screen->frontOffset = dri_priv->frontOffset; 1168 screen->frontPitch = dri_priv->frontPitch; 1169 screen->backOffset = dri_priv->backOffset; 1170 screen->backPitch = dri_priv->backPitch; 1171 screen->depthOffset = dri_priv->depthOffset; 1172 screen->depthPitch = dri_priv->depthPitch; 1173 1174 /* Check if ddx has set up a surface reg to cover depth buffer */ 1175 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1176 /* these chips don't use tiled z without hyperz. So always pretend 1177 we have set up a surface which will cause linear reads/writes */ 1178 (IS_R100_CLASS(screen) && 1179 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1180 1181 if ( dri_priv->textureSize == 0 ) { 1182 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1183 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1184 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1185 dri_priv->log2GARTTexGran; 1186 } else { 1187 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1188 + screen->fbLocation; 1189 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1190 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1191 dri_priv->log2TexGran; 1192 } 1193 1194 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1195 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1196 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1197 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1198 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1199 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1200 } else { 1201 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1202 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1203 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1204 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1205 dri_priv->log2GARTTexGran; 1206 } 1207 1208 i = 0; 1209 screen->extensions[i++] = &driCopySubBufferExtension.base; 1210 screen->extensions[i++] = &driFrameTrackingExtension.base; 1211 screen->extensions[i++] = &driReadDrawableExtension; 1212 1213 if ( screen->irq != 0 ) { 1214 screen->extensions[i++] = &driSwapControlExtension.base; 1215 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1216 } 1217 1218 if (!screen->kernel_mm) { 1219#if !RADEON_COMMON 1220 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1221#endif 1222 1223#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1224 if (IS_R200_CLASS(screen)) 1225 screen->extensions[i++] = &r200AllocateExtension.base; 1226 1227 screen->extensions[i++] = &r200texOffsetExtension.base; 1228#endif 1229 1230#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1231 screen->extensions[i++] = &r300texOffsetExtension.base; 1232#endif 1233 1234#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1235 screen->extensions[i++] = &r600texOffsetExtension.base; 1236#endif 1237 } 1238 1239 screen->extensions[i++] = NULL; 1240 sPriv->extensions = screen->extensions; 1241 1242 screen->driScreen = sPriv; 1243 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1244 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1245 screen->sarea_priv_offset); 1246 1247 if (screen->kernel_mm) 1248 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1249 else 1250 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1251 if (screen->bom == NULL) { 1252 free(screen); 1253 return NULL; 1254 } 1255 1256 return screen; 1257} 1258 1259static radeonScreenPtr 1260radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1261{ 1262 radeonScreenPtr screen; 1263 int i; 1264 int ret; 1265 uint32_t device_id; 1266 uint32_t temp = 0; 1267 1268 /* Allocate the private area */ 1269 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1270 if ( !screen ) { 1271 __driUtilMessage("%s: Could not allocate memory for screen structure", 1272 __FUNCTION__); 1273 fprintf(stderr, "leaving here\n"); 1274 return NULL; 1275 } 1276 1277#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1278 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1279#endif 1280 1281 /* parse information in __driConfigOptions */ 1282 driParseOptionInfo (&screen->optionCache, 1283 __driConfigOptions, __driNConfigOptions); 1284 1285 screen->kernel_mm = 1; 1286 screen->chip_flags = 0; 1287 1288 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, &screen->irq); 1289 1290 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1291 if (ret) { 1292 FREE( screen ); 1293 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1294 return NULL; 1295 } 1296 1297 ret = radeon_set_screen_flags(screen, device_id); 1298 if (ret == -1) 1299 return NULL; 1300 1301 if (getenv("R300_NO_TCL")) 1302 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1303 1304 if (screen->chip_family <= CHIP_FAMILY_RS200) 1305 screen->chip_flags |= RADEON_CLASS_R100; 1306 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1307 screen->chip_flags |= RADEON_CLASS_R200; 1308 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1309 screen->chip_flags |= RADEON_CLASS_R300; 1310 else 1311 screen->chip_flags |= RADEON_CLASS_R600; 1312 1313 if (IS_R300_CLASS(screen)) { 1314 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1315 if (ret) { 1316 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1317 switch (screen->chip_family) { 1318 case CHIP_FAMILY_R300: 1319 case CHIP_FAMILY_R350: 1320 screen->num_gb_pipes = 2; 1321 break; 1322 case CHIP_FAMILY_R420: 1323 case CHIP_FAMILY_R520: 1324 case CHIP_FAMILY_R580: 1325 case CHIP_FAMILY_RV560: 1326 case CHIP_FAMILY_RV570: 1327 screen->num_gb_pipes = 4; 1328 break; 1329 case CHIP_FAMILY_RV350: 1330 case CHIP_FAMILY_RV515: 1331 case CHIP_FAMILY_RV530: 1332 case CHIP_FAMILY_RV410: 1333 default: 1334 screen->num_gb_pipes = 1; 1335 break; 1336 } 1337 } else { 1338 screen->num_gb_pipes = temp; 1339 } 1340 } 1341 1342 i = 0; 1343 screen->extensions[i++] = &driCopySubBufferExtension.base; 1344 screen->extensions[i++] = &driFrameTrackingExtension.base; 1345 screen->extensions[i++] = &driReadDrawableExtension; 1346 1347 if ( screen->irq != 0 ) { 1348 screen->extensions[i++] = &driSwapControlExtension.base; 1349 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1350 } 1351 1352#if !RADEON_COMMON 1353 screen->extensions[i++] = &radeonTexBufferExtension.base; 1354#endif 1355 1356#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1357 if (IS_R200_CLASS(screen)) 1358 screen->extensions[i++] = &r200AllocateExtension.base; 1359 1360 screen->extensions[i++] = &r200TexBufferExtension.base; 1361#endif 1362 1363#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1364 screen->extensions[i++] = &r300TexBufferExtension.base; 1365#endif 1366 1367#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1368 screen->extensions[i++] = &r600TexBufferExtension.base; 1369#endif 1370 1371 screen->extensions[i++] = NULL; 1372 sPriv->extensions = screen->extensions; 1373 1374 screen->driScreen = sPriv; 1375 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1376 if (screen->bom == NULL) { 1377 free(screen); 1378 return NULL; 1379 } 1380 return screen; 1381} 1382 1383/* Destroy the device specific screen private data struct. 1384 */ 1385static void 1386radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1387{ 1388 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1389 1390 if (!screen) 1391 return; 1392 1393 if (screen->kernel_mm) { 1394#ifdef RADEON_BO_TRACK 1395 radeon_tracker_print(&screen->bom->tracker, stderr); 1396#endif 1397 radeon_bo_manager_gem_dtor(screen->bom); 1398 } else { 1399 radeon_bo_manager_legacy_dtor(screen->bom); 1400 1401 if ( screen->gartTextures.map ) { 1402 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1403 } 1404 drmUnmapBufs( screen->buffers ); 1405 drmUnmap( screen->status.map, screen->status.size ); 1406 drmUnmap( screen->mmio.map, screen->mmio.size ); 1407 } 1408 1409 /* free all option information */ 1410 driDestroyOptionInfo (&screen->optionCache); 1411 1412 FREE( screen ); 1413 sPriv->private = NULL; 1414} 1415 1416 1417/* Initialize the driver specific screen private data. 1418 */ 1419static GLboolean 1420radeonInitDriver( __DRIscreenPrivate *sPriv ) 1421{ 1422 if (sPriv->dri2.enabled) { 1423 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1424 } else { 1425 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1426 } 1427 if ( !sPriv->private ) { 1428 radeonDestroyScreen( sPriv ); 1429 return GL_FALSE; 1430 } 1431 1432 return GL_TRUE; 1433} 1434 1435 1436 1437/** 1438 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1439 * 1440 * \todo This function (and its interface) will need to be updated to support 1441 * pbuffers. 1442 */ 1443static GLboolean 1444radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1445 __DRIdrawablePrivate *driDrawPriv, 1446 const __GLcontextModes *mesaVis, 1447 GLboolean isPixmap ) 1448{ 1449 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1450 1451 const GLboolean swDepth = GL_FALSE; 1452 const GLboolean swAlpha = GL_FALSE; 1453 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1454 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1455 mesaVis->depthBits != 24; 1456 GLenum rgbFormat; 1457 struct radeon_framebuffer *rfb; 1458 1459 if (isPixmap) 1460 return GL_FALSE; /* not implemented */ 1461 1462 rfb = CALLOC_STRUCT(radeon_framebuffer); 1463 if (!rfb) 1464 return GL_FALSE; 1465 1466 _mesa_initialize_framebuffer(&rfb->base, mesaVis); 1467 1468 if (mesaVis->redBits == 5) 1469 rgbFormat = GL_RGB5; 1470 else if (mesaVis->alphaBits == 0) 1471 rgbFormat = GL_RGB8; 1472 else 1473 rgbFormat = GL_RGBA8; 1474 1475 /* front color renderbuffer */ 1476 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1477 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1478 rfb->color_rb[0]->has_surface = 1; 1479 1480 /* back color renderbuffer */ 1481 if (mesaVis->doubleBufferMode) { 1482 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1483 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1484 rfb->color_rb[1]->has_surface = 1; 1485 } 1486 1487 if (mesaVis->depthBits == 24) { 1488 if (mesaVis->stencilBits == 8) { 1489 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); 1490 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1491 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1492 depthStencilRb->has_surface = screen->depthHasSurface; 1493 } else { 1494 /* depth renderbuffer */ 1495 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); 1496 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1497 depth->has_surface = screen->depthHasSurface; 1498 } 1499 } else if (mesaVis->depthBits == 16) { 1500 /* just 16-bit depth buffer, no hw stencil */ 1501 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); 1502 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1503 depth->has_surface = screen->depthHasSurface; 1504 } 1505 1506 _mesa_add_soft_renderbuffers(&rfb->base, 1507 GL_FALSE, /* color */ 1508 swDepth, 1509 swStencil, 1510 swAccum, 1511 swAlpha, 1512 GL_FALSE /* aux */); 1513 driDrawPriv->driverPrivate = (void *) rfb; 1514 1515 return (driDrawPriv->driverPrivate != NULL); 1516} 1517 1518 1519static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1520{ 1521 struct radeon_renderbuffer *rb; 1522 1523 rb = rfb->color_rb[0]; 1524 if (rb && rb->bo) { 1525 radeon_bo_unref(rb->bo); 1526 rb->bo = NULL; 1527 } 1528 rb = rfb->color_rb[1]; 1529 if (rb && rb->bo) { 1530 radeon_bo_unref(rb->bo); 1531 rb->bo = NULL; 1532 } 1533 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1534 if (rb && rb->bo) { 1535 radeon_bo_unref(rb->bo); 1536 rb->bo = NULL; 1537 } 1538} 1539 1540void 1541radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1542{ 1543 struct radeon_framebuffer *rfb; 1544 if (!driDrawPriv) 1545 return; 1546 1547 rfb = (void*)driDrawPriv->driverPrivate; 1548 if (!rfb) 1549 return; 1550 radeon_cleanup_renderbuffers(rfb); 1551 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1552} 1553 1554/** 1555 * Choose the appropriate CreateContext function based on the chipset. 1556 * Eventually, all drivers will go through this process. 1557 */ 1558static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1559 __DRIcontextPrivate * driContextPriv, 1560 void *sharedContextPriv) 1561{ 1562 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1563 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1564#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1565 if (IS_R600_CLASS(screen)) 1566 return r600CreateContext(glVisual, driContextPriv, sharedContextPriv); 1567#endif 1568 1569#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1570 if (IS_R300_CLASS(screen)) 1571 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1572#endif 1573 1574#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1575 if (IS_R200_CLASS(screen)) 1576 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv); 1577#endif 1578 1579#if !RADEON_COMMON 1580 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); 1581#endif 1582 return GL_FALSE; 1583} 1584 1585 1586/** 1587 * This is the driver specific part of the createNewScreen entry point. 1588 * 1589 * \todo maybe fold this into intelInitDriver 1590 * 1591 * \return the __GLcontextModes supported by this driver 1592 */ 1593static const __DRIconfig ** 1594radeonInitScreen(__DRIscreenPrivate *psp) 1595{ 1596#if !RADEON_COMMON 1597 static const char *driver_name = "Radeon"; 1598 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1599 static const __DRIversion dri_expected = { 4, 0, 0 }; 1600 static const __DRIversion drm_expected = { 1, 6, 0 }; 1601#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1602 static const char *driver_name = "R200"; 1603 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1604 static const __DRIversion dri_expected = { 4, 0, 0 }; 1605 static const __DRIversion drm_expected = { 1, 6, 0 }; 1606#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1607 static const char *driver_name = "R300"; 1608 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1609 static const __DRIversion dri_expected = { 4, 0, 0 }; 1610 static const __DRIversion drm_expected = { 1, 24, 0 }; 1611#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1612 static const char *driver_name = "R600"; 1613 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1614 static const __DRIversion dri_expected = { 4, 0, 0 }; 1615 static const __DRIversion drm_expected = { 1, 24, 0 }; 1616#endif 1617 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1618 1619 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1620 &psp->dri_version, & dri_expected, 1621 &psp->ddx_version, & ddx_expected, 1622 &psp->drm_version, & drm_expected ) ) { 1623 return NULL; 1624 } 1625 1626 /* Calling driInitExtensions here, with a NULL context pointer, 1627 * does not actually enable the extensions. It just makes sure 1628 * that all the dispatch offsets for all the extensions that 1629 * *might* be enables are known. This is needed because the 1630 * dispatch offsets need to be known when _mesa_context_create 1631 * is called, but we can't enable the extensions until we have a 1632 * context pointer. 1633 * 1634 * Hello chicken. Hello egg. How are you two today? 1635 */ 1636 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1637#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1638 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1639 driInitSingleExtension( NULL, ARB_vp_extension ); 1640 driInitSingleExtension( NULL, NV_vp_extension ); 1641 driInitSingleExtension( NULL, ATI_fs_extension ); 1642 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1643#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 1644 driInitSingleExtension( NULL, gl_20_extension ); 1645#endif 1646 1647 if (!radeonInitDriver(psp)) 1648 return NULL; 1649 1650 /* for now fill in all modes */ 1651 return radeonFillInModes( psp, 1652 dri_priv->bpp, 1653 (dri_priv->bpp == 16) ? 16 : 24, 1654 (dri_priv->bpp == 16) ? 0 : 8, 1); 1655} 1656#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1657 1658/** 1659 * This is the driver specific part of the createNewScreen entry point. 1660 * Called when using DRI2. 1661 * 1662 * \return the __GLcontextModes supported by this driver 1663 */ 1664static const 1665__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1666{ 1667 GLenum fb_format[3]; 1668 GLenum fb_type[3]; 1669 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1670 * support pageflipping at all. 1671 */ 1672 static const GLenum back_buffer_modes[] = { 1673 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1674 }; 1675 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1676 int color; 1677 __DRIconfig **configs = NULL; 1678 1679 /* Calling driInitExtensions here, with a NULL context pointer, 1680 * does not actually enable the extensions. It just makes sure 1681 * that all the dispatch offsets for all the extensions that 1682 * *might* be enables are known. This is needed because the 1683 * dispatch offsets need to be known when _mesa_context_create 1684 * is called, but we can't enable the extensions until we have a 1685 * context pointer. 1686 * 1687 * Hello chicken. Hello egg. How are you two today? 1688 */ 1689 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1690 driInitExtensions( NULL, mm_extensions, GL_FALSE ); 1691#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1692 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1693 driInitSingleExtension( NULL, ARB_vp_extension ); 1694 driInitSingleExtension( NULL, NV_vp_extension ); 1695 driInitSingleExtension( NULL, ATI_fs_extension ); 1696 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1697#endif 1698 1699 if (!radeonInitDriver(psp)) { 1700 return NULL; 1701 } 1702 depth_bits[0] = 0; 1703 stencil_bits[0] = 0; 1704 depth_bits[1] = 16; 1705 stencil_bits[1] = 0; 1706 depth_bits[2] = 24; 1707 stencil_bits[2] = 0; 1708 depth_bits[3] = 24; 1709 stencil_bits[3] = 8; 1710 1711 msaa_samples_array[0] = 0; 1712 1713 fb_format[0] = GL_RGB; 1714 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1715 1716 fb_format[1] = GL_BGR; 1717 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1718 1719 fb_format[2] = GL_BGRA; 1720 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1721 1722 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1723 __DRIconfig **new_configs; 1724 1725 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1726 depth_bits, 1727 stencil_bits, 1728 ARRAY_SIZE(depth_bits), 1729 back_buffer_modes, 1730 ARRAY_SIZE(back_buffer_modes), 1731 msaa_samples_array, 1732 ARRAY_SIZE(msaa_samples_array)); 1733 if (configs == NULL) 1734 configs = new_configs; 1735 else 1736 configs = driConcatConfigs(configs, new_configs); 1737 } 1738 1739 if (configs == NULL) { 1740 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1741 __LINE__); 1742 return NULL; 1743 } 1744 1745 return (const __DRIconfig **)configs; 1746} 1747 1748/** 1749 * Get information about previous buffer swaps. 1750 */ 1751static int 1752getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1753{ 1754 struct radeon_framebuffer *rfb; 1755 1756 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1757 || (dPriv->driContextPriv->driverPrivate == NULL) 1758 || (sInfo == NULL) ) { 1759 return -1; 1760 } 1761 1762 rfb = dPriv->driverPrivate; 1763 sInfo->swap_count = rfb->swap_count; 1764 sInfo->swap_ust = rfb->swap_ust; 1765 sInfo->swap_missed_count = rfb->swap_missed_count; 1766 1767 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1768 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1769 : 0.0; 1770 1771 return 0; 1772} 1773 1774const struct __DriverAPIRec driDriverAPI = { 1775 .InitScreen = radeonInitScreen, 1776 .DestroyScreen = radeonDestroyScreen, 1777 .CreateContext = radeonCreateContext, 1778 .DestroyContext = radeonDestroyContext, 1779 .CreateBuffer = radeonCreateBuffer, 1780 .DestroyBuffer = radeonDestroyBuffer, 1781 .SwapBuffers = radeonSwapBuffers, 1782 .MakeCurrent = radeonMakeCurrent, 1783 .UnbindContext = radeonUnbindContext, 1784 .GetSwapInfo = getSwapInfo, 1785 .GetDrawableMSC = driDrawableGetMSC32, 1786 .WaitForMSC = driWaitForMSC32, 1787 .WaitForSBC = NULL, 1788 .SwapBuffersMSC = NULL, 1789 .CopySubBuffer = radeonCopySubBuffer, 1790 /* DRI2 */ 1791 .InitScreen2 = radeonInitScreen2, 1792}; 1793 1794