radeon_screen.c revision 831fc138c1617f5cb49da589ea5126c8eda364a4 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author  Gareth Hughes <gareth@valinux.com>
37 */
38
39#include "glheader.h"
40#include "imports.h"
41#include "mtypes.h"
42#include "framebuffer.h"
43#include "renderbuffer.h"
44
45#define STANDALONE_MMIO
46#include "radeon_chipset.h"
47#include "radeon_macros.h"
48#include "radeon_screen.h"
49#if !RADEON_COMMON
50#include "radeon_context.h"
51#include "radeon_span.h"
52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53#include "r200_context.h"
54#include "r200_ioctl.h"
55#include "r200_span.h"
56#include "r200_tex.h"
57#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58#include "r300_context.h"
59#include "r300_fragprog.h"
60#include "r300_tex.h"
61#include "radeon_span.h"
62#endif
63
64#include "utils.h"
65#include "context.h"
66#include "vblank.h"
67#include "drirenderbuffer.h"
68
69#include "GL/internal/dri_interface.h"
70
71/* Radeon configuration
72 */
73#include "xmlpool.h"
74
75#if !RADEON_COMMON	/* R100 */
76PUBLIC const char __driConfigOptions[] =
77DRI_CONF_BEGIN
78    DRI_CONF_SECTION_PERFORMANCE
79        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
80        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
81        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
82        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
83        DRI_CONF_HYPERZ(false)
84    DRI_CONF_SECTION_END
85    DRI_CONF_SECTION_QUALITY
86        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
87        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
88        DRI_CONF_NO_NEG_LOD_BIAS(false)
89        DRI_CONF_FORCE_S3TC_ENABLE(false)
90        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
91        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
92        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
93        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
94    DRI_CONF_SECTION_END
95    DRI_CONF_SECTION_DEBUG
96        DRI_CONF_NO_RAST(false)
97    DRI_CONF_SECTION_END
98DRI_CONF_END;
99static const GLuint __driNConfigOptions = 14;
100
101#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102
103PUBLIC const char __driConfigOptions[] =
104DRI_CONF_BEGIN
105    DRI_CONF_SECTION_PERFORMANCE
106        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
107        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
108        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
109        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
110        DRI_CONF_HYPERZ(false)
111    DRI_CONF_SECTION_END
112    DRI_CONF_SECTION_QUALITY
113        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
114        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
115        DRI_CONF_NO_NEG_LOD_BIAS(false)
116        DRI_CONF_FORCE_S3TC_ENABLE(false)
117        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
118        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
119        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
120        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
121        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122    DRI_CONF_SECTION_END
123    DRI_CONF_SECTION_DEBUG
124        DRI_CONF_NO_RAST(false)
125    DRI_CONF_SECTION_END
126    DRI_CONF_SECTION_SOFTWARE
127        DRI_CONF_NV_VERTEX_PROGRAM(false)
128    DRI_CONF_SECTION_END
129DRI_CONF_END;
130static const GLuint __driNConfigOptions = 16;
131
132extern const struct dri_extension blend_extensions[];
133extern const struct dri_extension ARB_vp_extension[];
134extern const struct dri_extension NV_vp_extension[];
135extern const struct dri_extension ATI_fs_extension[];
136extern const struct dri_extension point_extensions[];
137
138#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139
140/* TODO: integrate these into xmlpool.h! */
141#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
142DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
143        DRI_CONF_DESC(en,"Number of texture image units") \
144        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
145DRI_CONF_OPT_END
146
147#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
148DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
149        DRI_CONF_DESC(en,"Number of texture coordinate units") \
150        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
151DRI_CONF_OPT_END
152
153#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
154DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
155        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
156        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
157DRI_CONF_OPT_END
158
159#define DRI_CONF_DISABLE_S3TC(def) \
160DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
161        DRI_CONF_DESC(en,"Disable S3TC compression") \
162DRI_CONF_OPT_END
163
164#define DRI_CONF_DISABLE_FALLBACK(def) \
165DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
166        DRI_CONF_DESC(en,"Disable Low-impact fallback") \
167DRI_CONF_OPT_END
168
169#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
170DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
171        DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
172DRI_CONF_OPT_END
173
174#define DRI_CONF_FP_OPTIMIZATION(def) \
175DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
176	DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
177                DRI_CONF_ENUM(0,"Optimize for Speed") \
178                DRI_CONF_ENUM(1,"Optimize for Quality") \
179        DRI_CONF_DESC_END \
180DRI_CONF_OPT_END
181
182PUBLIC const char __driConfigOptions[] =
183DRI_CONF_BEGIN
184	DRI_CONF_SECTION_PERFORMANCE
185		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
186		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
187		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
188		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
189		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
190		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
191		DRI_CONF_DISABLE_FALLBACK(false)
192		DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193	DRI_CONF_SECTION_END
194	DRI_CONF_SECTION_QUALITY
195		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
196		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
197		DRI_CONF_NO_NEG_LOD_BIAS(false)
198                DRI_CONF_FORCE_S3TC_ENABLE(false)
199		DRI_CONF_DISABLE_S3TC(false)
200		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
201		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
202		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
203		DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
204	DRI_CONF_SECTION_END
205	DRI_CONF_SECTION_DEBUG
206		DRI_CONF_NO_RAST(false)
207	DRI_CONF_SECTION_END
208DRI_CONF_END;
209static const GLuint __driNConfigOptions = 18;
210
211#ifndef RADEON_DEBUG
212int RADEON_DEBUG = 0;
213
214static const struct dri_debug_control debug_control[] = {
215	{"fall", DEBUG_FALLBACKS},
216	{"tex", DEBUG_TEXTURE},
217	{"ioctl", DEBUG_IOCTL},
218	{"prim", DEBUG_PRIMS},
219	{"vert", DEBUG_VERTS},
220	{"state", DEBUG_STATE},
221	{"code", DEBUG_CODEGEN},
222	{"vfmt", DEBUG_VFMT},
223	{"vtxf", DEBUG_VFMT},
224	{"verb", DEBUG_VERBOSE},
225	{"dri", DEBUG_DRI},
226	{"dma", DEBUG_DMA},
227	{"san", DEBUG_SANITY},
228	{"sync", DEBUG_SYNC},
229	{"pix", DEBUG_PIXEL},
230	{"mem", DEBUG_MEMORY},
231	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
232	{NULL, 0}
233};
234#endif /* RADEON_DEBUG */
235
236#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237
238extern const struct dri_extension card_extensions[];
239
240static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
241
242static int
243radeonGetParam(int fd, int param, void *value)
244{
245  int ret;
246  drm_radeon_getparam_t gp;
247
248  gp.param = param;
249  gp.value = value;
250
251  ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
252  return ret;
253}
254
255static const __DRIconfig **
256radeonFillInModes( __DRIscreenPrivate *psp,
257		   unsigned pixel_bits, unsigned depth_bits,
258		   unsigned stencil_bits, GLboolean have_back_buffer )
259{
260    __DRIconfig **configs;
261    __GLcontextModes *m;
262    unsigned depth_buffer_factor;
263    unsigned back_buffer_factor;
264    GLenum fb_format;
265    GLenum fb_type;
266    int i;
267
268    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269     * enough to add support.  Basically, if a context is created with an
270     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271     * will never be used.
272     */
273    static const GLenum back_buffer_modes[] = {
274	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275    };
276
277    u_int8_t depth_bits_array[2];
278    u_int8_t stencil_bits_array[2];
279
280
281    depth_bits_array[0] = depth_bits;
282    depth_bits_array[1] = depth_bits;
283
284    /* Just like with the accumulation buffer, always provide some modes
285     * with a stencil buffer.  It will be a sw fallback, but some apps won't
286     * care about that.
287     */
288    stencil_bits_array[0] = 0;
289    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291    depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
292    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
293
294    if ( pixel_bits == 16 ) {
295        fb_format = GL_RGB;
296        fb_type = GL_UNSIGNED_SHORT_5_6_5;
297    }
298    else {
299        fb_format = GL_BGRA;
300        fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
301    }
302
303    configs = driCreateConfigs(fb_format, fb_type,
304			       depth_bits_array, stencil_bits_array,
305			       depth_buffer_factor,
306			       back_buffer_modes, back_buffer_factor);
307    if (configs == NULL) {
308	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
309		 __func__, __LINE__ );
310	return NULL;
311    }
312
313    /* Mark the visual as slow if there are "fake" stencil bits.
314     */
315    for (i = 0; configs[i]; i++) {
316	m = &configs[i]->modes;
317	if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
318	    m->visualRating = GLX_SLOW_CONFIG;
319	}
320    }
321
322    return (const __DRIconfig **) configs;
323}
324
325#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
326static const __DRIallocateExtension r200AllocateExtension = {
327    { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
328    r200AllocateMemoryMESA,
329    r200FreeMemoryMESA,
330    r200GetMemoryOffsetMESA
331};
332
333static const __DRItexOffsetExtension r200texOffsetExtension = {
334    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
335   r200SetTexOffset,
336};
337#endif
338
339#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
340static const __DRItexOffsetExtension r300texOffsetExtension = {
341    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
342   r300SetTexOffset,
343};
344#endif
345
346/* Create the device specific screen private data struct.
347 */
348static radeonScreenPtr
349radeonCreateScreen( __DRIscreenPrivate *sPriv )
350{
351   radeonScreenPtr screen;
352   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
353   unsigned char *RADEONMMIO;
354   int i;
355   int ret;
356   uint32_t temp;
357
358   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
359      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
360      return GL_FALSE;
361   }
362
363   /* Allocate the private area */
364   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
365   if ( !screen ) {
366      __driUtilMessage("%s: Could not allocate memory for screen structure",
367		       __FUNCTION__);
368      return NULL;
369   }
370
371#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
372	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
373#endif
374
375   /* parse information in __driConfigOptions */
376   driParseOptionInfo (&screen->optionCache,
377		       __driConfigOptions, __driNConfigOptions);
378
379   /* This is first since which regions we map depends on whether or
380    * not we are using a PCI card.
381    */
382   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
383   {
384      int ret;
385      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
386			    &screen->gart_buffer_offset);
387
388      if (ret) {
389	 FREE( screen );
390	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
391	 return NULL;
392      }
393
394      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
395			    &screen->gart_base);
396      if (ret) {
397	 FREE( screen );
398	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
399	 return NULL;
400      }
401
402      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
403			    &screen->irq);
404      if (ret) {
405	 FREE( screen );
406	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
407	 return NULL;
408      }
409      screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
410      screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
411      screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
412      screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
413      screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
414      screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
415      screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
416   }
417
418   screen->mmio.handle = dri_priv->registerHandle;
419   screen->mmio.size   = dri_priv->registerSize;
420   if ( drmMap( sPriv->fd,
421		screen->mmio.handle,
422		screen->mmio.size,
423		&screen->mmio.map ) ) {
424      FREE( screen );
425      __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
426      return NULL;
427   }
428
429   RADEONMMIO = screen->mmio.map;
430
431   screen->status.handle = dri_priv->statusHandle;
432   screen->status.size   = dri_priv->statusSize;
433   if ( drmMap( sPriv->fd,
434		screen->status.handle,
435		screen->status.size,
436		&screen->status.map ) ) {
437      drmUnmap( screen->mmio.map, screen->mmio.size );
438      FREE( screen );
439      __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
440      return NULL;
441   }
442   screen->scratch = (__volatile__ u_int32_t *)
443      ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
444
445   screen->buffers = drmMapBufs( sPriv->fd );
446   if ( !screen->buffers ) {
447      drmUnmap( screen->status.map, screen->status.size );
448      drmUnmap( screen->mmio.map, screen->mmio.size );
449      FREE( screen );
450      __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
451      return NULL;
452   }
453
454   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
455      screen->gartTextures.handle = dri_priv->gartTexHandle;
456      screen->gartTextures.size   = dri_priv->gartTexMapSize;
457      if ( drmMap( sPriv->fd,
458		   screen->gartTextures.handle,
459		   screen->gartTextures.size,
460		   (drmAddressPtr)&screen->gartTextures.map ) ) {
461	 drmUnmapBufs( screen->buffers );
462	 drmUnmap( screen->status.map, screen->status.size );
463	 drmUnmap( screen->mmio.map, screen->mmio.size );
464	 FREE( screen );
465	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
466	 return NULL;
467      }
468
469      screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
470   }
471
472   screen->chip_flags = 0;
473   /* XXX: add more chipsets */
474   switch ( dri_priv->deviceID ) {
475   case PCI_CHIP_RADEON_LY:
476   case PCI_CHIP_RADEON_LZ:
477   case PCI_CHIP_RADEON_QY:
478   case PCI_CHIP_RADEON_QZ:
479   case PCI_CHIP_RN50_515E:
480   case PCI_CHIP_RN50_5969:
481      screen->chip_family = CHIP_FAMILY_RV100;
482      break;
483
484   case PCI_CHIP_RS100_4136:
485   case PCI_CHIP_RS100_4336:
486      screen->chip_family = CHIP_FAMILY_RS100;
487      break;
488
489   case PCI_CHIP_RS200_4137:
490   case PCI_CHIP_RS200_4337:
491   case PCI_CHIP_RS250_4237:
492   case PCI_CHIP_RS250_4437:
493      screen->chip_family = CHIP_FAMILY_RS200;
494      break;
495
496   case PCI_CHIP_RADEON_QD:
497   case PCI_CHIP_RADEON_QE:
498   case PCI_CHIP_RADEON_QF:
499   case PCI_CHIP_RADEON_QG:
500      /* all original radeons (7200) presumably have a stencil op bug */
501      screen->chip_family = CHIP_FAMILY_R100;
502      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
503      break;
504
505   case PCI_CHIP_RV200_QW:
506   case PCI_CHIP_RV200_QX:
507   case PCI_CHIP_RADEON_LW:
508   case PCI_CHIP_RADEON_LX:
509      screen->chip_family = CHIP_FAMILY_RV200;
510      screen->chip_flags = RADEON_CHIPSET_TCL;
511      break;
512
513   case PCI_CHIP_R200_BB:
514   case PCI_CHIP_R200_BC:
515   case PCI_CHIP_R200_QH:
516   case PCI_CHIP_R200_QL:
517   case PCI_CHIP_R200_QM:
518      screen->chip_family = CHIP_FAMILY_R200;
519      screen->chip_flags = RADEON_CHIPSET_TCL;
520      break;
521
522   case PCI_CHIP_RV250_If:
523   case PCI_CHIP_RV250_Ig:
524   case PCI_CHIP_RV250_Ld:
525   case PCI_CHIP_RV250_Lf:
526   case PCI_CHIP_RV250_Lg:
527      screen->chip_family = CHIP_FAMILY_RV250;
528      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
529      break;
530
531   case PCI_CHIP_RV280_5960:
532   case PCI_CHIP_RV280_5961:
533   case PCI_CHIP_RV280_5962:
534   case PCI_CHIP_RV280_5964:
535   case PCI_CHIP_RV280_5965:
536   case PCI_CHIP_RV280_5C61:
537   case PCI_CHIP_RV280_5C63:
538      screen->chip_family = CHIP_FAMILY_RV280;
539      screen->chip_flags = RADEON_CHIPSET_TCL;
540      break;
541
542   case PCI_CHIP_RS300_5834:
543   case PCI_CHIP_RS300_5835:
544   case PCI_CHIP_RS350_7834:
545   case PCI_CHIP_RS350_7835:
546      screen->chip_family = CHIP_FAMILY_RS300;
547      break;
548
549      /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
550   case PCI_CHIP_R300_AD:
551      screen->chip_family = CHIP_FAMILY_RV350;
552      screen->chip_flags = RADEON_CHIPSET_TCL;
553      break;
554   case PCI_CHIP_R300_AE:
555   case PCI_CHIP_R300_AF:
556   case PCI_CHIP_R300_AG:
557   case PCI_CHIP_R300_ND:
558   case PCI_CHIP_R300_NE:
559   case PCI_CHIP_R300_NF:
560   case PCI_CHIP_R300_NG:
561      screen->chip_family = CHIP_FAMILY_R300;
562      screen->chip_flags = RADEON_CHIPSET_TCL;
563      break;
564
565   case PCI_CHIP_RV350_AP:
566   case PCI_CHIP_RV350_AQ:
567   case PCI_CHIP_RV350_AR:
568   case PCI_CHIP_RV350_AS:
569   case PCI_CHIP_RV350_AT:
570   case PCI_CHIP_RV350_AV:
571   case PCI_CHIP_RV350_AU:
572   case PCI_CHIP_RV350_NP:
573   case PCI_CHIP_RV350_NQ:
574   case PCI_CHIP_RV350_NR:
575   case PCI_CHIP_RV350_NS:
576   case PCI_CHIP_RV350_NT:
577   case PCI_CHIP_RV350_NV:
578      screen->chip_family = CHIP_FAMILY_RV350;
579      screen->chip_flags = RADEON_CHIPSET_TCL;
580      break;
581
582   case PCI_CHIP_R350_AH:
583   case PCI_CHIP_R350_AI:
584   case PCI_CHIP_R350_AJ:
585   case PCI_CHIP_R350_AK:
586   case PCI_CHIP_R350_NH:
587   case PCI_CHIP_R350_NI:
588   case PCI_CHIP_R360_NJ:
589   case PCI_CHIP_R350_NK:
590      screen->chip_family = CHIP_FAMILY_R350;
591      screen->chip_flags = RADEON_CHIPSET_TCL;
592      break;
593
594   case PCI_CHIP_RV370_5460:
595   case PCI_CHIP_RV370_5462:
596   case PCI_CHIP_RV370_5464:
597   case PCI_CHIP_RV370_5B60:
598   case PCI_CHIP_RV370_5B62:
599   case PCI_CHIP_RV370_5B63:
600   case PCI_CHIP_RV370_5B64:
601   case PCI_CHIP_RV370_5B65:
602   case PCI_CHIP_RV370_5657:
603   case PCI_CHIP_RV380_3150:
604   case PCI_CHIP_RV380_3152:
605   case PCI_CHIP_RV380_3154:
606   case PCI_CHIP_RV380_3E50:
607   case PCI_CHIP_RV380_3E54:
608      screen->chip_family = CHIP_FAMILY_RV380;
609      screen->chip_flags = RADEON_CHIPSET_TCL;
610      break;
611
612   case PCI_CHIP_R420_JN:
613   case PCI_CHIP_R420_JH:
614   case PCI_CHIP_R420_JI:
615   case PCI_CHIP_R420_JJ:
616   case PCI_CHIP_R420_JK:
617   case PCI_CHIP_R420_JL:
618   case PCI_CHIP_R420_JM:
619   case PCI_CHIP_R420_JO:
620   case PCI_CHIP_R420_JP:
621   case PCI_CHIP_R420_JT:
622   case PCI_CHIP_R481_4B49:
623   case PCI_CHIP_R481_4B4A:
624   case PCI_CHIP_R481_4B4B:
625   case PCI_CHIP_R481_4B4C:
626   case PCI_CHIP_R423_UH:
627   case PCI_CHIP_R423_UI:
628   case PCI_CHIP_R423_UJ:
629   case PCI_CHIP_R423_UK:
630   case PCI_CHIP_R430_554C:
631   case PCI_CHIP_R430_554D:
632   case PCI_CHIP_R430_554E:
633   case PCI_CHIP_R430_554F:
634   case PCI_CHIP_R423_5550:
635   case PCI_CHIP_R423_UQ:
636   case PCI_CHIP_R423_UR:
637   case PCI_CHIP_R423_UT:
638   case PCI_CHIP_R430_5D48:
639   case PCI_CHIP_R430_5D49:
640   case PCI_CHIP_R430_5D4A:
641   case PCI_CHIP_R480_5D4C:
642   case PCI_CHIP_R480_5D4D:
643   case PCI_CHIP_R480_5D4E:
644   case PCI_CHIP_R480_5D4F:
645   case PCI_CHIP_R480_5D50:
646   case PCI_CHIP_R480_5D52:
647   case PCI_CHIP_R423_5D57:
648      screen->chip_family = CHIP_FAMILY_R420;
649      screen->chip_flags = RADEON_CHIPSET_TCL;
650      break;
651
652   /* RV410 SE chips have half the pipes of regular RV410 */
653   case PCI_CHIP_RV410_5E4C:
654   case PCI_CHIP_RV410_5E4F:
655      screen->chip_family = CHIP_FAMILY_RV380;
656      screen->chip_flags = RADEON_CHIPSET_TCL;
657      break;
658
659   case PCI_CHIP_RV410_564A:
660   case PCI_CHIP_RV410_564B:
661   case PCI_CHIP_RV410_564F:
662   case PCI_CHIP_RV410_5652:
663   case PCI_CHIP_RV410_5653:
664   case PCI_CHIP_RV410_5E48:
665   case PCI_CHIP_RV410_5E4A:
666   case PCI_CHIP_RV410_5E4B:
667   case PCI_CHIP_RV410_5E4D:
668      screen->chip_family = CHIP_FAMILY_RV410;
669      screen->chip_flags = RADEON_CHIPSET_TCL;
670      break;
671
672   case PCI_CHIP_RS480_5954:
673   case PCI_CHIP_RS480_5955:
674   case PCI_CHIP_RS482_5974:
675   case PCI_CHIP_RS482_5975:
676   case PCI_CHIP_RS400_5A41:
677   case PCI_CHIP_RS400_5A42:
678   case PCI_CHIP_RC410_5A61:
679   case PCI_CHIP_RC410_5A62:
680      screen->chip_family = CHIP_FAMILY_RS400;
681      fprintf(stderr, "Warning, xpress200 detected.\n");
682      break;
683
684   case PCI_CHIP_RS690_791E:
685   case PCI_CHIP_RS690_791F:
686      screen->chip_family = CHIP_FAMILY_RS690;
687      fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n");
688      break;
689   case PCI_CHIP_RS740_796C:
690   case PCI_CHIP_RS740_796D:
691   case PCI_CHIP_RS740_796E:
692   case PCI_CHIP_RS740_796F:
693      screen->chip_family = CHIP_FAMILY_RS740;
694      fprintf(stderr, "Warning, RS740 detected, 3D support is incomplete.\n");
695      break;
696
697   case PCI_CHIP_R520_7100:
698   case PCI_CHIP_R520_7101:
699   case PCI_CHIP_R520_7102:
700   case PCI_CHIP_R520_7103:
701   case PCI_CHIP_R520_7104:
702   case PCI_CHIP_R520_7105:
703   case PCI_CHIP_R520_7106:
704   case PCI_CHIP_R520_7108:
705   case PCI_CHIP_R520_7109:
706   case PCI_CHIP_R520_710A:
707   case PCI_CHIP_R520_710B:
708   case PCI_CHIP_R520_710C:
709   case PCI_CHIP_R520_710E:
710   case PCI_CHIP_R520_710F:
711      screen->chip_family = CHIP_FAMILY_R520;
712      fprintf(stderr, "Warning, R520 detected, 3D HAHAHAHAHA!!.\n");
713      break;
714
715   case PCI_CHIP_RV515_7140:
716   case PCI_CHIP_RV515_7141:
717   case PCI_CHIP_RV515_7142:
718   case PCI_CHIP_RV515_7143:
719   case PCI_CHIP_RV515_7144:
720   case PCI_CHIP_RV515_7145:
721   case PCI_CHIP_RV515_7146:
722   case PCI_CHIP_RV515_7147:
723   case PCI_CHIP_RV515_7149:
724   case PCI_CHIP_RV515_714A:
725   case PCI_CHIP_RV515_714B:
726   case PCI_CHIP_RV515_714C:
727   case PCI_CHIP_RV515_714D:
728   case PCI_CHIP_RV515_714E:
729   case PCI_CHIP_RV515_714F:
730   case PCI_CHIP_RV515_7151:
731   case PCI_CHIP_RV515_7152:
732   case PCI_CHIP_RV515_7153:
733   case PCI_CHIP_RV515_715E:
734   case PCI_CHIP_RV515_715F:
735   case PCI_CHIP_RV515_7180:
736   case PCI_CHIP_RV515_7181:
737   case PCI_CHIP_RV515_7183:
738   case PCI_CHIP_RV515_7186:
739   case PCI_CHIP_RV515_7187:
740   case PCI_CHIP_RV515_7188:
741   case PCI_CHIP_RV515_718A:
742   case PCI_CHIP_RV515_718B:
743   case PCI_CHIP_RV515_718C:
744   case PCI_CHIP_RV515_718D:
745   case PCI_CHIP_RV515_718F:
746   case PCI_CHIP_RV515_7193:
747   case PCI_CHIP_RV515_7196:
748   case PCI_CHIP_RV515_719B:
749   case PCI_CHIP_RV515_719F:
750   case PCI_CHIP_RV515_7200:
751   case PCI_CHIP_RV515_7210:
752   case PCI_CHIP_RV515_7211:
753      screen->chip_family = CHIP_FAMILY_RV515;
754      fprintf(stderr, "Warning, RV515 detected, 3D HAHAHAHAHA!!.\n");
755      break;
756
757   case PCI_CHIP_RV530_71C0:
758   case PCI_CHIP_RV530_71C1:
759   case PCI_CHIP_RV530_71C2:
760   case PCI_CHIP_RV530_71C3:
761   case PCI_CHIP_RV530_71C4:
762   case PCI_CHIP_RV530_71C5:
763   case PCI_CHIP_RV530_71C6:
764   case PCI_CHIP_RV530_71C7:
765   case PCI_CHIP_RV530_71CD:
766   case PCI_CHIP_RV530_71CE:
767   case PCI_CHIP_RV530_71D2:
768   case PCI_CHIP_RV530_71D4:
769   case PCI_CHIP_RV530_71D5:
770   case PCI_CHIP_RV530_71D6:
771   case PCI_CHIP_RV530_71DA:
772   case PCI_CHIP_RV530_71DE:
773      screen->chip_family = CHIP_FAMILY_RV530;
774      fprintf(stderr, "Warning, RV530 detected, 3D HAHAHAHAHA!!.\n");
775      break;
776
777   case PCI_CHIP_R580_7240:
778   case PCI_CHIP_R580_7243:
779   case PCI_CHIP_R580_7244:
780   case PCI_CHIP_R580_7245:
781   case PCI_CHIP_R580_7246:
782   case PCI_CHIP_R580_7247:
783   case PCI_CHIP_R580_7248:
784   case PCI_CHIP_R580_7249:
785   case PCI_CHIP_R580_724A:
786   case PCI_CHIP_R580_724B:
787   case PCI_CHIP_R580_724C:
788   case PCI_CHIP_R580_724D:
789   case PCI_CHIP_R580_724E:
790   case PCI_CHIP_R580_724F:
791   case PCI_CHIP_R580_7284:
792      screen->chip_family = CHIP_FAMILY_R580;
793      fprintf(stderr, "Warning, R580 detected, 3D HAHAHAHAHA!!.\n");
794      break;
795
796   case PCI_CHIP_RV570_7280:
797   case PCI_CHIP_RV560_7281:
798   case PCI_CHIP_RV560_7283:
799   case PCI_CHIP_RV560_7287:
800   case PCI_CHIP_RV570_7288:
801   case PCI_CHIP_RV570_7289:
802   case PCI_CHIP_RV570_728B:
803   case PCI_CHIP_RV570_728C:
804   case PCI_CHIP_RV560_7290:
805   case PCI_CHIP_RV560_7291:
806   case PCI_CHIP_RV560_7293:
807   case PCI_CHIP_RV560_7297:
808      screen->chip_family = CHIP_FAMILY_RV560;
809      fprintf(stderr, "Warning, RV560 detected, 3D HAHAHAHAHA!!.\n");
810      break;
811
812   default:
813      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
814	      dri_priv->deviceID);
815      return NULL;
816   }
817   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
818       sPriv->ddx_version.minor < 2) {
819      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
820      return NULL;
821   }
822
823   if (screen->chip_family <= CHIP_FAMILY_RS200)
824      screen->chip_flags |= RADEON_CLASS_R100;
825   else if (screen->chip_family <= CHIP_FAMILY_RV280)
826      screen->chip_flags |= RADEON_CLASS_R200;
827   else
828      screen->chip_flags |= RADEON_CLASS_R300;
829
830   screen->cpp = dri_priv->bpp / 8;
831   screen->AGPMode = dri_priv->AGPMode;
832
833   ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
834                         &temp);
835   if (ret) {
836       if (screen->chip_family < CHIP_FAMILY_RS690)
837	   screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
838       else {
839           FREE( screen );
840           fprintf(stderr, "Unable to get fb location need newer drm\n");
841           return NULL;
842       }
843   } else {
844       screen->fbLocation = (temp & 0xffff) << 16;
845   }
846
847   if ( sPriv->drm_version.minor >= 10 ) {
848      drm_radeon_setparam_t sp;
849
850      sp.param = RADEON_SETPARAM_FB_LOCATION;
851      sp.value = screen->fbLocation;
852
853      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
854		       &sp, sizeof( sp ) );
855   }
856
857   screen->frontOffset	= dri_priv->frontOffset;
858   screen->frontPitch	= dri_priv->frontPitch;
859   screen->backOffset	= dri_priv->backOffset;
860   screen->backPitch	= dri_priv->backPitch;
861   screen->depthOffset	= dri_priv->depthOffset;
862   screen->depthPitch	= dri_priv->depthPitch;
863
864   /* Check if ddx has set up a surface reg to cover depth buffer */
865   screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
866      /* these chips don't use tiled z without hyperz. So always pretend
867         we have set up a surface which will cause linear reads/writes */
868      ((screen->chip_family & RADEON_CLASS_R100) &&
869      !(screen->chip_flags & RADEON_CHIPSET_TCL));
870
871   if ( dri_priv->textureSize == 0 ) {
872      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
873      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
874      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
875	 dri_priv->log2GARTTexGran;
876   } else {
877      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
878				               + screen->fbLocation;
879      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
880      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
881	 dri_priv->log2TexGran;
882   }
883
884   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
885	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
886      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
887      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
888      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
889      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
890   } else {
891      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
892      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
893      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
894      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
895	 dri_priv->log2GARTTexGran;
896   }
897
898   i = 0;
899   screen->extensions[i++] = &driCopySubBufferExtension.base;
900   screen->extensions[i++] = &driFrameTrackingExtension.base;
901   screen->extensions[i++] = &driReadDrawableExtension;
902
903   if ( screen->irq != 0 ) {
904       screen->extensions[i++] = &driSwapControlExtension.base;
905       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
906   }
907
908#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
909   if (IS_R200_CLASS(screen))
910       screen->extensions[i++] = &r200AllocateExtension.base;
911
912   screen->extensions[i++] = &r200texOffsetExtension.base;
913#endif
914
915#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
916   screen->extensions[i++] = &r300texOffsetExtension.base;
917#endif
918
919   screen->extensions[i++] = NULL;
920   sPriv->extensions = screen->extensions;
921
922   screen->driScreen = sPriv;
923   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
924   return screen;
925}
926
927/* Destroy the device specific screen private data struct.
928 */
929static void
930radeonDestroyScreen( __DRIscreenPrivate *sPriv )
931{
932   radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
933
934   if (!screen)
935      return;
936
937   if ( screen->gartTextures.map ) {
938      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
939   }
940   drmUnmapBufs( screen->buffers );
941   drmUnmap( screen->status.map, screen->status.size );
942   drmUnmap( screen->mmio.map, screen->mmio.size );
943
944   /* free all option information */
945   driDestroyOptionInfo (&screen->optionCache);
946
947   FREE( screen );
948   sPriv->private = NULL;
949}
950
951
952/* Initialize the driver specific screen private data.
953 */
954static GLboolean
955radeonInitDriver( __DRIscreenPrivate *sPriv )
956{
957   sPriv->private = (void *) radeonCreateScreen( sPriv );
958   if ( !sPriv->private ) {
959      radeonDestroyScreen( sPriv );
960      return GL_FALSE;
961   }
962
963   return GL_TRUE;
964}
965
966
967/**
968 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
969 *
970 * \todo This function (and its interface) will need to be updated to support
971 * pbuffers.
972 */
973static GLboolean
974radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
975                    __DRIdrawablePrivate *driDrawPriv,
976                    const __GLcontextModes *mesaVis,
977                    GLboolean isPixmap )
978{
979   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
980
981   if (isPixmap) {
982      return GL_FALSE; /* not implemented */
983   }
984   else {
985      const GLboolean swDepth = GL_FALSE;
986      const GLboolean swAlpha = GL_FALSE;
987      const GLboolean swAccum = mesaVis->accumRedBits > 0;
988      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
989         mesaVis->depthBits != 24;
990      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
991
992      /* front color renderbuffer */
993      {
994         driRenderbuffer *frontRb
995            = driNewRenderbuffer(GL_RGBA,
996                                 driScrnPriv->pFB + screen->frontOffset,
997                                 screen->cpp,
998                                 screen->frontOffset, screen->frontPitch,
999                                 driDrawPriv);
1000         radeonSetSpanFunctions(frontRb, mesaVis);
1001         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1002      }
1003
1004      /* back color renderbuffer */
1005      if (mesaVis->doubleBufferMode) {
1006         driRenderbuffer *backRb
1007            = driNewRenderbuffer(GL_RGBA,
1008                                 driScrnPriv->pFB + screen->backOffset,
1009                                 screen->cpp,
1010                                 screen->backOffset, screen->backPitch,
1011                                 driDrawPriv);
1012         radeonSetSpanFunctions(backRb, mesaVis);
1013         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1014      }
1015
1016      /* depth renderbuffer */
1017      if (mesaVis->depthBits == 16) {
1018         driRenderbuffer *depthRb
1019            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1020                                 driScrnPriv->pFB + screen->depthOffset,
1021                                 screen->cpp,
1022                                 screen->depthOffset, screen->depthPitch,
1023                                 driDrawPriv);
1024         radeonSetSpanFunctions(depthRb, mesaVis);
1025         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1026	 depthRb->depthHasSurface = screen->depthHasSurface;
1027      }
1028      else if (mesaVis->depthBits == 24) {
1029         driRenderbuffer *depthRb
1030            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1031                                 driScrnPriv->pFB + screen->depthOffset,
1032                                 screen->cpp,
1033                                 screen->depthOffset, screen->depthPitch,
1034                                 driDrawPriv);
1035         radeonSetSpanFunctions(depthRb, mesaVis);
1036         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1037	 depthRb->depthHasSurface = screen->depthHasSurface;
1038      }
1039
1040      /* stencil renderbuffer */
1041      if (mesaVis->stencilBits > 0 && !swStencil) {
1042         driRenderbuffer *stencilRb
1043            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1044                                 driScrnPriv->pFB + screen->depthOffset,
1045                                 screen->cpp,
1046                                 screen->depthOffset, screen->depthPitch,
1047                                 driDrawPriv);
1048         radeonSetSpanFunctions(stencilRb, mesaVis);
1049         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1050	 stencilRb->depthHasSurface = screen->depthHasSurface;
1051      }
1052
1053      _mesa_add_soft_renderbuffers(fb,
1054                                   GL_FALSE, /* color */
1055                                   swDepth,
1056                                   swStencil,
1057                                   swAccum,
1058                                   swAlpha,
1059                                   GL_FALSE /* aux */);
1060      driDrawPriv->driverPrivate = (void *) fb;
1061
1062      return (driDrawPriv->driverPrivate != NULL);
1063   }
1064}
1065
1066
1067static void
1068radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1069{
1070   _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1071}
1072
1073#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1074/**
1075 * Choose the appropriate CreateContext function based on the chipset.
1076 * Eventually, all drivers will go through this process.
1077 */
1078static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1079				     __DRIcontextPrivate * driContextPriv,
1080				     void *sharedContextPriv)
1081{
1082	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1083	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1084
1085	if (IS_R300_CLASS(screen))
1086		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1087        return GL_FALSE;
1088}
1089
1090/**
1091 * Choose the appropriate DestroyContext function based on the chipset.
1092 */
1093static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1094{
1095	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1096
1097	if (IS_R300_CLASS(radeon->radeonScreen))
1098		return r300DestroyContext(driContextPriv);
1099}
1100
1101
1102#endif
1103
1104/**
1105 * This is the driver specific part of the createNewScreen entry point.
1106 *
1107 * \todo maybe fold this into intelInitDriver
1108 *
1109 * \return the __GLcontextModes supported by this driver
1110 */
1111static const __DRIconfig **
1112radeonInitScreen(__DRIscreenPrivate *psp)
1113{
1114#if !RADEON_COMMON
1115   static const char *driver_name = "Radeon";
1116   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1117   static const __DRIversion dri_expected = { 4, 0, 0 };
1118   static const __DRIversion drm_expected = { 1, 6, 0 };
1119#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1120   static const char *driver_name = "R200";
1121   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1122   static const __DRIversion dri_expected = { 4, 0, 0 };
1123   static const __DRIversion drm_expected = { 1, 6, 0 };
1124#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1125   static const char *driver_name = "R300";
1126   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1127   static const __DRIversion dri_expected = { 4, 0, 0 };
1128   static const __DRIversion drm_expected = { 1, 24, 0 };
1129#endif
1130   RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1131
1132   if ( ! driCheckDriDdxDrmVersions3( driver_name,
1133				      &psp->dri_version, & dri_expected,
1134				      &psp->ddx_version, & ddx_expected,
1135				      &psp->drm_version, & drm_expected ) ) {
1136      return NULL;
1137   }
1138
1139   /* Calling driInitExtensions here, with a NULL context pointer,
1140    * does not actually enable the extensions.  It just makes sure
1141    * that all the dispatch offsets for all the extensions that
1142    * *might* be enables are known.  This is needed because the
1143    * dispatch offsets need to be known when _mesa_context_create
1144    * is called, but we can't enable the extensions until we have a
1145    * context pointer.
1146    *
1147    * Hello chicken.  Hello egg.  How are you two today?
1148    */
1149   driInitExtensions( NULL, card_extensions, GL_FALSE );
1150#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1151   driInitExtensions( NULL, blend_extensions, GL_FALSE );
1152   driInitSingleExtension( NULL, ARB_vp_extension );
1153   driInitSingleExtension( NULL, NV_vp_extension );
1154   driInitSingleExtension( NULL, ATI_fs_extension );
1155   driInitExtensions( NULL, point_extensions, GL_FALSE );
1156#endif
1157
1158   if (!radeonInitDriver(psp))
1159       return NULL;
1160
1161   return radeonFillInModes( psp,
1162			     dri_priv->bpp,
1163			     (dri_priv->bpp == 16) ? 16 : 24,
1164			     (dri_priv->bpp == 16) ? 0  : 8,
1165			     (dri_priv->backOffset != dri_priv->depthOffset) );
1166}
1167
1168
1169/**
1170 * Get information about previous buffer swaps.
1171 */
1172static int
1173getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1174{
1175#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1176   radeonContextPtr  rmesa;
1177#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1178   r200ContextPtr  rmesa;
1179#endif
1180
1181   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1182	|| (dPriv->driContextPriv->driverPrivate == NULL)
1183	|| (sInfo == NULL) ) {
1184      return -1;
1185   }
1186
1187   rmesa = dPriv->driContextPriv->driverPrivate;
1188   sInfo->swap_count = rmesa->swap_count;
1189   sInfo->swap_ust = rmesa->swap_ust;
1190   sInfo->swap_missed_count = rmesa->swap_missed_count;
1191
1192   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1193       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1194       : 0.0;
1195
1196   return 0;
1197}
1198
1199#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1200const struct __DriverAPIRec driDriverAPI = {
1201   .InitScreen      = radeonInitScreen,
1202   .DestroyScreen   = radeonDestroyScreen,
1203   .CreateContext   = radeonCreateContext,
1204   .DestroyContext  = radeonDestroyContext,
1205   .CreateBuffer    = radeonCreateBuffer,
1206   .DestroyBuffer   = radeonDestroyBuffer,
1207   .SwapBuffers     = radeonSwapBuffers,
1208   .MakeCurrent     = radeonMakeCurrent,
1209   .UnbindContext   = radeonUnbindContext,
1210   .GetSwapInfo     = getSwapInfo,
1211   .GetDrawableMSC  = driDrawableGetMSC32,
1212   .WaitForMSC      = driWaitForMSC32,
1213   .WaitForSBC      = NULL,
1214   .SwapBuffersMSC  = NULL,
1215   .CopySubBuffer   = radeonCopySubBuffer,
1216};
1217#else
1218const struct __DriverAPIRec driDriverAPI = {
1219   .InitScreen      = radeonInitScreen,
1220   .DestroyScreen   = radeonDestroyScreen,
1221   .CreateContext   = r200CreateContext,
1222   .DestroyContext  = r200DestroyContext,
1223   .CreateBuffer    = radeonCreateBuffer,
1224   .DestroyBuffer   = radeonDestroyBuffer,
1225   .SwapBuffers     = r200SwapBuffers,
1226   .MakeCurrent     = r200MakeCurrent,
1227   .UnbindContext   = r200UnbindContext,
1228   .GetSwapInfo     = getSwapInfo,
1229   .GetDrawableMSC  = driDrawableGetMSC32,
1230   .WaitForMSC      = driWaitForMSC32,
1231   .WaitForSBC      = NULL,
1232   .SwapBuffersMSC  = NULL,
1233   .CopySubBuffer   = r200CopySubBuffer,
1234};
1235#endif
1236