radeon_screen.c revision 85af4fde7fd5c7f6a6976fbd9d6529a9082f42b7 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author  Gareth Hughes <gareth@valinux.com>
37 */
38
39#include "glheader.h"
40#include "imports.h"
41#include "mtypes.h"
42#include "framebuffer.h"
43#include "renderbuffer.h"
44
45#define STANDALONE_MMIO
46#include "radeon_chipset.h"
47#include "radeon_macros.h"
48#include "radeon_screen.h"
49#if !RADEON_COMMON
50#include "radeon_context.h"
51#include "radeon_span.h"
52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53#include "r200_context.h"
54#include "r200_ioctl.h"
55#include "r200_span.h"
56#include "r200_tex.h"
57#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58#include "r300_context.h"
59#include "r300_fragprog.h"
60#include "r300_tex.h"
61#include "radeon_span.h"
62#endif
63
64#include "utils.h"
65#include "context.h"
66#include "vblank.h"
67#include "drirenderbuffer.h"
68
69#include "GL/internal/dri_interface.h"
70
71/* Radeon configuration
72 */
73#include "xmlpool.h"
74
75#if !RADEON_COMMON	/* R100 */
76PUBLIC const char __driConfigOptions[] =
77DRI_CONF_BEGIN
78    DRI_CONF_SECTION_PERFORMANCE
79        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
80        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
81        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
82        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
83        DRI_CONF_HYPERZ(false)
84    DRI_CONF_SECTION_END
85    DRI_CONF_SECTION_QUALITY
86        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
87        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
88        DRI_CONF_NO_NEG_LOD_BIAS(false)
89        DRI_CONF_FORCE_S3TC_ENABLE(false)
90        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
91        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
92        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
93        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
94    DRI_CONF_SECTION_END
95    DRI_CONF_SECTION_DEBUG
96        DRI_CONF_NO_RAST(false)
97    DRI_CONF_SECTION_END
98DRI_CONF_END;
99static const GLuint __driNConfigOptions = 14;
100
101#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102
103PUBLIC const char __driConfigOptions[] =
104DRI_CONF_BEGIN
105    DRI_CONF_SECTION_PERFORMANCE
106        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
107        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
108        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
109        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
110        DRI_CONF_HYPERZ(false)
111    DRI_CONF_SECTION_END
112    DRI_CONF_SECTION_QUALITY
113        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
114        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
115        DRI_CONF_NO_NEG_LOD_BIAS(false)
116        DRI_CONF_FORCE_S3TC_ENABLE(false)
117        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
118        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
119        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
120        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
121        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122    DRI_CONF_SECTION_END
123    DRI_CONF_SECTION_DEBUG
124        DRI_CONF_NO_RAST(false)
125    DRI_CONF_SECTION_END
126    DRI_CONF_SECTION_SOFTWARE
127        DRI_CONF_NV_VERTEX_PROGRAM(false)
128    DRI_CONF_SECTION_END
129DRI_CONF_END;
130static const GLuint __driNConfigOptions = 16;
131
132extern const struct dri_extension blend_extensions[];
133extern const struct dri_extension ARB_vp_extension[];
134extern const struct dri_extension NV_vp_extension[];
135extern const struct dri_extension ATI_fs_extension[];
136extern const struct dri_extension point_extensions[];
137
138#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139
140/* TODO: integrate these into xmlpool.h! */
141#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
142DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
143        DRI_CONF_DESC(en,"Number of texture image units") \
144        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
145DRI_CONF_OPT_END
146
147#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
148DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
149        DRI_CONF_DESC(en,"Number of texture coordinate units") \
150        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
151DRI_CONF_OPT_END
152
153#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
154DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
155        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
156        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
157DRI_CONF_OPT_END
158
159#define DRI_CONF_DISABLE_S3TC(def) \
160DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
161        DRI_CONF_DESC(en,"Disable S3TC compression") \
162DRI_CONF_OPT_END
163
164#define DRI_CONF_DISABLE_FALLBACK(def) \
165DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
166        DRI_CONF_DESC(en,"Disable Low-impact fallback") \
167DRI_CONF_OPT_END
168
169#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
170DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
171        DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
172DRI_CONF_OPT_END
173
174#define DRI_CONF_FP_OPTIMIZATION(def) \
175DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
176	DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
177                DRI_CONF_ENUM(0,"Optimize for Speed") \
178                DRI_CONF_ENUM(1,"Optimize for Quality") \
179        DRI_CONF_DESC_END \
180DRI_CONF_OPT_END
181
182PUBLIC const char __driConfigOptions[] =
183DRI_CONF_BEGIN
184	DRI_CONF_SECTION_PERFORMANCE
185		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
186		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
187		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
188		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
189		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
190		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
191		DRI_CONF_DISABLE_FALLBACK(false)
192		DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193	DRI_CONF_SECTION_END
194	DRI_CONF_SECTION_QUALITY
195		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
196		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
197		DRI_CONF_NO_NEG_LOD_BIAS(false)
198                DRI_CONF_FORCE_S3TC_ENABLE(false)
199		DRI_CONF_DISABLE_S3TC(false)
200		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
201		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
202		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
203		DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
204	DRI_CONF_SECTION_END
205	DRI_CONF_SECTION_DEBUG
206		DRI_CONF_NO_RAST(false)
207	DRI_CONF_SECTION_END
208DRI_CONF_END;
209static const GLuint __driNConfigOptions = 18;
210
211#ifndef RADEON_DEBUG
212int RADEON_DEBUG = 0;
213
214static const struct dri_debug_control debug_control[] = {
215	{"fall", DEBUG_FALLBACKS},
216	{"tex", DEBUG_TEXTURE},
217	{"ioctl", DEBUG_IOCTL},
218	{"prim", DEBUG_PRIMS},
219	{"vert", DEBUG_VERTS},
220	{"state", DEBUG_STATE},
221	{"code", DEBUG_CODEGEN},
222	{"vfmt", DEBUG_VFMT},
223	{"vtxf", DEBUG_VFMT},
224	{"verb", DEBUG_VERBOSE},
225	{"dri", DEBUG_DRI},
226	{"dma", DEBUG_DMA},
227	{"san", DEBUG_SANITY},
228	{"sync", DEBUG_SYNC},
229	{"pix", DEBUG_PIXEL},
230	{"mem", DEBUG_MEMORY},
231	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
232	{NULL, 0}
233};
234#endif /* RADEON_DEBUG */
235
236#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237
238extern const struct dri_extension card_extensions[];
239
240static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
241
242static int
243radeonGetParam(int fd, int param, void *value)
244{
245  int ret;
246  drm_radeon_getparam_t gp;
247
248  gp.param = param;
249  gp.value = value;
250
251  ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
252  return ret;
253}
254
255static const __DRIconfig **
256radeonFillInModes( __DRIscreenPrivate *psp,
257		   unsigned pixel_bits, unsigned depth_bits,
258		   unsigned stencil_bits, GLboolean have_back_buffer )
259{
260    __DRIconfig **configs;
261    __GLcontextModes *m;
262    unsigned depth_buffer_factor;
263    unsigned back_buffer_factor;
264    GLenum fb_format;
265    GLenum fb_type;
266    int i;
267
268    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269     * enough to add support.  Basically, if a context is created with an
270     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271     * will never be used.
272     */
273    static const GLenum back_buffer_modes[] = {
274	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275    };
276
277    u_int8_t depth_bits_array[2];
278    u_int8_t stencil_bits_array[2];
279
280
281    depth_bits_array[0] = depth_bits;
282    depth_bits_array[1] = depth_bits;
283
284    /* Just like with the accumulation buffer, always provide some modes
285     * with a stencil buffer.  It will be a sw fallback, but some apps won't
286     * care about that.
287     */
288    stencil_bits_array[0] = 0;
289    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291    depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
292    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
293
294    if ( pixel_bits == 16 ) {
295        fb_format = GL_RGB;
296        fb_type = GL_UNSIGNED_SHORT_5_6_5;
297    }
298    else {
299        fb_format = GL_BGRA;
300        fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
301    }
302
303    configs = driCreateConfigs(fb_format, fb_type,
304			       depth_bits_array, stencil_bits_array,
305			       depth_buffer_factor,
306			       back_buffer_modes, back_buffer_factor);
307    if (configs == NULL) {
308	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
309		 __func__, __LINE__ );
310	return NULL;
311    }
312
313    /* Mark the visual as slow if there are "fake" stencil bits.
314     */
315    for (i = 0; configs[i]; i++) {
316	m = &configs[i]->modes;
317	if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
318	    m->visualRating = GLX_SLOW_CONFIG;
319	}
320    }
321
322    return (const __DRIconfig **) configs;
323}
324
325#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
326static const __DRIallocateExtension r200AllocateExtension = {
327    { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
328    r200AllocateMemoryMESA,
329    r200FreeMemoryMESA,
330    r200GetMemoryOffsetMESA
331};
332
333static const __DRItexOffsetExtension r200texOffsetExtension = {
334    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
335   r200SetTexOffset,
336};
337#endif
338
339#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
340static const __DRItexOffsetExtension r300texOffsetExtension = {
341    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
342   r300SetTexOffset,
343};
344#endif
345
346/* Create the device specific screen private data struct.
347 */
348static radeonScreenPtr
349radeonCreateScreen( __DRIscreenPrivate *sPriv )
350{
351   radeonScreenPtr screen;
352   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
353   unsigned char *RADEONMMIO;
354   int i;
355   int ret;
356   uint32_t temp;
357
358   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
359      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
360      return GL_FALSE;
361   }
362
363   /* Allocate the private area */
364   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
365   if ( !screen ) {
366      __driUtilMessage("%s: Could not allocate memory for screen structure",
367		       __FUNCTION__);
368      return NULL;
369   }
370
371#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
372	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
373#endif
374
375   /* parse information in __driConfigOptions */
376   driParseOptionInfo (&screen->optionCache,
377		       __driConfigOptions, __driNConfigOptions);
378
379   /* This is first since which regions we map depends on whether or
380    * not we are using a PCI card.
381    */
382   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
383   {
384      int ret;
385      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
386			    &screen->gart_buffer_offset);
387
388      if (ret) {
389	 FREE( screen );
390	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
391	 return NULL;
392      }
393
394      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
395			    &screen->gart_base);
396      if (ret) {
397	 FREE( screen );
398	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
399	 return NULL;
400      }
401
402      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
403			    &screen->irq);
404      if (ret) {
405	 FREE( screen );
406	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
407	 return NULL;
408      }
409      screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
410      screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
411      screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
412      screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
413      screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
414      screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
415      screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
416   }
417
418   screen->mmio.handle = dri_priv->registerHandle;
419   screen->mmio.size   = dri_priv->registerSize;
420   if ( drmMap( sPriv->fd,
421		screen->mmio.handle,
422		screen->mmio.size,
423		&screen->mmio.map ) ) {
424      FREE( screen );
425      __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
426      return NULL;
427   }
428
429   RADEONMMIO = screen->mmio.map;
430
431   screen->status.handle = dri_priv->statusHandle;
432   screen->status.size   = dri_priv->statusSize;
433   if ( drmMap( sPriv->fd,
434		screen->status.handle,
435		screen->status.size,
436		&screen->status.map ) ) {
437      drmUnmap( screen->mmio.map, screen->mmio.size );
438      FREE( screen );
439      __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
440      return NULL;
441   }
442   screen->scratch = (__volatile__ u_int32_t *)
443      ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
444
445   screen->buffers = drmMapBufs( sPriv->fd );
446   if ( !screen->buffers ) {
447      drmUnmap( screen->status.map, screen->status.size );
448      drmUnmap( screen->mmio.map, screen->mmio.size );
449      FREE( screen );
450      __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
451      return NULL;
452   }
453
454   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
455      screen->gartTextures.handle = dri_priv->gartTexHandle;
456      screen->gartTextures.size   = dri_priv->gartTexMapSize;
457      if ( drmMap( sPriv->fd,
458		   screen->gartTextures.handle,
459		   screen->gartTextures.size,
460		   (drmAddressPtr)&screen->gartTextures.map ) ) {
461	 drmUnmapBufs( screen->buffers );
462	 drmUnmap( screen->status.map, screen->status.size );
463	 drmUnmap( screen->mmio.map, screen->mmio.size );
464	 FREE( screen );
465	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
466	 return NULL;
467      }
468
469      screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
470   }
471
472   screen->chip_flags = 0;
473   /* XXX: add more chipsets */
474   switch ( dri_priv->deviceID ) {
475   case PCI_CHIP_RADEON_LY:
476   case PCI_CHIP_RADEON_LZ:
477   case PCI_CHIP_RADEON_QY:
478   case PCI_CHIP_RADEON_QZ:
479   case PCI_CHIP_RN50_515E:
480   case PCI_CHIP_RN50_5969:
481      screen->chip_family = CHIP_FAMILY_RV100;
482      break;
483
484   case PCI_CHIP_RS100_4136:
485   case PCI_CHIP_RS100_4336:
486      screen->chip_family = CHIP_FAMILY_RS100;
487      break;
488
489   case PCI_CHIP_RS200_4137:
490   case PCI_CHIP_RS200_4337:
491   case PCI_CHIP_RS250_4237:
492   case PCI_CHIP_RS250_4437:
493      screen->chip_family = CHIP_FAMILY_RS200;
494      break;
495
496   case PCI_CHIP_RADEON_QD:
497   case PCI_CHIP_RADEON_QE:
498   case PCI_CHIP_RADEON_QF:
499   case PCI_CHIP_RADEON_QG:
500      /* all original radeons (7200) presumably have a stencil op bug */
501      screen->chip_family = CHIP_FAMILY_R100;
502      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
503      break;
504
505   case PCI_CHIP_RV200_QW:
506   case PCI_CHIP_RV200_QX:
507   case PCI_CHIP_RADEON_LW:
508   case PCI_CHIP_RADEON_LX:
509      screen->chip_family = CHIP_FAMILY_RV200;
510      screen->chip_flags = RADEON_CHIPSET_TCL;
511      break;
512
513   case PCI_CHIP_R200_BB:
514   case PCI_CHIP_R200_BC:
515   case PCI_CHIP_R200_QH:
516   case PCI_CHIP_R200_QL:
517   case PCI_CHIP_R200_QM:
518      screen->chip_family = CHIP_FAMILY_R200;
519      screen->chip_flags = RADEON_CHIPSET_TCL;
520      break;
521
522   case PCI_CHIP_RV250_If:
523   case PCI_CHIP_RV250_Ig:
524   case PCI_CHIP_RV250_Ld:
525   case PCI_CHIP_RV250_Lf:
526   case PCI_CHIP_RV250_Lg:
527      screen->chip_family = CHIP_FAMILY_RV250;
528      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
529      break;
530
531   case PCI_CHIP_RV280_5960:
532   case PCI_CHIP_RV280_5961:
533   case PCI_CHIP_RV280_5962:
534   case PCI_CHIP_RV280_5964:
535   case PCI_CHIP_RV280_5965:
536   case PCI_CHIP_RV280_5C61:
537   case PCI_CHIP_RV280_5C63:
538      screen->chip_family = CHIP_FAMILY_RV280;
539      screen->chip_flags = RADEON_CHIPSET_TCL;
540      break;
541
542   case PCI_CHIP_RS300_5834:
543   case PCI_CHIP_RS300_5835:
544   case PCI_CHIP_RS350_7834:
545   case PCI_CHIP_RS350_7835:
546      screen->chip_family = CHIP_FAMILY_RS300;
547      break;
548
549      /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
550   case PCI_CHIP_R300_AD:
551      screen->chip_family = CHIP_FAMILY_RV350;
552      screen->chip_flags = RADEON_CHIPSET_TCL;
553      break;
554   case PCI_CHIP_R300_AE:
555   case PCI_CHIP_R300_AF:
556   case PCI_CHIP_R300_AG:
557   case PCI_CHIP_R300_ND:
558   case PCI_CHIP_R300_NE:
559   case PCI_CHIP_R300_NF:
560   case PCI_CHIP_R300_NG:
561      screen->chip_family = CHIP_FAMILY_R300;
562      screen->chip_flags = RADEON_CHIPSET_TCL;
563      break;
564
565   case PCI_CHIP_RV350_AP:
566   case PCI_CHIP_RV350_AQ:
567   case PCI_CHIP_RV350_AR:
568   case PCI_CHIP_RV350_AS:
569   case PCI_CHIP_RV350_AT:
570   case PCI_CHIP_RV350_AV:
571   case PCI_CHIP_RV350_AU:
572   case PCI_CHIP_RV350_NP:
573   case PCI_CHIP_RV350_NQ:
574   case PCI_CHIP_RV350_NR:
575   case PCI_CHIP_RV350_NS:
576   case PCI_CHIP_RV350_NT:
577   case PCI_CHIP_RV350_NV:
578      screen->chip_family = CHIP_FAMILY_RV350;
579      screen->chip_flags = RADEON_CHIPSET_TCL;
580      break;
581
582   case PCI_CHIP_R350_AH:
583   case PCI_CHIP_R350_AI:
584   case PCI_CHIP_R350_AJ:
585   case PCI_CHIP_R350_AK:
586   case PCI_CHIP_R350_NH:
587   case PCI_CHIP_R350_NI:
588   case PCI_CHIP_R360_NJ:
589   case PCI_CHIP_R350_NK:
590      screen->chip_family = CHIP_FAMILY_R350;
591      screen->chip_flags = RADEON_CHIPSET_TCL;
592      break;
593
594   case PCI_CHIP_RV370_5460:
595   case PCI_CHIP_RV370_5462:
596   case PCI_CHIP_RV370_5464:
597   case PCI_CHIP_RV370_5B60:
598   case PCI_CHIP_RV370_5B62:
599   case PCI_CHIP_RV370_5B63:
600   case PCI_CHIP_RV370_5B64:
601   case PCI_CHIP_RV370_5B65:
602   case PCI_CHIP_RV370_5657:
603   case PCI_CHIP_RV380_3150:
604   case PCI_CHIP_RV380_3152:
605   case PCI_CHIP_RV380_3154:
606   case PCI_CHIP_RV380_3E50:
607   case PCI_CHIP_RV380_3E54:
608      screen->chip_family = CHIP_FAMILY_RV380;
609      screen->chip_flags = RADEON_CHIPSET_TCL;
610      break;
611
612   case PCI_CHIP_R420_JN:
613   case PCI_CHIP_R420_JH:
614   case PCI_CHIP_R420_JI:
615   case PCI_CHIP_R420_JJ:
616   case PCI_CHIP_R420_JK:
617   case PCI_CHIP_R420_JL:
618   case PCI_CHIP_R420_JM:
619   case PCI_CHIP_R420_JO:
620   case PCI_CHIP_R420_JP:
621   case PCI_CHIP_R420_JT:
622   case PCI_CHIP_R481_4B49:
623   case PCI_CHIP_R481_4B4A:
624   case PCI_CHIP_R481_4B4B:
625   case PCI_CHIP_R481_4B4C:
626   case PCI_CHIP_R423_UH:
627   case PCI_CHIP_R423_UI:
628   case PCI_CHIP_R423_UJ:
629   case PCI_CHIP_R423_UK:
630   case PCI_CHIP_R430_554C:
631   case PCI_CHIP_R430_554D:
632   case PCI_CHIP_R430_554E:
633   case PCI_CHIP_R430_554F:
634   case PCI_CHIP_R423_5550:
635   case PCI_CHIP_R423_UQ:
636   case PCI_CHIP_R423_UR:
637   case PCI_CHIP_R423_UT:
638   case PCI_CHIP_R430_5D48:
639   case PCI_CHIP_R430_5D49:
640   case PCI_CHIP_R430_5D4A:
641   case PCI_CHIP_R480_5D4C:
642   case PCI_CHIP_R480_5D4D:
643   case PCI_CHIP_R480_5D4E:
644   case PCI_CHIP_R480_5D4F:
645   case PCI_CHIP_R480_5D50:
646   case PCI_CHIP_R480_5D52:
647   case PCI_CHIP_R423_5D57:
648      screen->chip_family = CHIP_FAMILY_R420;
649      screen->chip_flags = RADEON_CHIPSET_TCL;
650      break;
651
652   case PCI_CHIP_RV410_5E4C:
653   case PCI_CHIP_RV410_5E4F:
654   case PCI_CHIP_RV410_564A:
655   case PCI_CHIP_RV410_564B:
656   case PCI_CHIP_RV410_564F:
657   case PCI_CHIP_RV410_5652:
658   case PCI_CHIP_RV410_5653:
659   case PCI_CHIP_RV410_5E48:
660   case PCI_CHIP_RV410_5E4A:
661   case PCI_CHIP_RV410_5E4B:
662   case PCI_CHIP_RV410_5E4D:
663      screen->chip_family = CHIP_FAMILY_RV410;
664      screen->chip_flags = RADEON_CHIPSET_TCL;
665      break;
666
667   case PCI_CHIP_RS480_5954:
668   case PCI_CHIP_RS480_5955:
669   case PCI_CHIP_RS482_5974:
670   case PCI_CHIP_RS482_5975:
671   case PCI_CHIP_RS400_5A41:
672   case PCI_CHIP_RS400_5A42:
673   case PCI_CHIP_RC410_5A61:
674   case PCI_CHIP_RC410_5A62:
675      screen->chip_family = CHIP_FAMILY_RS400;
676      break;
677
678   case PCI_CHIP_RS690_791E:
679   case PCI_CHIP_RS690_791F:
680      screen->chip_family = CHIP_FAMILY_RS690;
681      break;
682   case PCI_CHIP_RS740_796C:
683   case PCI_CHIP_RS740_796D:
684   case PCI_CHIP_RS740_796E:
685   case PCI_CHIP_RS740_796F:
686      screen->chip_family = CHIP_FAMILY_RS740;
687      break;
688
689   case PCI_CHIP_R520_7100:
690   case PCI_CHIP_R520_7101:
691   case PCI_CHIP_R520_7102:
692   case PCI_CHIP_R520_7103:
693   case PCI_CHIP_R520_7104:
694   case PCI_CHIP_R520_7105:
695   case PCI_CHIP_R520_7106:
696   case PCI_CHIP_R520_7108:
697   case PCI_CHIP_R520_7109:
698   case PCI_CHIP_R520_710A:
699   case PCI_CHIP_R520_710B:
700   case PCI_CHIP_R520_710C:
701   case PCI_CHIP_R520_710E:
702   case PCI_CHIP_R520_710F:
703      screen->chip_family = CHIP_FAMILY_R520;
704      screen->chip_flags = RADEON_CHIPSET_TCL;
705      break;
706
707   case PCI_CHIP_RV515_7140:
708   case PCI_CHIP_RV515_7141:
709   case PCI_CHIP_RV515_7142:
710   case PCI_CHIP_RV515_7143:
711   case PCI_CHIP_RV515_7144:
712   case PCI_CHIP_RV515_7145:
713   case PCI_CHIP_RV515_7146:
714   case PCI_CHIP_RV515_7147:
715   case PCI_CHIP_RV515_7149:
716   case PCI_CHIP_RV515_714A:
717   case PCI_CHIP_RV515_714B:
718   case PCI_CHIP_RV515_714C:
719   case PCI_CHIP_RV515_714D:
720   case PCI_CHIP_RV515_714E:
721   case PCI_CHIP_RV515_714F:
722   case PCI_CHIP_RV515_7151:
723   case PCI_CHIP_RV515_7152:
724   case PCI_CHIP_RV515_7153:
725   case PCI_CHIP_RV515_715E:
726   case PCI_CHIP_RV515_715F:
727   case PCI_CHIP_RV515_7180:
728   case PCI_CHIP_RV515_7181:
729   case PCI_CHIP_RV515_7183:
730   case PCI_CHIP_RV515_7186:
731   case PCI_CHIP_RV515_7187:
732   case PCI_CHIP_RV515_7188:
733   case PCI_CHIP_RV515_718A:
734   case PCI_CHIP_RV515_718B:
735   case PCI_CHIP_RV515_718C:
736   case PCI_CHIP_RV515_718D:
737   case PCI_CHIP_RV515_718F:
738   case PCI_CHIP_RV515_7193:
739   case PCI_CHIP_RV515_7196:
740   case PCI_CHIP_RV515_719B:
741   case PCI_CHIP_RV515_719F:
742   case PCI_CHIP_RV515_7200:
743   case PCI_CHIP_RV515_7210:
744   case PCI_CHIP_RV515_7211:
745      screen->chip_family = CHIP_FAMILY_RV515;
746      screen->chip_flags = RADEON_CHIPSET_TCL;
747      break;
748
749   case PCI_CHIP_RV530_71C0:
750   case PCI_CHIP_RV530_71C1:
751   case PCI_CHIP_RV530_71C2:
752   case PCI_CHIP_RV530_71C3:
753   case PCI_CHIP_RV530_71C4:
754   case PCI_CHIP_RV530_71C5:
755   case PCI_CHIP_RV530_71C6:
756   case PCI_CHIP_RV530_71C7:
757   case PCI_CHIP_RV530_71CD:
758   case PCI_CHIP_RV530_71CE:
759   case PCI_CHIP_RV530_71D2:
760   case PCI_CHIP_RV530_71D4:
761   case PCI_CHIP_RV530_71D5:
762   case PCI_CHIP_RV530_71D6:
763   case PCI_CHIP_RV530_71DA:
764   case PCI_CHIP_RV530_71DE:
765      screen->chip_family = CHIP_FAMILY_RV530;
766      screen->chip_flags = RADEON_CHIPSET_TCL;
767      break;
768
769   case PCI_CHIP_R580_7240:
770   case PCI_CHIP_R580_7243:
771   case PCI_CHIP_R580_7244:
772   case PCI_CHIP_R580_7245:
773   case PCI_CHIP_R580_7246:
774   case PCI_CHIP_R580_7247:
775   case PCI_CHIP_R580_7248:
776   case PCI_CHIP_R580_7249:
777   case PCI_CHIP_R580_724A:
778   case PCI_CHIP_R580_724B:
779   case PCI_CHIP_R580_724C:
780   case PCI_CHIP_R580_724D:
781   case PCI_CHIP_R580_724E:
782   case PCI_CHIP_R580_724F:
783   case PCI_CHIP_R580_7284:
784      screen->chip_family = CHIP_FAMILY_R580;
785      screen->chip_flags = RADEON_CHIPSET_TCL;
786      break;
787
788   case PCI_CHIP_RV570_7280:
789   case PCI_CHIP_RV560_7281:
790   case PCI_CHIP_RV560_7283:
791   case PCI_CHIP_RV560_7287:
792   case PCI_CHIP_RV570_7288:
793   case PCI_CHIP_RV570_7289:
794   case PCI_CHIP_RV570_728B:
795   case PCI_CHIP_RV570_728C:
796   case PCI_CHIP_RV560_7290:
797   case PCI_CHIP_RV560_7291:
798   case PCI_CHIP_RV560_7293:
799   case PCI_CHIP_RV560_7297:
800      screen->chip_family = CHIP_FAMILY_RV560;
801      screen->chip_flags = RADEON_CHIPSET_TCL;
802      break;
803
804   default:
805      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
806	      dri_priv->deviceID);
807      return NULL;
808   }
809   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
810       sPriv->ddx_version.minor < 2) {
811      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
812      return NULL;
813   }
814
815   if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
816      fprintf(stderr, "R500 support requires a newer drm.\n");
817      return NULL;
818   }
819
820   if (getenv("R300_NO_TCL"))
821     screen->chip_flags &= ~RADEON_CHIPSET_TCL;
822
823   if (screen->chip_family <= CHIP_FAMILY_RS200)
824      screen->chip_flags |= RADEON_CLASS_R100;
825   else if (screen->chip_family <= CHIP_FAMILY_RV280)
826      screen->chip_flags |= RADEON_CLASS_R200;
827   else
828      screen->chip_flags |= RADEON_CLASS_R300;
829
830   screen->cpp = dri_priv->bpp / 8;
831   screen->AGPMode = dri_priv->AGPMode;
832
833   ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
834                         &temp);
835   if (ret) {
836       if (screen->chip_family < CHIP_FAMILY_RS690)
837	   screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
838       else {
839           FREE( screen );
840           fprintf(stderr, "Unable to get fb location need newer drm\n");
841           return NULL;
842       }
843   } else {
844       screen->fbLocation = (temp & 0xffff) << 16;
845   }
846
847   if (screen->chip_family >= CHIP_FAMILY_RV515) {
848       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
849			     &temp);
850       if (ret) {
851	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
852	   switch (screen->chip_family) {
853	   case CHIP_FAMILY_R300:
854	   case CHIP_FAMILY_R350:
855	       screen->num_gb_pipes = 2;
856	       break;
857	   case CHIP_FAMILY_R420:
858	   case CHIP_FAMILY_R520:
859	   case CHIP_FAMILY_R580:
860	   case CHIP_FAMILY_RV560:
861	   case CHIP_FAMILY_RV570:
862	       screen->num_gb_pipes = 4;
863	       break;
864	   case CHIP_FAMILY_RV350:
865	   case CHIP_FAMILY_RV515:
866	   case CHIP_FAMILY_RV530:
867	   case CHIP_FAMILY_RV410:
868	   default:
869	       screen->num_gb_pipes = 1;
870	       break;
871	   }
872       } else {
873	   screen->num_gb_pipes = temp;
874       }
875   }
876
877   if ( sPriv->drm_version.minor >= 10 ) {
878      drm_radeon_setparam_t sp;
879
880      sp.param = RADEON_SETPARAM_FB_LOCATION;
881      sp.value = screen->fbLocation;
882
883      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
884		       &sp, sizeof( sp ) );
885   }
886
887   screen->frontOffset	= dri_priv->frontOffset;
888   screen->frontPitch	= dri_priv->frontPitch;
889   screen->backOffset	= dri_priv->backOffset;
890   screen->backPitch	= dri_priv->backPitch;
891   screen->depthOffset	= dri_priv->depthOffset;
892   screen->depthPitch	= dri_priv->depthPitch;
893
894   /* Check if ddx has set up a surface reg to cover depth buffer */
895   screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
896      /* these chips don't use tiled z without hyperz. So always pretend
897         we have set up a surface which will cause linear reads/writes */
898      ((screen->chip_family & RADEON_CLASS_R100) &&
899      !(screen->chip_flags & RADEON_CHIPSET_TCL));
900
901   if ( dri_priv->textureSize == 0 ) {
902      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
903      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
904      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
905	 dri_priv->log2GARTTexGran;
906   } else {
907      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
908				               + screen->fbLocation;
909      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
910      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
911	 dri_priv->log2TexGran;
912   }
913
914   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
915	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
916      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
917      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
918      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
919      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
920   } else {
921      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
922      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
923      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
924      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
925	 dri_priv->log2GARTTexGran;
926   }
927
928   i = 0;
929   screen->extensions[i++] = &driCopySubBufferExtension.base;
930   screen->extensions[i++] = &driFrameTrackingExtension.base;
931   screen->extensions[i++] = &driReadDrawableExtension;
932
933   if ( screen->irq != 0 ) {
934       screen->extensions[i++] = &driSwapControlExtension.base;
935       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
936   }
937
938#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
939   if (IS_R200_CLASS(screen))
940       screen->extensions[i++] = &r200AllocateExtension.base;
941
942   screen->extensions[i++] = &r200texOffsetExtension.base;
943#endif
944
945#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
946   screen->extensions[i++] = &r300texOffsetExtension.base;
947#endif
948
949   screen->extensions[i++] = NULL;
950   sPriv->extensions = screen->extensions;
951
952   screen->driScreen = sPriv;
953   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
954   return screen;
955}
956
957/* Destroy the device specific screen private data struct.
958 */
959static void
960radeonDestroyScreen( __DRIscreenPrivate *sPriv )
961{
962   radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
963
964   if (!screen)
965      return;
966
967   if ( screen->gartTextures.map ) {
968      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
969   }
970   drmUnmapBufs( screen->buffers );
971   drmUnmap( screen->status.map, screen->status.size );
972   drmUnmap( screen->mmio.map, screen->mmio.size );
973
974   /* free all option information */
975   driDestroyOptionInfo (&screen->optionCache);
976
977   FREE( screen );
978   sPriv->private = NULL;
979}
980
981
982/* Initialize the driver specific screen private data.
983 */
984static GLboolean
985radeonInitDriver( __DRIscreenPrivate *sPriv )
986{
987   sPriv->private = (void *) radeonCreateScreen( sPriv );
988   if ( !sPriv->private ) {
989      radeonDestroyScreen( sPriv );
990      return GL_FALSE;
991   }
992
993   return GL_TRUE;
994}
995
996
997/**
998 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
999 *
1000 * \todo This function (and its interface) will need to be updated to support
1001 * pbuffers.
1002 */
1003static GLboolean
1004radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1005                    __DRIdrawablePrivate *driDrawPriv,
1006                    const __GLcontextModes *mesaVis,
1007                    GLboolean isPixmap )
1008{
1009   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1010
1011   if (isPixmap) {
1012      return GL_FALSE; /* not implemented */
1013   }
1014   else {
1015      const GLboolean swDepth = GL_FALSE;
1016      const GLboolean swAlpha = GL_FALSE;
1017      const GLboolean swAccum = mesaVis->accumRedBits > 0;
1018      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1019         mesaVis->depthBits != 24;
1020      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1021
1022      /* front color renderbuffer */
1023      {
1024         driRenderbuffer *frontRb
1025            = driNewRenderbuffer(GL_RGBA,
1026                                 driScrnPriv->pFB + screen->frontOffset,
1027                                 screen->cpp,
1028                                 screen->frontOffset, screen->frontPitch,
1029                                 driDrawPriv);
1030         radeonSetSpanFunctions(frontRb, mesaVis);
1031         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1032      }
1033
1034      /* back color renderbuffer */
1035      if (mesaVis->doubleBufferMode) {
1036         driRenderbuffer *backRb
1037            = driNewRenderbuffer(GL_RGBA,
1038                                 driScrnPriv->pFB + screen->backOffset,
1039                                 screen->cpp,
1040                                 screen->backOffset, screen->backPitch,
1041                                 driDrawPriv);
1042         radeonSetSpanFunctions(backRb, mesaVis);
1043         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1044      }
1045
1046      /* depth renderbuffer */
1047      if (mesaVis->depthBits == 16) {
1048         driRenderbuffer *depthRb
1049            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1050                                 driScrnPriv->pFB + screen->depthOffset,
1051                                 screen->cpp,
1052                                 screen->depthOffset, screen->depthPitch,
1053                                 driDrawPriv);
1054         radeonSetSpanFunctions(depthRb, mesaVis);
1055         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1056	 depthRb->depthHasSurface = screen->depthHasSurface;
1057      }
1058      else if (mesaVis->depthBits == 24) {
1059         driRenderbuffer *depthRb
1060            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1061                                 driScrnPriv->pFB + screen->depthOffset,
1062                                 screen->cpp,
1063                                 screen->depthOffset, screen->depthPitch,
1064                                 driDrawPriv);
1065         radeonSetSpanFunctions(depthRb, mesaVis);
1066         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1067	 depthRb->depthHasSurface = screen->depthHasSurface;
1068      }
1069
1070      /* stencil renderbuffer */
1071      if (mesaVis->stencilBits > 0 && !swStencil) {
1072         driRenderbuffer *stencilRb
1073            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1074                                 driScrnPriv->pFB + screen->depthOffset,
1075                                 screen->cpp,
1076                                 screen->depthOffset, screen->depthPitch,
1077                                 driDrawPriv);
1078         radeonSetSpanFunctions(stencilRb, mesaVis);
1079         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1080	 stencilRb->depthHasSurface = screen->depthHasSurface;
1081      }
1082
1083      _mesa_add_soft_renderbuffers(fb,
1084                                   GL_FALSE, /* color */
1085                                   swDepth,
1086                                   swStencil,
1087                                   swAccum,
1088                                   swAlpha,
1089                                   GL_FALSE /* aux */);
1090      driDrawPriv->driverPrivate = (void *) fb;
1091
1092      return (driDrawPriv->driverPrivate != NULL);
1093   }
1094}
1095
1096
1097static void
1098radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1099{
1100   _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1101}
1102
1103#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1104/**
1105 * Choose the appropriate CreateContext function based on the chipset.
1106 * Eventually, all drivers will go through this process.
1107 */
1108static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1109				     __DRIcontextPrivate * driContextPriv,
1110				     void *sharedContextPriv)
1111{
1112	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1113	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1114
1115	if (IS_R300_CLASS(screen))
1116		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1117        return GL_FALSE;
1118}
1119
1120/**
1121 * Choose the appropriate DestroyContext function based on the chipset.
1122 */
1123static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1124{
1125	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1126
1127	if (IS_R300_CLASS(radeon->radeonScreen))
1128		return r300DestroyContext(driContextPriv);
1129}
1130
1131
1132#endif
1133
1134/**
1135 * This is the driver specific part of the createNewScreen entry point.
1136 *
1137 * \todo maybe fold this into intelInitDriver
1138 *
1139 * \return the __GLcontextModes supported by this driver
1140 */
1141static const __DRIconfig **
1142radeonInitScreen(__DRIscreenPrivate *psp)
1143{
1144#if !RADEON_COMMON
1145   static const char *driver_name = "Radeon";
1146   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1147   static const __DRIversion dri_expected = { 4, 0, 0 };
1148   static const __DRIversion drm_expected = { 1, 6, 0 };
1149#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1150   static const char *driver_name = "R200";
1151   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1152   static const __DRIversion dri_expected = { 4, 0, 0 };
1153   static const __DRIversion drm_expected = { 1, 6, 0 };
1154#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1155   static const char *driver_name = "R300";
1156   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1157   static const __DRIversion dri_expected = { 4, 0, 0 };
1158   static const __DRIversion drm_expected = { 1, 24, 0 };
1159#endif
1160   RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1161
1162   if ( ! driCheckDriDdxDrmVersions3( driver_name,
1163				      &psp->dri_version, & dri_expected,
1164				      &psp->ddx_version, & ddx_expected,
1165				      &psp->drm_version, & drm_expected ) ) {
1166      return NULL;
1167   }
1168
1169   /* Calling driInitExtensions here, with a NULL context pointer,
1170    * does not actually enable the extensions.  It just makes sure
1171    * that all the dispatch offsets for all the extensions that
1172    * *might* be enables are known.  This is needed because the
1173    * dispatch offsets need to be known when _mesa_context_create
1174    * is called, but we can't enable the extensions until we have a
1175    * context pointer.
1176    *
1177    * Hello chicken.  Hello egg.  How are you two today?
1178    */
1179   driInitExtensions( NULL, card_extensions, GL_FALSE );
1180#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1181   driInitExtensions( NULL, blend_extensions, GL_FALSE );
1182   driInitSingleExtension( NULL, ARB_vp_extension );
1183   driInitSingleExtension( NULL, NV_vp_extension );
1184   driInitSingleExtension( NULL, ATI_fs_extension );
1185   driInitExtensions( NULL, point_extensions, GL_FALSE );
1186#endif
1187
1188   if (!radeonInitDriver(psp))
1189       return NULL;
1190
1191   return radeonFillInModes( psp,
1192			     dri_priv->bpp,
1193			     (dri_priv->bpp == 16) ? 16 : 24,
1194			     (dri_priv->bpp == 16) ? 0  : 8,
1195			     (dri_priv->backOffset != dri_priv->depthOffset) );
1196}
1197
1198
1199/**
1200 * Get information about previous buffer swaps.
1201 */
1202static int
1203getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1204{
1205#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1206   radeonContextPtr  rmesa;
1207#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1208   r200ContextPtr  rmesa;
1209#endif
1210
1211   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1212	|| (dPriv->driContextPriv->driverPrivate == NULL)
1213	|| (sInfo == NULL) ) {
1214      return -1;
1215   }
1216
1217   rmesa = dPriv->driContextPriv->driverPrivate;
1218   sInfo->swap_count = rmesa->swap_count;
1219   sInfo->swap_ust = rmesa->swap_ust;
1220   sInfo->swap_missed_count = rmesa->swap_missed_count;
1221
1222   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1223       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1224       : 0.0;
1225
1226   return 0;
1227}
1228
1229#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1230const struct __DriverAPIRec driDriverAPI = {
1231   .InitScreen      = radeonInitScreen,
1232   .DestroyScreen   = radeonDestroyScreen,
1233   .CreateContext   = radeonCreateContext,
1234   .DestroyContext  = radeonDestroyContext,
1235   .CreateBuffer    = radeonCreateBuffer,
1236   .DestroyBuffer   = radeonDestroyBuffer,
1237   .SwapBuffers     = radeonSwapBuffers,
1238   .MakeCurrent     = radeonMakeCurrent,
1239   .UnbindContext   = radeonUnbindContext,
1240   .GetSwapInfo     = getSwapInfo,
1241   .GetDrawableMSC  = driDrawableGetMSC32,
1242   .WaitForMSC      = driWaitForMSC32,
1243   .WaitForSBC      = NULL,
1244   .SwapBuffersMSC  = NULL,
1245   .CopySubBuffer   = radeonCopySubBuffer,
1246};
1247#else
1248const struct __DriverAPIRec driDriverAPI = {
1249   .InitScreen      = radeonInitScreen,
1250   .DestroyScreen   = radeonDestroyScreen,
1251   .CreateContext   = r200CreateContext,
1252   .DestroyContext  = r200DestroyContext,
1253   .CreateBuffer    = radeonCreateBuffer,
1254   .DestroyBuffer   = radeonDestroyBuffer,
1255   .SwapBuffers     = r200SwapBuffers,
1256   .MakeCurrent     = r200MakeCurrent,
1257   .UnbindContext   = r200UnbindContext,
1258   .GetSwapInfo     = getSwapInfo,
1259   .GetDrawableMSC  = driDrawableGetMSC32,
1260   .WaitForMSC      = driWaitForMSC32,
1261   .WaitForSBC      = NULL,
1262   .SwapBuffersMSC  = NULL,
1263   .CopySubBuffer   = r200CopySubBuffer,
1264};
1265#endif
1266