radeon_screen.c revision 918ef7ff18dc407d8ab1d6dc9cfb1267618c6534
15c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)/************************************************************************** 25c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 35c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 45c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) VA Linux Systems Inc., Fremont, California. 55c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 65c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)All Rights Reserved. 75c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 85c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)Permission is hereby granted, free of charge, to any person obtaining 95c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)a copy of this software and associated documentation files (the 105c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)"Software"), to deal in the Software without restriction, including 115c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)without limitation the rights to use, copy, modify, merge, publish, 125c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)distribute, sublicense, and/or sell copies of the Software, and to 135c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)permit persons to whom the Software is furnished to do so, subject to 145c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)the following conditions: 155c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 165c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)The above copyright notice and this permission notice (including the 175c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)next paragraph) shall be included in all copies or substantial 185c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)portions of the Software. 195c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 205c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 215c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 225c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 235c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 245c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 255c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 265c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 275c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 285c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)**************************************************************************/ 295c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 305c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)/** 315c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) * \file radeon_screen.c 325c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) * Screen initialization functions for the Radeon driver. 335c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) * 345c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) * \author Kevin E. Martin <martin@valinux.com> 355c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) * \author Gareth Hughes <gareth@valinux.com> 365c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) */ 375c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 385c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include <errno.h> 395c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "main/glheader.h" 40926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)#include "main/imports.h" 415c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "main/mtypes.h" 42926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)#include "main/framebuffer.h" 4309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)#include "main/renderbuffer.h" 4409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 4509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)#define STANDALONE_MMIO 465c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "radeon_chipset.h" 475c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "radeon_macros.h" 485c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "radeon_screen.h" 495c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "radeon_common.h" 505c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#if defined(RADEON_R100) 515c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "radeon_context.h" 525c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "radeon_tex.h" 535c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#elif defined(RADEON_R200) 545c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r200_context.h" 555c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r200_tex.h" 565c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#elif defined(RADEON_R300) 575c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r300_context.h" 585c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r300_tex.h" 595c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#elif defined(RADEON_R600) 605c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r600_context.h" 615c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r700_driconf.h" /* +r6/r7 */ 625c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "r600_tex.h" /* +r6/r7 */ 635c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#endif 645c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 655c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#include "utils.h" 66926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)#include "vblank.h" 67926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 68926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)#include "radeon_bocs_wrapper.h" 69926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 70926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)#include "GL/internal/dri_interface.h" 7109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 7209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)/* Radeon configuration 7309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) */ 7409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)#include "xmlpool.h" 7509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 7609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 7709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 7809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 7909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 8009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)DRI_CONF_OPT_END 8109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 8209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)#if defined(RADEON_R100) /* R100 */ 8309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)PUBLIC const char __driConfigOptions[] = 8409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)DRI_CONF_BEGIN 8509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_PERFORMANCE 865c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 875c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 885c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 895c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 905c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_HYPERZ(false) 915c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 925c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 935c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_QUALITY 945c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 955c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 965c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_NO_NEG_LOD_BIAS(false) 975c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_FORCE_S3TC_ENABLE(false) 985c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 995c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 1005c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 1015c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_ALLOW_LARGE_TEXTURES(2) 1025c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 1035c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_DEBUG 1045c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_NO_RAST(false) 1055c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 1065c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_END; 1075c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)static const GLuint __driNConfigOptions = 15; 1085c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1095c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#elif defined(RADEON_R200) 1105c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1115c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)PUBLIC const char __driConfigOptions[] = 1125c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_BEGIN 1135c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_PERFORMANCE 1145c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 1155c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 1165c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 1175c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 1185c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_HYPERZ(false) 1195c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 1205c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 1215c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_QUALITY 1225c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 1235c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 1245c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_NO_NEG_LOD_BIAS(false) 1255c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_FORCE_S3TC_ENABLE(false) 1265c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 1275c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 1285c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 1295c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_ALLOW_LARGE_TEXTURES(2) 1305c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 1315c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 1325c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_DEBUG 1335c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_NO_RAST(false) 1345c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 1355c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_SOFTWARE 1365c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_NV_VERTEX_PROGRAM(false) 1375c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_SECTION_END 1385c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_END; 1395c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)static const GLuint __driNConfigOptions = 17; 1405c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1415c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#elif defined(RADEON_R300) || defined(RADEON_R600) 1425c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1435c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_FP_OPTIMIZATION_SPEED 0 1445c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1 1455c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1465c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)/* TODO: integrate these into xmlpool.h! */ 1475c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 1485c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 1495c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(en,"Number of texture image units") \ 1505c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 1515c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_END 1525c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1535c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 1545c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 1555c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(en,"Number of texture coordinate units") \ 1565c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 1575c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_END 1585c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1595c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1605c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1615c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_DISABLE_S3TC(def) \ 1625c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 1635c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(en,"Disable S3TC compression") \ 1645c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_END 1655c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1665c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_DISABLE_FALLBACK(def) \ 1675c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 1685c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 1695c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_END 1705c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1715c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 1725c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 1735c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 1745c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_END 1755c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 1765c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define DRI_CONF_FP_OPTIMIZATION(def) \ 1775c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 1785c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 17909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_ENUM(0,"Optimize for Speed") \ 18009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_ENUM(1,"Optimize for Quality") \ 18109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DESC_END \ 18209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)DRI_CONF_OPT_END 18309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 18409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)PUBLIC const char __driConfigOptions[] = 18509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)DRI_CONF_BEGIN 18609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_PERFORMANCE 18709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 18809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 18909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 19009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 19109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 19209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 19309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DISABLE_FALLBACK(true) 19409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 19509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_END 19609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_QUALITY 19709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 19809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 19909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_FORCE_S3TC_ENABLE(false) 20009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DISABLE_S3TC(false) 20109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 20209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 20309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 20409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 20509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_END 20609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_DEBUG 20709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_NO_RAST(false) 20809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) DRI_CONF_SECTION_END 20909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)DRI_CONF_END; 21009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)static const GLuint __driNConfigOptions = 17; 21109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 2125c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#endif 2135c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 2145c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ); 2155c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 2165c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#ifndef RADEON_INFO_TILE_CONFIG 2175c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)#define RADEON_INFO_TILE_CONFIG 0x6 218d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)#endif 2195c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 2205c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)static int 2215c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles)radeonGetParam(__DRIscreen *sPriv, int param, void *value) 2225c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles){ 223d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) int ret; 2245c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) drm_radeon_getparam_t gp = { 0 }; 225d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) struct drm_radeon_info info = { 0 }; 226d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 2275c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) if (sPriv->drm_version.major >= 2) { 2285c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) info.value = (uint64_t)(uintptr_t)value; 2295c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) switch (param) { 2305c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) case RADEON_PARAM_DEVICE_ID: 2315c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) info.request = RADEON_INFO_DEVICE_ID; 2325c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) break; 2335c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) case RADEON_PARAM_NUM_GB_PIPES: 234d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) info.request = RADEON_INFO_NUM_GB_PIPES; 235d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) break; 236d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) case RADEON_PARAM_NUM_Z_PIPES: 2375c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) info.request = RADEON_INFO_NUM_Z_PIPES; 2385c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) break; 2395c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) case RADEON_INFO_TILE_CONFIG: 2405c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) info.request = RADEON_INFO_TILE_CONFIG; 2415c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) break; 2425c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) default: 2435c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) return -EINVAL; 2445c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) } 245d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 2465c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) } else { 247d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) gp.param = param; 2485c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) gp.value = value; 2495c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) 2505c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 2515c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) } 2525c87bf8b86a7c82ef50fb7a89697d8e02e2553beTorne (Richard Coles) return ret; 253926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)} 254926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 255926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)static const __DRIconfig ** 256926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles)radeonFillInModes( __DRIscreen *psp, 257926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) unsigned pixel_bits, unsigned depth_bits, 258926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) unsigned stencil_bits, GLboolean have_back_buffer ) 259926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles){ 260926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) __DRIconfig **configs; 261926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) __GLcontextModes *m; 262926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) unsigned depth_buffer_factor; 263926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) unsigned back_buffer_factor; 264926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) int i; 265926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 266926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 267926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) * enough to add support. Basically, if a context is created with an 268926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 269926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) * will never be used. 270926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) */ 271926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) static const GLenum back_buffer_modes[] = { 272926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 273926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) }; 274926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 275926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) uint8_t depth_bits_array[2]; 276926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) uint8_t stencil_bits_array[2]; 277926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) uint8_t msaa_samples_array[1]; 278926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 279926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) depth_bits_array[0] = depth_bits; 280926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) depth_bits_array[1] = depth_bits; 281926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 282926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) /* Just like with the accumulation buffer, always provide some modes 283926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) * with a stencil buffer. It will be a sw fallback, but some apps won't 284926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) * care about that. 285926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) */ 286926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) stencil_bits_array[0] = stencil_bits; 287926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 288926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 289926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) msaa_samples_array[0] = 0; 290926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 291926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) depth_buffer_factor = (stencil_bits == 0) ? 2 : 1; 292926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) back_buffer_factor = (have_back_buffer) ? 2 : 1; 293926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 294926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) if (pixel_bits == 16) { 295926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) __DRIconfig **configs_a8r8g8b8; 296926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) __DRIconfig **configs_r5g6b5; 297926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 298926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 299926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) depth_bits_array, stencil_bits_array, 300926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) depth_buffer_factor, back_buffer_modes, 301926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) back_buffer_factor, msaa_samples_array, 302926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 1, GL_TRUE); 303926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 304926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) depth_bits_array, stencil_bits_array, 305926b001d589ce2f10facb93dd4b87578ea35a855Torne (Richard Coles) 1, back_buffer_modes, 1, 306 msaa_samples_array, 1, GL_TRUE); 307 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 308 } else 309 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 310 depth_bits_array, stencil_bits_array, 311 depth_buffer_factor, 312 back_buffer_modes, back_buffer_factor, 313 msaa_samples_array, 1, GL_TRUE); 314 315 if (configs == NULL) { 316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 317 __func__, __LINE__ ); 318 return NULL; 319 } 320 321 /* Mark the visual as slow if there are "fake" stencil bits. 322 */ 323 for (i = 0; configs[i]; i++) { 324 m = &configs[i]->modes; 325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 326 m->visualRating = GLX_SLOW_CONFIG; 327 } 328 } 329 330 return (const __DRIconfig **) configs; 331} 332 333#if defined(RADEON_R100) 334static const __DRItexOffsetExtension radeonTexOffsetExtension = { 335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 336 radeonSetTexOffset, 337}; 338 339static const __DRItexBufferExtension radeonTexBufferExtension = { 340 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 341 radeonSetTexBuffer, 342 radeonSetTexBuffer2, 343}; 344#endif 345 346#if defined(RADEON_R200) 347 348static const __DRItexOffsetExtension r200texOffsetExtension = { 349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 350 r200SetTexOffset, 351}; 352 353static const __DRItexBufferExtension r200TexBufferExtension = { 354 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 355 r200SetTexBuffer, 356 r200SetTexBuffer2, 357}; 358#endif 359 360#if defined(RADEON_R300) 361static const __DRItexOffsetExtension r300texOffsetExtension = { 362 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 363 r300SetTexOffset, 364}; 365 366static const __DRItexBufferExtension r300TexBufferExtension = { 367 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 368 r300SetTexBuffer, 369 r300SetTexBuffer2, 370}; 371#endif 372 373#if defined(RADEON_R600) 374static const __DRItexOffsetExtension r600texOffsetExtension = { 375 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 376 r600SetTexOffset, /* +r6/r7 */ 377}; 378 379static const __DRItexBufferExtension r600TexBufferExtension = { 380 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 381 r600SetTexBuffer, /* +r6/r7 */ 382 r600SetTexBuffer2, /* +r6/r7 */ 383}; 384#endif 385 386static void 387radeonDRI2Flush(__DRIdrawable *drawable) 388{ 389 radeonContextPtr rmesa; 390 391 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; 392 radeonFlush(rmesa->glCtx); 393} 394 395static const struct __DRI2flushExtensionRec radeonFlushExtension = { 396 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION }, 397 radeonDRI2Flush, 398 dri2InvalidateDrawable, 399}; 400 401static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 402{ 403 screen->device_id = device_id; 404 screen->chip_flags = 0; 405 switch ( device_id ) { 406 case PCI_CHIP_RN50_515E: 407 case PCI_CHIP_RN50_5969: 408 return -1; 409 410 case PCI_CHIP_RADEON_LY: 411 case PCI_CHIP_RADEON_LZ: 412 case PCI_CHIP_RADEON_QY: 413 case PCI_CHIP_RADEON_QZ: 414 screen->chip_family = CHIP_FAMILY_RV100; 415 break; 416 417 case PCI_CHIP_RS100_4136: 418 case PCI_CHIP_RS100_4336: 419 screen->chip_family = CHIP_FAMILY_RS100; 420 break; 421 422 case PCI_CHIP_RS200_4137: 423 case PCI_CHIP_RS200_4337: 424 case PCI_CHIP_RS250_4237: 425 case PCI_CHIP_RS250_4437: 426 screen->chip_family = CHIP_FAMILY_RS200; 427 break; 428 429 case PCI_CHIP_RADEON_QD: 430 case PCI_CHIP_RADEON_QE: 431 case PCI_CHIP_RADEON_QF: 432 case PCI_CHIP_RADEON_QG: 433 /* all original radeons (7200) presumably have a stencil op bug */ 434 screen->chip_family = CHIP_FAMILY_R100; 435 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 436 break; 437 438 case PCI_CHIP_RV200_QW: 439 case PCI_CHIP_RV200_QX: 440 case PCI_CHIP_RADEON_LW: 441 case PCI_CHIP_RADEON_LX: 442 screen->chip_family = CHIP_FAMILY_RV200; 443 screen->chip_flags = RADEON_CHIPSET_TCL; 444 break; 445 446 case PCI_CHIP_R200_BB: 447 case PCI_CHIP_R200_BC: 448 case PCI_CHIP_R200_QH: 449 case PCI_CHIP_R200_QL: 450 case PCI_CHIP_R200_QM: 451 screen->chip_family = CHIP_FAMILY_R200; 452 screen->chip_flags = RADEON_CHIPSET_TCL; 453 break; 454 455 case PCI_CHIP_RV250_If: 456 case PCI_CHIP_RV250_Ig: 457 case PCI_CHIP_RV250_Ld: 458 case PCI_CHIP_RV250_Lf: 459 case PCI_CHIP_RV250_Lg: 460 screen->chip_family = CHIP_FAMILY_RV250; 461 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 462 break; 463 464 case PCI_CHIP_RV280_5960: 465 case PCI_CHIP_RV280_5961: 466 case PCI_CHIP_RV280_5962: 467 case PCI_CHIP_RV280_5964: 468 case PCI_CHIP_RV280_5965: 469 case PCI_CHIP_RV280_5C61: 470 case PCI_CHIP_RV280_5C63: 471 screen->chip_family = CHIP_FAMILY_RV280; 472 screen->chip_flags = RADEON_CHIPSET_TCL; 473 break; 474 475 case PCI_CHIP_RS300_5834: 476 case PCI_CHIP_RS300_5835: 477 case PCI_CHIP_RS350_7834: 478 case PCI_CHIP_RS350_7835: 479 screen->chip_family = CHIP_FAMILY_RS300; 480 break; 481 482 case PCI_CHIP_R300_AD: 483 case PCI_CHIP_R300_AE: 484 case PCI_CHIP_R300_AF: 485 case PCI_CHIP_R300_AG: 486 case PCI_CHIP_R300_ND: 487 case PCI_CHIP_R300_NE: 488 case PCI_CHIP_R300_NF: 489 case PCI_CHIP_R300_NG: 490 screen->chip_family = CHIP_FAMILY_R300; 491 screen->chip_flags = RADEON_CHIPSET_TCL; 492 break; 493 494 case PCI_CHIP_RV350_AP: 495 case PCI_CHIP_RV350_AQ: 496 case PCI_CHIP_RV350_AR: 497 case PCI_CHIP_RV350_AS: 498 case PCI_CHIP_RV350_AT: 499 case PCI_CHIP_RV350_AV: 500 case PCI_CHIP_RV350_AU: 501 case PCI_CHIP_RV350_NP: 502 case PCI_CHIP_RV350_NQ: 503 case PCI_CHIP_RV350_NR: 504 case PCI_CHIP_RV350_NS: 505 case PCI_CHIP_RV350_NT: 506 case PCI_CHIP_RV350_NV: 507 screen->chip_family = CHIP_FAMILY_RV350; 508 screen->chip_flags = RADEON_CHIPSET_TCL; 509 break; 510 511 case PCI_CHIP_R350_AH: 512 case PCI_CHIP_R350_AI: 513 case PCI_CHIP_R350_AJ: 514 case PCI_CHIP_R350_AK: 515 case PCI_CHIP_R350_NH: 516 case PCI_CHIP_R350_NI: 517 case PCI_CHIP_R360_NJ: 518 case PCI_CHIP_R350_NK: 519 screen->chip_family = CHIP_FAMILY_R350; 520 screen->chip_flags = RADEON_CHIPSET_TCL; 521 break; 522 523 case PCI_CHIP_RV370_5460: 524 case PCI_CHIP_RV370_5462: 525 case PCI_CHIP_RV370_5464: 526 case PCI_CHIP_RV370_5B60: 527 case PCI_CHIP_RV370_5B62: 528 case PCI_CHIP_RV370_5B63: 529 case PCI_CHIP_RV370_5B64: 530 case PCI_CHIP_RV370_5B65: 531 case PCI_CHIP_RV380_3150: 532 case PCI_CHIP_RV380_3152: 533 case PCI_CHIP_RV380_3154: 534 case PCI_CHIP_RV380_3155: 535 case PCI_CHIP_RV380_3E50: 536 case PCI_CHIP_RV380_3E54: 537 screen->chip_family = CHIP_FAMILY_RV380; 538 screen->chip_flags = RADEON_CHIPSET_TCL; 539 break; 540 541 case PCI_CHIP_R420_JN: 542 case PCI_CHIP_R420_JH: 543 case PCI_CHIP_R420_JI: 544 case PCI_CHIP_R420_JJ: 545 case PCI_CHIP_R420_JK: 546 case PCI_CHIP_R420_JL: 547 case PCI_CHIP_R420_JM: 548 case PCI_CHIP_R420_JO: 549 case PCI_CHIP_R420_JP: 550 case PCI_CHIP_R420_JT: 551 case PCI_CHIP_R481_4B49: 552 case PCI_CHIP_R481_4B4A: 553 case PCI_CHIP_R481_4B4B: 554 case PCI_CHIP_R481_4B4C: 555 case PCI_CHIP_R423_UH: 556 case PCI_CHIP_R423_UI: 557 case PCI_CHIP_R423_UJ: 558 case PCI_CHIP_R423_UK: 559 case PCI_CHIP_R430_554C: 560 case PCI_CHIP_R430_554D: 561 case PCI_CHIP_R430_554E: 562 case PCI_CHIP_R430_554F: 563 case PCI_CHIP_R423_5550: 564 case PCI_CHIP_R423_UQ: 565 case PCI_CHIP_R423_UR: 566 case PCI_CHIP_R423_UT: 567 case PCI_CHIP_R430_5D48: 568 case PCI_CHIP_R430_5D49: 569 case PCI_CHIP_R430_5D4A: 570 case PCI_CHIP_R480_5D4C: 571 case PCI_CHIP_R480_5D4D: 572 case PCI_CHIP_R480_5D4E: 573 case PCI_CHIP_R480_5D4F: 574 case PCI_CHIP_R480_5D50: 575 case PCI_CHIP_R480_5D52: 576 case PCI_CHIP_R423_5D57: 577 screen->chip_family = CHIP_FAMILY_R420; 578 screen->chip_flags = RADEON_CHIPSET_TCL; 579 break; 580 581 case PCI_CHIP_RV410_5E4C: 582 case PCI_CHIP_RV410_5E4F: 583 case PCI_CHIP_RV410_564A: 584 case PCI_CHIP_RV410_564B: 585 case PCI_CHIP_RV410_564F: 586 case PCI_CHIP_RV410_5652: 587 case PCI_CHIP_RV410_5653: 588 case PCI_CHIP_RV410_5657: 589 case PCI_CHIP_RV410_5E48: 590 case PCI_CHIP_RV410_5E4A: 591 case PCI_CHIP_RV410_5E4B: 592 case PCI_CHIP_RV410_5E4D: 593 screen->chip_family = CHIP_FAMILY_RV410; 594 screen->chip_flags = RADEON_CHIPSET_TCL; 595 break; 596 597 case PCI_CHIP_RS480_5954: 598 case PCI_CHIP_RS480_5955: 599 case PCI_CHIP_RS482_5974: 600 case PCI_CHIP_RS482_5975: 601 case PCI_CHIP_RS400_5A41: 602 case PCI_CHIP_RS400_5A42: 603 case PCI_CHIP_RC410_5A61: 604 case PCI_CHIP_RC410_5A62: 605 screen->chip_family = CHIP_FAMILY_RS400; 606 break; 607 608 case PCI_CHIP_RS600_793F: 609 case PCI_CHIP_RS600_7941: 610 case PCI_CHIP_RS600_7942: 611 screen->chip_family = CHIP_FAMILY_RS600; 612 break; 613 614 case PCI_CHIP_RS690_791E: 615 case PCI_CHIP_RS690_791F: 616 screen->chip_family = CHIP_FAMILY_RS690; 617 break; 618 case PCI_CHIP_RS740_796C: 619 case PCI_CHIP_RS740_796D: 620 case PCI_CHIP_RS740_796E: 621 case PCI_CHIP_RS740_796F: 622 screen->chip_family = CHIP_FAMILY_RS740; 623 break; 624 625 case PCI_CHIP_R520_7100: 626 case PCI_CHIP_R520_7101: 627 case PCI_CHIP_R520_7102: 628 case PCI_CHIP_R520_7103: 629 case PCI_CHIP_R520_7104: 630 case PCI_CHIP_R520_7105: 631 case PCI_CHIP_R520_7106: 632 case PCI_CHIP_R520_7108: 633 case PCI_CHIP_R520_7109: 634 case PCI_CHIP_R520_710A: 635 case PCI_CHIP_R520_710B: 636 case PCI_CHIP_R520_710C: 637 case PCI_CHIP_R520_710E: 638 case PCI_CHIP_R520_710F: 639 screen->chip_family = CHIP_FAMILY_R520; 640 screen->chip_flags = RADEON_CHIPSET_TCL; 641 break; 642 643 case PCI_CHIP_RV515_7140: 644 case PCI_CHIP_RV515_7141: 645 case PCI_CHIP_RV515_7142: 646 case PCI_CHIP_RV515_7143: 647 case PCI_CHIP_RV515_7144: 648 case PCI_CHIP_RV515_7145: 649 case PCI_CHIP_RV515_7146: 650 case PCI_CHIP_RV515_7147: 651 case PCI_CHIP_RV515_7149: 652 case PCI_CHIP_RV515_714A: 653 case PCI_CHIP_RV515_714B: 654 case PCI_CHIP_RV515_714C: 655 case PCI_CHIP_RV515_714D: 656 case PCI_CHIP_RV515_714E: 657 case PCI_CHIP_RV515_714F: 658 case PCI_CHIP_RV515_7151: 659 case PCI_CHIP_RV515_7152: 660 case PCI_CHIP_RV515_7153: 661 case PCI_CHIP_RV515_715E: 662 case PCI_CHIP_RV515_715F: 663 case PCI_CHIP_RV515_7180: 664 case PCI_CHIP_RV515_7181: 665 case PCI_CHIP_RV515_7183: 666 case PCI_CHIP_RV515_7186: 667 case PCI_CHIP_RV515_7187: 668 case PCI_CHIP_RV515_7188: 669 case PCI_CHIP_RV515_718A: 670 case PCI_CHIP_RV515_718B: 671 case PCI_CHIP_RV515_718C: 672 case PCI_CHIP_RV515_718D: 673 case PCI_CHIP_RV515_718F: 674 case PCI_CHIP_RV515_7193: 675 case PCI_CHIP_RV515_7196: 676 case PCI_CHIP_RV515_719B: 677 case PCI_CHIP_RV515_719F: 678 case PCI_CHIP_RV515_7200: 679 case PCI_CHIP_RV515_7210: 680 case PCI_CHIP_RV515_7211: 681 screen->chip_family = CHIP_FAMILY_RV515; 682 screen->chip_flags = RADEON_CHIPSET_TCL; 683 break; 684 685 case PCI_CHIP_RV530_71C0: 686 case PCI_CHIP_RV530_71C1: 687 case PCI_CHIP_RV530_71C2: 688 case PCI_CHIP_RV530_71C3: 689 case PCI_CHIP_RV530_71C4: 690 case PCI_CHIP_RV530_71C5: 691 case PCI_CHIP_RV530_71C6: 692 case PCI_CHIP_RV530_71C7: 693 case PCI_CHIP_RV530_71CD: 694 case PCI_CHIP_RV530_71CE: 695 case PCI_CHIP_RV530_71D2: 696 case PCI_CHIP_RV530_71D4: 697 case PCI_CHIP_RV530_71D5: 698 case PCI_CHIP_RV530_71D6: 699 case PCI_CHIP_RV530_71DA: 700 case PCI_CHIP_RV530_71DE: 701 screen->chip_family = CHIP_FAMILY_RV530; 702 screen->chip_flags = RADEON_CHIPSET_TCL; 703 break; 704 705 case PCI_CHIP_R580_7240: 706 case PCI_CHIP_R580_7243: 707 case PCI_CHIP_R580_7244: 708 case PCI_CHIP_R580_7245: 709 case PCI_CHIP_R580_7246: 710 case PCI_CHIP_R580_7247: 711 case PCI_CHIP_R580_7248: 712 case PCI_CHIP_R580_7249: 713 case PCI_CHIP_R580_724A: 714 case PCI_CHIP_R580_724B: 715 case PCI_CHIP_R580_724C: 716 case PCI_CHIP_R580_724D: 717 case PCI_CHIP_R580_724E: 718 case PCI_CHIP_R580_724F: 719 case PCI_CHIP_R580_7284: 720 screen->chip_family = CHIP_FAMILY_R580; 721 screen->chip_flags = RADEON_CHIPSET_TCL; 722 break; 723 724 case PCI_CHIP_RV570_7280: 725 case PCI_CHIP_RV560_7281: 726 case PCI_CHIP_RV560_7283: 727 case PCI_CHIP_RV560_7287: 728 case PCI_CHIP_RV570_7288: 729 case PCI_CHIP_RV570_7289: 730 case PCI_CHIP_RV570_728B: 731 case PCI_CHIP_RV570_728C: 732 case PCI_CHIP_RV560_7290: 733 case PCI_CHIP_RV560_7291: 734 case PCI_CHIP_RV560_7293: 735 case PCI_CHIP_RV560_7297: 736 screen->chip_family = CHIP_FAMILY_RV560; 737 screen->chip_flags = RADEON_CHIPSET_TCL; 738 break; 739 740 case PCI_CHIP_R600_9400: 741 case PCI_CHIP_R600_9401: 742 case PCI_CHIP_R600_9402: 743 case PCI_CHIP_R600_9403: 744 case PCI_CHIP_R600_9405: 745 case PCI_CHIP_R600_940A: 746 case PCI_CHIP_R600_940B: 747 case PCI_CHIP_R600_940F: 748 screen->chip_family = CHIP_FAMILY_R600; 749 screen->chip_flags = RADEON_CHIPSET_TCL; 750 break; 751 752 case PCI_CHIP_RV610_94C0: 753 case PCI_CHIP_RV610_94C1: 754 case PCI_CHIP_RV610_94C3: 755 case PCI_CHIP_RV610_94C4: 756 case PCI_CHIP_RV610_94C5: 757 case PCI_CHIP_RV610_94C6: 758 case PCI_CHIP_RV610_94C7: 759 case PCI_CHIP_RV610_94C8: 760 case PCI_CHIP_RV610_94C9: 761 case PCI_CHIP_RV610_94CB: 762 case PCI_CHIP_RV610_94CC: 763 case PCI_CHIP_RV610_94CD: 764 screen->chip_family = CHIP_FAMILY_RV610; 765 screen->chip_flags = RADEON_CHIPSET_TCL; 766 break; 767 768 case PCI_CHIP_RV630_9580: 769 case PCI_CHIP_RV630_9581: 770 case PCI_CHIP_RV630_9583: 771 case PCI_CHIP_RV630_9586: 772 case PCI_CHIP_RV630_9587: 773 case PCI_CHIP_RV630_9588: 774 case PCI_CHIP_RV630_9589: 775 case PCI_CHIP_RV630_958A: 776 case PCI_CHIP_RV630_958B: 777 case PCI_CHIP_RV630_958C: 778 case PCI_CHIP_RV630_958D: 779 case PCI_CHIP_RV630_958E: 780 case PCI_CHIP_RV630_958F: 781 screen->chip_family = CHIP_FAMILY_RV630; 782 screen->chip_flags = RADEON_CHIPSET_TCL; 783 break; 784 785 case PCI_CHIP_RV670_9500: 786 case PCI_CHIP_RV670_9501: 787 case PCI_CHIP_RV670_9504: 788 case PCI_CHIP_RV670_9505: 789 case PCI_CHIP_RV670_9506: 790 case PCI_CHIP_RV670_9507: 791 case PCI_CHIP_RV670_9508: 792 case PCI_CHIP_RV670_9509: 793 case PCI_CHIP_RV670_950F: 794 case PCI_CHIP_RV670_9511: 795 case PCI_CHIP_RV670_9515: 796 case PCI_CHIP_RV670_9517: 797 case PCI_CHIP_RV670_9519: 798 screen->chip_family = CHIP_FAMILY_RV670; 799 screen->chip_flags = RADEON_CHIPSET_TCL; 800 break; 801 802 case PCI_CHIP_RV620_95C0: 803 case PCI_CHIP_RV620_95C2: 804 case PCI_CHIP_RV620_95C4: 805 case PCI_CHIP_RV620_95C5: 806 case PCI_CHIP_RV620_95C6: 807 case PCI_CHIP_RV620_95C7: 808 case PCI_CHIP_RV620_95C9: 809 case PCI_CHIP_RV620_95CC: 810 case PCI_CHIP_RV620_95CD: 811 case PCI_CHIP_RV620_95CE: 812 case PCI_CHIP_RV620_95CF: 813 screen->chip_family = CHIP_FAMILY_RV620; 814 screen->chip_flags = RADEON_CHIPSET_TCL; 815 break; 816 817 case PCI_CHIP_RV635_9590: 818 case PCI_CHIP_RV635_9591: 819 case PCI_CHIP_RV635_9593: 820 case PCI_CHIP_RV635_9595: 821 case PCI_CHIP_RV635_9596: 822 case PCI_CHIP_RV635_9597: 823 case PCI_CHIP_RV635_9598: 824 case PCI_CHIP_RV635_9599: 825 case PCI_CHIP_RV635_959B: 826 screen->chip_family = CHIP_FAMILY_RV635; 827 screen->chip_flags = RADEON_CHIPSET_TCL; 828 break; 829 830 case PCI_CHIP_RS780_9610: 831 case PCI_CHIP_RS780_9611: 832 case PCI_CHIP_RS780_9612: 833 case PCI_CHIP_RS780_9613: 834 case PCI_CHIP_RS780_9614: 835 case PCI_CHIP_RS780_9615: 836 case PCI_CHIP_RS780_9616: 837 screen->chip_family = CHIP_FAMILY_RS780; 838 screen->chip_flags = RADEON_CHIPSET_TCL; 839 break; 840 case PCI_CHIP_RS880_9710: 841 case PCI_CHIP_RS880_9711: 842 case PCI_CHIP_RS880_9712: 843 case PCI_CHIP_RS880_9713: 844 case PCI_CHIP_RS880_9714: 845 case PCI_CHIP_RS880_9715: 846 screen->chip_family = CHIP_FAMILY_RS880; 847 screen->chip_flags = RADEON_CHIPSET_TCL; 848 break; 849 850 case PCI_CHIP_RV770_9440: 851 case PCI_CHIP_RV770_9441: 852 case PCI_CHIP_RV770_9442: 853 case PCI_CHIP_RV770_9443: 854 case PCI_CHIP_RV770_9444: 855 case PCI_CHIP_RV770_9446: 856 case PCI_CHIP_RV770_944A: 857 case PCI_CHIP_RV770_944B: 858 case PCI_CHIP_RV770_944C: 859 case PCI_CHIP_RV770_944E: 860 case PCI_CHIP_RV770_9450: 861 case PCI_CHIP_RV770_9452: 862 case PCI_CHIP_RV770_9456: 863 case PCI_CHIP_RV770_945A: 864 case PCI_CHIP_RV770_945B: 865 case PCI_CHIP_RV770_945E: 866 case PCI_CHIP_RV790_9460: 867 case PCI_CHIP_RV790_9462: 868 case PCI_CHIP_RV770_946A: 869 case PCI_CHIP_RV770_946B: 870 case PCI_CHIP_RV770_947A: 871 case PCI_CHIP_RV770_947B: 872 screen->chip_family = CHIP_FAMILY_RV770; 873 screen->chip_flags = RADEON_CHIPSET_TCL; 874 break; 875 876 case PCI_CHIP_RV730_9480: 877 case PCI_CHIP_RV730_9487: 878 case PCI_CHIP_RV730_9488: 879 case PCI_CHIP_RV730_9489: 880 case PCI_CHIP_RV730_948A: 881 case PCI_CHIP_RV730_948F: 882 case PCI_CHIP_RV730_9490: 883 case PCI_CHIP_RV730_9491: 884 case PCI_CHIP_RV730_9495: 885 case PCI_CHIP_RV730_9498: 886 case PCI_CHIP_RV730_949C: 887 case PCI_CHIP_RV730_949E: 888 case PCI_CHIP_RV730_949F: 889 screen->chip_family = CHIP_FAMILY_RV730; 890 screen->chip_flags = RADEON_CHIPSET_TCL; 891 break; 892 893 case PCI_CHIP_RV710_9540: 894 case PCI_CHIP_RV710_9541: 895 case PCI_CHIP_RV710_9542: 896 case PCI_CHIP_RV710_954E: 897 case PCI_CHIP_RV710_954F: 898 case PCI_CHIP_RV710_9552: 899 case PCI_CHIP_RV710_9553: 900 case PCI_CHIP_RV710_9555: 901 case PCI_CHIP_RV710_9557: 902 case PCI_CHIP_RV710_955F: 903 screen->chip_family = CHIP_FAMILY_RV710; 904 screen->chip_flags = RADEON_CHIPSET_TCL; 905 break; 906 907 case PCI_CHIP_RV740_94A0: 908 case PCI_CHIP_RV740_94A1: 909 case PCI_CHIP_RV740_94A3: 910 case PCI_CHIP_RV740_94B1: 911 case PCI_CHIP_RV740_94B3: 912 case PCI_CHIP_RV740_94B4: 913 case PCI_CHIP_RV740_94B5: 914 case PCI_CHIP_RV740_94B9: 915 screen->chip_family = CHIP_FAMILY_RV740; 916 screen->chip_flags = RADEON_CHIPSET_TCL; 917 break; 918 919 default: 920 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 921 device_id); 922 return -1; 923 } 924 925 return 0; 926} 927 928 929/* Create the device specific screen private data struct. 930 */ 931static radeonScreenPtr 932radeonCreateScreen( __DRIscreen *sPriv ) 933{ 934 radeonScreenPtr screen; 935 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 936 unsigned char *RADEONMMIO = NULL; 937 int i; 938 int ret; 939 uint32_t temp = 0; 940 941 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 942 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 943 return GL_FALSE; 944 } 945 946 /* Allocate the private area */ 947 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 948 if ( !screen ) { 949 __driUtilMessage("%s: Could not allocate memory for screen structure", 950 __FUNCTION__); 951 return NULL; 952 } 953 954 radeon_init_debug(); 955 956 /* parse information in __driConfigOptions */ 957 driParseOptionInfo (&screen->optionCache, 958 __driConfigOptions, __driNConfigOptions); 959 960 /* This is first since which regions we map depends on whether or 961 * not we are using a PCI card. 962 */ 963 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 964 { 965 int ret; 966 967 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 968 &screen->gart_buffer_offset); 969 970 if (ret) { 971 FREE( screen ); 972 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 973 return NULL; 974 } 975 976 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 977 &screen->gart_base); 978 if (ret) { 979 FREE( screen ); 980 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 981 return NULL; 982 } 983 984 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 985 &screen->irq); 986 if (ret) { 987 FREE( screen ); 988 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 989 return NULL; 990 } 991 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 992 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 993 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 994 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 995 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 996 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 997 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 998 screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30); 999 } 1000 1001 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 1002 if (ret == -1) 1003 return NULL; 1004 1005 screen->mmio.handle = dri_priv->registerHandle; 1006 screen->mmio.size = dri_priv->registerSize; 1007 if ( drmMap( sPriv->fd, 1008 screen->mmio.handle, 1009 screen->mmio.size, 1010 &screen->mmio.map ) ) { 1011 FREE( screen ); 1012 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 1013 return NULL; 1014 } 1015 1016 RADEONMMIO = screen->mmio.map; 1017 1018 screen->status.handle = dri_priv->statusHandle; 1019 screen->status.size = dri_priv->statusSize; 1020 if ( drmMap( sPriv->fd, 1021 screen->status.handle, 1022 screen->status.size, 1023 &screen->status.map ) ) { 1024 drmUnmap( screen->mmio.map, screen->mmio.size ); 1025 FREE( screen ); 1026 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1027 return NULL; 1028 } 1029 if (screen->chip_family < CHIP_FAMILY_R600) 1030 screen->scratch = (__volatile__ uint32_t *) 1031 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1032 else 1033 screen->scratch = (__volatile__ uint32_t *) 1034 ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET); 1035 1036 screen->buffers = drmMapBufs( sPriv->fd ); 1037 if ( !screen->buffers ) { 1038 drmUnmap( screen->status.map, screen->status.size ); 1039 drmUnmap( screen->mmio.map, screen->mmio.size ); 1040 FREE( screen ); 1041 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1042 return NULL; 1043 } 1044 1045 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1046 screen->gartTextures.handle = dri_priv->gartTexHandle; 1047 screen->gartTextures.size = dri_priv->gartTexMapSize; 1048 if ( drmMap( sPriv->fd, 1049 screen->gartTextures.handle, 1050 screen->gartTextures.size, 1051 (drmAddressPtr)&screen->gartTextures.map ) ) { 1052 drmUnmapBufs( screen->buffers ); 1053 drmUnmap( screen->status.map, screen->status.size ); 1054 drmUnmap( screen->mmio.map, screen->mmio.size ); 1055 FREE( screen ); 1056 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1057 return NULL; 1058 } 1059 1060 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1061 } 1062 1063 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1064 sPriv->ddx_version.minor < 2) { 1065 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1066 return NULL; 1067 } 1068 1069 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1070 fprintf(stderr, "R500 support requires a newer drm.\n"); 1071 return NULL; 1072 } 1073 1074 if (getenv("R300_NO_TCL")) 1075 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1076 1077 if (screen->chip_family <= CHIP_FAMILY_RS200) 1078 screen->chip_flags |= RADEON_CLASS_R100; 1079 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1080 screen->chip_flags |= RADEON_CLASS_R200; 1081 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1082 screen->chip_flags |= RADEON_CLASS_R300; 1083 else 1084 screen->chip_flags |= RADEON_CLASS_R600; 1085 1086 screen->cpp = dri_priv->bpp / 8; 1087 screen->AGPMode = dri_priv->AGPMode; 1088 1089 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1090 1091 /* +r6/r7 */ 1092 if(screen->chip_family >= CHIP_FAMILY_R600) 1093 { 1094 if (ret) 1095 { 1096 FREE( screen ); 1097 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1098 return NULL; 1099 } 1100 else 1101 { 1102 screen->fbLocation = (temp & 0xffff) << 24; 1103 } 1104 } 1105 else 1106 { 1107 if (ret) 1108 { 1109 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1110 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1111 else 1112 { 1113 FREE( screen ); 1114 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1115 return NULL; 1116 } 1117 } 1118 else 1119 { 1120 screen->fbLocation = (temp & 0xffff) << 16; 1121 } 1122 } 1123 1124 if (IS_R300_CLASS(screen)) { 1125 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1126 if (ret) { 1127 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1128 switch (screen->chip_family) { 1129 case CHIP_FAMILY_R300: 1130 case CHIP_FAMILY_R350: 1131 screen->num_gb_pipes = 2; 1132 break; 1133 case CHIP_FAMILY_R420: 1134 case CHIP_FAMILY_R520: 1135 case CHIP_FAMILY_R580: 1136 case CHIP_FAMILY_RV560: 1137 case CHIP_FAMILY_RV570: 1138 screen->num_gb_pipes = 4; 1139 break; 1140 case CHIP_FAMILY_RV350: 1141 case CHIP_FAMILY_RV515: 1142 case CHIP_FAMILY_RV530: 1143 case CHIP_FAMILY_RV410: 1144 default: 1145 screen->num_gb_pipes = 1; 1146 break; 1147 } 1148 } else { 1149 screen->num_gb_pipes = temp; 1150 } 1151 1152 /* pipe overrides */ 1153 switch (dri_priv->deviceID) { 1154 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1155 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */ 1156 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1157 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1158 screen->num_gb_pipes = 1; 1159 break; 1160 default: 1161 break; 1162 } 1163 1164 if ( sPriv->drm_version.minor >= 31 ) { 1165 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1166 if (ret) 1167 screen->num_z_pipes = 2; 1168 else 1169 screen->num_z_pipes = temp; 1170 } else 1171 screen->num_z_pipes = 2; 1172 } 1173 1174 if ( sPriv->drm_version.minor >= 10 ) { 1175 drm_radeon_setparam_t sp; 1176 1177 sp.param = RADEON_SETPARAM_FB_LOCATION; 1178 sp.value = screen->fbLocation; 1179 1180 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1181 &sp, sizeof( sp ) ); 1182 } 1183 1184 screen->frontOffset = dri_priv->frontOffset; 1185 screen->frontPitch = dri_priv->frontPitch; 1186 screen->backOffset = dri_priv->backOffset; 1187 screen->backPitch = dri_priv->backPitch; 1188 screen->depthOffset = dri_priv->depthOffset; 1189 screen->depthPitch = dri_priv->depthPitch; 1190 1191 /* Check if ddx has set up a surface reg to cover depth buffer */ 1192 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1193 /* these chips don't use tiled z without hyperz. So always pretend 1194 we have set up a surface which will cause linear reads/writes */ 1195 (IS_R100_CLASS(screen) && 1196 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1197 1198 if ( dri_priv->textureSize == 0 ) { 1199 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1200 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1201 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1202 dri_priv->log2GARTTexGran; 1203 } else { 1204 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1205 + screen->fbLocation; 1206 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1207 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1208 dri_priv->log2TexGran; 1209 } 1210 1211 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1212 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1213 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1214 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1215 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1216 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1217 } else { 1218 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1219 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1220 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1221 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1222 dri_priv->log2GARTTexGran; 1223 } 1224 1225 i = 0; 1226 screen->extensions[i++] = &driCopySubBufferExtension.base; 1227 screen->extensions[i++] = &driReadDrawableExtension; 1228 1229 if ( screen->irq != 0 ) { 1230 screen->extensions[i++] = &driSwapControlExtension.base; 1231 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1232 } 1233 1234#if defined(RADEON_R100) 1235 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1236#endif 1237 1238#if defined(RADEON_R200) 1239 screen->extensions[i++] = &r200texOffsetExtension.base; 1240#endif 1241 1242#if defined(RADEON_R300) 1243 screen->extensions[i++] = &r300texOffsetExtension.base; 1244#endif 1245 1246#if defined(RADEON_R600) 1247 screen->extensions[i++] = &r600texOffsetExtension.base; 1248#endif 1249 1250 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1251 1252 screen->extensions[i++] = NULL; 1253 sPriv->extensions = screen->extensions; 1254 1255 screen->driScreen = sPriv; 1256 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1257 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1258 screen->sarea_priv_offset); 1259 1260 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1261 if (screen->bom == NULL) { 1262 free(screen); 1263 return NULL; 1264 } 1265 1266 return screen; 1267} 1268 1269static radeonScreenPtr 1270radeonCreateScreen2(__DRIscreen *sPriv) 1271{ 1272 radeonScreenPtr screen; 1273 int i; 1274 int ret; 1275 uint32_t device_id = 0; 1276 uint32_t temp = 0; 1277 1278 /* Allocate the private area */ 1279 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1280 if ( !screen ) { 1281 __driUtilMessage("%s: Could not allocate memory for screen structure", 1282 __FUNCTION__); 1283 fprintf(stderr, "leaving here\n"); 1284 return NULL; 1285 } 1286 1287 radeon_init_debug(); 1288 1289 /* parse information in __driConfigOptions */ 1290 driParseOptionInfo (&screen->optionCache, 1291 __driConfigOptions, __driNConfigOptions); 1292 1293 screen->kernel_mm = 1; 1294 screen->chip_flags = 0; 1295 1296 /* if we have kms we can support all of these */ 1297 screen->drmSupportsCubeMapsR200 = 1; 1298 screen->drmSupportsBlendColor = 1; 1299 screen->drmSupportsTriPerf = 1; 1300 screen->drmSupportsFragShader = 1; 1301 screen->drmSupportsPointSprites = 1; 1302 screen->drmSupportsCubeMapsR100 = 1; 1303 screen->drmSupportsVertexProgram = 1; 1304 screen->drmSupportsOcclusionQueries = 1; 1305 screen->irq = 1; 1306 1307 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1308 if (ret) { 1309 FREE( screen ); 1310 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1311 return NULL; 1312 } 1313 1314 ret = radeon_set_screen_flags(screen, device_id); 1315 if (ret == -1) 1316 return NULL; 1317 1318 if (getenv("R300_NO_TCL")) 1319 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1320 1321 if (screen->chip_family <= CHIP_FAMILY_RS200) 1322 screen->chip_flags |= RADEON_CLASS_R100; 1323 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1324 screen->chip_flags |= RADEON_CLASS_R200; 1325 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1326 screen->chip_flags |= RADEON_CLASS_R300; 1327 else 1328 screen->chip_flags |= RADEON_CLASS_R600; 1329 1330 /* r6xx+ tiling */ 1331 if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) { 1332 ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp); 1333 if (ret) 1334 fprintf(stderr, "failed to get tiling info\n"); 1335 else { 1336 screen->tile_config = temp; 1337 screen->r7xx_bank_op = 0; 1338 switch((screen->tile_config & 0xe) >> 1) { 1339 case 0: 1340 screen->num_channels = 1; 1341 break; 1342 case 1: 1343 screen->num_channels = 2; 1344 break; 1345 case 2: 1346 screen->num_channels = 4; 1347 break; 1348 case 3: 1349 screen->num_channels = 8; 1350 break; 1351 default: 1352 fprintf(stderr, "bad channels\n"); 1353 break; 1354 } 1355 switch((screen->tile_config & 0x30) >> 4) { 1356 case 0: 1357 screen->num_banks = 4; 1358 break; 1359 case 1: 1360 screen->num_banks = 8; 1361 break; 1362 default: 1363 fprintf(stderr, "bad banks\n"); 1364 break; 1365 } 1366 switch((screen->tile_config & 0xc0) >> 6) { 1367 case 0: 1368 screen->group_bytes = 256; 1369 break; 1370 case 1: 1371 screen->group_bytes = 512; 1372 break; 1373 default: 1374 fprintf(stderr, "bad group_bytes\n"); 1375 break; 1376 } 1377 } 1378 } 1379 1380 if (IS_R300_CLASS(screen)) { 1381 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1382 if (ret) { 1383 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1384 switch (screen->chip_family) { 1385 case CHIP_FAMILY_R300: 1386 case CHIP_FAMILY_R350: 1387 screen->num_gb_pipes = 2; 1388 break; 1389 case CHIP_FAMILY_R420: 1390 case CHIP_FAMILY_R520: 1391 case CHIP_FAMILY_R580: 1392 case CHIP_FAMILY_RV560: 1393 case CHIP_FAMILY_RV570: 1394 screen->num_gb_pipes = 4; 1395 break; 1396 case CHIP_FAMILY_RV350: 1397 case CHIP_FAMILY_RV515: 1398 case CHIP_FAMILY_RV530: 1399 case CHIP_FAMILY_RV410: 1400 default: 1401 screen->num_gb_pipes = 1; 1402 break; 1403 } 1404 } else { 1405 screen->num_gb_pipes = temp; 1406 } 1407 1408 /* pipe overrides */ 1409 switch (device_id) { 1410 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1411 case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */ 1412 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1413 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1414 screen->num_gb_pipes = 1; 1415 break; 1416 default: 1417 break; 1418 } 1419 1420 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp); 1421 if (ret) 1422 screen->num_z_pipes = 2; 1423 else 1424 screen->num_z_pipes = temp; 1425 1426 } 1427 1428 i = 0; 1429 screen->extensions[i++] = &driCopySubBufferExtension.base; 1430 screen->extensions[i++] = &driReadDrawableExtension; 1431 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1432 1433 if ( screen->irq != 0 ) { 1434 screen->extensions[i++] = &driSwapControlExtension.base; 1435 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1436 } 1437 1438#if defined(RADEON_R100) 1439 screen->extensions[i++] = &radeonTexBufferExtension.base; 1440#endif 1441 1442#if defined(RADEON_R200) 1443 screen->extensions[i++] = &r200TexBufferExtension.base; 1444#endif 1445 1446#if defined(RADEON_R300) 1447 screen->extensions[i++] = &r300TexBufferExtension.base; 1448#endif 1449 1450#if defined(RADEON_R600) 1451 screen->extensions[i++] = &r600TexBufferExtension.base; 1452#endif 1453 1454 screen->extensions[i++] = &radeonFlushExtension.base; 1455 1456 screen->extensions[i++] = NULL; 1457 sPriv->extensions = screen->extensions; 1458 1459 screen->driScreen = sPriv; 1460 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1461 if (screen->bom == NULL) { 1462 free(screen); 1463 return NULL; 1464 } 1465 return screen; 1466} 1467 1468/* Destroy the device specific screen private data struct. 1469 */ 1470static void 1471radeonDestroyScreen( __DRIscreen *sPriv ) 1472{ 1473 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1474 1475 if (!screen) 1476 return; 1477 1478 if (screen->kernel_mm) { 1479#ifdef RADEON_BO_TRACK 1480 radeon_tracker_print(&screen->bom->tracker, stderr); 1481#endif 1482 radeon_bo_manager_gem_dtor(screen->bom); 1483 } else { 1484 radeon_bo_manager_legacy_dtor(screen->bom); 1485 1486 if ( screen->gartTextures.map ) { 1487 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1488 } 1489 drmUnmapBufs( screen->buffers ); 1490 drmUnmap( screen->status.map, screen->status.size ); 1491 drmUnmap( screen->mmio.map, screen->mmio.size ); 1492 } 1493 1494 /* free all option information */ 1495 driDestroyOptionInfo (&screen->optionCache); 1496 1497 FREE( screen ); 1498 sPriv->private = NULL; 1499} 1500 1501 1502/* Initialize the driver specific screen private data. 1503 */ 1504static GLboolean 1505radeonInitDriver( __DRIscreen *sPriv ) 1506{ 1507 if (sPriv->dri2.enabled) { 1508 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1509 } else { 1510 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1511 } 1512 if ( !sPriv->private ) { 1513 radeonDestroyScreen( sPriv ); 1514 return GL_FALSE; 1515 } 1516 1517 return GL_TRUE; 1518} 1519 1520 1521 1522/** 1523 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1524 * 1525 * \todo This function (and its interface) will need to be updated to support 1526 * pbuffers. 1527 */ 1528static GLboolean 1529radeonCreateBuffer( __DRIscreen *driScrnPriv, 1530 __DRIdrawable *driDrawPriv, 1531 const __GLcontextModes *mesaVis, 1532 GLboolean isPixmap ) 1533{ 1534 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1535 1536 const GLboolean swDepth = GL_FALSE; 1537 const GLboolean swAlpha = GL_FALSE; 1538 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1539 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1540 mesaVis->depthBits != 24; 1541 gl_format rgbFormat; 1542 struct radeon_framebuffer *rfb; 1543 1544 if (isPixmap) 1545 return GL_FALSE; /* not implemented */ 1546 1547 rfb = CALLOC_STRUCT(radeon_framebuffer); 1548 if (!rfb) 1549 return GL_FALSE; 1550 1551 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis); 1552 1553 if (mesaVis->redBits == 5) 1554 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV; 1555 else if (mesaVis->alphaBits == 0) 1556 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV; 1557 else 1558 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV; 1559 1560 /* front color renderbuffer */ 1561 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1562 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1563 rfb->color_rb[0]->has_surface = 1; 1564 1565 /* back color renderbuffer */ 1566 if (mesaVis->doubleBufferMode) { 1567 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1568 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1569 rfb->color_rb[1]->has_surface = 1; 1570 } 1571 1572 if (mesaVis->depthBits == 24) { 1573 if (mesaVis->stencilBits == 8) { 1574 struct radeon_renderbuffer *depthStencilRb = 1575 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); 1576 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1577 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1578 depthStencilRb->has_surface = screen->depthHasSurface; 1579 } else { 1580 /* depth renderbuffer */ 1581 struct radeon_renderbuffer *depth = 1582 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); 1583 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1584 depth->has_surface = screen->depthHasSurface; 1585 } 1586 } else if (mesaVis->depthBits == 16) { 1587 /* just 16-bit depth buffer, no hw stencil */ 1588 struct radeon_renderbuffer *depth = 1589 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); 1590 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1591 depth->has_surface = screen->depthHasSurface; 1592 } 1593 1594 _mesa_add_soft_renderbuffers(&rfb->base, 1595 GL_FALSE, /* color */ 1596 swDepth, 1597 swStencil, 1598 swAccum, 1599 swAlpha, 1600 GL_FALSE /* aux */); 1601 driDrawPriv->driverPrivate = (void *) rfb; 1602 1603 return (driDrawPriv->driverPrivate != NULL); 1604} 1605 1606 1607static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1608{ 1609 struct radeon_renderbuffer *rb; 1610 1611 rb = rfb->color_rb[0]; 1612 if (rb && rb->bo) { 1613 radeon_bo_unref(rb->bo); 1614 rb->bo = NULL; 1615 } 1616 rb = rfb->color_rb[1]; 1617 if (rb && rb->bo) { 1618 radeon_bo_unref(rb->bo); 1619 rb->bo = NULL; 1620 } 1621 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1622 if (rb && rb->bo) { 1623 radeon_bo_unref(rb->bo); 1624 rb->bo = NULL; 1625 } 1626} 1627 1628void 1629radeonDestroyBuffer(__DRIdrawable *driDrawPriv) 1630{ 1631 struct radeon_framebuffer *rfb; 1632 if (!driDrawPriv) 1633 return; 1634 1635 rfb = (void*)driDrawPriv->driverPrivate; 1636 if (!rfb) 1637 return; 1638 radeon_cleanup_renderbuffers(rfb); 1639 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1640} 1641 1642 1643/** 1644 * This is the driver specific part of the createNewScreen entry point. 1645 * 1646 * \todo maybe fold this into intelInitDriver 1647 * 1648 * \return the __GLcontextModes supported by this driver 1649 */ 1650static const __DRIconfig ** 1651radeonInitScreen(__DRIscreen *psp) 1652{ 1653#if defined(RADEON_R100) 1654 static const char *driver_name = "Radeon"; 1655 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1656 static const __DRIversion dri_expected = { 4, 0, 0 }; 1657 static const __DRIversion drm_expected = { 1, 6, 0 }; 1658#elif defined(RADEON_R200) 1659 static const char *driver_name = "R200"; 1660 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1661 static const __DRIversion dri_expected = { 4, 0, 0 }; 1662 static const __DRIversion drm_expected = { 1, 6, 0 }; 1663#elif defined(RADEON_R300) 1664 static const char *driver_name = "R300"; 1665 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1666 static const __DRIversion dri_expected = { 4, 0, 0 }; 1667 static const __DRIversion drm_expected = { 1, 24, 0 }; 1668#elif defined(RADEON_R600) 1669 static const char *driver_name = "R600"; 1670 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1671 static const __DRIversion dri_expected = { 4, 0, 0 }; 1672 static const __DRIversion drm_expected = { 1, 24, 0 }; 1673#endif 1674 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1675 1676 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1677 &psp->dri_version, & dri_expected, 1678 &psp->ddx_version, & ddx_expected, 1679 &psp->drm_version, & drm_expected ) ) { 1680 return NULL; 1681 } 1682 1683 if (!radeonInitDriver(psp)) 1684 return NULL; 1685 1686 /* for now fill in all modes */ 1687 return radeonFillInModes( psp, 1688 dri_priv->bpp, 1689 (dri_priv->bpp == 16) ? 16 : 24, 1690 (dri_priv->bpp == 16) ? 0 : 8, 1); 1691} 1692#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1693 1694/** 1695 * This is the driver specific part of the createNewScreen entry point. 1696 * Called when using DRI2. 1697 * 1698 * \return the __GLcontextModes supported by this driver 1699 */ 1700static const 1701__DRIconfig **radeonInitScreen2(__DRIscreen *psp) 1702{ 1703 GLenum fb_format[3]; 1704 GLenum fb_type[3]; 1705 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1706 * support pageflipping at all. 1707 */ 1708 static const GLenum back_buffer_modes[] = { 1709 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1710 }; 1711 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1712 int color; 1713 __DRIconfig **configs = NULL; 1714 1715 if (!radeonInitDriver(psp)) { 1716 return NULL; 1717 } 1718 depth_bits[0] = 0; 1719 stencil_bits[0] = 0; 1720 depth_bits[1] = 16; 1721 stencil_bits[1] = 0; 1722 depth_bits[2] = 24; 1723 stencil_bits[2] = 0; 1724 depth_bits[3] = 24; 1725 stencil_bits[3] = 8; 1726 1727 msaa_samples_array[0] = 0; 1728 1729 fb_format[0] = GL_RGB; 1730 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1731 1732 fb_format[1] = GL_BGR; 1733 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1734 1735 fb_format[2] = GL_BGRA; 1736 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1737 1738 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1739 __DRIconfig **new_configs; 1740 1741 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1742 depth_bits, 1743 stencil_bits, 1744 ARRAY_SIZE(depth_bits), 1745 back_buffer_modes, 1746 ARRAY_SIZE(back_buffer_modes), 1747 msaa_samples_array, 1748 ARRAY_SIZE(msaa_samples_array), 1749 GL_TRUE); 1750 if (configs == NULL) 1751 configs = new_configs; 1752 else 1753 configs = driConcatConfigs(configs, new_configs); 1754 } 1755 1756 if (configs == NULL) { 1757 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1758 __LINE__); 1759 return NULL; 1760 } 1761 1762 return (const __DRIconfig **)configs; 1763} 1764 1765/** 1766 * Get information about previous buffer swaps. 1767 */ 1768static int 1769getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ) 1770{ 1771 struct radeon_framebuffer *rfb; 1772 1773 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1774 || (dPriv->driContextPriv->driverPrivate == NULL) 1775 || (sInfo == NULL) ) { 1776 return -1; 1777 } 1778 1779 rfb = dPriv->driverPrivate; 1780 sInfo->swap_count = rfb->swap_count; 1781 sInfo->swap_ust = rfb->swap_ust; 1782 sInfo->swap_missed_count = rfb->swap_missed_count; 1783 1784 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1785 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1786 : 0.0; 1787 1788 return 0; 1789} 1790 1791const struct __DriverAPIRec driDriverAPI = { 1792 .InitScreen = radeonInitScreen, 1793 .DestroyScreen = radeonDestroyScreen, 1794#if defined(RADEON_R200) 1795 .CreateContext = r200CreateContext, 1796 .DestroyContext = r200DestroyContext, 1797#elif defined(RADEON_R600) 1798 .CreateContext = r600CreateContext, 1799 .DestroyContext = radeonDestroyContext, 1800#elif defined(RADEON_R300) 1801 .CreateContext = r300CreateContext, 1802 .DestroyContext = radeonDestroyContext, 1803#else 1804 .CreateContext = r100CreateContext, 1805 .DestroyContext = radeonDestroyContext, 1806#endif 1807 .CreateBuffer = radeonCreateBuffer, 1808 .DestroyBuffer = radeonDestroyBuffer, 1809 .SwapBuffers = radeonSwapBuffers, 1810 .MakeCurrent = radeonMakeCurrent, 1811 .UnbindContext = radeonUnbindContext, 1812 .GetSwapInfo = getSwapInfo, 1813 .GetDrawableMSC = driDrawableGetMSC32, 1814 .WaitForMSC = driWaitForMSC32, 1815 .WaitForSBC = NULL, 1816 .SwapBuffersMSC = NULL, 1817 .CopySubBuffer = radeonCopySubBuffer, 1818 /* DRI2 */ 1819 .InitScreen2 = radeonInitScreen2, 1820}; 1821 1822/* This is the table of extensions that the loader will dlsym() for. */ 1823PUBLIC const __DRIextension *__driDriverExtensions[] = { 1824 &driCoreExtension.base, 1825 &driLegacyExtension.base, 1826 &driDRI2Extension.base, 1827 NULL 1828}; 1829