radeon_screen.c revision 9cb82f7917b11288169146035700b992b86a7ec2 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author  Gareth Hughes <gareth@valinux.com>
37 */
38
39#include "glheader.h"
40#include "imports.h"
41#include "mtypes.h"
42#include "framebuffer.h"
43#include "renderbuffer.h"
44
45#define STANDALONE_MMIO
46#include "radeon_chipset.h"
47#include "radeon_macros.h"
48#include "radeon_screen.h"
49#if !RADEON_COMMON
50#include "radeon_context.h"
51#include "radeon_span.h"
52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53#include "r200_context.h"
54#include "r200_ioctl.h"
55#include "r200_span.h"
56#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
57#include "r300_context.h"
58#include "radeon_span.h"
59#endif
60
61#include "utils.h"
62#include "context.h"
63#include "vblank.h"
64#include "drirenderbuffer.h"
65
66#include "GL/internal/dri_interface.h"
67
68/* Radeon configuration
69 */
70#include "xmlpool.h"
71
72#if !RADEON_COMMON	/* R100 */
73PUBLIC const char __driConfigOptions[] =
74DRI_CONF_BEGIN
75    DRI_CONF_SECTION_PERFORMANCE
76        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
77        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
78        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
79        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
80        DRI_CONF_HYPERZ(false)
81    DRI_CONF_SECTION_END
82    DRI_CONF_SECTION_QUALITY
83        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
84        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
85        DRI_CONF_NO_NEG_LOD_BIAS(false)
86        DRI_CONF_FORCE_S3TC_ENABLE(false)
87        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
88        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
89        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
90        DRI_CONF_ALLOW_LARGE_TEXTURES(1)
91    DRI_CONF_SECTION_END
92    DRI_CONF_SECTION_DEBUG
93        DRI_CONF_NO_RAST(false)
94    DRI_CONF_SECTION_END
95DRI_CONF_END;
96static const GLuint __driNConfigOptions = 14;
97
98#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
99
100PUBLIC const char __driConfigOptions[] =
101DRI_CONF_BEGIN
102    DRI_CONF_SECTION_PERFORMANCE
103        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
104        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
105        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
106        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
107        DRI_CONF_HYPERZ(false)
108    DRI_CONF_SECTION_END
109    DRI_CONF_SECTION_QUALITY
110        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
111        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
112        DRI_CONF_NO_NEG_LOD_BIAS(false)
113        DRI_CONF_FORCE_S3TC_ENABLE(false)
114        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
115        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
116        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
117        DRI_CONF_ALLOW_LARGE_TEXTURES(1)
118        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
119    DRI_CONF_SECTION_END
120    DRI_CONF_SECTION_DEBUG
121        DRI_CONF_NO_RAST(false)
122    DRI_CONF_SECTION_END
123    DRI_CONF_SECTION_SOFTWARE
124        DRI_CONF_NV_VERTEX_PROGRAM(false)
125    DRI_CONF_SECTION_END
126DRI_CONF_END;
127static const GLuint __driNConfigOptions = 16;
128
129extern const struct dri_extension blend_extensions[];
130extern const struct dri_extension ARB_vp_extension[];
131extern const struct dri_extension NV_vp_extension[];
132extern const struct dri_extension ATI_fs_extension[];
133
134#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
135
136/* TODO: integrate these into xmlpool.h! */
137#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
138DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
139        DRI_CONF_DESC(en,"Number of texture image units") \
140        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
141DRI_CONF_OPT_END
142
143#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
144DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
145        DRI_CONF_DESC(en,"Number of texture coordinate units") \
146        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
147DRI_CONF_OPT_END
148
149#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
150DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
151        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
152        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
153DRI_CONF_OPT_END
154
155const char __driConfigOptions[] =
156DRI_CONF_BEGIN
157	DRI_CONF_SECTION_PERFORMANCE
158		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
159		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
160		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
161		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
162		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
163		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
164	DRI_CONF_SECTION_END
165	DRI_CONF_SECTION_QUALITY
166		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
167		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
168		DRI_CONF_NO_NEG_LOD_BIAS(false)
169                DRI_CONF_FORCE_S3TC_ENABLE(false)
170		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
171		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
172		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
173	DRI_CONF_SECTION_END
174	DRI_CONF_SECTION_DEBUG
175		DRI_CONF_NO_RAST(false)
176	DRI_CONF_SECTION_END
177DRI_CONF_END;
178static const GLuint __driNConfigOptions = 14;
179
180#ifndef RADEON_DEBUG
181int RADEON_DEBUG = 0;
182
183static const struct dri_debug_control debug_control[] = {
184	{"fall", DEBUG_FALLBACKS},
185	{"tex", DEBUG_TEXTURE},
186	{"ioctl", DEBUG_IOCTL},
187	{"prim", DEBUG_PRIMS},
188	{"vert", DEBUG_VERTS},
189	{"state", DEBUG_STATE},
190	{"code", DEBUG_CODEGEN},
191	{"vfmt", DEBUG_VFMT},
192	{"vtxf", DEBUG_VFMT},
193	{"verb", DEBUG_VERBOSE},
194	{"dri", DEBUG_DRI},
195	{"dma", DEBUG_DMA},
196	{"san", DEBUG_SANITY},
197	{"sync", DEBUG_SYNC},
198	{"pix", DEBUG_PIXEL},
199	{"mem", DEBUG_MEMORY},
200	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
201	{NULL, 0}
202};
203#endif /* RADEON_DEBUG */
204
205#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
206
207extern const struct dri_extension card_extensions[];
208
209static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
210
211static int
212radeonGetParam(int fd, int param, void *value)
213{
214  int ret;
215  drm_radeon_getparam_t gp;
216
217  gp.param = param;
218  gp.value = value;
219
220  ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
221  return ret;
222}
223
224static __GLcontextModes *
225radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
226		 unsigned stencil_bits, GLboolean have_back_buffer )
227{
228    __GLcontextModes * modes;
229    __GLcontextModes * m;
230    unsigned num_modes;
231    unsigned depth_buffer_factor;
232    unsigned back_buffer_factor;
233    GLenum fb_format;
234    GLenum fb_type;
235
236    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
237     * enough to add support.  Basically, if a context is created with an
238     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
239     * will never be used.
240     */
241    static const GLenum back_buffer_modes[] = {
242	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
243    };
244
245    u_int8_t depth_bits_array[2];
246    u_int8_t stencil_bits_array[2];
247
248
249    depth_bits_array[0] = depth_bits;
250    depth_bits_array[1] = depth_bits;
251
252    /* Just like with the accumulation buffer, always provide some modes
253     * with a stencil buffer.  It will be a sw fallback, but some apps won't
254     * care about that.
255     */
256    stencil_bits_array[0] = 0;
257    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
258
259    depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
260    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
261
262    num_modes = depth_buffer_factor * back_buffer_factor * 4;
263
264    if ( pixel_bits == 16 ) {
265        fb_format = GL_RGB;
266        fb_type = GL_UNSIGNED_SHORT_5_6_5;
267    }
268    else {
269        fb_format = GL_BGRA;
270        fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
271    }
272
273    modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
274    m = modes;
275    if ( ! driFillInModes( & m, fb_format, fb_type,
276			   depth_bits_array, stencil_bits_array, depth_buffer_factor,
277			   back_buffer_modes, back_buffer_factor,
278			   GLX_TRUE_COLOR ) ) {
279	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
280		 __func__, __LINE__ );
281	return NULL;
282    }
283
284    if ( ! driFillInModes( & m, fb_format, fb_type,
285			   depth_bits_array, stencil_bits_array, depth_buffer_factor,
286			   back_buffer_modes, back_buffer_factor,
287			   GLX_DIRECT_COLOR ) ) {
288	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
289		 __func__, __LINE__ );
290	return NULL;
291    }
292
293    /* Mark the visual as slow if there are "fake" stencil bits.
294     */
295    for ( m = modes ; m != NULL ; m = m->next ) {
296	if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
297	    m->visualRating = GLX_SLOW_CONFIG;
298	}
299    }
300
301    return modes;
302}
303
304
305/* Create the device specific screen private data struct.
306 */
307static radeonScreenPtr
308radeonCreateScreen( __DRIscreenPrivate *sPriv )
309{
310   radeonScreenPtr screen;
311   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
312   unsigned char *RADEONMMIO;
313   PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
314     (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
315   void * const psc = sPriv->psc->screenConfigs;
316
317   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
318      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
319      return GL_FALSE;
320   }
321
322   /* Allocate the private area */
323   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
324   if ( !screen ) {
325      __driUtilMessage("%s: Could not allocate memory for screen structure",
326		       __FUNCTION__);
327      return NULL;
328   }
329
330#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
331	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
332#endif
333
334   /* parse information in __driConfigOptions */
335   driParseOptionInfo (&screen->optionCache,
336		       __driConfigOptions, __driNConfigOptions);
337
338   /* This is first since which regions we map depends on whether or
339    * not we are using a PCI card.
340    */
341   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
342   {
343      int ret;
344      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
345			    &screen->gart_buffer_offset);
346
347      if (ret) {
348	 FREE( screen );
349	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
350	 return NULL;
351      }
352
353      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
354			    &screen->gart_base);
355      if (ret) {
356	 FREE( screen );
357	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
358	 return NULL;
359      }
360
361      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
362			    &screen->irq);
363      if (ret) {
364	 FREE( screen );
365	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
366	 return NULL;
367      }
368      screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7);
369      screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
370      screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
371      screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
372      screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
373      screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15);
374      screen->drmSupportsVertexProgram = (sPriv->drmMinor >= 25);
375   }
376
377   screen->mmio.handle = dri_priv->registerHandle;
378   screen->mmio.size   = dri_priv->registerSize;
379   if ( drmMap( sPriv->fd,
380		screen->mmio.handle,
381		screen->mmio.size,
382		&screen->mmio.map ) ) {
383      FREE( screen );
384      __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
385      return NULL;
386   }
387
388   RADEONMMIO = screen->mmio.map;
389
390   screen->status.handle = dri_priv->statusHandle;
391   screen->status.size   = dri_priv->statusSize;
392   if ( drmMap( sPriv->fd,
393		screen->status.handle,
394		screen->status.size,
395		&screen->status.map ) ) {
396      drmUnmap( screen->mmio.map, screen->mmio.size );
397      FREE( screen );
398      __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
399      return NULL;
400   }
401   screen->scratch = (__volatile__ u_int32_t *)
402      ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
403
404   screen->buffers = drmMapBufs( sPriv->fd );
405   if ( !screen->buffers ) {
406      drmUnmap( screen->status.map, screen->status.size );
407      drmUnmap( screen->mmio.map, screen->mmio.size );
408      FREE( screen );
409      __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
410      return NULL;
411   }
412
413   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
414      screen->gartTextures.handle = dri_priv->gartTexHandle;
415      screen->gartTextures.size   = dri_priv->gartTexMapSize;
416      if ( drmMap( sPriv->fd,
417		   screen->gartTextures.handle,
418		   screen->gartTextures.size,
419		   (drmAddressPtr)&screen->gartTextures.map ) ) {
420	 drmUnmapBufs( screen->buffers );
421	 drmUnmap( screen->status.map, screen->status.size );
422	 drmUnmap( screen->mmio.map, screen->mmio.size );
423	 FREE( screen );
424	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
425	 return NULL;
426      }
427
428      screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
429   }
430
431   screen->chip_flags = 0;
432   /* XXX: add more chipsets */
433   switch ( dri_priv->deviceID ) {
434   case PCI_CHIP_RADEON_LY:
435   case PCI_CHIP_RADEON_LZ:
436   case PCI_CHIP_RADEON_QY:
437   case PCI_CHIP_RADEON_QZ:
438   case PCI_CHIP_RN50_515E:
439   case PCI_CHIP_RN50_5969:
440      screen->chip_family = CHIP_FAMILY_RV100;
441      break;
442
443   case PCI_CHIP_RS100_4136:
444   case PCI_CHIP_RS100_4336:
445      screen->chip_family = CHIP_FAMILY_RS100;
446      break;
447
448   case PCI_CHIP_RS200_4137:
449   case PCI_CHIP_RS200_4337:
450   case PCI_CHIP_RS250_4237:
451   case PCI_CHIP_RS250_4437:
452      screen->chip_family = CHIP_FAMILY_RS200;
453      break;
454
455   case PCI_CHIP_RADEON_QD:
456   case PCI_CHIP_RADEON_QE:
457   case PCI_CHIP_RADEON_QF:
458   case PCI_CHIP_RADEON_QG:
459      /* all original radeons (7200) presumably have a stencil op bug */
460      screen->chip_family = CHIP_FAMILY_R100;
461      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
462      break;
463
464   case PCI_CHIP_RV200_QW:
465   case PCI_CHIP_RV200_QX:
466   case PCI_CHIP_RADEON_LW:
467   case PCI_CHIP_RADEON_LX:
468      screen->chip_family = CHIP_FAMILY_RV200;
469      screen->chip_flags = RADEON_CHIPSET_TCL;
470      break;
471
472   case PCI_CHIP_R200_BB:
473   case PCI_CHIP_R200_BC:
474   case PCI_CHIP_R200_QH:
475   case PCI_CHIP_R200_QL:
476   case PCI_CHIP_R200_QM:
477      screen->chip_family = CHIP_FAMILY_R200;
478      screen->chip_flags = RADEON_CHIPSET_TCL;
479      break;
480
481   case PCI_CHIP_RV250_If:
482   case PCI_CHIP_RV250_Ig:
483   case PCI_CHIP_RV250_Ld:
484   case PCI_CHIP_RV250_Lf:
485   case PCI_CHIP_RV250_Lg:
486      screen->chip_family = CHIP_FAMILY_RV250;
487      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
488      break;
489
490   case PCI_CHIP_RV280_5960:
491   case PCI_CHIP_RV280_5961:
492   case PCI_CHIP_RV280_5962:
493   case PCI_CHIP_RV280_5964:
494   case PCI_CHIP_RV280_5965:
495   case PCI_CHIP_RV280_5C61:
496   case PCI_CHIP_RV280_5C63:
497      screen->chip_family = CHIP_FAMILY_RV280;
498      screen->chip_flags = RADEON_CHIPSET_TCL;
499      break;
500
501   case PCI_CHIP_RS300_5834:
502   case PCI_CHIP_RS300_5835:
503   case PCI_CHIP_RS350_7834:
504   case PCI_CHIP_RS350_7835:
505      screen->chip_family = CHIP_FAMILY_RS300;
506      break;
507
508   case PCI_CHIP_R300_AD:
509   case PCI_CHIP_R300_AE:
510   case PCI_CHIP_R300_AF:
511   case PCI_CHIP_R300_AG:
512   case PCI_CHIP_R300_ND:
513   case PCI_CHIP_R300_NE:
514   case PCI_CHIP_R300_NF:
515   case PCI_CHIP_R300_NG:
516      screen->chip_family = CHIP_FAMILY_R300;
517      screen->chip_flags = RADEON_CHIPSET_TCL;
518      break;
519
520   case PCI_CHIP_RV350_AP:
521   case PCI_CHIP_RV350_AQ:
522   case PCI_CHIP_RV350_AR:
523   case PCI_CHIP_RV350_AS:
524   case PCI_CHIP_RV350_AT:
525   case PCI_CHIP_RV350_AV:
526   case PCI_CHIP_RV350_AU:
527   case PCI_CHIP_RV350_NP:
528   case PCI_CHIP_RV350_NQ:
529   case PCI_CHIP_RV350_NR:
530   case PCI_CHIP_RV350_NS:
531   case PCI_CHIP_RV350_NT:
532   case PCI_CHIP_RV350_NV:
533      screen->chip_family = CHIP_FAMILY_RV350;
534      screen->chip_flags = RADEON_CHIPSET_TCL;
535      break;
536
537   case PCI_CHIP_R350_AH:
538   case PCI_CHIP_R350_AI:
539   case PCI_CHIP_R350_AJ:
540   case PCI_CHIP_R350_AK:
541   case PCI_CHIP_R350_NH:
542   case PCI_CHIP_R350_NI:
543   case PCI_CHIP_R360_NJ:
544   case PCI_CHIP_R350_NK:
545      screen->chip_family = CHIP_FAMILY_R350;
546      screen->chip_flags = RADEON_CHIPSET_TCL;
547      break;
548
549   case PCI_CHIP_RV370_5460:
550   case PCI_CHIP_RV370_5462:
551   case PCI_CHIP_RV370_5464:
552   case PCI_CHIP_RV370_5B60:
553   case PCI_CHIP_RV370_5B62:
554   case PCI_CHIP_RV370_5B63:
555   case PCI_CHIP_RV370_5B64:
556   case PCI_CHIP_RV370_5B65:
557   case PCI_CHIP_RV380_3150:
558   case PCI_CHIP_RV380_3152:
559   case PCI_CHIP_RV380_3154:
560   case PCI_CHIP_RV380_3E50:
561   case PCI_CHIP_RV380_3E54:
562      screen->chip_family = CHIP_FAMILY_RV380;
563      screen->chip_flags = RADEON_CHIPSET_TCL;
564      break;
565
566   case PCI_CHIP_R420_JN:
567   case PCI_CHIP_R420_JH:
568   case PCI_CHIP_R420_JI:
569   case PCI_CHIP_R420_JJ:
570   case PCI_CHIP_R420_JK:
571   case PCI_CHIP_R420_JL:
572   case PCI_CHIP_R420_JM:
573   case PCI_CHIP_R420_JO:
574   case PCI_CHIP_R420_JP:
575   case PCI_CHIP_R420_JT:
576   case PCI_CHIP_R481_4B49:
577   case PCI_CHIP_R481_4B4A:
578   case PCI_CHIP_R481_4B4B:
579   case PCI_CHIP_R481_4B4C:
580   case PCI_CHIP_R423_UH:
581   case PCI_CHIP_R423_UI:
582   case PCI_CHIP_R423_UJ:
583   case PCI_CHIP_R423_UK:
584   case PCI_CHIP_R430_554C:
585   case PCI_CHIP_R430_554D:
586   case PCI_CHIP_R430_554E:
587   case PCI_CHIP_R430_554F:
588   case PCI_CHIP_R423_5550:
589   case PCI_CHIP_R423_UQ:
590   case PCI_CHIP_R423_UR:
591   case PCI_CHIP_R423_UT:
592   case PCI_CHIP_R430_5D48:
593   case PCI_CHIP_R430_5D49:
594   case PCI_CHIP_R430_5D4A:
595   case PCI_CHIP_R480_5D4C:
596   case PCI_CHIP_R480_5D4D:
597   case PCI_CHIP_R480_5D4E:
598   case PCI_CHIP_R480_5D4F:
599   case PCI_CHIP_R480_5D50:
600   case PCI_CHIP_R480_5D52:
601   case PCI_CHIP_R423_5D57:
602      screen->chip_family = CHIP_FAMILY_R420;
603      screen->chip_flags = RADEON_CHIPSET_TCL;
604      break;
605
606   case PCI_CHIP_RV410_564A:
607   case PCI_CHIP_RV410_564B:
608   case PCI_CHIP_RV410_564F:
609   case PCI_CHIP_RV410_5652:
610   case PCI_CHIP_RV410_5653:
611   case PCI_CHIP_RV410_5E48:
612   case PCI_CHIP_RV410_5E4A:
613   case PCI_CHIP_RV410_5E4B:
614   case PCI_CHIP_RV410_5E4C:
615   case PCI_CHIP_RV410_5E4D:
616   case PCI_CHIP_RV410_5E4F:
617      screen->chip_family = CHIP_FAMILY_RV410;
618      screen->chip_flags = RADEON_CHIPSET_TCL;
619      break;
620
621   case PCI_CHIP_RS480_5954:
622   case PCI_CHIP_RS480_5955:
623   case PCI_CHIP_RS482_5974:
624   case PCI_CHIP_RS482_5975:
625   case PCI_CHIP_RS400_5A41:
626   case PCI_CHIP_RS400_5A42:
627   case PCI_CHIP_RC410_5A61:
628   case PCI_CHIP_RC410_5A62:
629      screen->chip_family = CHIP_FAMILY_RS400;
630      fprintf(stderr, "Warning, xpress200 detected. Probably won't work.\n");
631      break;
632
633   default:
634      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
635	      dri_priv->deviceID);
636      return NULL;
637   }
638   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
639       sPriv->ddxMinor < 2) {
640      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
641      return NULL;
642   }
643
644   if (screen->chip_family <= CHIP_FAMILY_RS200)
645      screen->chip_flags |= RADEON_CLASS_R100;
646   else if (screen->chip_family <= CHIP_FAMILY_RV280)
647      screen->chip_flags |= RADEON_CLASS_R200;
648   else
649      screen->chip_flags |= RADEON_CLASS_R300;
650
651   screen->cpp = dri_priv->bpp / 8;
652   screen->AGPMode = dri_priv->AGPMode;
653
654   screen->fbLocation	= ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
655
656   if ( sPriv->drmMinor >= 10 ) {
657      drm_radeon_setparam_t sp;
658
659      sp.param = RADEON_SETPARAM_FB_LOCATION;
660      sp.value = screen->fbLocation;
661
662      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
663		       &sp, sizeof( sp ) );
664   }
665
666   screen->frontOffset	= dri_priv->frontOffset;
667   screen->frontPitch	= dri_priv->frontPitch;
668   screen->backOffset	= dri_priv->backOffset;
669   screen->backPitch	= dri_priv->backPitch;
670   screen->depthOffset	= dri_priv->depthOffset;
671   screen->depthPitch	= dri_priv->depthPitch;
672
673   /* Check if ddx has set up a surface reg to cover depth buffer */
674   screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
675      (screen->chip_flags & RADEON_CHIPSET_TCL));
676
677   if ( dri_priv->textureSize == 0 ) {
678      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
679      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
680      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
681	 dri_priv->log2GARTTexGran;
682   } else {
683      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
684				               + screen->fbLocation;
685      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
686      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
687	 dri_priv->log2TexGran;
688   }
689
690   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
691	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
692      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
693      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
694      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
695      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
696   } else {
697      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
698      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
699      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
700      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
701	 dri_priv->log2GARTTexGran;
702   }
703
704   if ( glx_enable_extension != NULL ) {
705      if ( screen->irq != 0 ) {
706	 (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
707	 (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
708	 (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
709      }
710
711      (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
712      if (IS_R200_CLASS(screen))
713	 (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
714
715      (*glx_enable_extension)( psc, "GLX_MESA_copy_sub_buffer" );
716   }
717
718#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
719   if (IS_R200_CLASS(screen)) {
720      sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
721      sPriv->psc->freeMemory     = (void *) r200FreeMemoryMESA;
722      sPriv->psc->memoryOffset   = (void *) r200GetMemoryOffsetMESA;
723   }
724#endif
725
726   screen->driScreen = sPriv;
727   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
728   return screen;
729}
730
731/* Destroy the device specific screen private data struct.
732 */
733static void
734radeonDestroyScreen( __DRIscreenPrivate *sPriv )
735{
736   radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
737
738   if (!screen)
739      return;
740
741   if ( screen->gartTextures.map ) {
742      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
743   }
744   drmUnmapBufs( screen->buffers );
745   drmUnmap( screen->status.map, screen->status.size );
746   drmUnmap( screen->mmio.map, screen->mmio.size );
747
748   /* free all option information */
749   driDestroyOptionInfo (&screen->optionCache);
750
751   FREE( screen );
752   sPriv->private = NULL;
753}
754
755
756/* Initialize the driver specific screen private data.
757 */
758static GLboolean
759radeonInitDriver( __DRIscreenPrivate *sPriv )
760{
761   sPriv->private = (void *) radeonCreateScreen( sPriv );
762   if ( !sPriv->private ) {
763      radeonDestroyScreen( sPriv );
764      return GL_FALSE;
765   }
766
767   return GL_TRUE;
768}
769
770
771/**
772 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
773 *
774 * \todo This function (and its interface) will need to be updated to support
775 * pbuffers.
776 */
777static GLboolean
778radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
779                    __DRIdrawablePrivate *driDrawPriv,
780                    const __GLcontextModes *mesaVis,
781                    GLboolean isPixmap )
782{
783   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
784
785   if (isPixmap) {
786      return GL_FALSE; /* not implemented */
787   }
788   else {
789      const GLboolean swDepth = GL_FALSE;
790      const GLboolean swAlpha = GL_FALSE;
791      const GLboolean swAccum = mesaVis->accumRedBits > 0;
792      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
793         mesaVis->depthBits != 24;
794      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
795
796      /* front color renderbuffer */
797      {
798         driRenderbuffer *frontRb
799            = driNewRenderbuffer(GL_RGBA,
800                                 driScrnPriv->pFB + screen->frontOffset,
801                                 screen->cpp,
802                                 screen->frontOffset, screen->frontPitch,
803                                 driDrawPriv);
804         radeonSetSpanFunctions(frontRb, mesaVis);
805         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
806      }
807
808      /* back color renderbuffer */
809      if (mesaVis->doubleBufferMode) {
810         driRenderbuffer *backRb
811            = driNewRenderbuffer(GL_RGBA,
812                                 driScrnPriv->pFB + screen->backOffset,
813                                 screen->cpp,
814                                 screen->backOffset, screen->backPitch,
815                                 driDrawPriv);
816         radeonSetSpanFunctions(backRb, mesaVis);
817         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
818      }
819
820      /* depth renderbuffer */
821      if (mesaVis->depthBits == 16) {
822         driRenderbuffer *depthRb
823            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
824                                 driScrnPriv->pFB + screen->depthOffset,
825                                 screen->cpp,
826                                 screen->depthOffset, screen->depthPitch,
827                                 driDrawPriv);
828         radeonSetSpanFunctions(depthRb, mesaVis);
829         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
830	 depthRb->depthHasSurface = screen->depthHasSurface;
831      }
832      else if (mesaVis->depthBits == 24) {
833         driRenderbuffer *depthRb
834            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
835                                 driScrnPriv->pFB + screen->depthOffset,
836                                 screen->cpp,
837                                 screen->depthOffset, screen->depthPitch,
838                                 driDrawPriv);
839         radeonSetSpanFunctions(depthRb, mesaVis);
840         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
841	 depthRb->depthHasSurface = screen->depthHasSurface;
842      }
843
844      /* stencil renderbuffer */
845      if (mesaVis->stencilBits > 0 && !swStencil) {
846         driRenderbuffer *stencilRb
847            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
848                                 driScrnPriv->pFB + screen->depthOffset,
849                                 screen->cpp,
850                                 screen->depthOffset, screen->depthPitch,
851                                 driDrawPriv);
852         radeonSetSpanFunctions(stencilRb, mesaVis);
853         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
854	 stencilRb->depthHasSurface = screen->depthHasSurface;
855      }
856
857      _mesa_add_soft_renderbuffers(fb,
858                                   GL_FALSE, /* color */
859                                   swDepth,
860                                   swStencil,
861                                   swAccum,
862                                   swAlpha,
863                                   GL_FALSE /* aux */);
864      driDrawPriv->driverPrivate = (void *) fb;
865
866      return (driDrawPriv->driverPrivate != NULL);
867   }
868}
869
870
871static void
872radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
873{
874   _mesa_destroy_framebuffer((GLframebuffer *) (driDrawPriv->driverPrivate));
875}
876
877#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
878/**
879 * Choose the appropriate CreateContext function based on the chipset.
880 * Eventually, all drivers will go through this process.
881 */
882static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
883				     __DRIcontextPrivate * driContextPriv,
884				     void *sharedContextPriv)
885{
886	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
887	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
888
889	if (IS_R300_CLASS(screen))
890		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
891        return GL_FALSE;
892}
893
894/**
895 * Choose the appropriate DestroyContext function based on the chipset.
896 */
897static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
898{
899	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
900
901	if (IS_R300_CLASS(radeon->radeonScreen))
902		return r300DestroyContext(driContextPriv);
903}
904
905
906#endif
907
908#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
909static struct __DriverAPIRec radeonAPI = {
910   .InitDriver      = radeonInitDriver,
911   .DestroyScreen   = radeonDestroyScreen,
912   .CreateContext   = radeonCreateContext,
913   .DestroyContext  = radeonDestroyContext,
914   .CreateBuffer    = radeonCreateBuffer,
915   .DestroyBuffer   = radeonDestroyBuffer,
916   .SwapBuffers     = radeonSwapBuffers,
917   .MakeCurrent     = radeonMakeCurrent,
918   .UnbindContext   = radeonUnbindContext,
919   .GetSwapInfo     = getSwapInfo,
920   .GetMSC          = driGetMSC32,
921   .WaitForMSC      = driWaitForMSC32,
922   .WaitForSBC      = NULL,
923   .SwapBuffersMSC  = NULL,
924   .CopySubBuffer   = radeonCopySubBuffer,
925};
926#else
927static const struct __DriverAPIRec r200API = {
928   .InitDriver      = radeonInitDriver,
929   .DestroyScreen   = radeonDestroyScreen,
930   .CreateContext   = r200CreateContext,
931   .DestroyContext  = r200DestroyContext,
932   .CreateBuffer    = radeonCreateBuffer,
933   .DestroyBuffer   = radeonDestroyBuffer,
934   .SwapBuffers     = r200SwapBuffers,
935   .MakeCurrent     = r200MakeCurrent,
936   .UnbindContext   = r200UnbindContext,
937   .GetSwapInfo     = getSwapInfo,
938   .GetMSC          = driGetMSC32,
939   .WaitForMSC      = driWaitForMSC32,
940   .WaitForSBC      = NULL,
941   .SwapBuffersMSC  = NULL,
942   .CopySubBuffer   = r200CopySubBuffer
943};
944#endif
945
946/**
947 * This is the bootstrap function for the driver.  libGL supplies all of the
948 * requisite information about the system, and the driver initializes itself.
949 * This routine also fills in the linked list pointed to by \c driver_modes
950 * with the \c __GLcontextModes that the driver can support for windows or
951 * pbuffers.
952 *
953 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
954 *         failure.
955 */
956PUBLIC void *
957__driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
958                             int scrn, __DRIscreen *psc,
959			     const __GLcontextModes * modes,
960			     const __DRIversion * ddx_version,
961			     const __DRIversion * dri_version,
962			     const __DRIversion * drm_version,
963			     const __DRIframebuffer * frame_buffer,
964			     drmAddress pSAREA, int fd,
965			     int internal_api_version,
966			     const __DRIinterfaceMethods * interface,
967			     __GLcontextModes ** driver_modes )
968{
969   __DRIscreenPrivate *psp;
970#if !RADEON_COMMON
971   static const char *driver_name = "Radeon";
972   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
973   static const __DRIversion dri_expected = { 4, 0, 0 };
974   static const __DRIversion drm_expected = { 1, 6, 0 };
975#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
976   static const char *driver_name = "R200";
977   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
978   static const __DRIversion dri_expected = { 4, 0, 0 };
979   static const __DRIversion drm_expected = { 1, 6, 0 };
980#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
981   static const char *driver_name = "R300";
982   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
983   static const __DRIversion dri_expected = { 4, 0, 0 };
984   static const __DRIversion drm_expected = { 1, 24, 0 };
985#endif
986
987   dri_interface = interface;
988
989   if ( ! driCheckDriDdxDrmVersions3( driver_name,
990				      dri_version, & dri_expected,
991				      ddx_version, & ddx_expected,
992				      drm_version, & drm_expected ) ) {
993      return NULL;
994   }
995#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
996   psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
997				  ddx_version, dri_version, drm_version,
998				  frame_buffer, pSAREA, fd,
999				  internal_api_version, &radeonAPI);
1000#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1001   psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
1002				  ddx_version, dri_version, drm_version,
1003				  frame_buffer, pSAREA, fd,
1004				  internal_api_version, &r200API);
1005#endif
1006
1007   if ( psp != NULL ) {
1008      RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1009      if (driver_modes) {
1010         *driver_modes = radeonFillInModes( dri_priv->bpp,
1011                                            (dri_priv->bpp == 16) ? 16 : 24,
1012                                            (dri_priv->bpp == 16) ? 0  : 8,
1013                                            (dri_priv->backOffset != dri_priv->depthOffset) );
1014      }
1015
1016      /* Calling driInitExtensions here, with a NULL context pointer,
1017       * does not actually enable the extensions.  It just makes sure
1018       * that all the dispatch offsets for all the extensions that
1019       * *might* be enables are known.  This is needed because the
1020       * dispatch offsets need to be known when _mesa_context_create
1021       * is called, but we can't enable the extensions until we have a
1022       * context pointer.
1023       *
1024       * Hello chicken.  Hello egg.  How are you two today?
1025       */
1026      driInitExtensions( NULL, card_extensions, GL_FALSE );
1027#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1028      driInitExtensions( NULL, blend_extensions, GL_FALSE );
1029      driInitSingleExtension( NULL, ARB_vp_extension );
1030      driInitSingleExtension( NULL, NV_vp_extension );
1031      driInitSingleExtension( NULL, ATI_fs_extension );
1032#endif
1033   }
1034
1035   return (void *) psp;
1036}
1037
1038
1039/**
1040 * Get information about previous buffer swaps.
1041 */
1042static int
1043getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1044{
1045#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1046   radeonContextPtr  rmesa;
1047#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1048   r200ContextPtr  rmesa;
1049#endif
1050
1051   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1052	|| (dPriv->driContextPriv->driverPrivate == NULL)
1053	|| (sInfo == NULL) ) {
1054      return -1;
1055   }
1056
1057   rmesa = dPriv->driContextPriv->driverPrivate;
1058   sInfo->swap_count = rmesa->swap_count;
1059   sInfo->swap_ust = rmesa->swap_ust;
1060   sInfo->swap_missed_count = rmesa->swap_missed_count;
1061
1062   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1063       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1064       : 0.0;
1065
1066   return 0;
1067}
1068