radeon_screen.c revision c0ae4d3c55a606ede41399e39e5221b1955ecc22
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#include "radeon_span.h" 51#if !RADEON_COMMON 52#include "radeon_context.h" 53#include "radeon_tex.h" 54#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_tex.h" 58#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59#include "r300_context.h" 60#include "r300_fragprog.h" 61#include "r300_tex.h" 62#endif 63 64#include "utils.h" 65#include "vblank.h" 66#include "drirenderbuffer.h" 67 68#include "radeon_bocs_wrapper.h" 69 70#include "GL/internal/dri_interface.h" 71 72/* Radeon configuration 73 */ 74#include "xmlpool.h" 75 76#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 77DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 80DRI_CONF_OPT_END 81 82#if !RADEON_COMMON /* R100 */ 83PUBLIC const char __driConfigOptions[] = 84DRI_CONF_BEGIN 85 DRI_CONF_SECTION_PERFORMANCE 86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 90 DRI_CONF_HYPERZ(false) 91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 92 DRI_CONF_SECTION_END 93 DRI_CONF_SECTION_QUALITY 94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 96 DRI_CONF_NO_NEG_LOD_BIAS(false) 97 DRI_CONF_FORCE_S3TC_ENABLE(false) 98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 101 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 102 DRI_CONF_SECTION_END 103 DRI_CONF_SECTION_DEBUG 104 DRI_CONF_NO_RAST(false) 105 DRI_CONF_SECTION_END 106DRI_CONF_END; 107static const GLuint __driNConfigOptions = 15; 108 109#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 110 111PUBLIC const char __driConfigOptions[] = 112DRI_CONF_BEGIN 113 DRI_CONF_SECTION_PERFORMANCE 114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 118 DRI_CONF_HYPERZ(false) 119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 120 DRI_CONF_SECTION_END 121 DRI_CONF_SECTION_QUALITY 122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 124 DRI_CONF_NO_NEG_LOD_BIAS(false) 125 DRI_CONF_FORCE_S3TC_ENABLE(false) 126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 129 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 131 DRI_CONF_SECTION_END 132 DRI_CONF_SECTION_DEBUG 133 DRI_CONF_NO_RAST(false) 134 DRI_CONF_SECTION_END 135 DRI_CONF_SECTION_SOFTWARE 136 DRI_CONF_NV_VERTEX_PROGRAM(false) 137 DRI_CONF_SECTION_END 138DRI_CONF_END; 139static const GLuint __driNConfigOptions = 17; 140 141extern const struct dri_extension blend_extensions[]; 142extern const struct dri_extension ARB_vp_extension[]; 143extern const struct dri_extension NV_vp_extension[]; 144extern const struct dri_extension ATI_fs_extension[]; 145extern const struct dri_extension point_extensions[]; 146 147#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 148 149/* TODO: integrate these into xmlpool.h! */ 150#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 151DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 152 DRI_CONF_DESC(en,"Number of texture image units") \ 153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 154DRI_CONF_OPT_END 155 156#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 157DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 158 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 160DRI_CONF_OPT_END 161 162 163 164#define DRI_CONF_DISABLE_S3TC(def) \ 165DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 166 DRI_CONF_DESC(en,"Disable S3TC compression") \ 167DRI_CONF_OPT_END 168 169#define DRI_CONF_DISABLE_FALLBACK(def) \ 170DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 172DRI_CONF_OPT_END 173 174#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 175DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 177DRI_CONF_OPT_END 178 179#define DRI_CONF_FP_OPTIMIZATION(def) \ 180DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 182 DRI_CONF_ENUM(0,"Optimize for Speed") \ 183 DRI_CONF_ENUM(1,"Optimize for Quality") \ 184 DRI_CONF_DESC_END \ 185DRI_CONF_OPT_END 186 187PUBLIC const char __driConfigOptions[] = 188DRI_CONF_BEGIN 189 DRI_CONF_SECTION_PERFORMANCE 190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 196 DRI_CONF_DISABLE_FALLBACK(true) 197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 198 DRI_CONF_SECTION_END 199 DRI_CONF_SECTION_QUALITY 200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 202 DRI_CONF_FORCE_S3TC_ENABLE(false) 203 DRI_CONF_DISABLE_S3TC(false) 204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 208 DRI_CONF_SECTION_END 209 DRI_CONF_SECTION_DEBUG 210 DRI_CONF_NO_RAST(false) 211 DRI_CONF_SECTION_END 212DRI_CONF_END; 213static const GLuint __driNConfigOptions = 17; 214 215extern const struct dri_extension gl_20_extension[]; 216 217#ifndef RADEON_DEBUG 218 219static const struct dri_debug_control debug_control[] = { 220 {"fall", DEBUG_FALLBACKS}, 221 {"tex", DEBUG_TEXTURE}, 222 {"ioctl", DEBUG_IOCTL}, 223 {"prim", DEBUG_PRIMS}, 224 {"vert", DEBUG_VERTS}, 225 {"state", DEBUG_STATE}, 226 {"code", DEBUG_CODEGEN}, 227 {"vfmt", DEBUG_VFMT}, 228 {"vtxf", DEBUG_VFMT}, 229 {"verb", DEBUG_VERBOSE}, 230 {"dri", DEBUG_DRI}, 231 {"dma", DEBUG_DMA}, 232 {"san", DEBUG_SANITY}, 233 {"sync", DEBUG_SYNC}, 234 {"pix", DEBUG_PIXEL}, 235 {"mem", DEBUG_MEMORY}, 236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 237 {NULL, 0} 238}; 239#endif /* RADEON_DEBUG */ 240 241#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 242 243extern const struct dri_extension card_extensions[]; 244 245static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 246 247static int 248radeonGetParam(int fd, int param, void *value) 249{ 250 int ret; 251 drm_radeon_getparam_t gp; 252 253 gp.param = param; 254 gp.value = value; 255 256 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 257 return ret; 258} 259 260static const __DRIconfig ** 261radeonFillInModes( __DRIscreenPrivate *psp, 262 unsigned pixel_bits, unsigned depth_bits, 263 unsigned stencil_bits, GLboolean have_back_buffer ) 264{ 265 __DRIconfig **configs; 266 __GLcontextModes *m; 267 unsigned depth_buffer_factor; 268 unsigned back_buffer_factor; 269 GLenum fb_format; 270 GLenum fb_type; 271 int i; 272 273 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 274 * enough to add support. Basically, if a context is created with an 275 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 276 * will never be used. 277 */ 278 static const GLenum back_buffer_modes[] = { 279 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 280 }; 281 282 uint8_t depth_bits_array[2]; 283 uint8_t stencil_bits_array[2]; 284 uint8_t msaa_samples_array[1]; 285 286 depth_bits_array[0] = depth_bits; 287 depth_bits_array[1] = depth_bits; 288 289 /* Just like with the accumulation buffer, always provide some modes 290 * with a stencil buffer. It will be a sw fallback, but some apps won't 291 * care about that. 292 */ 293 stencil_bits_array[0] = 0; 294 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 295 296 msaa_samples_array[0] = 0; 297 298 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 299 back_buffer_factor = (have_back_buffer) ? 2 : 1; 300 301 if ( pixel_bits == 16 ) { 302 fb_format = GL_RGB; 303 fb_type = GL_UNSIGNED_SHORT_5_6_5; 304 } 305 else { 306 fb_format = GL_BGRA; 307 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 308 } 309 310 configs = driCreateConfigs(fb_format, fb_type, 311 depth_bits_array, stencil_bits_array, 312 depth_buffer_factor, 313 back_buffer_modes, back_buffer_factor, 314 msaa_samples_array, 1); 315 if (configs == NULL) { 316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 317 __func__, __LINE__ ); 318 return NULL; 319 } 320 321 /* Mark the visual as slow if there are "fake" stencil bits. 322 */ 323 for (i = 0; configs[i]; i++) { 324 m = &configs[i]->modes; 325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 326 m->visualRating = GLX_SLOW_CONFIG; 327 } 328 } 329 330 return (const __DRIconfig **) configs; 331} 332 333#if !RADEON_COMMON 334static const __DRItexOffsetExtension radeonTexOffsetExtension = { 335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 336 radeonSetTexOffset, 337}; 338#endif 339 340#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 341static const __DRIallocateExtension r200AllocateExtension = { 342 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 343 r200AllocateMemoryMESA, 344 r200FreeMemoryMESA, 345 r200GetMemoryOffsetMESA 346}; 347 348static const __DRItexOffsetExtension r200texOffsetExtension = { 349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 350 r200SetTexOffset, 351}; 352#endif 353 354#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 355static const __DRItexOffsetExtension r300texOffsetExtension = { 356 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 357 r300SetTexOffset, 358}; 359 360static const __DRItexBufferExtension r300TexBufferExtension = { 361 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 362 r300SetTexBuffer, 363}; 364#endif 365 366static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 367{ 368 screen->chip_flags = 0; 369 switch ( device_id ) { 370 case PCI_CHIP_RADEON_LY: 371 case PCI_CHIP_RADEON_LZ: 372 case PCI_CHIP_RADEON_QY: 373 case PCI_CHIP_RADEON_QZ: 374 case PCI_CHIP_RN50_515E: 375 case PCI_CHIP_RN50_5969: 376 screen->chip_family = CHIP_FAMILY_RV100; 377 break; 378 379 case PCI_CHIP_RS100_4136: 380 case PCI_CHIP_RS100_4336: 381 screen->chip_family = CHIP_FAMILY_RS100; 382 break; 383 384 case PCI_CHIP_RS200_4137: 385 case PCI_CHIP_RS200_4337: 386 case PCI_CHIP_RS250_4237: 387 case PCI_CHIP_RS250_4437: 388 screen->chip_family = CHIP_FAMILY_RS200; 389 break; 390 391 case PCI_CHIP_RADEON_QD: 392 case PCI_CHIP_RADEON_QE: 393 case PCI_CHIP_RADEON_QF: 394 case PCI_CHIP_RADEON_QG: 395 /* all original radeons (7200) presumably have a stencil op bug */ 396 screen->chip_family = CHIP_FAMILY_R100; 397 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 398 break; 399 400 case PCI_CHIP_RV200_QW: 401 case PCI_CHIP_RV200_QX: 402 case PCI_CHIP_RADEON_LW: 403 case PCI_CHIP_RADEON_LX: 404 screen->chip_family = CHIP_FAMILY_RV200; 405 screen->chip_flags = RADEON_CHIPSET_TCL; 406 break; 407 408 case PCI_CHIP_R200_BB: 409 case PCI_CHIP_R200_BC: 410 case PCI_CHIP_R200_QH: 411 case PCI_CHIP_R200_QL: 412 case PCI_CHIP_R200_QM: 413 screen->chip_family = CHIP_FAMILY_R200; 414 screen->chip_flags = RADEON_CHIPSET_TCL; 415 break; 416 417 case PCI_CHIP_RV250_If: 418 case PCI_CHIP_RV250_Ig: 419 case PCI_CHIP_RV250_Ld: 420 case PCI_CHIP_RV250_Lf: 421 case PCI_CHIP_RV250_Lg: 422 screen->chip_family = CHIP_FAMILY_RV250; 423 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 424 break; 425 426 case PCI_CHIP_RV280_5960: 427 case PCI_CHIP_RV280_5961: 428 case PCI_CHIP_RV280_5962: 429 case PCI_CHIP_RV280_5964: 430 case PCI_CHIP_RV280_5965: 431 case PCI_CHIP_RV280_5C61: 432 case PCI_CHIP_RV280_5C63: 433 screen->chip_family = CHIP_FAMILY_RV280; 434 screen->chip_flags = RADEON_CHIPSET_TCL; 435 break; 436 437 case PCI_CHIP_RS300_5834: 438 case PCI_CHIP_RS300_5835: 439 case PCI_CHIP_RS350_7834: 440 case PCI_CHIP_RS350_7835: 441 screen->chip_family = CHIP_FAMILY_RS300; 442 break; 443 444 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 445 case PCI_CHIP_R300_AD: 446 screen->chip_family = CHIP_FAMILY_RV350; 447 screen->chip_flags = RADEON_CHIPSET_TCL; 448 break; 449 case PCI_CHIP_R300_AE: 450 case PCI_CHIP_R300_AF: 451 case PCI_CHIP_R300_AG: 452 case PCI_CHIP_R300_ND: 453 case PCI_CHIP_R300_NE: 454 case PCI_CHIP_R300_NF: 455 case PCI_CHIP_R300_NG: 456 screen->chip_family = CHIP_FAMILY_R300; 457 screen->chip_flags = RADEON_CHIPSET_TCL; 458 break; 459 460 case PCI_CHIP_RV350_AP: 461 case PCI_CHIP_RV350_AQ: 462 case PCI_CHIP_RV350_AR: 463 case PCI_CHIP_RV350_AS: 464 case PCI_CHIP_RV350_AT: 465 case PCI_CHIP_RV350_AV: 466 case PCI_CHIP_RV350_AU: 467 case PCI_CHIP_RV350_NP: 468 case PCI_CHIP_RV350_NQ: 469 case PCI_CHIP_RV350_NR: 470 case PCI_CHIP_RV350_NS: 471 case PCI_CHIP_RV350_NT: 472 case PCI_CHIP_RV350_NV: 473 screen->chip_family = CHIP_FAMILY_RV350; 474 screen->chip_flags = RADEON_CHIPSET_TCL; 475 break; 476 477 case PCI_CHIP_R350_AH: 478 case PCI_CHIP_R350_AI: 479 case PCI_CHIP_R350_AJ: 480 case PCI_CHIP_R350_AK: 481 case PCI_CHIP_R350_NH: 482 case PCI_CHIP_R350_NI: 483 case PCI_CHIP_R360_NJ: 484 case PCI_CHIP_R350_NK: 485 screen->chip_family = CHIP_FAMILY_R350; 486 screen->chip_flags = RADEON_CHIPSET_TCL; 487 break; 488 489 case PCI_CHIP_RV370_5460: 490 case PCI_CHIP_RV370_5462: 491 case PCI_CHIP_RV370_5464: 492 case PCI_CHIP_RV370_5B60: 493 case PCI_CHIP_RV370_5B62: 494 case PCI_CHIP_RV370_5B63: 495 case PCI_CHIP_RV370_5B64: 496 case PCI_CHIP_RV370_5B65: 497 case PCI_CHIP_RV380_3150: 498 case PCI_CHIP_RV380_3152: 499 case PCI_CHIP_RV380_3154: 500 case PCI_CHIP_RV380_3E50: 501 case PCI_CHIP_RV380_3E54: 502 screen->chip_family = CHIP_FAMILY_RV380; 503 screen->chip_flags = RADEON_CHIPSET_TCL; 504 break; 505 506 case PCI_CHIP_R420_JN: 507 case PCI_CHIP_R420_JH: 508 case PCI_CHIP_R420_JI: 509 case PCI_CHIP_R420_JJ: 510 case PCI_CHIP_R420_JK: 511 case PCI_CHIP_R420_JL: 512 case PCI_CHIP_R420_JM: 513 case PCI_CHIP_R420_JO: 514 case PCI_CHIP_R420_JP: 515 case PCI_CHIP_R420_JT: 516 case PCI_CHIP_R481_4B49: 517 case PCI_CHIP_R481_4B4A: 518 case PCI_CHIP_R481_4B4B: 519 case PCI_CHIP_R481_4B4C: 520 case PCI_CHIP_R423_UH: 521 case PCI_CHIP_R423_UI: 522 case PCI_CHIP_R423_UJ: 523 case PCI_CHIP_R423_UK: 524 case PCI_CHIP_R430_554C: 525 case PCI_CHIP_R430_554D: 526 case PCI_CHIP_R430_554E: 527 case PCI_CHIP_R430_554F: 528 case PCI_CHIP_R423_5550: 529 case PCI_CHIP_R423_UQ: 530 case PCI_CHIP_R423_UR: 531 case PCI_CHIP_R423_UT: 532 case PCI_CHIP_R430_5D48: 533 case PCI_CHIP_R430_5D49: 534 case PCI_CHIP_R430_5D4A: 535 case PCI_CHIP_R480_5D4C: 536 case PCI_CHIP_R480_5D4D: 537 case PCI_CHIP_R480_5D4E: 538 case PCI_CHIP_R480_5D4F: 539 case PCI_CHIP_R480_5D50: 540 case PCI_CHIP_R480_5D52: 541 case PCI_CHIP_R423_5D57: 542 screen->chip_family = CHIP_FAMILY_R420; 543 screen->chip_flags = RADEON_CHIPSET_TCL; 544 break; 545 546 case PCI_CHIP_RV410_5E4C: 547 case PCI_CHIP_RV410_5E4F: 548 case PCI_CHIP_RV410_564A: 549 case PCI_CHIP_RV410_564B: 550 case PCI_CHIP_RV410_564F: 551 case PCI_CHIP_RV410_5652: 552 case PCI_CHIP_RV410_5653: 553 case PCI_CHIP_RV410_5657: 554 case PCI_CHIP_RV410_5E48: 555 case PCI_CHIP_RV410_5E4A: 556 case PCI_CHIP_RV410_5E4B: 557 case PCI_CHIP_RV410_5E4D: 558 screen->chip_family = CHIP_FAMILY_RV410; 559 screen->chip_flags = RADEON_CHIPSET_TCL; 560 break; 561 562 case PCI_CHIP_RS480_5954: 563 case PCI_CHIP_RS480_5955: 564 case PCI_CHIP_RS482_5974: 565 case PCI_CHIP_RS482_5975: 566 case PCI_CHIP_RS400_5A41: 567 case PCI_CHIP_RS400_5A42: 568 case PCI_CHIP_RC410_5A61: 569 case PCI_CHIP_RC410_5A62: 570 screen->chip_family = CHIP_FAMILY_RS400; 571 break; 572 573 case PCI_CHIP_RS690_791E: 574 case PCI_CHIP_RS690_791F: 575 screen->chip_family = CHIP_FAMILY_RS690; 576 break; 577 case PCI_CHIP_RS740_796C: 578 case PCI_CHIP_RS740_796D: 579 case PCI_CHIP_RS740_796E: 580 case PCI_CHIP_RS740_796F: 581 screen->chip_family = CHIP_FAMILY_RS740; 582 break; 583 584 case PCI_CHIP_R520_7100: 585 case PCI_CHIP_R520_7101: 586 case PCI_CHIP_R520_7102: 587 case PCI_CHIP_R520_7103: 588 case PCI_CHIP_R520_7104: 589 case PCI_CHIP_R520_7105: 590 case PCI_CHIP_R520_7106: 591 case PCI_CHIP_R520_7108: 592 case PCI_CHIP_R520_7109: 593 case PCI_CHIP_R520_710A: 594 case PCI_CHIP_R520_710B: 595 case PCI_CHIP_R520_710C: 596 case PCI_CHIP_R520_710E: 597 case PCI_CHIP_R520_710F: 598 screen->chip_family = CHIP_FAMILY_R520; 599 screen->chip_flags = RADEON_CHIPSET_TCL; 600 break; 601 602 case PCI_CHIP_RV515_7140: 603 case PCI_CHIP_RV515_7141: 604 case PCI_CHIP_RV515_7142: 605 case PCI_CHIP_RV515_7143: 606 case PCI_CHIP_RV515_7144: 607 case PCI_CHIP_RV515_7145: 608 case PCI_CHIP_RV515_7146: 609 case PCI_CHIP_RV515_7147: 610 case PCI_CHIP_RV515_7149: 611 case PCI_CHIP_RV515_714A: 612 case PCI_CHIP_RV515_714B: 613 case PCI_CHIP_RV515_714C: 614 case PCI_CHIP_RV515_714D: 615 case PCI_CHIP_RV515_714E: 616 case PCI_CHIP_RV515_714F: 617 case PCI_CHIP_RV515_7151: 618 case PCI_CHIP_RV515_7152: 619 case PCI_CHIP_RV515_7153: 620 case PCI_CHIP_RV515_715E: 621 case PCI_CHIP_RV515_715F: 622 case PCI_CHIP_RV515_7180: 623 case PCI_CHIP_RV515_7181: 624 case PCI_CHIP_RV515_7183: 625 case PCI_CHIP_RV515_7186: 626 case PCI_CHIP_RV515_7187: 627 case PCI_CHIP_RV515_7188: 628 case PCI_CHIP_RV515_718A: 629 case PCI_CHIP_RV515_718B: 630 case PCI_CHIP_RV515_718C: 631 case PCI_CHIP_RV515_718D: 632 case PCI_CHIP_RV515_718F: 633 case PCI_CHIP_RV515_7193: 634 case PCI_CHIP_RV515_7196: 635 case PCI_CHIP_RV515_719B: 636 case PCI_CHIP_RV515_719F: 637 case PCI_CHIP_RV515_7200: 638 case PCI_CHIP_RV515_7210: 639 case PCI_CHIP_RV515_7211: 640 screen->chip_family = CHIP_FAMILY_RV515; 641 screen->chip_flags = RADEON_CHIPSET_TCL; 642 break; 643 644 case PCI_CHIP_RV530_71C0: 645 case PCI_CHIP_RV530_71C1: 646 case PCI_CHIP_RV530_71C2: 647 case PCI_CHIP_RV530_71C3: 648 case PCI_CHIP_RV530_71C4: 649 case PCI_CHIP_RV530_71C5: 650 case PCI_CHIP_RV530_71C6: 651 case PCI_CHIP_RV530_71C7: 652 case PCI_CHIP_RV530_71CD: 653 case PCI_CHIP_RV530_71CE: 654 case PCI_CHIP_RV530_71D2: 655 case PCI_CHIP_RV530_71D4: 656 case PCI_CHIP_RV530_71D5: 657 case PCI_CHIP_RV530_71D6: 658 case PCI_CHIP_RV530_71DA: 659 case PCI_CHIP_RV530_71DE: 660 screen->chip_family = CHIP_FAMILY_RV530; 661 screen->chip_flags = RADEON_CHIPSET_TCL; 662 break; 663 664 case PCI_CHIP_R580_7240: 665 case PCI_CHIP_R580_7243: 666 case PCI_CHIP_R580_7244: 667 case PCI_CHIP_R580_7245: 668 case PCI_CHIP_R580_7246: 669 case PCI_CHIP_R580_7247: 670 case PCI_CHIP_R580_7248: 671 case PCI_CHIP_R580_7249: 672 case PCI_CHIP_R580_724A: 673 case PCI_CHIP_R580_724B: 674 case PCI_CHIP_R580_724C: 675 case PCI_CHIP_R580_724D: 676 case PCI_CHIP_R580_724E: 677 case PCI_CHIP_R580_724F: 678 case PCI_CHIP_R580_7284: 679 screen->chip_family = CHIP_FAMILY_R580; 680 screen->chip_flags = RADEON_CHIPSET_TCL; 681 break; 682 683 case PCI_CHIP_RV570_7280: 684 case PCI_CHIP_RV560_7281: 685 case PCI_CHIP_RV560_7283: 686 case PCI_CHIP_RV560_7287: 687 case PCI_CHIP_RV570_7288: 688 case PCI_CHIP_RV570_7289: 689 case PCI_CHIP_RV570_728B: 690 case PCI_CHIP_RV570_728C: 691 case PCI_CHIP_RV560_7290: 692 case PCI_CHIP_RV560_7291: 693 case PCI_CHIP_RV560_7293: 694 case PCI_CHIP_RV560_7297: 695 screen->chip_family = CHIP_FAMILY_RV560; 696 screen->chip_flags = RADEON_CHIPSET_TCL; 697 break; 698 699 default: 700 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 701 device_id); 702 return -1; 703 } 704 705 return 0; 706} 707 708 709/* Create the device specific screen private data struct. 710 */ 711static radeonScreenPtr 712radeonCreateScreen( __DRIscreenPrivate *sPriv ) 713{ 714 radeonScreenPtr screen; 715 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 716 unsigned char *RADEONMMIO = NULL; 717 int i; 718 int ret; 719 uint32_t temp; 720 721 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 722 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 723 return GL_FALSE; 724 } 725 726 /* Allocate the private area */ 727 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 728 if ( !screen ) { 729 __driUtilMessage("%s: Could not allocate memory for screen structure", 730 __FUNCTION__); 731 return NULL; 732 } 733 734#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 735 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 736#endif 737 738 /* parse information in __driConfigOptions */ 739 driParseOptionInfo (&screen->optionCache, 740 __driConfigOptions, __driNConfigOptions); 741 742 /* This is first since which regions we map depends on whether or 743 * not we are using a PCI card. 744 */ 745 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 746 { 747 int ret; 748 749#ifdef RADEON_PARAM_KERNEL_MM 750 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, 751 &screen->kernel_mm); 752 753 if (ret && ret != -EINVAL) { 754 FREE( screen ); 755 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 756 return NULL; 757 } 758 759 if (ret == -EINVAL) 760 screen->kernel_mm = 0; 761#endif 762 763 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 764 &screen->gart_buffer_offset); 765 766 if (ret) { 767 FREE( screen ); 768 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 769 return NULL; 770 } 771 772 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 773 &screen->gart_base); 774 if (ret) { 775 FREE( screen ); 776 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 777 return NULL; 778 } 779 780 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 781 &screen->irq); 782 if (ret) { 783 FREE( screen ); 784 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 785 return NULL; 786 } 787 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 788 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 789 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 790 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 791 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 792 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 793 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 794 } 795 796 if (!screen->kernel_mm) { 797 screen->mmio.handle = dri_priv->registerHandle; 798 screen->mmio.size = dri_priv->registerSize; 799 if ( drmMap( sPriv->fd, 800 screen->mmio.handle, 801 screen->mmio.size, 802 &screen->mmio.map ) ) { 803 FREE( screen ); 804 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 805 return NULL; 806 } 807 808 RADEONMMIO = screen->mmio.map; 809 810 screen->status.handle = dri_priv->statusHandle; 811 screen->status.size = dri_priv->statusSize; 812 if ( drmMap( sPriv->fd, 813 screen->status.handle, 814 screen->status.size, 815 &screen->status.map ) ) { 816 drmUnmap( screen->mmio.map, screen->mmio.size ); 817 FREE( screen ); 818 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 819 return NULL; 820 } 821 screen->scratch = (__volatile__ uint32_t *) 822 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 823 824 screen->buffers = drmMapBufs( sPriv->fd ); 825 if ( !screen->buffers ) { 826 drmUnmap( screen->status.map, screen->status.size ); 827 drmUnmap( screen->mmio.map, screen->mmio.size ); 828 FREE( screen ); 829 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 830 return NULL; 831 } 832 833 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 834 screen->gartTextures.handle = dri_priv->gartTexHandle; 835 screen->gartTextures.size = dri_priv->gartTexMapSize; 836 if ( drmMap( sPriv->fd, 837 screen->gartTextures.handle, 838 screen->gartTextures.size, 839 (drmAddressPtr)&screen->gartTextures.map ) ) { 840 drmUnmapBufs( screen->buffers ); 841 drmUnmap( screen->status.map, screen->status.size ); 842 drmUnmap( screen->mmio.map, screen->mmio.size ); 843 FREE( screen ); 844 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 845 return NULL; 846 } 847 848 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 849 } 850 } 851 852 853 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 854 if (ret == -1) 855 return NULL; 856 857 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 858 sPriv->ddx_version.minor < 2) { 859 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 860 return NULL; 861 } 862 863 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 864 fprintf(stderr, "R500 support requires a newer drm.\n"); 865 return NULL; 866 } 867 868 if (getenv("R300_NO_TCL")) 869 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 870 871 if (screen->chip_family <= CHIP_FAMILY_RS200) 872 screen->chip_flags |= RADEON_CLASS_R100; 873 else if (screen->chip_family <= CHIP_FAMILY_RV280) 874 screen->chip_flags |= RADEON_CLASS_R200; 875 else 876 screen->chip_flags |= RADEON_CLASS_R300; 877 878 screen->cpp = dri_priv->bpp / 8; 879 screen->AGPMode = dri_priv->AGPMode; 880 881 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 882 &temp); 883 if (ret) { 884 if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) 885 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 886 else { 887 FREE( screen ); 888 fprintf(stderr, "Unable to get fb location need newer drm\n"); 889 return NULL; 890 } 891 } else { 892 screen->fbLocation = (temp & 0xffff) << 16; 893 } 894 895 if (screen->chip_family >= CHIP_FAMILY_RV515) { 896 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 897 &temp); 898 if (ret) { 899 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 900 switch (screen->chip_family) { 901 case CHIP_FAMILY_R300: 902 case CHIP_FAMILY_R350: 903 screen->num_gb_pipes = 2; 904 break; 905 case CHIP_FAMILY_R420: 906 case CHIP_FAMILY_R520: 907 case CHIP_FAMILY_R580: 908 case CHIP_FAMILY_RV560: 909 case CHIP_FAMILY_RV570: 910 screen->num_gb_pipes = 4; 911 break; 912 case CHIP_FAMILY_RV350: 913 case CHIP_FAMILY_RV515: 914 case CHIP_FAMILY_RV530: 915 case CHIP_FAMILY_RV410: 916 default: 917 screen->num_gb_pipes = 1; 918 break; 919 } 920 } else { 921 screen->num_gb_pipes = temp; 922 } 923 } 924 925 if ( sPriv->drm_version.minor >= 10 ) { 926 drm_radeon_setparam_t sp; 927 928 sp.param = RADEON_SETPARAM_FB_LOCATION; 929 sp.value = screen->fbLocation; 930 931 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 932 &sp, sizeof( sp ) ); 933 } 934 935 screen->frontOffset = dri_priv->frontOffset; 936 screen->frontPitch = dri_priv->frontPitch; 937 screen->backOffset = dri_priv->backOffset; 938 screen->backPitch = dri_priv->backPitch; 939 screen->depthOffset = dri_priv->depthOffset; 940 screen->depthPitch = dri_priv->depthPitch; 941 942 /* Check if ddx has set up a surface reg to cover depth buffer */ 943 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 944 /* these chips don't use tiled z without hyperz. So always pretend 945 we have set up a surface which will cause linear reads/writes */ 946 (IS_R100_CLASS(screen) && 947 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 948 949 if ( dri_priv->textureSize == 0 ) { 950 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 951 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 952 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 953 dri_priv->log2GARTTexGran; 954 } else { 955 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 956 + screen->fbLocation; 957 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 958 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 959 dri_priv->log2TexGran; 960 } 961 962 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 963 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 964 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 965 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 966 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 967 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 968 } else { 969 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 970 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 971 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 972 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 973 dri_priv->log2GARTTexGran; 974 } 975 976 i = 0; 977 screen->extensions[i++] = &driCopySubBufferExtension.base; 978 screen->extensions[i++] = &driFrameTrackingExtension.base; 979 screen->extensions[i++] = &driReadDrawableExtension; 980 981 if ( screen->irq != 0 ) { 982 screen->extensions[i++] = &driSwapControlExtension.base; 983 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 984 } 985 986#if !RADEON_COMMON 987 screen->extensions[i++] = &radeonTexOffsetExtension.base; 988#endif 989 990#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 991 if (IS_R200_CLASS(screen)) 992 screen->extensions[i++] = &r200AllocateExtension.base; 993 994 screen->extensions[i++] = &r200texOffsetExtension.base; 995#endif 996 997#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 998 //screen->extensions[i++] = &r300texOffsetExtension.base; 999#endif 1000 1001 screen->extensions[i++] = NULL; 1002 sPriv->extensions = screen->extensions; 1003 1004 screen->driScreen = sPriv; 1005 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1006 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1007 screen->sarea_priv_offset); 1008 1009 if (screen->kernel_mm) 1010 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1011 else 1012 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1013 if (screen->bom == NULL) { 1014 free(screen); 1015 return NULL; 1016 } 1017 1018 return screen; 1019} 1020 1021static radeonScreenPtr 1022radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1023{ 1024 radeonScreenPtr screen; 1025 int i; 1026 int ret; 1027 uint32_t device_id; 1028 1029 /* Allocate the private area */ 1030 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1031 if ( !screen ) { 1032 __driUtilMessage("%s: Could not allocate memory for screen structure", 1033 __FUNCTION__); 1034 fprintf(stderr, "leaving here\n"); 1035 return NULL; 1036 } 1037 1038#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1039 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1040#endif 1041 1042 /* parse information in __driConfigOptions */ 1043 driParseOptionInfo (&screen->optionCache, 1044 __driConfigOptions, __driNConfigOptions); 1045 1046 screen->kernel_mm = 1; 1047 screen->chip_flags = 0; 1048 1049 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 1050 &screen->irq); 1051 1052 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, 1053 &device_id); 1054 if (ret) { 1055 FREE( screen ); 1056 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1057 return NULL; 1058 } 1059 1060 ret = radeon_set_screen_flags(screen, device_id); 1061 if (ret == -1) 1062 return NULL; 1063 1064 if (screen->chip_family <= CHIP_FAMILY_RS200) 1065 screen->chip_flags |= RADEON_CLASS_R100; 1066 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1067 screen->chip_flags |= RADEON_CLASS_R200; 1068 else 1069 screen->chip_flags |= RADEON_CLASS_R300; 1070 1071 i = 0; 1072 screen->extensions[i++] = &driCopySubBufferExtension.base; 1073 screen->extensions[i++] = &driFrameTrackingExtension.base; 1074 screen->extensions[i++] = &driReadDrawableExtension; 1075 1076 if ( screen->irq != 0 ) { 1077 screen->extensions[i++] = &driSwapControlExtension.base; 1078 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1079 } 1080 1081#if !RADEON_COMMON 1082 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1083#endif 1084 1085#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1086 if (IS_R200_CLASS(screen)) 1087 screen->extensions[i++] = &r200AllocateExtension.base; 1088 1089 screen->extensions[i++] = &r200texOffsetExtension.base; 1090#endif 1091 1092#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1093 screen->extensions[i++] = &r300texOffsetExtension.base; 1094 screen->extensions[i++] = &r300TexBufferExtension.base; 1095#endif 1096 1097 screen->extensions[i++] = NULL; 1098 sPriv->extensions = screen->extensions; 1099 1100 screen->driScreen = sPriv; 1101 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1102 if (screen->bom == NULL) { 1103 free(screen); 1104 return NULL; 1105 } 1106 return screen; 1107} 1108 1109/* Destroy the device specific screen private data struct. 1110 */ 1111static void 1112radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1113{ 1114 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1115 1116 if (!screen) 1117 return; 1118 1119 if (screen->kernel_mm) { 1120#ifdef RADEON_BO_TRACK 1121 radeon_tracker_print(&screen->bom->tracker, stderr); 1122#endif 1123 radeon_bo_manager_gem_dtor(screen->bom); 1124 } else { 1125 radeon_bo_manager_legacy_dtor(screen->bom); 1126 1127 if ( screen->gartTextures.map ) { 1128 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1129 } 1130 drmUnmapBufs( screen->buffers ); 1131 drmUnmap( screen->status.map, screen->status.size ); 1132 drmUnmap( screen->mmio.map, screen->mmio.size ); 1133 } 1134 1135 /* free all option information */ 1136 driDestroyOptionInfo (&screen->optionCache); 1137 1138 FREE( screen ); 1139 sPriv->private = NULL; 1140} 1141 1142 1143/* Initialize the driver specific screen private data. 1144 */ 1145static GLboolean 1146radeonInitDriver( __DRIscreenPrivate *sPriv ) 1147{ 1148 if (sPriv->dri2.enabled) { 1149 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1150 } else { 1151 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1152 } 1153 if ( !sPriv->private ) { 1154 radeonDestroyScreen( sPriv ); 1155 return GL_FALSE; 1156 } 1157 1158 return GL_TRUE; 1159} 1160 1161static GLboolean 1162radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, 1163 GLenum intFormat, GLuint w, GLuint h) 1164{ 1165 rb->Width = w; 1166 rb->Height = h; 1167 rb->_ActualFormat = intFormat; 1168 1169 return GL_TRUE; 1170} 1171 1172 1173static struct radeon_renderbuffer * 1174radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) 1175{ 1176 struct radeon_renderbuffer *ret; 1177 1178 ret = CALLOC_STRUCT(radeon_renderbuffer); 1179 if (!ret) 1180 return NULL; 1181 1182 _mesa_init_renderbuffer(&ret->base, 0); 1183 1184 /* XXX format junk */ 1185 switch (format) { 1186 case GL_RGB5: 1187 ret->base._ActualFormat = GL_RGB5; 1188 ret->base._BaseFormat = GL_RGBA; 1189 ret->base.RedBits = 5; 1190 ret->base.GreenBits = 6; 1191 ret->base.BlueBits = 5; 1192 ret->base.DataType = GL_UNSIGNED_BYTE; 1193 break; 1194 case GL_RGBA8: 1195 ret->base._ActualFormat = GL_RGBA8; 1196 ret->base._BaseFormat = GL_RGBA; 1197 ret->base.RedBits = 8; 1198 ret->base.GreenBits = 8; 1199 ret->base.BlueBits = 8; 1200 ret->base.AlphaBits = 8; 1201 ret->base.DataType = GL_UNSIGNED_BYTE; 1202 break; 1203 case GL_STENCIL_INDEX8_EXT: 1204 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; 1205 ret->base._BaseFormat = GL_STENCIL_INDEX; 1206 ret->base.StencilBits = 8; 1207 ret->base.DataType = GL_UNSIGNED_BYTE; 1208 break; 1209 case GL_DEPTH_COMPONENT16: 1210 ret->base._ActualFormat = GL_DEPTH_COMPONENT16; 1211 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1212 ret->base.DepthBits = 16; 1213 ret->base.DataType = GL_UNSIGNED_SHORT; 1214 break; 1215 case GL_DEPTH_COMPONENT24: 1216 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1217 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1218 ret->base.DepthBits = 24; 1219 ret->base.DataType = GL_UNSIGNED_INT; 1220 break; 1221 case GL_DEPTH24_STENCIL8_EXT: 1222 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1223 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; 1224 ret->base.DepthBits = 24; 1225 ret->base.StencilBits = 8; 1226 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; 1227 break; 1228 default: 1229 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); 1230 _mesa_delete_renderbuffer(&ret->base); 1231 return NULL; 1232 } 1233 1234 ret->dPriv = driDrawPriv; 1235 ret->base.InternalFormat = format; 1236 1237 ret->base.AllocStorage = radeon_alloc_window_storage; 1238 1239 radeonSetSpanFunctions(ret); 1240 1241 ret->bo = NULL; 1242 return ret; 1243} 1244 1245/** 1246 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1247 * 1248 * \todo This function (and its interface) will need to be updated to support 1249 * pbuffers. 1250 */ 1251static GLboolean 1252radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1253 __DRIdrawablePrivate *driDrawPriv, 1254 const __GLcontextModes *mesaVis, 1255 GLboolean isPixmap ) 1256{ 1257 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1258 1259 const GLboolean swDepth = GL_FALSE; 1260 const GLboolean swAlpha = GL_FALSE; 1261 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1262 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1263 mesaVis->depthBits != 24; 1264 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); 1265 GLenum depthFormat = GL_NONE; 1266 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1267 1268 if (mesaVis->depthBits == 16) 1269 depthFormat = GL_DEPTH_COMPONENT16; 1270 else if (mesaVis->depthBits == 24) 1271 depthFormat = GL_DEPTH_COMPONENT24; 1272 1273 /* front color renderbuffer */ 1274 { 1275 struct radeon_renderbuffer *front = 1276 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1277 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); 1278 front->has_surface = 1; 1279 } 1280 1281 /* back color renderbuffer */ 1282 if (mesaVis->doubleBufferMode) { 1283 struct radeon_renderbuffer *back = 1284 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1285 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); 1286 back->has_surface = 1; 1287 } 1288 1289 /* depth renderbuffer */ 1290 if (depthFormat != GL_NONE) { 1291 struct radeon_renderbuffer *depth = 1292 radeon_create_renderbuffer(depthFormat, driDrawPriv); 1293 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); 1294 depth->has_surface = screen->depthHasSurface; 1295 } 1296 1297 /* stencil renderbuffer */ 1298 if (mesaVis->stencilBits > 0 && !swStencil) { 1299 struct radeon_renderbuffer *stencil = 1300 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); 1301 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); 1302 stencil->has_surface = screen->depthHasSurface; 1303 } 1304 1305 _mesa_add_soft_renderbuffers(fb, 1306 GL_FALSE, /* color */ 1307 swDepth, 1308 swStencil, 1309 swAccum, 1310 swAlpha, 1311 GL_FALSE /* aux */); 1312 driDrawPriv->driverPrivate = (void *) fb; 1313 1314 return (driDrawPriv->driverPrivate != NULL); 1315} 1316 1317static void 1318radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1319{ 1320 struct radeon_renderbuffer *rb; 1321 GLframebuffer *fb; 1322 1323 fb = (void*)driDrawPriv->driverPrivate; 1324 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; 1325 if (rb && rb->bo) { 1326 radeon_bo_unref(rb->bo); 1327 rb->bo = NULL; 1328 } 1329 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 1330 if (rb && rb->bo) { 1331 radeon_bo_unref(rb->bo); 1332 rb->bo = NULL; 1333 } 1334 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; 1335 if (rb && rb->bo) { 1336 radeon_bo_unref(rb->bo); 1337 rb->bo = NULL; 1338 } 1339 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1340} 1341 1342#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1343/** 1344 * Choose the appropriate CreateContext function based on the chipset. 1345 * Eventually, all drivers will go through this process. 1346 */ 1347static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1348 __DRIcontextPrivate * driContextPriv, 1349 void *sharedContextPriv) 1350{ 1351 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1352 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1353 1354 if (IS_R300_CLASS(screen)) 1355 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1356 return GL_FALSE; 1357} 1358 1359/** 1360 * Choose the appropriate DestroyContext function based on the chipset. 1361 */ 1362static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1363{ 1364 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1365 1366 if (IS_R300_CLASS(radeon->radeonScreen)) 1367 return r300DestroyContext(driContextPriv); 1368} 1369 1370 1371#endif 1372 1373 1374/** 1375 * This is the driver specific part of the createNewScreen entry point. 1376 * 1377 * \todo maybe fold this into intelInitDriver 1378 * 1379 * \return the __GLcontextModes supported by this driver 1380 */ 1381static const __DRIconfig ** 1382radeonInitScreen(__DRIscreenPrivate *psp) 1383{ 1384#if !RADEON_COMMON 1385 static const char *driver_name = "Radeon"; 1386 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1387 static const __DRIversion dri_expected = { 4, 0, 0 }; 1388 static const __DRIversion drm_expected = { 1, 6, 0 }; 1389#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1390 static const char *driver_name = "R200"; 1391 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1392 static const __DRIversion dri_expected = { 4, 0, 0 }; 1393 static const __DRIversion drm_expected = { 1, 6, 0 }; 1394#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1395 static const char *driver_name = "R300"; 1396 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1397 static const __DRIversion dri_expected = { 4, 0, 0 }; 1398 static const __DRIversion drm_expected = { 1, 24, 0 }; 1399#endif 1400 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1401 1402 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1403 &psp->dri_version, & dri_expected, 1404 &psp->ddx_version, & ddx_expected, 1405 &psp->drm_version, & drm_expected ) ) { 1406 return NULL; 1407 } 1408 1409 /* Calling driInitExtensions here, with a NULL context pointer, 1410 * does not actually enable the extensions. It just makes sure 1411 * that all the dispatch offsets for all the extensions that 1412 * *might* be enables are known. This is needed because the 1413 * dispatch offsets need to be known when _mesa_context_create 1414 * is called, but we can't enable the extensions until we have a 1415 * context pointer. 1416 * 1417 * Hello chicken. Hello egg. How are you two today? 1418 */ 1419 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1420#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1421 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1422 driInitSingleExtension( NULL, ARB_vp_extension ); 1423 driInitSingleExtension( NULL, NV_vp_extension ); 1424 driInitSingleExtension( NULL, ATI_fs_extension ); 1425 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1426#elif defined(RADEON_COMMON_FOR_R300) 1427 driInitSingleExtension( NULL, gl_20_extension ); 1428#endif 1429 1430 if (!radeonInitDriver(psp)) 1431 return NULL; 1432 1433 /* for now fill in all modes */ 1434 return radeonFillInModes( psp, 1435 dri_priv->bpp, 1436 (dri_priv->bpp == 16) ? 16 : 24, 1437 (dri_priv->bpp == 16) ? 0 : 8, 1); 1438} 1439 1440/** 1441 * This is the driver specific part of the createNewScreen entry point. 1442 * Called when using DRI2. 1443 * 1444 * \return the __GLcontextModes supported by this driver 1445 */ 1446static const 1447__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1448{ 1449 /* Calling driInitExtensions here, with a NULL context pointer, 1450 * does not actually enable the extensions. It just makes sure 1451 * that all the dispatch offsets for all the extensions that 1452 * *might* be enables are known. This is needed because the 1453 * dispatch offsets need to be known when _mesa_context_create 1454 * is called, but we can't enable the extensions until we have a 1455 * context pointer. 1456 * 1457 * Hello chicken. Hello egg. How are you two today? 1458 */ 1459 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1460#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1461 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1462 driInitSingleExtension( NULL, ARB_vp_extension ); 1463 driInitSingleExtension( NULL, NV_vp_extension ); 1464 driInitSingleExtension( NULL, ATI_fs_extension ); 1465 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1466#endif 1467 1468 if (!radeonInitDriver(psp)) { 1469 return NULL; 1470 } 1471 1472 /* for now fill in all modes */ 1473 return radeonFillInModes( psp, 24, 24, 8, 1); 1474} 1475 1476/** 1477 * Get information about previous buffer swaps. 1478 */ 1479static int 1480getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1481{ 1482 radeonContextPtr rmesa; 1483 1484 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1485 || (dPriv->driContextPriv->driverPrivate == NULL) 1486 || (sInfo == NULL) ) { 1487 return -1; 1488 } 1489 1490 rmesa = dPriv->driContextPriv->driverPrivate; 1491 sInfo->swap_count = rmesa->swap_count; 1492 sInfo->swap_ust = rmesa->swap_ust; 1493 sInfo->swap_missed_count = rmesa->swap_missed_count; 1494 1495 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1496 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1497 : 0.0; 1498 1499 return 0; 1500} 1501 1502#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1503const struct __DriverAPIRec driDriverAPI = { 1504 .InitScreen = radeonInitScreen, 1505 .DestroyScreen = radeonDestroyScreen, 1506 .CreateContext = radeonCreateContext, 1507 .DestroyContext = radeonDestroyContext, 1508 .CreateBuffer = radeonCreateBuffer, 1509 .DestroyBuffer = radeonDestroyBuffer, 1510 .SwapBuffers = radeonSwapBuffers, 1511 .MakeCurrent = radeonMakeCurrent, 1512 .UnbindContext = radeonUnbindContext, 1513 .GetSwapInfo = getSwapInfo, 1514 .GetDrawableMSC = driDrawableGetMSC32, 1515 .WaitForMSC = driWaitForMSC32, 1516 .WaitForSBC = NULL, 1517 .SwapBuffersMSC = NULL, 1518 .CopySubBuffer = radeonCopySubBuffer, 1519 /* DRI2 */ 1520 .InitScreen2 = radeonInitScreen2, 1521}; 1522#else 1523const struct __DriverAPIRec driDriverAPI = { 1524 .InitScreen = radeonInitScreen, 1525 .DestroyScreen = radeonDestroyScreen, 1526 .CreateContext = r200CreateContext, 1527 .DestroyContext = r200DestroyContext, 1528 .CreateBuffer = radeonCreateBuffer, 1529 .DestroyBuffer = radeonDestroyBuffer, 1530 .SwapBuffers = radeonSwapBuffers, 1531 .MakeCurrent = radeonMakeCurrent, 1532 .UnbindContext = radeonUnbindContext, 1533 .GetSwapInfo = getSwapInfo, 1534 .GetDrawableMSC = driDrawableGetMSC32, 1535 .WaitForMSC = driWaitForMSC32, 1536 .WaitForSBC = NULL, 1537 .SwapBuffersMSC = NULL, 1538 .CopySubBuffer = radeonCopySubBuffer, 1539}; 1540#endif 1541 1542