radeon_screen.c revision c5d9a7ab3034b90614689f223b94ac81b8a84338
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_buffer.h" 50#include "common_misc.h" 51#include "radeon_span.h" 52#if !RADEON_COMMON 53#include "radeon_context.h" 54#include "radeon_tex.h" 55#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 56#include "r200_context.h" 57#include "r200_ioctl.h" 58#include "r200_tex.h" 59#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 60#include "r300_context.h" 61#include "r300_fragprog.h" 62#include "r300_tex.h" 63#endif 64 65#include "utils.h" 66#include "vblank.h" 67#include "drirenderbuffer.h" 68 69#include "GL/internal/dri_interface.h" 70 71/* Radeon configuration 72 */ 73#include "xmlpool.h" 74#include "radeon_bo_legacy.h" 75#include "radeon_bo_gem.h" 76 77#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 78DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 79 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 80 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 81DRI_CONF_OPT_END 82 83#if !RADEON_COMMON /* R100 */ 84PUBLIC const char __driConfigOptions[] = 85DRI_CONF_BEGIN 86 DRI_CONF_SECTION_PERFORMANCE 87 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 88 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 89 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 90 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 91 DRI_CONF_HYPERZ(false) 92 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 93 DRI_CONF_SECTION_END 94 DRI_CONF_SECTION_QUALITY 95 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 96 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 97 DRI_CONF_NO_NEG_LOD_BIAS(false) 98 DRI_CONF_FORCE_S3TC_ENABLE(false) 99 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 100 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 101 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 102 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 103 DRI_CONF_SECTION_END 104 DRI_CONF_SECTION_DEBUG 105 DRI_CONF_NO_RAST(false) 106 DRI_CONF_SECTION_END 107DRI_CONF_END; 108static const GLuint __driNConfigOptions = 15; 109 110#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 111 112PUBLIC const char __driConfigOptions[] = 113DRI_CONF_BEGIN 114 DRI_CONF_SECTION_PERFORMANCE 115 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 116 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 117 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 118 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 119 DRI_CONF_HYPERZ(false) 120 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 121 DRI_CONF_SECTION_END 122 DRI_CONF_SECTION_QUALITY 123 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 124 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 125 DRI_CONF_NO_NEG_LOD_BIAS(false) 126 DRI_CONF_FORCE_S3TC_ENABLE(false) 127 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 128 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 129 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 130 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 131 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 132 DRI_CONF_SECTION_END 133 DRI_CONF_SECTION_DEBUG 134 DRI_CONF_NO_RAST(false) 135 DRI_CONF_SECTION_END 136 DRI_CONF_SECTION_SOFTWARE 137 DRI_CONF_NV_VERTEX_PROGRAM(false) 138 DRI_CONF_SECTION_END 139DRI_CONF_END; 140static const GLuint __driNConfigOptions = 17; 141 142extern const struct dri_extension blend_extensions[]; 143extern const struct dri_extension ARB_vp_extension[]; 144extern const struct dri_extension NV_vp_extension[]; 145extern const struct dri_extension ATI_fs_extension[]; 146extern const struct dri_extension point_extensions[]; 147 148#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 149 150/* TODO: integrate these into xmlpool.h! */ 151#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 152DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 153 DRI_CONF_DESC(en,"Number of texture image units") \ 154 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 155DRI_CONF_OPT_END 156 157#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 158DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 159 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 160 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 161DRI_CONF_OPT_END 162 163 164 165#define DRI_CONF_DISABLE_S3TC(def) \ 166DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 167 DRI_CONF_DESC(en,"Disable S3TC compression") \ 168DRI_CONF_OPT_END 169 170#define DRI_CONF_DISABLE_FALLBACK(def) \ 171DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 172 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 173DRI_CONF_OPT_END 174 175#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 176DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 177 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 178DRI_CONF_OPT_END 179 180#define DRI_CONF_FP_OPTIMIZATION(def) \ 181DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 182 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 183 DRI_CONF_ENUM(0,"Optimize for Speed") \ 184 DRI_CONF_ENUM(1,"Optimize for Quality") \ 185 DRI_CONF_DESC_END \ 186DRI_CONF_OPT_END 187 188PUBLIC const char __driConfigOptions[] = 189DRI_CONF_BEGIN 190 DRI_CONF_SECTION_PERFORMANCE 191 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 192 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 193 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 194 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 195 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 196 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 197 DRI_CONF_DISABLE_FALLBACK(true) 198 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 199 DRI_CONF_SECTION_END 200 DRI_CONF_SECTION_QUALITY 201 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 202 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 203 DRI_CONF_FORCE_S3TC_ENABLE(false) 204 DRI_CONF_DISABLE_S3TC(false) 205 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 206 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 207 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 208 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 209 DRI_CONF_SECTION_END 210 DRI_CONF_SECTION_DEBUG 211 DRI_CONF_NO_RAST(false) 212 DRI_CONF_SECTION_END 213DRI_CONF_END; 214static const GLuint __driNConfigOptions = 17; 215 216#ifndef RADEON_DEBUG 217 218static const struct dri_debug_control debug_control[] = { 219 {"fall", DEBUG_FALLBACKS}, 220 {"tex", DEBUG_TEXTURE}, 221 {"ioctl", DEBUG_IOCTL}, 222 {"prim", DEBUG_PRIMS}, 223 {"vert", DEBUG_VERTS}, 224 {"state", DEBUG_STATE}, 225 {"code", DEBUG_CODEGEN}, 226 {"vfmt", DEBUG_VFMT}, 227 {"vtxf", DEBUG_VFMT}, 228 {"verb", DEBUG_VERBOSE}, 229 {"dri", DEBUG_DRI}, 230 {"dma", DEBUG_DMA}, 231 {"san", DEBUG_SANITY}, 232 {"sync", DEBUG_SYNC}, 233 {"pix", DEBUG_PIXEL}, 234 {"mem", DEBUG_MEMORY}, 235 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 236 {NULL, 0} 237}; 238#endif /* RADEON_DEBUG */ 239 240#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 241 242extern const struct dri_extension card_extensions[]; 243 244static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 245 246static int 247radeonGetParam(int fd, int param, void *value) 248{ 249 int ret; 250 drm_radeon_getparam_t gp; 251 252 gp.param = param; 253 gp.value = value; 254 255 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 256 return ret; 257} 258 259static const __DRIconfig ** 260radeonFillInModes( __DRIscreenPrivate *psp, 261 unsigned pixel_bits, unsigned depth_bits, 262 unsigned stencil_bits, GLboolean have_back_buffer ) 263{ 264 __DRIconfig **configs; 265 __GLcontextModes *m; 266 unsigned depth_buffer_factor; 267 unsigned back_buffer_factor; 268 GLenum fb_format; 269 GLenum fb_type; 270 int i; 271 272 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 273 * enough to add support. Basically, if a context is created with an 274 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 275 * will never be used. 276 */ 277 static const GLenum back_buffer_modes[] = { 278 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 279 }; 280 281 uint8_t depth_bits_array[2]; 282 uint8_t stencil_bits_array[2]; 283 284 285 depth_bits_array[0] = depth_bits; 286 depth_bits_array[1] = depth_bits; 287 288 /* Just like with the accumulation buffer, always provide some modes 289 * with a stencil buffer. It will be a sw fallback, but some apps won't 290 * care about that. 291 */ 292 stencil_bits_array[0] = 0; 293 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 294 295 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 296 back_buffer_factor = (have_back_buffer) ? 2 : 1; 297 298 if ( pixel_bits == 16 ) { 299 fb_format = GL_RGB; 300 fb_type = GL_UNSIGNED_SHORT_5_6_5; 301 } 302 else { 303 fb_format = GL_BGRA; 304 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 305 } 306 307 configs = driCreateConfigs(fb_format, fb_type, 308 depth_bits_array, stencil_bits_array, 309 depth_buffer_factor, 310 back_buffer_modes, back_buffer_factor); 311 if (configs == NULL) { 312 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 313 __func__, __LINE__ ); 314 return NULL; 315 } 316 317 /* Mark the visual as slow if there are "fake" stencil bits. 318 */ 319 for (i = 0; configs[i]; i++) { 320 m = &configs[i]->modes; 321 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 322 m->visualRating = GLX_SLOW_CONFIG; 323 } 324 } 325 326 return (const __DRIconfig **) configs; 327} 328 329#if !RADEON_COMMON 330static const __DRItexOffsetExtension radeonTexOffsetExtension = { 331 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 332 radeonSetTexOffset, 333}; 334#endif 335 336#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 337static const __DRIallocateExtension r200AllocateExtension = { 338 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 339 r200AllocateMemoryMESA, 340 r200FreeMemoryMESA, 341 r200GetMemoryOffsetMESA 342}; 343 344static const __DRItexOffsetExtension r200texOffsetExtension = { 345 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 346 r200SetTexOffset, 347}; 348#endif 349 350#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 351static const __DRItexOffsetExtension r300texOffsetExtension = { 352 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 353 r300SetTexOffset, 354}; 355 356void r300SetTexBuffer(__DRIcontext *pDRICtx, 357 GLint target, 358 __DRIdrawable *dPriv); 359static const __DRItexBufferExtension r300TexBufferExtension = { 360 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 361 r300SetTexBuffer, 362}; 363#endif 364 365int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 366{ 367 screen->chip_flags = 0; 368 switch ( device_id ) { 369 case PCI_CHIP_RADEON_LY: 370 case PCI_CHIP_RADEON_LZ: 371 case PCI_CHIP_RADEON_QY: 372 case PCI_CHIP_RADEON_QZ: 373 case PCI_CHIP_RN50_515E: 374 case PCI_CHIP_RN50_5969: 375 screen->chip_family = CHIP_FAMILY_RV100; 376 break; 377 378 case PCI_CHIP_RS100_4136: 379 case PCI_CHIP_RS100_4336: 380 screen->chip_family = CHIP_FAMILY_RS100; 381 break; 382 383 case PCI_CHIP_RS200_4137: 384 case PCI_CHIP_RS200_4337: 385 case PCI_CHIP_RS250_4237: 386 case PCI_CHIP_RS250_4437: 387 screen->chip_family = CHIP_FAMILY_RS200; 388 break; 389 390 case PCI_CHIP_RADEON_QD: 391 case PCI_CHIP_RADEON_QE: 392 case PCI_CHIP_RADEON_QF: 393 case PCI_CHIP_RADEON_QG: 394 /* all original radeons (7200) presumably have a stencil op bug */ 395 screen->chip_family = CHIP_FAMILY_R100; 396 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 397 break; 398 399 case PCI_CHIP_RV200_QW: 400 case PCI_CHIP_RV200_QX: 401 case PCI_CHIP_RADEON_LW: 402 case PCI_CHIP_RADEON_LX: 403 screen->chip_family = CHIP_FAMILY_RV200; 404 screen->chip_flags = RADEON_CHIPSET_TCL; 405 break; 406 407 case PCI_CHIP_R200_BB: 408 case PCI_CHIP_R200_BC: 409 case PCI_CHIP_R200_QH: 410 case PCI_CHIP_R200_QL: 411 case PCI_CHIP_R200_QM: 412 screen->chip_family = CHIP_FAMILY_R200; 413 screen->chip_flags = RADEON_CHIPSET_TCL; 414 break; 415 416 case PCI_CHIP_RV250_If: 417 case PCI_CHIP_RV250_Ig: 418 case PCI_CHIP_RV250_Ld: 419 case PCI_CHIP_RV250_Lf: 420 case PCI_CHIP_RV250_Lg: 421 screen->chip_family = CHIP_FAMILY_RV250; 422 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 423 break; 424 425 case PCI_CHIP_RV280_5960: 426 case PCI_CHIP_RV280_5961: 427 case PCI_CHIP_RV280_5962: 428 case PCI_CHIP_RV280_5964: 429 case PCI_CHIP_RV280_5965: 430 case PCI_CHIP_RV280_5C61: 431 case PCI_CHIP_RV280_5C63: 432 screen->chip_family = CHIP_FAMILY_RV280; 433 screen->chip_flags = RADEON_CHIPSET_TCL; 434 break; 435 436 case PCI_CHIP_RS300_5834: 437 case PCI_CHIP_RS300_5835: 438 case PCI_CHIP_RS350_7834: 439 case PCI_CHIP_RS350_7835: 440 screen->chip_family = CHIP_FAMILY_RS300; 441 break; 442 443 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 444 case PCI_CHIP_R300_AD: 445 screen->chip_family = CHIP_FAMILY_RV350; 446 screen->chip_flags = RADEON_CHIPSET_TCL; 447 break; 448 case PCI_CHIP_R300_AE: 449 case PCI_CHIP_R300_AF: 450 case PCI_CHIP_R300_AG: 451 case PCI_CHIP_R300_ND: 452 case PCI_CHIP_R300_NE: 453 case PCI_CHIP_R300_NF: 454 case PCI_CHIP_R300_NG: 455 screen->chip_family = CHIP_FAMILY_R300; 456 screen->chip_flags = RADEON_CHIPSET_TCL; 457 break; 458 459 case PCI_CHIP_RV350_AP: 460 case PCI_CHIP_RV350_AQ: 461 case PCI_CHIP_RV350_AR: 462 case PCI_CHIP_RV350_AS: 463 case PCI_CHIP_RV350_AT: 464 case PCI_CHIP_RV350_AV: 465 case PCI_CHIP_RV350_AU: 466 case PCI_CHIP_RV350_NP: 467 case PCI_CHIP_RV350_NQ: 468 case PCI_CHIP_RV350_NR: 469 case PCI_CHIP_RV350_NS: 470 case PCI_CHIP_RV350_NT: 471 case PCI_CHIP_RV350_NV: 472 screen->chip_family = CHIP_FAMILY_RV350; 473 screen->chip_flags = RADEON_CHIPSET_TCL; 474 break; 475 476 case PCI_CHIP_R350_AH: 477 case PCI_CHIP_R350_AI: 478 case PCI_CHIP_R350_AJ: 479 case PCI_CHIP_R350_AK: 480 case PCI_CHIP_R350_NH: 481 case PCI_CHIP_R350_NI: 482 case PCI_CHIP_R360_NJ: 483 case PCI_CHIP_R350_NK: 484 screen->chip_family = CHIP_FAMILY_R350; 485 screen->chip_flags = RADEON_CHIPSET_TCL; 486 break; 487 488 case PCI_CHIP_RV370_5460: 489 case PCI_CHIP_RV370_5462: 490 case PCI_CHIP_RV370_5464: 491 case PCI_CHIP_RV370_5B60: 492 case PCI_CHIP_RV370_5B62: 493 case PCI_CHIP_RV370_5B63: 494 case PCI_CHIP_RV370_5B64: 495 case PCI_CHIP_RV370_5B65: 496 case PCI_CHIP_RV380_3150: 497 case PCI_CHIP_RV380_3152: 498 case PCI_CHIP_RV380_3154: 499 case PCI_CHIP_RV380_3E50: 500 case PCI_CHIP_RV380_3E54: 501 screen->chip_family = CHIP_FAMILY_RV380; 502 screen->chip_flags = RADEON_CHIPSET_TCL; 503 break; 504 505 case PCI_CHIP_R420_JN: 506 case PCI_CHIP_R420_JH: 507 case PCI_CHIP_R420_JI: 508 case PCI_CHIP_R420_JJ: 509 case PCI_CHIP_R420_JK: 510 case PCI_CHIP_R420_JL: 511 case PCI_CHIP_R420_JM: 512 case PCI_CHIP_R420_JO: 513 case PCI_CHIP_R420_JP: 514 case PCI_CHIP_R420_JT: 515 case PCI_CHIP_R481_4B49: 516 case PCI_CHIP_R481_4B4A: 517 case PCI_CHIP_R481_4B4B: 518 case PCI_CHIP_R481_4B4C: 519 case PCI_CHIP_R423_UH: 520 case PCI_CHIP_R423_UI: 521 case PCI_CHIP_R423_UJ: 522 case PCI_CHIP_R423_UK: 523 case PCI_CHIP_R430_554C: 524 case PCI_CHIP_R430_554D: 525 case PCI_CHIP_R430_554E: 526 case PCI_CHIP_R430_554F: 527 case PCI_CHIP_R423_5550: 528 case PCI_CHIP_R423_UQ: 529 case PCI_CHIP_R423_UR: 530 case PCI_CHIP_R423_UT: 531 case PCI_CHIP_R430_5D48: 532 case PCI_CHIP_R430_5D49: 533 case PCI_CHIP_R430_5D4A: 534 case PCI_CHIP_R480_5D4C: 535 case PCI_CHIP_R480_5D4D: 536 case PCI_CHIP_R480_5D4E: 537 case PCI_CHIP_R480_5D4F: 538 case PCI_CHIP_R480_5D50: 539 case PCI_CHIP_R480_5D52: 540 case PCI_CHIP_R423_5D57: 541 screen->chip_family = CHIP_FAMILY_R420; 542 screen->chip_flags = RADEON_CHIPSET_TCL; 543 break; 544 545 case PCI_CHIP_RV410_5E4C: 546 case PCI_CHIP_RV410_5E4F: 547 case PCI_CHIP_RV410_564A: 548 case PCI_CHIP_RV410_564B: 549 case PCI_CHIP_RV410_564F: 550 case PCI_CHIP_RV410_5652: 551 case PCI_CHIP_RV410_5653: 552 case PCI_CHIP_RV410_5657: 553 case PCI_CHIP_RV410_5E48: 554 case PCI_CHIP_RV410_5E4A: 555 case PCI_CHIP_RV410_5E4B: 556 case PCI_CHIP_RV410_5E4D: 557 screen->chip_family = CHIP_FAMILY_RV410; 558 screen->chip_flags = RADEON_CHIPSET_TCL; 559 break; 560 561 case PCI_CHIP_RS480_5954: 562 case PCI_CHIP_RS480_5955: 563 case PCI_CHIP_RS482_5974: 564 case PCI_CHIP_RS482_5975: 565 case PCI_CHIP_RS400_5A41: 566 case PCI_CHIP_RS400_5A42: 567 case PCI_CHIP_RC410_5A61: 568 case PCI_CHIP_RC410_5A62: 569 screen->chip_family = CHIP_FAMILY_RS400; 570 break; 571 572 case PCI_CHIP_RS690_791E: 573 case PCI_CHIP_RS690_791F: 574 screen->chip_family = CHIP_FAMILY_RS690; 575 break; 576 case PCI_CHIP_RS740_796C: 577 case PCI_CHIP_RS740_796D: 578 case PCI_CHIP_RS740_796E: 579 case PCI_CHIP_RS740_796F: 580 screen->chip_family = CHIP_FAMILY_RS740; 581 break; 582 583 case PCI_CHIP_R520_7100: 584 case PCI_CHIP_R520_7101: 585 case PCI_CHIP_R520_7102: 586 case PCI_CHIP_R520_7103: 587 case PCI_CHIP_R520_7104: 588 case PCI_CHIP_R520_7105: 589 case PCI_CHIP_R520_7106: 590 case PCI_CHIP_R520_7108: 591 case PCI_CHIP_R520_7109: 592 case PCI_CHIP_R520_710A: 593 case PCI_CHIP_R520_710B: 594 case PCI_CHIP_R520_710C: 595 case PCI_CHIP_R520_710E: 596 case PCI_CHIP_R520_710F: 597 screen->chip_family = CHIP_FAMILY_R520; 598 screen->chip_flags = RADEON_CHIPSET_TCL; 599 break; 600 601 case PCI_CHIP_RV515_7140: 602 case PCI_CHIP_RV515_7141: 603 case PCI_CHIP_RV515_7142: 604 case PCI_CHIP_RV515_7143: 605 case PCI_CHIP_RV515_7144: 606 case PCI_CHIP_RV515_7145: 607 case PCI_CHIP_RV515_7146: 608 case PCI_CHIP_RV515_7147: 609 case PCI_CHIP_RV515_7149: 610 case PCI_CHIP_RV515_714A: 611 case PCI_CHIP_RV515_714B: 612 case PCI_CHIP_RV515_714C: 613 case PCI_CHIP_RV515_714D: 614 case PCI_CHIP_RV515_714E: 615 case PCI_CHIP_RV515_714F: 616 case PCI_CHIP_RV515_7151: 617 case PCI_CHIP_RV515_7152: 618 case PCI_CHIP_RV515_7153: 619 case PCI_CHIP_RV515_715E: 620 case PCI_CHIP_RV515_715F: 621 case PCI_CHIP_RV515_7180: 622 case PCI_CHIP_RV515_7181: 623 case PCI_CHIP_RV515_7183: 624 case PCI_CHIP_RV515_7186: 625 case PCI_CHIP_RV515_7187: 626 case PCI_CHIP_RV515_7188: 627 case PCI_CHIP_RV515_718A: 628 case PCI_CHIP_RV515_718B: 629 case PCI_CHIP_RV515_718C: 630 case PCI_CHIP_RV515_718D: 631 case PCI_CHIP_RV515_718F: 632 case PCI_CHIP_RV515_7193: 633 case PCI_CHIP_RV515_7196: 634 case PCI_CHIP_RV515_719B: 635 case PCI_CHIP_RV515_719F: 636 case PCI_CHIP_RV515_7200: 637 case PCI_CHIP_RV515_7210: 638 case PCI_CHIP_RV515_7211: 639 screen->chip_family = CHIP_FAMILY_RV515; 640 screen->chip_flags = RADEON_CHIPSET_TCL; 641 break; 642 643 case PCI_CHIP_RV530_71C0: 644 case PCI_CHIP_RV530_71C1: 645 case PCI_CHIP_RV530_71C2: 646 case PCI_CHIP_RV530_71C3: 647 case PCI_CHIP_RV530_71C4: 648 case PCI_CHIP_RV530_71C5: 649 case PCI_CHIP_RV530_71C6: 650 case PCI_CHIP_RV530_71C7: 651 case PCI_CHIP_RV530_71CD: 652 case PCI_CHIP_RV530_71CE: 653 case PCI_CHIP_RV530_71D2: 654 case PCI_CHIP_RV530_71D4: 655 case PCI_CHIP_RV530_71D5: 656 case PCI_CHIP_RV530_71D6: 657 case PCI_CHIP_RV530_71DA: 658 case PCI_CHIP_RV530_71DE: 659 screen->chip_family = CHIP_FAMILY_RV530; 660 screen->chip_flags = RADEON_CHIPSET_TCL; 661 break; 662 663 case PCI_CHIP_R580_7240: 664 case PCI_CHIP_R580_7243: 665 case PCI_CHIP_R580_7244: 666 case PCI_CHIP_R580_7245: 667 case PCI_CHIP_R580_7246: 668 case PCI_CHIP_R580_7247: 669 case PCI_CHIP_R580_7248: 670 case PCI_CHIP_R580_7249: 671 case PCI_CHIP_R580_724A: 672 case PCI_CHIP_R580_724B: 673 case PCI_CHIP_R580_724C: 674 case PCI_CHIP_R580_724D: 675 case PCI_CHIP_R580_724E: 676 case PCI_CHIP_R580_724F: 677 case PCI_CHIP_R580_7284: 678 screen->chip_family = CHIP_FAMILY_R580; 679 screen->chip_flags = RADEON_CHIPSET_TCL; 680 break; 681 682 case PCI_CHIP_RV570_7280: 683 case PCI_CHIP_RV560_7281: 684 case PCI_CHIP_RV560_7283: 685 case PCI_CHIP_RV560_7287: 686 case PCI_CHIP_RV570_7288: 687 case PCI_CHIP_RV570_7289: 688 case PCI_CHIP_RV570_728B: 689 case PCI_CHIP_RV570_728C: 690 case PCI_CHIP_RV560_7290: 691 case PCI_CHIP_RV560_7291: 692 case PCI_CHIP_RV560_7293: 693 case PCI_CHIP_RV560_7297: 694 screen->chip_family = CHIP_FAMILY_RV560; 695 screen->chip_flags = RADEON_CHIPSET_TCL; 696 break; 697 698 default: 699 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 700 device_id); 701 return -1; 702 } 703 704 return 0; 705} 706 707 708/* Create the device specific screen private data struct. 709 */ 710static radeonScreenPtr 711radeonCreateScreen( __DRIscreenPrivate *sPriv ) 712{ 713 radeonScreenPtr screen; 714 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 715 unsigned char *RADEONMMIO = NULL; 716 int i; 717 int ret; 718 uint32_t temp; 719 720 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 721 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 722 return GL_FALSE; 723 } 724 725 /* Allocate the private area */ 726 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 727 if ( !screen ) { 728 __driUtilMessage("%s: Could not allocate memory for screen structure", 729 __FUNCTION__); 730 return NULL; 731 } 732 733#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 734 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 735#endif 736 737 /* parse information in __driConfigOptions */ 738 driParseOptionInfo (&screen->optionCache, 739 __driConfigOptions, __driNConfigOptions); 740 741 /* This is first since which regions we map depends on whether or 742 * not we are using a PCI card. 743 */ 744 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 745 { 746 int ret; 747 748#ifdef RADEON_PARAM_KERNEL_MM 749 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, 750 &screen->kernel_mm); 751 752 if (ret && ret != -EINVAL) { 753 FREE( screen ); 754 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 755 return NULL; 756 } 757 758 if (ret == -EINVAL) 759 screen->kernel_mm = 0; 760#endif 761 762 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 763 &screen->gart_buffer_offset); 764 765 if (ret) { 766 FREE( screen ); 767 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 768 return NULL; 769 } 770 771 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 772 &screen->gart_base); 773 if (ret) { 774 FREE( screen ); 775 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 776 return NULL; 777 } 778 779 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 780 &screen->irq); 781 if (ret) { 782 FREE( screen ); 783 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 784 return NULL; 785 } 786 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 787 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 788 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 789 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 790 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 791 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 792 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 793 } 794 795 if (!screen->kernel_mm) { 796 screen->mmio.handle = dri_priv->registerHandle; 797 screen->mmio.size = dri_priv->registerSize; 798 if ( drmMap( sPriv->fd, 799 screen->mmio.handle, 800 screen->mmio.size, 801 &screen->mmio.map ) ) { 802 FREE( screen ); 803 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 804 return NULL; 805 } 806 807 RADEONMMIO = screen->mmio.map; 808 809 screen->status.handle = dri_priv->statusHandle; 810 screen->status.size = dri_priv->statusSize; 811 if ( drmMap( sPriv->fd, 812 screen->status.handle, 813 screen->status.size, 814 &screen->status.map ) ) { 815 drmUnmap( screen->mmio.map, screen->mmio.size ); 816 FREE( screen ); 817 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 818 return NULL; 819 } 820 screen->scratch = (__volatile__ uint32_t *) 821 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 822 823 screen->buffers = drmMapBufs( sPriv->fd ); 824 if ( !screen->buffers ) { 825 drmUnmap( screen->status.map, screen->status.size ); 826 drmUnmap( screen->mmio.map, screen->mmio.size ); 827 FREE( screen ); 828 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 829 return NULL; 830 } 831 832 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 833 screen->gartTextures.handle = dri_priv->gartTexHandle; 834 screen->gartTextures.size = dri_priv->gartTexMapSize; 835 if ( drmMap( sPriv->fd, 836 screen->gartTextures.handle, 837 screen->gartTextures.size, 838 (drmAddressPtr)&screen->gartTextures.map ) ) { 839 drmUnmapBufs( screen->buffers ); 840 drmUnmap( screen->status.map, screen->status.size ); 841 drmUnmap( screen->mmio.map, screen->mmio.size ); 842 FREE( screen ); 843 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 844 return NULL; 845 } 846 847 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 848 } 849 } 850 851 852 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 853 if (ret == -1) 854 return NULL; 855 856 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 857 sPriv->ddx_version.minor < 2) { 858 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 859 return NULL; 860 } 861 862 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 863 fprintf(stderr, "R500 support requires a newer drm.\n"); 864 return NULL; 865 } 866 867 if (getenv("R300_NO_TCL")) 868 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 869 870 if (screen->chip_family <= CHIP_FAMILY_RS200) 871 screen->chip_flags |= RADEON_CLASS_R100; 872 else if (screen->chip_family <= CHIP_FAMILY_RV280) 873 screen->chip_flags |= RADEON_CLASS_R200; 874 else 875 screen->chip_flags |= RADEON_CLASS_R300; 876 877 screen->cpp = dri_priv->bpp / 8; 878 screen->AGPMode = dri_priv->AGPMode; 879 880 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 881 &temp); 882 if (ret) { 883 if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) 884 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 885 else { 886 FREE( screen ); 887 fprintf(stderr, "Unable to get fb location need newer drm\n"); 888 return NULL; 889 } 890 } else { 891 screen->fbLocation = (temp & 0xffff) << 16; 892 } 893 894 if (screen->chip_family >= CHIP_FAMILY_RV515) { 895 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 896 &temp); 897 if (ret) { 898 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 899 switch (screen->chip_family) { 900 case CHIP_FAMILY_R300: 901 case CHIP_FAMILY_R350: 902 screen->num_gb_pipes = 2; 903 break; 904 case CHIP_FAMILY_R420: 905 case CHIP_FAMILY_R520: 906 case CHIP_FAMILY_R580: 907 case CHIP_FAMILY_RV560: 908 case CHIP_FAMILY_RV570: 909 screen->num_gb_pipes = 4; 910 break; 911 case CHIP_FAMILY_RV350: 912 case CHIP_FAMILY_RV515: 913 case CHIP_FAMILY_RV530: 914 case CHIP_FAMILY_RV410: 915 default: 916 screen->num_gb_pipes = 1; 917 break; 918 } 919 } else { 920 screen->num_gb_pipes = temp; 921 } 922 } 923 924 if ( sPriv->drm_version.minor >= 10 ) { 925 drm_radeon_setparam_t sp; 926 927 sp.param = RADEON_SETPARAM_FB_LOCATION; 928 sp.value = screen->fbLocation; 929 930 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 931 &sp, sizeof( sp ) ); 932 } 933 934 screen->frontOffset = dri_priv->frontOffset; 935 screen->frontPitch = dri_priv->frontPitch; 936 screen->backOffset = dri_priv->backOffset; 937 screen->backPitch = dri_priv->backPitch; 938 screen->depthOffset = dri_priv->depthOffset; 939 screen->depthPitch = dri_priv->depthPitch; 940 941 /* Check if ddx has set up a surface reg to cover depth buffer */ 942 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 943 /* these chips don't use tiled z without hyperz. So always pretend 944 we have set up a surface which will cause linear reads/writes */ 945 (IS_R100_CLASS(screen) && 946 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 947 948 if ( dri_priv->textureSize == 0 ) { 949 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 950 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 951 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 952 dri_priv->log2GARTTexGran; 953 } else { 954 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 955 + screen->fbLocation; 956 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 957 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 958 dri_priv->log2TexGran; 959 } 960 961 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 962 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 963 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 964 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 965 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 966 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 967 } else { 968 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 969 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 970 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 971 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 972 dri_priv->log2GARTTexGran; 973 } 974 975 i = 0; 976 screen->extensions[i++] = &driCopySubBufferExtension.base; 977 screen->extensions[i++] = &driFrameTrackingExtension.base; 978 screen->extensions[i++] = &driReadDrawableExtension; 979 980 if ( screen->irq != 0 ) { 981 screen->extensions[i++] = &driSwapControlExtension.base; 982 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 983 } 984 985#if !RADEON_COMMON 986 screen->extensions[i++] = &radeonTexOffsetExtension.base; 987#endif 988 989#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 990 if (IS_R200_CLASS(screen)) 991 screen->extensions[i++] = &r200AllocateExtension.base; 992 993 screen->extensions[i++] = &r200texOffsetExtension.base; 994#endif 995 996#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 997 //screen->extensions[i++] = &r300texOffsetExtension.base; 998#endif 999 1000 screen->extensions[i++] = NULL; 1001 sPriv->extensions = screen->extensions; 1002 1003 screen->driScreen = sPriv; 1004 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1005 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1006 screen->sarea_priv_offset); 1007 1008 if (screen->kernel_mm) 1009 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1010 else 1011 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1012 if (screen->bom == NULL) { 1013 free(screen); 1014 return NULL; 1015 } 1016 1017 return screen; 1018} 1019 1020static radeonScreenPtr 1021radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1022{ 1023 radeonScreenPtr screen; 1024 int i; 1025 int ret; 1026 uint32_t device_id; 1027 1028 /* Allocate the private area */ 1029 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1030 if ( !screen ) { 1031 __driUtilMessage("%s: Could not allocate memory for screen structure", 1032 __FUNCTION__); 1033 fprintf(stderr, "leaving here\n"); 1034 return NULL; 1035 } 1036 1037#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1038 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1039#endif 1040 1041 /* parse information in __driConfigOptions */ 1042 driParseOptionInfo (&screen->optionCache, 1043 __driConfigOptions, __driNConfigOptions); 1044 1045 screen->kernel_mm = 1; 1046 screen->chip_flags = 0; 1047 1048 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 1049 &screen->irq); 1050 1051 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, 1052 &device_id); 1053 if (ret) { 1054 FREE( screen ); 1055 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1056 return NULL; 1057 } 1058 1059 ret = radeon_set_screen_flags(screen, device_id); 1060 if (ret == -1) 1061 return NULL; 1062 1063 if (screen->chip_family <= CHIP_FAMILY_RS200) 1064 screen->chip_flags |= RADEON_CLASS_R100; 1065 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1066 screen->chip_flags |= RADEON_CLASS_R200; 1067 else 1068 screen->chip_flags |= RADEON_CLASS_R300; 1069 1070 i = 0; 1071 screen->extensions[i++] = &driCopySubBufferExtension.base; 1072 screen->extensions[i++] = &driFrameTrackingExtension.base; 1073 screen->extensions[i++] = &driReadDrawableExtension; 1074 1075 if ( screen->irq != 0 ) { 1076 screen->extensions[i++] = &driSwapControlExtension.base; 1077 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1078 } 1079 1080#if !RADEON_COMMON 1081 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1082#endif 1083 1084#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1085 if (IS_R200_CLASS(screen)) 1086 screen->extensions[i++] = &r200AllocateExtension.base; 1087 1088 screen->extensions[i++] = &r200texOffsetExtension.base; 1089#endif 1090 1091#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1092 screen->extensions[i++] = &r300texOffsetExtension.base; 1093 screen->extensions[i++] = &r300TexBufferExtension.base; 1094#endif 1095 1096 screen->extensions[i++] = NULL; 1097 sPriv->extensions = screen->extensions; 1098 1099 screen->driScreen = sPriv; 1100 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1101 if (screen->bom == NULL) { 1102 free(screen); 1103 return NULL; 1104 } 1105 return screen; 1106} 1107 1108/* Destroy the device specific screen private data struct. 1109 */ 1110static void 1111radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1112{ 1113 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1114 1115 if (!screen) 1116 return; 1117 1118 if (screen->kernel_mm) { 1119 radeon_tracker_print(&screen->bom->tracker, stderr); 1120 radeon_bo_manager_gem_dtor(screen->bom); 1121 } else { 1122 radeon_bo_manager_legacy_dtor(screen->bom); 1123 1124 if ( screen->gartTextures.map ) { 1125 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1126 } 1127 drmUnmapBufs( screen->buffers ); 1128 drmUnmap( screen->status.map, screen->status.size ); 1129 drmUnmap( screen->mmio.map, screen->mmio.size ); 1130 } 1131 1132 /* free all option information */ 1133 driDestroyOptionInfo (&screen->optionCache); 1134 1135 FREE( screen ); 1136 sPriv->private = NULL; 1137} 1138 1139 1140/* Initialize the driver specific screen private data. 1141 */ 1142static GLboolean 1143radeonInitDriver( __DRIscreenPrivate *sPriv ) 1144{ 1145 if (sPriv->dri2.enabled) { 1146 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1147 } else { 1148 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1149 } 1150 if ( !sPriv->private ) { 1151 radeonDestroyScreen( sPriv ); 1152 return GL_FALSE; 1153 } 1154 1155 return GL_TRUE; 1156} 1157 1158static GLboolean 1159radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, 1160 GLenum intFormat, GLuint w, GLuint h) 1161{ 1162 rb->Width = w; 1163 rb->Height = h; 1164 rb->_ActualFormat = intFormat; 1165 1166 return GL_TRUE; 1167} 1168 1169 1170static struct radeon_renderbuffer * 1171radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) 1172{ 1173 struct radeon_renderbuffer *ret; 1174 1175 ret = CALLOC_STRUCT(radeon_renderbuffer); 1176 if (!ret) 1177 return NULL; 1178 1179 _mesa_init_renderbuffer(&ret->base, 0); 1180 1181 /* XXX format junk */ 1182 switch (format) { 1183 case GL_RGB5: 1184 ret->base._ActualFormat = GL_RGB5; 1185 ret->base._BaseFormat = GL_RGBA; 1186 ret->base.RedBits = 5; 1187 ret->base.GreenBits = 6; 1188 ret->base.BlueBits = 5; 1189 ret->base.DataType = GL_UNSIGNED_BYTE; 1190 break; 1191 case GL_RGBA8: 1192 ret->base._ActualFormat = GL_RGBA8; 1193 ret->base._BaseFormat = GL_RGBA; 1194 ret->base.RedBits = 8; 1195 ret->base.GreenBits = 8; 1196 ret->base.BlueBits = 8; 1197 ret->base.AlphaBits = 8; 1198 ret->base.DataType = GL_UNSIGNED_BYTE; 1199 break; 1200 case GL_STENCIL_INDEX8_EXT: 1201 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; 1202 ret->base._BaseFormat = GL_STENCIL_INDEX; 1203 ret->base.StencilBits = 8; 1204 ret->base.DataType = GL_UNSIGNED_BYTE; 1205 break; 1206 case GL_DEPTH_COMPONENT16: 1207 ret->base._ActualFormat = GL_DEPTH_COMPONENT16; 1208 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1209 ret->base.DepthBits = 16; 1210 ret->base.DataType = GL_UNSIGNED_SHORT; 1211 break; 1212 case GL_DEPTH_COMPONENT24: 1213 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1214 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1215 ret->base.DepthBits = 24; 1216 ret->base.DataType = GL_UNSIGNED_INT; 1217 break; 1218 case GL_DEPTH24_STENCIL8_EXT: 1219 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1220 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; 1221 ret->base.DepthBits = 24; 1222 ret->base.StencilBits = 8; 1223 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; 1224 break; 1225 default: 1226 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); 1227 _mesa_delete_renderbuffer(&ret->base); 1228 return NULL; 1229 } 1230 1231 ret->dPriv = driDrawPriv; 1232 ret->base.InternalFormat = format; 1233 1234 ret->base.AllocStorage = radeon_alloc_window_storage; 1235 1236 radeonSetSpanFunctions(ret); 1237 1238 ret->bo = NULL; 1239 return ret; 1240} 1241 1242/** 1243 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1244 * 1245 * \todo This function (and its interface) will need to be updated to support 1246 * pbuffers. 1247 */ 1248static GLboolean 1249radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1250 __DRIdrawablePrivate *driDrawPriv, 1251 const __GLcontextModes *mesaVis, 1252 GLboolean isPixmap ) 1253{ 1254 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1255 1256 const GLboolean swDepth = GL_FALSE; 1257 const GLboolean swAlpha = GL_FALSE; 1258 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1259 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1260 mesaVis->depthBits != 24; 1261 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); 1262 GLenum depthFormat = GL_NONE; 1263 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1264 1265 if (mesaVis->depthBits == 16) 1266 depthFormat = GL_DEPTH_COMPONENT16; 1267 else if (mesaVis->depthBits == 24) 1268 depthFormat = GL_DEPTH_COMPONENT24; 1269 1270 /* front color renderbuffer */ 1271 { 1272 struct radeon_renderbuffer *front = 1273 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1274 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); 1275 front->has_surface = 1; 1276 } 1277 1278 /* back color renderbuffer */ 1279 if (mesaVis->doubleBufferMode) { 1280 struct radeon_renderbuffer *back = 1281 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1282 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); 1283 back->has_surface = 1; 1284 } 1285 1286 /* depth renderbuffer */ 1287 if (depthFormat != GL_NONE) { 1288 struct radeon_renderbuffer *depth = 1289 radeon_create_renderbuffer(depthFormat, driDrawPriv); 1290 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); 1291 depth->has_surface = screen->depthHasSurface; 1292 } 1293 1294 /* stencil renderbuffer */ 1295 if (mesaVis->stencilBits > 0 && !swStencil) { 1296 struct radeon_renderbuffer *stencil = 1297 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); 1298 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); 1299 stencil->has_surface = screen->depthHasSurface; 1300 } 1301 1302 _mesa_add_soft_renderbuffers(fb, 1303 GL_FALSE, /* color */ 1304 swDepth, 1305 swStencil, 1306 swAccum, 1307 swAlpha, 1308 GL_FALSE /* aux */); 1309 driDrawPriv->driverPrivate = (void *) fb; 1310 1311 return (driDrawPriv->driverPrivate != NULL); 1312} 1313 1314static void 1315radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1316{ 1317 struct radeon_renderbuffer *rb; 1318 GLframebuffer *fb; 1319 1320 fb = (void*)driDrawPriv->driverPrivate; 1321 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; 1322 if (rb && rb->bo) { 1323 radeon_bo_unref(rb->bo); 1324 rb->bo = NULL; 1325 } 1326 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 1327 if (rb && rb->bo) { 1328 radeon_bo_unref(rb->bo); 1329 rb->bo = NULL; 1330 } 1331 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; 1332 if (rb && rb->bo) { 1333 radeon_bo_unref(rb->bo); 1334 rb->bo = NULL; 1335 } 1336 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1337} 1338 1339#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1340/** 1341 * Choose the appropriate CreateContext function based on the chipset. 1342 * Eventually, all drivers will go through this process. 1343 */ 1344static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1345 __DRIcontextPrivate * driContextPriv, 1346 void *sharedContextPriv) 1347{ 1348 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1349 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1350 1351 if (IS_R300_CLASS(screen)) 1352 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1353 return GL_FALSE; 1354} 1355 1356/** 1357 * Choose the appropriate DestroyContext function based on the chipset. 1358 */ 1359static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1360{ 1361 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1362 1363 if (IS_R300_CLASS(radeon->radeonScreen)) 1364 return r300DestroyContext(driContextPriv); 1365} 1366 1367 1368#endif 1369 1370/** 1371 * This is the driver specific part of the createNewScreen entry point. 1372 * 1373 * \todo maybe fold this into intelInitDriver 1374 * 1375 * \return the __GLcontextModes supported by this driver 1376 */ 1377static const __DRIconfig ** 1378radeonInitScreen(__DRIscreenPrivate *psp) 1379{ 1380#if !RADEON_COMMON 1381 static const char *driver_name = "Radeon"; 1382 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1383 static const __DRIversion dri_expected = { 4, 0, 0 }; 1384 static const __DRIversion drm_expected = { 1, 6, 0 }; 1385#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1386 static const char *driver_name = "R200"; 1387 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1388 static const __DRIversion dri_expected = { 4, 0, 0 }; 1389 static const __DRIversion drm_expected = { 1, 6, 0 }; 1390#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1391 static const char *driver_name = "R300"; 1392 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1393 static const __DRIversion dri_expected = { 4, 0, 0 }; 1394 static const __DRIversion drm_expected = { 1, 24, 0 }; 1395#endif 1396 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1397 1398 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1399 &psp->dri_version, & dri_expected, 1400 &psp->ddx_version, & ddx_expected, 1401 &psp->drm_version, & drm_expected ) ) { 1402 return NULL; 1403 } 1404 1405 /* Calling driInitExtensions here, with a NULL context pointer, 1406 * does not actually enable the extensions. It just makes sure 1407 * that all the dispatch offsets for all the extensions that 1408 * *might* be enables are known. This is needed because the 1409 * dispatch offsets need to be known when _mesa_context_create 1410 * is called, but we can't enable the extensions until we have a 1411 * context pointer. 1412 * 1413 * Hello chicken. Hello egg. How are you two today? 1414 */ 1415 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1416#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1417 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1418 driInitSingleExtension( NULL, ARB_vp_extension ); 1419 driInitSingleExtension( NULL, NV_vp_extension ); 1420 driInitSingleExtension( NULL, ATI_fs_extension ); 1421 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1422#endif 1423 1424 if (!radeonInitDriver(psp)) 1425 return NULL; 1426 1427 /* for now fill in all modes */ 1428 return radeonFillInModes( psp, 1429 dri_priv->bpp, 1430 (dri_priv->bpp == 16) ? 16 : 24, 1431 (dri_priv->bpp == 16) ? 0 : 8, 1); 1432} 1433 1434/** 1435 * This is the driver specific part of the createNewScreen entry point. 1436 * Called when using DRI2. 1437 * 1438 * \return the __GLcontextModes supported by this driver 1439 */ 1440static const 1441__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1442{ 1443 /* Calling driInitExtensions here, with a NULL context pointer, 1444 * does not actually enable the extensions. It just makes sure 1445 * that all the dispatch offsets for all the extensions that 1446 * *might* be enables are known. This is needed because the 1447 * dispatch offsets need to be known when _mesa_context_create 1448 * is called, but we can't enable the extensions until we have a 1449 * context pointer. 1450 * 1451 * Hello chicken. Hello egg. How are you two today? 1452 */ 1453 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1454#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1455 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1456 driInitSingleExtension( NULL, ARB_vp_extension ); 1457 driInitSingleExtension( NULL, NV_vp_extension ); 1458 driInitSingleExtension( NULL, ATI_fs_extension ); 1459 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1460#endif 1461 1462 if (!radeonInitDriver(psp)) { 1463 return NULL; 1464 } 1465 1466 /* for now fill in all modes */ 1467 return radeonFillInModes( psp, 24, 24, 8, 1); 1468} 1469 1470/** 1471 * Get information about previous buffer swaps. 1472 */ 1473static int 1474getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1475{ 1476 radeonContextPtr rmesa; 1477 1478 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1479 || (dPriv->driContextPriv->driverPrivate == NULL) 1480 || (sInfo == NULL) ) { 1481 return -1; 1482 } 1483 1484 rmesa = dPriv->driContextPriv->driverPrivate; 1485 sInfo->swap_count = rmesa->swap_count; 1486 sInfo->swap_ust = rmesa->swap_ust; 1487 sInfo->swap_missed_count = rmesa->swap_missed_count; 1488 1489 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1490 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1491 : 0.0; 1492 1493 return 0; 1494} 1495 1496#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1497const struct __DriverAPIRec driDriverAPI = { 1498 .InitScreen = radeonInitScreen, 1499 .DestroyScreen = radeonDestroyScreen, 1500 .CreateContext = radeonCreateContext, 1501 .DestroyContext = radeonDestroyContext, 1502 .CreateBuffer = radeonCreateBuffer, 1503 .DestroyBuffer = radeonDestroyBuffer, 1504 .SwapBuffers = radeonSwapBuffers, 1505 .MakeCurrent = radeonMakeCurrent, 1506 .UnbindContext = radeonUnbindContext, 1507 .GetSwapInfo = getSwapInfo, 1508 .GetDrawableMSC = driDrawableGetMSC32, 1509 .WaitForMSC = driWaitForMSC32, 1510 .WaitForSBC = NULL, 1511 .SwapBuffersMSC = NULL, 1512 .CopySubBuffer = radeonCopySubBuffer, 1513 /* DRI2 */ 1514 .InitScreen2 = radeonInitScreen2, 1515}; 1516#else 1517const struct __DriverAPIRec driDriverAPI = { 1518 .InitScreen = radeonInitScreen, 1519 .DestroyScreen = radeonDestroyScreen, 1520 .CreateContext = r200CreateContext, 1521 .DestroyContext = r200DestroyContext, 1522 .CreateBuffer = radeonCreateBuffer, 1523 .DestroyBuffer = radeonDestroyBuffer, 1524 .SwapBuffers = radeonSwapBuffers, 1525 .MakeCurrent = radeonMakeCurrent, 1526 .UnbindContext = r200UnbindContext, 1527 .GetSwapInfo = getSwapInfo, 1528 .GetDrawableMSC = driDrawableGetMSC32, 1529 .WaitForMSC = driWaitForMSC32, 1530 .WaitForSBC = NULL, 1531 .SwapBuffersMSC = NULL, 1532 .CopySubBuffer = radeonCopySubBuffer, 1533}; 1534#endif 1535 1536