radeon_screen.c revision c83d0bfe0645a58e7dd028b4472dbd54e479ab32
1aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy/************************************************************************** 2aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 3aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy VA Linux Systems Inc., Fremont, California. 5aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 6aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyAll Rights Reserved. 7aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 8aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyPermission is hereby granted, free of charge, to any person obtaining 9aa6c24c21c727a196451332448d4e3b11a80be69Romain Guya copy of this software and associated documentation files (the 10aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy"Software"), to deal in the Software without restriction, including 11aa6c24c21c727a196451332448d4e3b11a80be69Romain Guywithout limitation the rights to use, copy, modify, merge, publish, 12aa6c24c21c727a196451332448d4e3b11a80be69Romain Guydistribute, sublicense, and/or sell copies of the Software, and to 13aa6c24c21c727a196451332448d4e3b11a80be69Romain Guypermit persons to whom the Software is furnished to do so, subject to 14aa6c24c21c727a196451332448d4e3b11a80be69Romain Guythe following conditions: 15aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 16aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyThe above copyright notice and this permission notice (including the 17aa6c24c21c727a196451332448d4e3b11a80be69Romain Guynext paragraph) shall be included in all copies or substantial 18aa6c24c21c727a196451332448d4e3b11a80be69Romain Guyportions of the Software. 19aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 2077a811610f99e21da7f88dafef60d09f345d0506Romain GuyTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22302a9df1d50373c82923bb84ff665dfce584fb22Romain GuyMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 246be3d5561cbeccf0a8257a4acb155657f868e548Romain GuyLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 28aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy**************************************************************************/ 29aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 30aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy/** 31aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * \file radeon_screen.c 32aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * Screen initialization functions for the Radeon driver. 33aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * 34aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * \author Kevin E. Martin <martin@valinux.com> 35aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * \author Gareth Hughes <gareth@valinux.com> 36aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy */ 37aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 38aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include <errno.h> 39aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "main/glheader.h" 40aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "main/imports.h" 41aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "main/mtypes.h" 42aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "main/framebuffer.h" 43aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "main/renderbuffer.h" 44aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 45aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#define STANDALONE_MMIO 46aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_chipset.h" 47aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_macros.h" 48aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_screen.h" 49aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_common.h" 50aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_span.h" 51aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#if !RADEON_COMMON 52aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_context.h" 53aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_tex.h" 54aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "r200_context.h" 56aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "r200_ioctl.h" 57aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "r200_tex.h" 58aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "r300_context.h" 60aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "r300_fragprog.h" 61aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "r300_tex.h" 62451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy#endif 63aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 64aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "utils.h" 65aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "vblank.h" 66aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "drirenderbuffer.h" 67aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 68aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "radeon_bocs_wrapper.h" 69aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 70aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#include "GL/internal/dri_interface.h" 71aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 72cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba/* Radeon configuration 738f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy */ 748f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy#include "xmlpool.h" 758f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy 76cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 77402f05530352f34d5320c2d23be43c274d97c4e2Grace KlobaDRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 78451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 79451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 80402f05530352f34d5320c2d23be43c274d97c4e2Grace KlobaDRI_CONF_OPT_END 81451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy 82cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba#if !RADEON_COMMON /* R100 */ 83cf559377b750271472aa0a717bf3b7d34abc0b39Grace KlobaPUBLIC const char __driConfigOptions[] = 8458f4edb7701bf20925468fa5fd1a06a461ff085bRomain GuyDRI_CONF_BEGIN 85cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba DRI_CONF_SECTION_PERFORMANCE 86aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 87aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 88aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 89aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 90aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_HYPERZ(false) 91aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 92aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_END 93aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_QUALITY 94aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 95aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 96462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy DRI_CONF_NO_NEG_LOD_BIAS(false) 97462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy DRI_CONF_FORCE_S3TC_ENABLE(false) 98462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 99462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 100462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 101aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_ALLOW_LARGE_TEXTURES(2) 102aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_END 103aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_DEBUG 104aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_NO_RAST(false) 10577a811610f99e21da7f88dafef60d09f345d0506Romain Guy DRI_CONF_SECTION_END 10677a811610f99e21da7f88dafef60d09f345d0506Romain GuyDRI_CONF_END; 107aa6c24c21c727a196451332448d4e3b11a80be69Romain Guystatic const GLuint __driNConfigOptions = 15; 108aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 109aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 11067603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy 111aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyPUBLIC const char __driConfigOptions[] = 112a9489274d67b540804aafb587a226f7c2ae4464dRomain GuyDRI_CONF_BEGIN 113c989d867f2580a99cde25fab0e49e445aea33f2fRomain Guy DRI_CONF_SECTION_PERFORMANCE 114302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 115302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 116302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 11758f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 11858f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy DRI_CONF_HYPERZ(false) 1192af3524beb75150d347accc925022daa53b4a789Jamie Gennis DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 12058f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy DRI_CONF_SECTION_END 1216be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy DRI_CONF_SECTION_QUALITY 1226be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 1236be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 1246be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy DRI_CONF_NO_NEG_LOD_BIAS(false) 125918ad523b2780e0c893f3d2a32d4ec13f2a7e921John Reck DRI_CONF_FORCE_S3TC_ENABLE(false) 12636bef0bf30d6bae48cf3837df351075ca4fce654Ashok Bhat DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 1276be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 128aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 129aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_ALLOW_LARGE_TEXTURES(2) 130aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 131aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_END 132aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_DEBUG 133aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_NO_RAST(false) 134aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_END 135aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_SOFTWARE 136aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_NV_VERTEX_PROGRAM(false) 137aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_END 138aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyDRI_CONF_END; 139aa6c24c21c727a196451332448d4e3b11a80be69Romain Guystatic const GLuint __driNConfigOptions = 17; 140aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 141aa6c24c21c727a196451332448d4e3b11a80be69Romain Guyextern const struct dri_extension blend_extensions[]; 142aa6c24c21c727a196451332448d4e3b11a80be69Romain Guyextern const struct dri_extension ARB_vp_extension[]; 143aa6c24c21c727a196451332448d4e3b11a80be69Romain Guyextern const struct dri_extension NV_vp_extension[]; 144aa6c24c21c727a196451332448d4e3b11a80be69Romain Guyextern const struct dri_extension ATI_fs_extension[]; 145aa6c24c21c727a196451332448d4e3b11a80be69Romain Guyextern const struct dri_extension point_extensions[]; 146aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 147aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 148aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 149aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy/* TODO: integrate these into xmlpool.h! */ 150aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 151aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyDRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 152aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_DESC(en,"Number of texture image units") \ 153aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 154617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_END 155617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette 156617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 157aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyDRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 158617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette DRI_CONF_DESC(en,"Number of texture coordinate units") \ 159617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 160617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_END 161617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette 162617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette 163617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette 164617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette#define DRI_CONF_DISABLE_S3TC(def) \ 165617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 166617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette DRI_CONF_DESC(en,"Disable S3TC compression") \ 167617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_END 168617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette 169617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette#define DRI_CONF_DISABLE_FALLBACK(def) \ 170617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 171617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 172617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_END 173617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette 174617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 175617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 176617feb99a06e7ffb3894e86a286bf30e085f321aAlan Viverette DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 177617feb99a06e7ffb3894e86a286bf30e085f321aAlan ViveretteDRI_CONF_OPT_END 178aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 179aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#define DRI_CONF_FP_OPTIMIZATION(def) \ 180aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyDRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 181aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 182aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_ENUM(0,"Optimize for Speed") \ 183aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_ENUM(1,"Optimize for Quality") \ 184aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_DESC_END \ 185a9489274d67b540804aafb587a226f7c2ae4464dRomain GuyDRI_CONF_OPT_END 186a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy 187a9489274d67b540804aafb587a226f7c2ae4464dRomain GuyPUBLIC const char __driConfigOptions[] = 188a9489274d67b540804aafb587a226f7c2ae4464dRomain GuyDRI_CONF_BEGIN 189a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_SECTION_PERFORMANCE 190a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 191a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 192a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 193a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 194a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 195a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 196a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_DISABLE_FALLBACK(true) 197a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 198a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_SECTION_END 199a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_SECTION_QUALITY 200a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 201a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 202a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_FORCE_S3TC_ENABLE(false) 203a8a2f97c100af4ba52c61c3b59c933f44a53dad4Romain Guy DRI_CONF_DISABLE_S3TC(false) 20488801b270f693ffd4125534724f204135f592f72Romain Guy DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 205a8a2f97c100af4ba52c61c3b59c933f44a53dad4Romain Guy DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 206a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 207a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 208a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy DRI_CONF_SECTION_END 209aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_DEBUG 210aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_NO_RAST(false) 211aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy DRI_CONF_SECTION_END 212aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyDRI_CONF_END; 213aa6c24c21c727a196451332448d4e3b11a80be69Romain Guystatic const GLuint __driNConfigOptions = 17; 21477a811610f99e21da7f88dafef60d09f345d0506Romain Guy 215aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#ifndef RADEON_DEBUG 216aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 21767603c6e1b88fa20db58f69354e3925ffba037d1Romain Guystatic const struct dri_debug_control debug_control[] = { 21867603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy {"fall", DEBUG_FALLBACKS}, 21967603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy {"tex", DEBUG_TEXTURE}, 22067603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy {"ioctl", DEBUG_IOCTL}, 22167603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy {"prim", DEBUG_PRIMS}, 222aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy {"vert", DEBUG_VERTS}, 223aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy {"state", DEBUG_STATE}, 224b14dfe20ef300c47cc5cdfbd844c21f7fd302f0cJohn Reck {"code", DEBUG_CODEGEN}, 225451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy {"vfmt", DEBUG_VFMT}, 226b14dfe20ef300c47cc5cdfbd844c21f7fd302f0cJohn Reck {"vtxf", DEBUG_VFMT}, 22719b6bcfd83eb7fb92ebd06d2fec89e308311f1d0John Reck {"verb", DEBUG_VERBOSE}, 228b14dfe20ef300c47cc5cdfbd844c21f7fd302f0cJohn Reck {"dri", DEBUG_DRI}, 22931f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy {"dma", DEBUG_DMA}, 230451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy {"san", DEBUG_SANITY}, 23131f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy {"sync", DEBUG_SYNC}, 23280429c458506485904715180d10584092a5cd082Romain Guy {"pix", DEBUG_PIXEL}, 233918ad523b2780e0c893f3d2a32d4ec13f2a7e921John Reck {"mem", DEBUG_MEMORY}, 2342af3524beb75150d347accc925022daa53b4a789Jamie Gennis {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 235402f05530352f34d5320c2d23be43c274d97c4e2Grace Kloba {NULL, 0} 236451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy}; 237402f05530352f34d5320c2d23be43c274d97c4e2Grace Kloba#endif /* RADEON_DEBUG */ 238451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy 239451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 2406be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy 2416be3d5561cbeccf0a8257a4acb155657f868e548Romain Guyextern const struct dri_extension card_extensions[]; 2426be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy 2436be3d5561cbeccf0a8257a4acb155657f868e548Romain Guystatic int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 2446be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy 245402f05530352f34d5320c2d23be43c274d97c4e2Grace Klobastatic int 246451ce44a18e4c48f8a43aa250957f76967a35d31Romain GuyradeonGetParam(int fd, int param, void *value) 247451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy{ 24867603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy int ret; 24967603c6e1b88fa20db58f69354e3925ffba037d1Romain Guy drm_radeon_getparam_t gp; 250451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy 251451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy gp.param = param; 252451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy gp.value = value; 253aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 254aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 255aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy return ret; 256aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy} 257aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 258aa6c24c21c727a196451332448d4e3b11a80be69Romain Guystatic const __DRIconfig ** 259aa6c24c21c727a196451332448d4e3b11a80be69Romain GuyradeonFillInModes( __DRIscreenPrivate *psp, 260aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy unsigned pixel_bits, unsigned depth_bits, 261aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy unsigned stencil_bits, GLboolean have_back_buffer ) 262aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy{ 263aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy __DRIconfig **configs; 264aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy __GLcontextModes *m; 265aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy unsigned depth_buffer_factor; 266aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy unsigned back_buffer_factor; 267aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy GLenum fb_format; 268aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy GLenum fb_type; 269c2079c968dc0a1da455be5be1c44a35028b00c70Romain Guy int i; 270aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 271aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 272aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * enough to add support. Basically, if a context is created with an 273aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 27425fbb3fa1138675379102a44405852555cefccbdJohn Reck * will never be used. 27525fbb3fa1138675379102a44405852555cefccbdJohn Reck */ 27625fbb3fa1138675379102a44405852555cefccbdJohn Reck static const GLenum back_buffer_modes[] = { 27725fbb3fa1138675379102a44405852555cefccbdJohn Reck GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 27825fbb3fa1138675379102a44405852555cefccbdJohn Reck }; 279aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 280aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy uint8_t depth_bits_array[2]; 281aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy uint8_t stencil_bits_array[2]; 282aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 283aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 284aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy depth_bits_array[0] = depth_bits; 285aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy depth_bits_array[1] = depth_bits; 286aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 28759c7f80dd20258cefa1fc4bdd3c9a709a8dd53b8Romain Guy /* Just like with the accumulation buffer, always provide some modes 28859c7f80dd20258cefa1fc4bdd3c9a709a8dd53b8Romain Guy * with a stencil buffer. It will be a sw fallback, but some apps won't 28959c7f80dd20258cefa1fc4bdd3c9a709a8dd53b8Romain Guy * care about that. 29059c7f80dd20258cefa1fc4bdd3c9a709a8dd53b8Romain Guy */ 29159c7f80dd20258cefa1fc4bdd3c9a709a8dd53b8Romain Guy stencil_bits_array[0] = 0; 292aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 293aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 294aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 295aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy back_buffer_factor = (have_back_buffer) ? 2 : 1; 296aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 297aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy if ( pixel_bits == 16 ) { 298aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy fb_format = GL_RGB; 299aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy fb_type = GL_UNSIGNED_SHORT_5_6_5; 300aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 301aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy else { 302aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy fb_format = GL_BGRA; 303aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 304aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 305aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 306aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy configs = driCreateConfigs(fb_format, fb_type, 30752b307ebc86e12e368694442eb8751e7e0de239eRomain Guy depth_bits_array, stencil_bits_array, 30852b307ebc86e12e368694442eb8751e7e0de239eRomain Guy depth_buffer_factor, 30952b307ebc86e12e368694442eb8751e7e0de239eRomain Guy back_buffer_modes, back_buffer_factor); 31058f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy if (configs == NULL) { 311c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 312aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy __func__, __LINE__ ); 313aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy return NULL; 314aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 315aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 316aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy /* Mark the visual as slow if there are "fake" stencil bits. 317aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy */ 318aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy for (i = 0; configs[i]; i++) { 319aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy m = &configs[i]->modes; 320aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 321aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy m->visualRating = GLX_SLOW_CONFIG; 322aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 323aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 324aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 3258f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy return (const __DRIconfig **) configs; 3268f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy} 3278f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy 32852a9a10b6b8c7b7a9f97777541841b94d4fd9754Mathias Agopian#if !RADEON_COMMON 32988801b270f693ffd4125534724f204135f592f72Romain Guystatic const __DRItexOffsetExtension radeonTexOffsetExtension = { 330451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 331451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy radeonSetTexOffset, 332451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy}; 3338f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy#endif 3348f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy 3358f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 3361766b0e25de5a66f9d0f6e73a2c342272fcadc71Romain Guystatic const __DRIallocateExtension r200AllocateExtension = { 3371766b0e25de5a66f9d0f6e73a2c342272fcadc71Romain Guy { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 3381766b0e25de5a66f9d0f6e73a2c342272fcadc71Romain Guy r200AllocateMemoryMESA, 33916260e73f6c1c9dc94acf0d328a3c564426b8711Romain Guy r200FreeMemoryMESA, 34031f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy r200GetMemoryOffsetMESA 34131f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy}; 34231f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy 34331f2c2e94656530fbf6282803e62edb47e9a894dRomain Guystatic const __DRItexOffsetExtension r200texOffsetExtension = { 34431f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 34531f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy r200SetTexOffset, 34631f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy}; 34731f2c2e94656530fbf6282803e62edb47e9a894dRomain Guy#endif 3487e52caf6db5feef2b847cfaa3d13690257122c3aMichael Jurka 34952b307ebc86e12e368694442eb8751e7e0de239eRomain Guy#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 35052b307ebc86e12e368694442eb8751e7e0de239eRomain Guystatic const __DRItexOffsetExtension r300texOffsetExtension = { 35152b307ebc86e12e368694442eb8751e7e0de239eRomain Guy { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 35252b307ebc86e12e368694442eb8751e7e0de239eRomain Guy r300SetTexOffset, 353aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy}; 35458f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy 35558f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guyvoid r300SetTexBuffer(__DRIcontext *pDRICtx, 35658f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy GLint target, 35758f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy __DRIdrawable *dPriv); 35804fc583c3dd3144bc6b718fcac4b3e1afdfdb067John Reckstatic const __DRItexBufferExtension r300TexBufferExtension = { 3592af3524beb75150d347accc925022daa53b4a789Jamie Gennis { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 3608a34d6800e70da45bac662873f6951c8d8295a15Jamie Gennis r300SetTexBuffer, 361918ad523b2780e0c893f3d2a32d4ec13f2a7e921John Reck}; 362918ad523b2780e0c893f3d2a32d4ec13f2a7e921John Reck#endif 3632af3524beb75150d347accc925022daa53b4a789Jamie Gennis 36452a9a10b6b8c7b7a9f97777541841b94d4fd9754Mathias Agopianstatic int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 3652af3524beb75150d347accc925022daa53b4a789Jamie Gennis{ 366aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy screen->chip_flags = 0; 367c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown switch ( device_id ) { 368aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy case PCI_CHIP_RADEON_LY: 3698a34d6800e70da45bac662873f6951c8d8295a15Jamie Gennis case PCI_CHIP_RADEON_LZ: 370451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy case PCI_CHIP_RADEON_QY: 371aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy case PCI_CHIP_RADEON_QZ: 372d15ebf25c595b855f6978d0600218e3ea5f31e92Chet Haase case PCI_CHIP_RN50_515E: 373aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy case PCI_CHIP_RN50_5969: 374aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy screen->chip_family = CHIP_FAMILY_RV100; 3752af3524beb75150d347accc925022daa53b4a789Jamie Gennis break; 3762af3524beb75150d347accc925022daa53b4a789Jamie Gennis 3772af3524beb75150d347accc925022daa53b4a789Jamie Gennis case PCI_CHIP_RS100_4136: 3782af3524beb75150d347accc925022daa53b4a789Jamie Gennis case PCI_CHIP_RS100_4336: 3792af3524beb75150d347accc925022daa53b4a789Jamie Gennis screen->chip_family = CHIP_FAMILY_RS100; 38051f7c6b3620549429cd6c62e38bace43085e04fbRomain Guy break; 38151f7c6b3620549429cd6c62e38bace43085e04fbRomain Guy 38251f7c6b3620549429cd6c62e38bace43085e04fbRomain Guy case PCI_CHIP_RS200_4137: 38388801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_RS200_4337: 38451f7c6b3620549429cd6c62e38bace43085e04fbRomain Guy case PCI_CHIP_RS250_4237: 38551f7c6b3620549429cd6c62e38bace43085e04fbRomain Guy case PCI_CHIP_RS250_4437: 38604fc583c3dd3144bc6b718fcac4b3e1afdfdb067John Reck screen->chip_family = CHIP_FAMILY_RS200; 38752a9a10b6b8c7b7a9f97777541841b94d4fd9754Mathias Agopian break; 3882af3524beb75150d347accc925022daa53b4a789Jamie Gennis 3892af3524beb75150d347accc925022daa53b4a789Jamie Gennis case PCI_CHIP_RADEON_QD: 39058f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RADEON_QE: 391c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RADEON_QF: 392302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RADEON_QG: 393aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy /* all original radeons (7200) presumably have a stencil op bug */ 394aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy screen->chip_family = CHIP_FAMILY_R100; 395aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 3968f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy break; 3978f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy 3988f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy case PCI_CHIP_RV200_QW: 3998f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy case PCI_CHIP_RV200_QX: 4008f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy case PCI_CHIP_RADEON_LW: 4018f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy case PCI_CHIP_RADEON_LX: 4028f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy screen->chip_family = CHIP_FAMILY_RV200; 4038f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 4048f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy break; 4052dedafb48f85e34a2f48262f12908866fc9de132John Reck 4062dedafb48f85e34a2f48262f12908866fc9de132John Reck case PCI_CHIP_R200_BB: 4072dedafb48f85e34a2f48262f12908866fc9de132John Reck case PCI_CHIP_R200_BC: 40888801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_R200_QH: 4098f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy case PCI_CHIP_R200_QL: 4108f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy case PCI_CHIP_R200_QM: 4118f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy screen->chip_family = CHIP_FAMILY_R200; 4128f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 4138f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy break; 4148f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy 415a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy case PCI_CHIP_RV250_If: 41688801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_RV250_Ig: 41788801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_RV250_Ld: 41888801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_RV250_Lf: 41988801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_RV250_Lg: 42088801b270f693ffd4125534724f204135f592f72Romain Guy screen->chip_family = CHIP_FAMILY_RV250; 42188801b270f693ffd4125534724f204135f592f72Romain Guy screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 42288801b270f693ffd4125534724f204135f592f72Romain Guy break; 42388801b270f693ffd4125534724f204135f592f72Romain Guy 42488801b270f693ffd4125534724f204135f592f72Romain Guy case PCI_CHIP_RV280_5960: 42558f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RV280_5961: 42658f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RV280_5962: 4272af3524beb75150d347accc925022daa53b4a789Jamie Gennis case PCI_CHIP_RV280_5964: 42858f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RV280_5965: 42958f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RV280_5C61: 430a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy case PCI_CHIP_RV280_5C63: 431a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy screen->chip_family = CHIP_FAMILY_RV280; 432a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 43358f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy break; 43458f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy 43558f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RS300_5834: 43658f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RS300_5835: 43758f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RS350_7834: 43858f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy case PCI_CHIP_RS350_7835: 43958f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy screen->chip_family = CHIP_FAMILY_RS300; 44058f4edb7701bf20925468fa5fd1a06a461ff085bRomain Guy break; 44104fc583c3dd3144bc6b718fcac4b3e1afdfdb067John Reck 44204fc583c3dd3144bc6b718fcac4b3e1afdfdb067John Reck /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 443a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy case PCI_CHIP_R300_AD: 444cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba screen->chip_family = CHIP_FAMILY_RV350; 445cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba screen->chip_flags = RADEON_CHIPSET_TCL; 446cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba break; 447a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy case PCI_CHIP_R300_AE: 448a9489274d67b540804aafb587a226f7c2ae4464dRomain Guy case PCI_CHIP_R300_AF: 449aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy case PCI_CHIP_R300_AG: 450302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R300_ND: 451302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R300_NE: 452302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R300_NF: 453302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R300_NG: 454302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_family = CHIP_FAMILY_R300; 455302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 456302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy break; 457302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy 458302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AP: 459302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AQ: 460302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AR: 461302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AS: 462302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AT: 463302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AV: 464302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_AU: 465302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_NP: 466302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_NQ: 467302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_NR: 468302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_NS: 469c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV350_NT: 470302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV350_NV: 471302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_family = CHIP_FAMILY_RV350; 472302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 473302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy break; 474302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy 475302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_AH: 476302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_AI: 477302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_AJ: 478302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_AK: 479302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_NH: 480302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_NI: 481302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R360_NJ: 482302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_R350_NK: 483302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_family = CHIP_FAMILY_R350; 484302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 485302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy break; 486302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy 487302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV370_5460: 488302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV370_5462: 489302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV370_5464: 490302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV370_5B60: 491302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV370_5B62: 492302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy case PCI_CHIP_RV370_5B63: 493c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV370_5B64: 49451f7c6b3620549429cd6c62e38bace43085e04fbRomain Guy case PCI_CHIP_RV370_5B65: 495c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV380_3150: 496c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV380_3152: 497c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV380_3154: 498c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV380_3E50: 499c01391fb4eb0eef33d142e89e060eac7e75de39dAlexandre Elias case PCI_CHIP_RV380_3E54: 500302a9df1d50373c82923bb84ff665dfce584fb22Romain Guy screen->chip_family = CHIP_FAMILY_RV380; 50177a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 50277a811610f99e21da7f88dafef60d09f345d0506Romain Guy break; 50377a811610f99e21da7f88dafef60d09f345d0506Romain Guy 50477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JN: 50577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JH: 50677a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JI: 50777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JJ: 50877a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JK: 50977a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JL: 51077a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JM: 511d6b2a00dd43257d1498b09175bff63663f6cb861Romain Guy case PCI_CHIP_R420_JO: 512d6b2a00dd43257d1498b09175bff63663f6cb861Romain Guy case PCI_CHIP_R420_JP: 51377a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R420_JT: 51477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R481_4B49: 51577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R481_4B4A: 51677a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R481_4B4B: 51777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R481_4B4C: 51877a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UH: 51977a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UI: 52077a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UJ: 52177a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UK: 52277a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_554C: 52377a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_554D: 52477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_554E: 52577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_554F: 52677a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_5550: 52777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UQ: 52877a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UR: 52977a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_UT: 53077a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_5D48: 53177a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_5D49: 53277a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R430_5D4A: 53377a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R480_5D4C: 53477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R480_5D4D: 535d6b2a00dd43257d1498b09175bff63663f6cb861Romain Guy case PCI_CHIP_R480_5D4E: 536d6b2a00dd43257d1498b09175bff63663f6cb861Romain Guy case PCI_CHIP_R480_5D4F: 53777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R480_5D50: 53877a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R480_5D52: 53977a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R423_5D57: 54077a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_family = CHIP_FAMILY_R420; 54177a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 54277a811610f99e21da7f88dafef60d09f345d0506Romain Guy break; 54377a811610f99e21da7f88dafef60d09f345d0506Romain Guy 54477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5E4C: 54577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5E4F: 54677a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_564A: 54777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_564B: 54877a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_564F: 549dde331cebd87982faded6818ad5f9927ff994c96Dianne Hackborn case PCI_CHIP_RV410_5652: 550dde331cebd87982faded6818ad5f9927ff994c96Dianne Hackborn case PCI_CHIP_RV410_5653: 55177a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5657: 55277a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5E48: 55377a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5E4A: 55477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5E4B: 55577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV410_5E4D: 55677a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_family = CHIP_FAMILY_RV410; 55777a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 55877a811610f99e21da7f88dafef60d09f345d0506Romain Guy break; 55977a811610f99e21da7f88dafef60d09f345d0506Romain Guy 56077a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS480_5954: 56177a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS480_5955: 56277a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS482_5974: 56377a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS482_5975: 564d6b2a00dd43257d1498b09175bff63663f6cb861Romain Guy case PCI_CHIP_RS400_5A41: 565d6b2a00dd43257d1498b09175bff63663f6cb861Romain Guy case PCI_CHIP_RS400_5A42: 56677a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RC410_5A61: 56777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RC410_5A62: 56877a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_family = CHIP_FAMILY_RS400; 56977a811610f99e21da7f88dafef60d09f345d0506Romain Guy break; 57077a811610f99e21da7f88dafef60d09f345d0506Romain Guy 57177a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS690_791E: 57277a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS690_791F: 57377a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_family = CHIP_FAMILY_RS690; 574589b0bb6ab81657ba201cbc441a49f85305170bcRomain Guy break; 575589b0bb6ab81657ba201cbc441a49f85305170bcRomain Guy case PCI_CHIP_RS740_796C: 576589b0bb6ab81657ba201cbc441a49f85305170bcRomain Guy case PCI_CHIP_RS740_796D: 57777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS740_796E: 57877a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RS740_796F: 57977a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_family = CHIP_FAMILY_RS740; 580589b0bb6ab81657ba201cbc441a49f85305170bcRomain Guy break; 581589b0bb6ab81657ba201cbc441a49f85305170bcRomain Guy 582589b0bb6ab81657ba201cbc441a49f85305170bcRomain Guy case PCI_CHIP_R520_7100: 58378245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7101: 58478245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7102: 58578245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7103: 58678245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7104: 58778245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7105: 58878245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7106: 58978245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7108: 59078245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_7109: 59178245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_710A: 59278245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_710B: 59378245f77d2724ee3a053f13fbcb0359751b9f842Romain Guy case PCI_CHIP_R520_710C: 59477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R520_710E: 59577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_R520_710F: 59677a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_family = CHIP_FAMILY_R520; 59777a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 59877a811610f99e21da7f88dafef60d09f345d0506Romain Guy break; 59977a811610f99e21da7f88dafef60d09f345d0506Romain Guy 60077a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7140: 60177a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7141: 60277a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7142: 60377a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7143: 60477a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7144: 60577a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7145: 60677a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7146: 60777a811610f99e21da7f88dafef60d09f345d0506Romain Guy case PCI_CHIP_RV515_7147: 6086be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7149: 6096be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_714A: 6106be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_714B: 6116be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_714C: 6126be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_714D: 6136be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_714E: 6146be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_714F: 6156be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7151: 6166be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7152: 6176be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7153: 6186be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_715E: 6196be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_715F: 620462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy case PCI_CHIP_RV515_7180: 621462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy case PCI_CHIP_RV515_7181: 622462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy case PCI_CHIP_RV515_7183: 623462785fa257671fe4905d1d3e6ca27e4a61ee946Romain Guy case PCI_CHIP_RV515_7186: 6246be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7187: 6256be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7188: 6266be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_718A: 6276be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_718B: 6286be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_718C: 6296be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_718D: 6306be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_718F: 6316be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7193: 6326be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7196: 6336be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_719B: 6346be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_719F: 6356be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7200: 6366be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7210: 6376be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV515_7211: 6386be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy screen->chip_family = CHIP_FAMILY_RV515; 63953bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 64053bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy break; 64153bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy 64253bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy case PCI_CHIP_RV530_71C0: 64353bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy case PCI_CHIP_RV530_71C1: 6446be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71C2: 6456be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71C3: 6466be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71C4: 6476be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71C5: 6486be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71C6: 6496be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71C7: 65053bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy case PCI_CHIP_RV530_71CD: 65153bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy case PCI_CHIP_RV530_71CE: 6526be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71D2: 6536be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71D4: 6546be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71D5: 6556be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71D6: 6566be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71DA: 6576be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV530_71DE: 6586be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy screen->chip_family = CHIP_FAMILY_RV530; 6596be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 6606be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy break; 66153bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy 66253bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy case PCI_CHIP_R580_7240: 66353bacf5a91a760f6c0a966ed2f50a25e7fe12aebRomain Guy case PCI_CHIP_R580_7243: 6646be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7244: 6656be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7245: 6666be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7246: 6676be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7247: 6686be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7248: 6696be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7249: 6706be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_724A: 6716be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_724B: 6726be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_724C: 6736be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_724D: 6746be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_724E: 6756be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_724F: 6766be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_R580_7284: 6776be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy screen->chip_family = CHIP_FAMILY_R580; 6786be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 6796be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy break; 6806be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy 6816be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV570_7280: 6826be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7281: 6836be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7283: 6846be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7287: 6856be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV570_7288: 6866be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV570_7289: 6876be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV570_728B: 6886be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV570_728C: 6896be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7290: 6906be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7291: 6916be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7293: 6926be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy case PCI_CHIP_RV560_7297: 693aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy screen->chip_family = CHIP_FAMILY_RV560; 69477a811610f99e21da7f88dafef60d09f345d0506Romain Guy screen->chip_flags = RADEON_CHIPSET_TCL; 69577a811610f99e21da7f88dafef60d09f345d0506Romain Guy break; 69677a811610f99e21da7f88dafef60d09f345d0506Romain Guy 69777a811610f99e21da7f88dafef60d09f345d0506Romain Guy default: 698aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 699aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy device_id); 700aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy return -1; 701aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 702aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 703aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy return 0; 7042af3524beb75150d347accc925022daa53b4a789Jamie Gennis} 7052af3524beb75150d347accc925022daa53b4a789Jamie Gennis 7062af3524beb75150d347accc925022daa53b4a789Jamie Gennis 7072af3524beb75150d347accc925022daa53b4a789Jamie Gennis/* Create the device specific screen private data struct. 7088a34d6800e70da45bac662873f6951c8d8295a15Jamie Gennis */ 7098a34d6800e70da45bac662873f6951c8d8295a15Jamie Gennisstatic radeonScreenPtr 7108a34d6800e70da45bac662873f6951c8d8295a15Jamie GennisradeonCreateScreen( __DRIscreenPrivate *sPriv ) 7112af3524beb75150d347accc925022daa53b4a789Jamie Gennis{ 7122af3524beb75150d347accc925022daa53b4a789Jamie Gennis radeonScreenPtr screen; 7132af3524beb75150d347accc925022daa53b4a789Jamie Gennis RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 7142af3524beb75150d347accc925022daa53b4a789Jamie Gennis unsigned char *RADEONMMIO = NULL; 7152af3524beb75150d347accc925022daa53b4a789Jamie Gennis int i; 7162af3524beb75150d347accc925022daa53b4a789Jamie Gennis int ret; 7172af3524beb75150d347accc925022daa53b4a789Jamie Gennis uint32_t temp; 7182af3524beb75150d347accc925022daa53b4a789Jamie Gennis 7192af3524beb75150d347accc925022daa53b4a789Jamie Gennis if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 7202af3524beb75150d347accc925022daa53b4a789Jamie Gennis fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 7212af3524beb75150d347accc925022daa53b4a789Jamie Gennis return GL_FALSE; 7222af3524beb75150d347accc925022daa53b4a789Jamie Gennis } 7232af3524beb75150d347accc925022daa53b4a789Jamie Gennis 7242af3524beb75150d347accc925022daa53b4a789Jamie Gennis /* Allocate the private area */ 7252af3524beb75150d347accc925022daa53b4a789Jamie Gennis screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 7262af3524beb75150d347accc925022daa53b4a789Jamie Gennis if ( !screen ) { 7272af3524beb75150d347accc925022daa53b4a789Jamie Gennis __driUtilMessage("%s: Could not allocate memory for screen structure", 7282af3524beb75150d347accc925022daa53b4a789Jamie Gennis __FUNCTION__); 7292af3524beb75150d347accc925022daa53b4a789Jamie Gennis return NULL; 7302af3524beb75150d347accc925022daa53b4a789Jamie Gennis } 731aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 732aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 733aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 734aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#endif 735aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 736aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy /* parse information in __driConfigOptions */ 737aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy driParseOptionInfo (&screen->optionCache, 738aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy __driConfigOptions, __driNConfigOptions); 739aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 740aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy /* This is first since which regions we map depends on whether or 741aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy * not we are using a PCI card. 742aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy */ 743aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 744aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy { 745aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy int ret; 746aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 747aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy#ifdef RADEON_PARAM_KERNEL_MM 748aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, 749aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy &screen->kernel_mm); 750aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 751aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy if (ret && ret != -EINVAL) { 752c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown FREE( screen ); 753c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 754c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown return NULL; 755c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown } 756c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown 757c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown if (ret == -EINVAL) 758c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown screen->kernel_mm = 0; 759c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown#endif 760c7282e57cd01f1576baac04356bf99bee34e4c18Jeff Brown 761aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 762aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy &screen->gart_buffer_offset); 763aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 764aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy if (ret) { 765aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy FREE( screen ); 766aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 767aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy return NULL; 768aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy } 769aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy 770aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 771451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy &screen->gart_base); 772451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy if (ret) { 773aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy FREE( screen ); 774451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 7758f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy return NULL; 7768f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy } 7778f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy 7788f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 7798f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy &screen->irq); 7808f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy if (ret) { 7818f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy FREE( screen ); 7828f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 7838f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy return NULL; 7848f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy } 785451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 786451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 787451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 788402f05530352f34d5320c2d23be43c274d97c4e2Grace Kloba screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 789402f05530352f34d5320c2d23be43c274d97c4e2Grace Kloba screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 79052b307ebc86e12e368694442eb8751e7e0de239eRomain Guy screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 791451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 792451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy } 793451ce44a18e4c48f8a43aa250957f76967a35d31Romain Guy 794402f05530352f34d5320c2d23be43c274d97c4e2Grace Kloba if (!screen->kernel_mm) { 795cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba screen->mmio.handle = dri_priv->registerHandle; 796cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba screen->mmio.size = dri_priv->registerSize; 797cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba if ( drmMap( sPriv->fd, 798cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba screen->mmio.handle, 799cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba screen->mmio.size, 800cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba &screen->mmio.map ) ) { 801cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba FREE( screen ); 802cf559377b750271472aa0a717bf3b7d34abc0b39Grace Kloba __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 803aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy return NULL; 8048f0095cd33558e9cc8a440047908e53b68906f5fRomain Guy } 8056be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy 8066be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy RADEONMMIO = screen->mmio.map; 8076be3d5561cbeccf0a8257a4acb155657f868e548Romain Guy 80836bef0bf30d6bae48cf3837df351075ca4fce654Ashok Bhat screen->status.handle = dri_priv->statusHandle; 80936bef0bf30d6bae48cf3837df351075ca4fce654Ashok Bhat screen->status.size = dri_priv->statusSize; 810aa6c24c21c727a196451332448d4e3b11a80be69Romain Guy if ( drmMap( sPriv->fd, 811 screen->status.handle, 812 screen->status.size, 813 &screen->status.map ) ) { 814 drmUnmap( screen->mmio.map, screen->mmio.size ); 815 FREE( screen ); 816 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 817 return NULL; 818 } 819 screen->scratch = (__volatile__ uint32_t *) 820 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 821 822 screen->buffers = drmMapBufs( sPriv->fd ); 823 if ( !screen->buffers ) { 824 drmUnmap( screen->status.map, screen->status.size ); 825 drmUnmap( screen->mmio.map, screen->mmio.size ); 826 FREE( screen ); 827 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 828 return NULL; 829 } 830 831 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 832 screen->gartTextures.handle = dri_priv->gartTexHandle; 833 screen->gartTextures.size = dri_priv->gartTexMapSize; 834 if ( drmMap( sPriv->fd, 835 screen->gartTextures.handle, 836 screen->gartTextures.size, 837 (drmAddressPtr)&screen->gartTextures.map ) ) { 838 drmUnmapBufs( screen->buffers ); 839 drmUnmap( screen->status.map, screen->status.size ); 840 drmUnmap( screen->mmio.map, screen->mmio.size ); 841 FREE( screen ); 842 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 843 return NULL; 844 } 845 846 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 847 } 848 } 849 850 851 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 852 if (ret == -1) 853 return NULL; 854 855 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 856 sPriv->ddx_version.minor < 2) { 857 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 858 return NULL; 859 } 860 861 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 862 fprintf(stderr, "R500 support requires a newer drm.\n"); 863 return NULL; 864 } 865 866 if (getenv("R300_NO_TCL")) 867 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 868 869 if (screen->chip_family <= CHIP_FAMILY_RS200) 870 screen->chip_flags |= RADEON_CLASS_R100; 871 else if (screen->chip_family <= CHIP_FAMILY_RV280) 872 screen->chip_flags |= RADEON_CLASS_R200; 873 else 874 screen->chip_flags |= RADEON_CLASS_R300; 875 876 screen->cpp = dri_priv->bpp / 8; 877 screen->AGPMode = dri_priv->AGPMode; 878 879 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 880 &temp); 881 if (ret) { 882 if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) 883 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 884 else { 885 FREE( screen ); 886 fprintf(stderr, "Unable to get fb location need newer drm\n"); 887 return NULL; 888 } 889 } else { 890 screen->fbLocation = (temp & 0xffff) << 16; 891 } 892 893 if (screen->chip_family >= CHIP_FAMILY_RV515) { 894 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 895 &temp); 896 if (ret) { 897 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 898 switch (screen->chip_family) { 899 case CHIP_FAMILY_R300: 900 case CHIP_FAMILY_R350: 901 screen->num_gb_pipes = 2; 902 break; 903 case CHIP_FAMILY_R420: 904 case CHIP_FAMILY_R520: 905 case CHIP_FAMILY_R580: 906 case CHIP_FAMILY_RV560: 907 case CHIP_FAMILY_RV570: 908 screen->num_gb_pipes = 4; 909 break; 910 case CHIP_FAMILY_RV350: 911 case CHIP_FAMILY_RV515: 912 case CHIP_FAMILY_RV530: 913 case CHIP_FAMILY_RV410: 914 default: 915 screen->num_gb_pipes = 1; 916 break; 917 } 918 } else { 919 screen->num_gb_pipes = temp; 920 } 921 } 922 923 if ( sPriv->drm_version.minor >= 10 ) { 924 drm_radeon_setparam_t sp; 925 926 sp.param = RADEON_SETPARAM_FB_LOCATION; 927 sp.value = screen->fbLocation; 928 929 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 930 &sp, sizeof( sp ) ); 931 } 932 933 screen->frontOffset = dri_priv->frontOffset; 934 screen->frontPitch = dri_priv->frontPitch; 935 screen->backOffset = dri_priv->backOffset; 936 screen->backPitch = dri_priv->backPitch; 937 screen->depthOffset = dri_priv->depthOffset; 938 screen->depthPitch = dri_priv->depthPitch; 939 940 /* Check if ddx has set up a surface reg to cover depth buffer */ 941 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 942 /* these chips don't use tiled z without hyperz. So always pretend 943 we have set up a surface which will cause linear reads/writes */ 944 (IS_R100_CLASS(screen) && 945 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 946 947 if ( dri_priv->textureSize == 0 ) { 948 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 949 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 950 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 951 dri_priv->log2GARTTexGran; 952 } else { 953 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 954 + screen->fbLocation; 955 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 956 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 957 dri_priv->log2TexGran; 958 } 959 960 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 961 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 962 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 963 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 964 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 965 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 966 } else { 967 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 968 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 969 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 970 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 971 dri_priv->log2GARTTexGran; 972 } 973 974 i = 0; 975 screen->extensions[i++] = &driCopySubBufferExtension.base; 976 screen->extensions[i++] = &driFrameTrackingExtension.base; 977 screen->extensions[i++] = &driReadDrawableExtension; 978 979 if ( screen->irq != 0 ) { 980 screen->extensions[i++] = &driSwapControlExtension.base; 981 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 982 } 983 984#if !RADEON_COMMON 985 screen->extensions[i++] = &radeonTexOffsetExtension.base; 986#endif 987 988#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 989 if (IS_R200_CLASS(screen)) 990 screen->extensions[i++] = &r200AllocateExtension.base; 991 992 screen->extensions[i++] = &r200texOffsetExtension.base; 993#endif 994 995#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 996 //screen->extensions[i++] = &r300texOffsetExtension.base; 997#endif 998 999 screen->extensions[i++] = NULL; 1000 sPriv->extensions = screen->extensions; 1001 1002 screen->driScreen = sPriv; 1003 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1004 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1005 screen->sarea_priv_offset); 1006 1007 if (screen->kernel_mm) 1008 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1009 else 1010 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1011 if (screen->bom == NULL) { 1012 free(screen); 1013 return NULL; 1014 } 1015 1016 return screen; 1017} 1018 1019#ifndef RADEON_PARAM_DEVICE_ID 1020#define RADEON_PARAM_DEVICE_ID 17 1021#endif 1022 1023static radeonScreenPtr 1024radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1025{ 1026 radeonScreenPtr screen; 1027 int i; 1028 int ret; 1029 uint32_t device_id; 1030 1031 /* Allocate the private area */ 1032 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1033 if ( !screen ) { 1034 __driUtilMessage("%s: Could not allocate memory for screen structure", 1035 __FUNCTION__); 1036 fprintf(stderr, "leaving here\n"); 1037 return NULL; 1038 } 1039 1040#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1041 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1042#endif 1043 1044 /* parse information in __driConfigOptions */ 1045 driParseOptionInfo (&screen->optionCache, 1046 __driConfigOptions, __driNConfigOptions); 1047 1048 screen->kernel_mm = 1; 1049 screen->chip_flags = 0; 1050 1051 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 1052 &screen->irq); 1053 1054 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, 1055 &device_id); 1056 if (ret) { 1057 FREE( screen ); 1058 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1059 return NULL; 1060 } 1061 1062 ret = radeon_set_screen_flags(screen, device_id); 1063 if (ret == -1) 1064 return NULL; 1065 1066 if (screen->chip_family <= CHIP_FAMILY_RS200) 1067 screen->chip_flags |= RADEON_CLASS_R100; 1068 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1069 screen->chip_flags |= RADEON_CLASS_R200; 1070 else 1071 screen->chip_flags |= RADEON_CLASS_R300; 1072 1073 i = 0; 1074 screen->extensions[i++] = &driCopySubBufferExtension.base; 1075 screen->extensions[i++] = &driFrameTrackingExtension.base; 1076 screen->extensions[i++] = &driReadDrawableExtension; 1077 1078 if ( screen->irq != 0 ) { 1079 screen->extensions[i++] = &driSwapControlExtension.base; 1080 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1081 } 1082 1083#if !RADEON_COMMON 1084 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1085#endif 1086 1087#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1088 if (IS_R200_CLASS(screen)) 1089 screen->extensions[i++] = &r200AllocateExtension.base; 1090 1091 screen->extensions[i++] = &r200texOffsetExtension.base; 1092#endif 1093 1094#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1095 screen->extensions[i++] = &r300texOffsetExtension.base; 1096 screen->extensions[i++] = &r300TexBufferExtension.base; 1097#endif 1098 1099 screen->extensions[i++] = NULL; 1100 sPriv->extensions = screen->extensions; 1101 1102 screen->driScreen = sPriv; 1103 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1104 if (screen->bom == NULL) { 1105 free(screen); 1106 return NULL; 1107 } 1108 return screen; 1109} 1110 1111/* Destroy the device specific screen private data struct. 1112 */ 1113static void 1114radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1115{ 1116 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1117 1118 if (!screen) 1119 return; 1120 1121 if (screen->kernel_mm) { 1122#ifdef RADEON_BO_TRACK 1123 radeon_tracker_print(&screen->bom->tracker, stderr); 1124#endif 1125 radeon_bo_manager_gem_dtor(screen->bom); 1126 } else { 1127 radeon_bo_manager_legacy_dtor(screen->bom); 1128 1129 if ( screen->gartTextures.map ) { 1130 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1131 } 1132 drmUnmapBufs( screen->buffers ); 1133 drmUnmap( screen->status.map, screen->status.size ); 1134 drmUnmap( screen->mmio.map, screen->mmio.size ); 1135 } 1136 1137 /* free all option information */ 1138 driDestroyOptionInfo (&screen->optionCache); 1139 1140 FREE( screen ); 1141 sPriv->private = NULL; 1142} 1143 1144 1145/* Initialize the driver specific screen private data. 1146 */ 1147static GLboolean 1148radeonInitDriver( __DRIscreenPrivate *sPriv ) 1149{ 1150 if (sPriv->dri2.enabled) { 1151 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1152 } else { 1153 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1154 } 1155 if ( !sPriv->private ) { 1156 radeonDestroyScreen( sPriv ); 1157 return GL_FALSE; 1158 } 1159 1160 return GL_TRUE; 1161} 1162 1163static GLboolean 1164radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, 1165 GLenum intFormat, GLuint w, GLuint h) 1166{ 1167 rb->Width = w; 1168 rb->Height = h; 1169 rb->_ActualFormat = intFormat; 1170 1171 return GL_TRUE; 1172} 1173 1174 1175static struct radeon_renderbuffer * 1176radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) 1177{ 1178 struct radeon_renderbuffer *ret; 1179 1180 ret = CALLOC_STRUCT(radeon_renderbuffer); 1181 if (!ret) 1182 return NULL; 1183 1184 _mesa_init_renderbuffer(&ret->base, 0); 1185 1186 /* XXX format junk */ 1187 switch (format) { 1188 case GL_RGB5: 1189 ret->base._ActualFormat = GL_RGB5; 1190 ret->base._BaseFormat = GL_RGBA; 1191 ret->base.RedBits = 5; 1192 ret->base.GreenBits = 6; 1193 ret->base.BlueBits = 5; 1194 ret->base.DataType = GL_UNSIGNED_BYTE; 1195 break; 1196 case GL_RGBA8: 1197 ret->base._ActualFormat = GL_RGBA8; 1198 ret->base._BaseFormat = GL_RGBA; 1199 ret->base.RedBits = 8; 1200 ret->base.GreenBits = 8; 1201 ret->base.BlueBits = 8; 1202 ret->base.AlphaBits = 8; 1203 ret->base.DataType = GL_UNSIGNED_BYTE; 1204 break; 1205 case GL_STENCIL_INDEX8_EXT: 1206 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; 1207 ret->base._BaseFormat = GL_STENCIL_INDEX; 1208 ret->base.StencilBits = 8; 1209 ret->base.DataType = GL_UNSIGNED_BYTE; 1210 break; 1211 case GL_DEPTH_COMPONENT16: 1212 ret->base._ActualFormat = GL_DEPTH_COMPONENT16; 1213 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1214 ret->base.DepthBits = 16; 1215 ret->base.DataType = GL_UNSIGNED_SHORT; 1216 break; 1217 case GL_DEPTH_COMPONENT24: 1218 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1219 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1220 ret->base.DepthBits = 24; 1221 ret->base.DataType = GL_UNSIGNED_INT; 1222 break; 1223 case GL_DEPTH24_STENCIL8_EXT: 1224 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1225 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; 1226 ret->base.DepthBits = 24; 1227 ret->base.StencilBits = 8; 1228 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; 1229 break; 1230 default: 1231 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); 1232 _mesa_delete_renderbuffer(&ret->base); 1233 return NULL; 1234 } 1235 1236 ret->dPriv = driDrawPriv; 1237 ret->base.InternalFormat = format; 1238 1239 ret->base.AllocStorage = radeon_alloc_window_storage; 1240 1241 radeonSetSpanFunctions(ret); 1242 1243 ret->bo = NULL; 1244 return ret; 1245} 1246 1247/** 1248 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1249 * 1250 * \todo This function (and its interface) will need to be updated to support 1251 * pbuffers. 1252 */ 1253static GLboolean 1254radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1255 __DRIdrawablePrivate *driDrawPriv, 1256 const __GLcontextModes *mesaVis, 1257 GLboolean isPixmap ) 1258{ 1259 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1260 1261 const GLboolean swDepth = GL_FALSE; 1262 const GLboolean swAlpha = GL_FALSE; 1263 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1264 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1265 mesaVis->depthBits != 24; 1266 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); 1267 GLenum depthFormat = GL_NONE; 1268 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1269 1270 if (mesaVis->depthBits == 16) 1271 depthFormat = GL_DEPTH_COMPONENT16; 1272 else if (mesaVis->depthBits == 24) 1273 depthFormat = GL_DEPTH_COMPONENT24; 1274 1275 /* front color renderbuffer */ 1276 { 1277 struct radeon_renderbuffer *front = 1278 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1279 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); 1280 front->has_surface = 1; 1281 } 1282 1283 /* back color renderbuffer */ 1284 if (mesaVis->doubleBufferMode) { 1285 struct radeon_renderbuffer *back = 1286 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1287 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); 1288 back->has_surface = 1; 1289 } 1290 1291 /* depth renderbuffer */ 1292 if (depthFormat != GL_NONE) { 1293 struct radeon_renderbuffer *depth = 1294 radeon_create_renderbuffer(depthFormat, driDrawPriv); 1295 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); 1296 depth->has_surface = screen->depthHasSurface; 1297 } 1298 1299 /* stencil renderbuffer */ 1300 if (mesaVis->stencilBits > 0 && !swStencil) { 1301 struct radeon_renderbuffer *stencil = 1302 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); 1303 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); 1304 stencil->has_surface = screen->depthHasSurface; 1305 } 1306 1307 _mesa_add_soft_renderbuffers(fb, 1308 GL_FALSE, /* color */ 1309 swDepth, 1310 swStencil, 1311 swAccum, 1312 swAlpha, 1313 GL_FALSE /* aux */); 1314 driDrawPriv->driverPrivate = (void *) fb; 1315 1316 return (driDrawPriv->driverPrivate != NULL); 1317} 1318 1319static void 1320radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1321{ 1322 struct radeon_renderbuffer *rb; 1323 GLframebuffer *fb; 1324 1325 fb = (void*)driDrawPriv->driverPrivate; 1326 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; 1327 if (rb && rb->bo) { 1328 radeon_bo_unref(rb->bo); 1329 rb->bo = NULL; 1330 } 1331 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 1332 if (rb && rb->bo) { 1333 radeon_bo_unref(rb->bo); 1334 rb->bo = NULL; 1335 } 1336 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; 1337 if (rb && rb->bo) { 1338 radeon_bo_unref(rb->bo); 1339 rb->bo = NULL; 1340 } 1341 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1342} 1343 1344#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1345/** 1346 * Choose the appropriate CreateContext function based on the chipset. 1347 * Eventually, all drivers will go through this process. 1348 */ 1349static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1350 __DRIcontextPrivate * driContextPriv, 1351 void *sharedContextPriv) 1352{ 1353 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1354 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1355 1356 if (IS_R300_CLASS(screen)) 1357 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1358 return GL_FALSE; 1359} 1360 1361/** 1362 * Choose the appropriate DestroyContext function based on the chipset. 1363 */ 1364static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1365{ 1366 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1367 1368 if (IS_R300_CLASS(radeon->radeonScreen)) 1369 return r300DestroyContext(driContextPriv); 1370} 1371 1372 1373#endif 1374 1375/** 1376 * This is the driver specific part of the createNewScreen entry point. 1377 * 1378 * \todo maybe fold this into intelInitDriver 1379 * 1380 * \return the __GLcontextModes supported by this driver 1381 */ 1382static const __DRIconfig ** 1383radeonInitScreen(__DRIscreenPrivate *psp) 1384{ 1385#if !RADEON_COMMON 1386 static const char *driver_name = "Radeon"; 1387 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1388 static const __DRIversion dri_expected = { 4, 0, 0 }; 1389 static const __DRIversion drm_expected = { 1, 6, 0 }; 1390#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1391 static const char *driver_name = "R200"; 1392 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1393 static const __DRIversion dri_expected = { 4, 0, 0 }; 1394 static const __DRIversion drm_expected = { 1, 6, 0 }; 1395#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1396 static const char *driver_name = "R300"; 1397 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1398 static const __DRIversion dri_expected = { 4, 0, 0 }; 1399 static const __DRIversion drm_expected = { 1, 24, 0 }; 1400#endif 1401 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1402 1403 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1404 &psp->dri_version, & dri_expected, 1405 &psp->ddx_version, & ddx_expected, 1406 &psp->drm_version, & drm_expected ) ) { 1407 return NULL; 1408 } 1409 1410 /* Calling driInitExtensions here, with a NULL context pointer, 1411 * does not actually enable the extensions. It just makes sure 1412 * that all the dispatch offsets for all the extensions that 1413 * *might* be enables are known. This is needed because the 1414 * dispatch offsets need to be known when _mesa_context_create 1415 * is called, but we can't enable the extensions until we have a 1416 * context pointer. 1417 * 1418 * Hello chicken. Hello egg. How are you two today? 1419 */ 1420 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1421#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1422 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1423 driInitSingleExtension( NULL, ARB_vp_extension ); 1424 driInitSingleExtension( NULL, NV_vp_extension ); 1425 driInitSingleExtension( NULL, ATI_fs_extension ); 1426 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1427#endif 1428 1429 if (!radeonInitDriver(psp)) 1430 return NULL; 1431 1432 /* for now fill in all modes */ 1433 return radeonFillInModes( psp, 1434 dri_priv->bpp, 1435 (dri_priv->bpp == 16) ? 16 : 24, 1436 (dri_priv->bpp == 16) ? 0 : 8, 1); 1437} 1438 1439/** 1440 * This is the driver specific part of the createNewScreen entry point. 1441 * Called when using DRI2. 1442 * 1443 * \return the __GLcontextModes supported by this driver 1444 */ 1445static const 1446__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1447{ 1448 /* Calling driInitExtensions here, with a NULL context pointer, 1449 * does not actually enable the extensions. It just makes sure 1450 * that all the dispatch offsets for all the extensions that 1451 * *might* be enables are known. This is needed because the 1452 * dispatch offsets need to be known when _mesa_context_create 1453 * is called, but we can't enable the extensions until we have a 1454 * context pointer. 1455 * 1456 * Hello chicken. Hello egg. How are you two today? 1457 */ 1458 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1459#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1460 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1461 driInitSingleExtension( NULL, ARB_vp_extension ); 1462 driInitSingleExtension( NULL, NV_vp_extension ); 1463 driInitSingleExtension( NULL, ATI_fs_extension ); 1464 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1465#endif 1466 1467 if (!radeonInitDriver(psp)) { 1468 return NULL; 1469 } 1470 1471 /* for now fill in all modes */ 1472 return radeonFillInModes( psp, 24, 24, 8, 1); 1473} 1474 1475/** 1476 * Get information about previous buffer swaps. 1477 */ 1478static int 1479getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1480{ 1481 radeonContextPtr rmesa; 1482 1483 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1484 || (dPriv->driContextPriv->driverPrivate == NULL) 1485 || (sInfo == NULL) ) { 1486 return -1; 1487 } 1488 1489 rmesa = dPriv->driContextPriv->driverPrivate; 1490 sInfo->swap_count = rmesa->swap_count; 1491 sInfo->swap_ust = rmesa->swap_ust; 1492 sInfo->swap_missed_count = rmesa->swap_missed_count; 1493 1494 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1495 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1496 : 0.0; 1497 1498 return 0; 1499} 1500 1501#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1502const struct __DriverAPIRec driDriverAPI = { 1503 .InitScreen = radeonInitScreen, 1504 .DestroyScreen = radeonDestroyScreen, 1505 .CreateContext = radeonCreateContext, 1506 .DestroyContext = radeonDestroyContext, 1507 .CreateBuffer = radeonCreateBuffer, 1508 .DestroyBuffer = radeonDestroyBuffer, 1509 .SwapBuffers = radeonSwapBuffers, 1510 .MakeCurrent = radeonMakeCurrent, 1511 .UnbindContext = radeonUnbindContext, 1512 .GetSwapInfo = getSwapInfo, 1513 .GetDrawableMSC = driDrawableGetMSC32, 1514 .WaitForMSC = driWaitForMSC32, 1515 .WaitForSBC = NULL, 1516 .SwapBuffersMSC = NULL, 1517 .CopySubBuffer = radeonCopySubBuffer, 1518 /* DRI2 */ 1519 .InitScreen2 = radeonInitScreen2, 1520}; 1521#else 1522const struct __DriverAPIRec driDriverAPI = { 1523 .InitScreen = radeonInitScreen, 1524 .DestroyScreen = radeonDestroyScreen, 1525 .CreateContext = r200CreateContext, 1526 .DestroyContext = r200DestroyContext, 1527 .CreateBuffer = radeonCreateBuffer, 1528 .DestroyBuffer = radeonDestroyBuffer, 1529 .SwapBuffers = radeonSwapBuffers, 1530 .MakeCurrent = radeonMakeCurrent, 1531 .UnbindContext = radeonUnbindContext, 1532 .GetSwapInfo = getSwapInfo, 1533 .GetDrawableMSC = driDrawableGetMSC32, 1534 .WaitForMSC = driWaitForMSC32, 1535 .WaitForSBC = NULL, 1536 .SwapBuffersMSC = NULL, 1537 .CopySubBuffer = radeonCopySubBuffer, 1538}; 1539#endif 1540 1541