radeon_screen.c revision eaf15db895e3a5c6c5ccc2f23a4f0fa522855868
1c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/************************************************************************** 2c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 3c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) VA Linux Systems Inc., Fremont, California. 5c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 6c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)All Rights Reserved. 7c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 87dbb3d5cf0c15f500944d211057644d6a2f37371Ben MurdochPermission is hereby granted, free of charge, to any person obtaining 97dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdocha copy of this software and associated documentation files (the 10558790d6acca3451cf3a6b497803a5f07d0bec58Ben Murdoch"Software"), to deal in the Software without restriction, including 11c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)without limitation the rights to use, copy, modify, merge, publish, 12c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)distribute, sublicense, and/or sell copies of the Software, and to 13c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)permit persons to whom the Software is furnished to do so, subject to 14c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)the following conditions: 15c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 16c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)The above copyright notice and this permission notice (including the 17c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)next paragraph) shall be included in all copies or substantial 18c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)portions of the Software. 19d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 20d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 28c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)**************************************************************************/ 29c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 30c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/** 31c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * \file radeon_screen.c 32c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * Screen initialization functions for the Radeon driver. 33c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * 34c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * \author Kevin E. Martin <martin@valinux.com> 35c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * \author Gareth Hughes <gareth@valinux.com> 36c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) */ 37c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 38c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "main/glheader.h" 39c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "main/imports.h" 40c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "main/mtypes.h" 41c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "main/framebuffer.h" 42c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "main/renderbuffer.h" 43c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 44c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#define STANDALONE_MMIO 45c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_chipset.h" 46c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_macros.h" 47c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_screen.h" 48c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#if !RADEON_COMMON 49c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_context.h" 50c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_span.h" 51c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_tex.h" 52c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 53c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "r200_context.h" 54d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#include "r200_ioctl.h" 55d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#include "r200_span.h" 56c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "r200_tex.h" 57c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 58d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#include "r300_context.h" 59c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "r300_fragprog.h" 60c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "r300_tex.h" 61c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "radeon_span.h" 62d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#endif 63d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 64d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#include "utils.h" 65c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "vblank.h" 66c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "drirenderbuffer.h" 677dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch 68c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "GL/internal/dri_interface.h" 697dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch 70c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/* Radeon configuration 717dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch */ 72c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#include "xmlpool.h" 73c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 74c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#if !RADEON_COMMON /* R100 */ 75c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)PUBLIC const char __driConfigOptions[] = 76c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)DRI_CONF_BEGIN 77c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_PERFORMANCE 78c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 79eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 80c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 81eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 82c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_HYPERZ(false) 83c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 84c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_QUALITY 85c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 86c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 87c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_NO_NEG_LOD_BIAS(false) 88c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_FORCE_S3TC_ENABLE(false) 89c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 907dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 91c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 927dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch DRI_CONF_ALLOW_LARGE_TEXTURES(2) 93c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 947dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch DRI_CONF_SECTION_DEBUG 95c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_NO_RAST(false) 96c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 97c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)DRI_CONF_END; 98c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static const GLuint __driNConfigOptions = 14; 99c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 100c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 101c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 102c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)PUBLIC const char __driConfigOptions[] = 103c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)DRI_CONF_BEGIN 104c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_PERFORMANCE 105c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 106c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 107c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 108c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 109c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_HYPERZ(false) 110c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 111c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_QUALITY 112c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 113c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 114c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_NO_NEG_LOD_BIAS(false) 115c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_FORCE_S3TC_ENABLE(false) 116c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 117c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 118c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 119c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_ALLOW_LARGE_TEXTURES(2) 120c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 121c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 122c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_DEBUG 123c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_NO_RAST(false) 124c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 125c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_SOFTWARE 126c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_NV_VERTEX_PROGRAM(false) 127c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) DRI_CONF_SECTION_END 128c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)DRI_CONF_END; 129c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static const GLuint __driNConfigOptions = 16; 130c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 131c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)extern const struct dri_extension blend_extensions[]; 132c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)extern const struct dri_extension ARB_vp_extension[]; 133c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)extern const struct dri_extension NV_vp_extension[]; 134c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)extern const struct dri_extension ATI_fs_extension[]; 1355f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)extern const struct dri_extension point_extensions[]; 1365f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1375f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1385f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1395f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)/* TODO: integrate these into xmlpool.h! */ 1405f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 1415f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 1425f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DRI_CONF_DESC(en,"Number of texture image units") \ 1435f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 1445f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DRI_CONF_OPT_END 1455f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1465f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 1475f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 1485f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DRI_CONF_DESC(en,"Number of texture coordinate units") \ 1495f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 1505f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DRI_CONF_OPT_END 1515f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) 1525f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 1535f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 1545f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 1555f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles) DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 1565f1c94371a64b3196d4be9466099bb892df9b88eTorne (Richard Coles)DRI_CONF_OPT_END 157424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 158424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#define DRI_CONF_DISABLE_S3TC(def) \ 159424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 160424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DESC(en,"Disable S3TC compression") \ 161424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_END 162424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 163424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#define DRI_CONF_DISABLE_FALLBACK(def) \ 164424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 165424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 166424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_END 167424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 168424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 169424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 170424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 171424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_END 172424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 173424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#define DRI_CONF_FP_OPTIMIZATION(def) \ 174424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 175424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 176424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_ENUM(0,"Optimize for Speed") \ 177424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_ENUM(1,"Optimize for Quality") \ 178424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DESC_END \ 179424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_OPT_END 180424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 181424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)PUBLIC const char __driConfigOptions[] = 182424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_BEGIN 183424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_SECTION_PERFORMANCE 184424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 185424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 186424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 187424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 188424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 189424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 190424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DISABLE_FALLBACK(true) 191424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 192424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_SECTION_END 193424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_SECTION_QUALITY 194424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 195424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 196424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_FORCE_S3TC_ENABLE(false) 197424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DISABLE_S3TC(false) 198424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 199424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 200424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 201424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 202424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_SECTION_END 203424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_SECTION_DEBUG 204424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_NO_RAST(false) 205424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) DRI_CONF_SECTION_END 206424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)DRI_CONF_END; 207424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)static const GLuint __driNConfigOptions = 17; 208424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 209424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)extern const struct dri_extension gl_20_extension[]; 210424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles) 211424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)#ifndef RADEON_DEBUG 212424c4d7b64af9d0d8fd9624f381f469654d5e3d2Torne (Richard Coles)int RADEON_DEBUG = 0; 213c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 214c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static const struct dri_debug_control debug_control[] = { 215c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"fall", DEBUG_FALLBACKS}, 216c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"tex", DEBUG_TEXTURE}, 217c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"ioctl", DEBUG_IOCTL}, 218c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"prim", DEBUG_PRIMS}, 219c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"vert", DEBUG_VERTS}, 220c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"state", DEBUG_STATE}, 221c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"code", DEBUG_CODEGEN}, 2224e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) {"vfmt", DEBUG_VFMT}, 2234e180b6a0b4720a9b8e9e959a882386f690f08ffTorne (Richard Coles) {"vtxf", DEBUG_VFMT}, 224c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"verb", DEBUG_VERBOSE}, 225c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"dri", DEBUG_DRI}, 226c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"dma", DEBUG_DMA}, 227c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"san", DEBUG_SANITY}, 228c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"sync", DEBUG_SYNC}, 229eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch {"pix", DEBUG_PIXEL}, 230eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch {"mem", DEBUG_MEMORY}, 231c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 232eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch {NULL, 0} 233eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch}; 234c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#endif /* RADEON_DEBUG */ 235c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 236c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 237eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch 238c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)extern const struct dri_extension card_extensions[]; 239c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 240c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 241c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 242c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static int 243c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)radeonGetParam(int fd, int param, void *value) 244c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles){ 245c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int ret; 246c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) drm_radeon_getparam_t gp; 247c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 248c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) gp.param = param; 249c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) gp.value = value; 250c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 251c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 252c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return ret; 253c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)} 254c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 255c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static const __DRIconfig ** 256c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)radeonFillInModes( __DRIscreenPrivate *psp, 257c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned pixel_bits, unsigned depth_bits, 258c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned stencil_bits, GLboolean have_back_buffer ) 259c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles){ 260c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) __DRIconfig **configs; 261c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) __GLcontextModes *m; 262c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned depth_buffer_factor; 263c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned back_buffer_factor; 264c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) GLenum fb_format; 265c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) GLenum fb_type; 266c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int i; 267c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 268c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 269c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * enough to add support. Basically, if a context is created with an 270c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 271c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * will never be used. 272c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) */ 273c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) static const GLenum back_buffer_modes[] = { 274c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 275c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) }; 276c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 277c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) uint8_t depth_bits_array[2]; 278c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) uint8_t stencil_bits_array[2]; 279c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) uint8_t msaa_samples_array[1]; 280c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 281c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) depth_bits_array[0] = depth_bits; 282eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch depth_bits_array[1] = depth_bits; 283c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 284eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /* Just like with the accumulation buffer, always provide some modes 285eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch * with a stencil buffer. It will be a sw fallback, but some apps won't 286c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * care about that. 287c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) */ 288c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) stencil_bits_array[0] = 0; 289c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 290c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 291c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) msaa_samples_array[0] = 0; 292c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 293c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 294c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) back_buffer_factor = (have_back_buffer) ? 2 : 1; 295c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 296c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if ( pixel_bits == 16 ) { 297c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fb_format = GL_RGB; 298c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fb_type = GL_UNSIGNED_SHORT_5_6_5; 299c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 300c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) else { 301c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fb_format = GL_BGRA; 302c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 303c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 304c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 305c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) configs = driCreateConfigs(fb_format, fb_type, 306c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) depth_bits_array, stencil_bits_array, 307c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) depth_buffer_factor, 308c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) back_buffer_modes, back_buffer_factor, 309c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) msaa_samples_array, 1); 310c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (configs == NULL) { 311c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 312c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) __func__, __LINE__ ); 313c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return NULL; 314c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 315c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 316c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /* Mark the visual as slow if there are "fake" stencil bits. 317c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) */ 318c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) for (i = 0; configs[i]; i++) { 319c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) m = &configs[i]->modes; 3207dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 3217dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch m->visualRating = GLX_SLOW_CONFIG; 3227dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch } 323c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 3247dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch 3257dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch return (const __DRIconfig **) configs; 326d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)} 327d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 328c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#if !RADEON_COMMON 329c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static const __DRItexOffsetExtension radeonTexOffsetExtension = { 330c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 331c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) radeonSetTexOffset, 332d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)}; 333d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#endif 334d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 335d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 336d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)static const __DRIallocateExtension r200AllocateExtension = { 337d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 338d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) r200AllocateMemoryMESA, 339d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) r200FreeMemoryMESA, 340d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) r200GetMemoryOffsetMESA 341d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)}; 342d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 343d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)static const __DRItexOffsetExtension r200texOffsetExtension = { 344d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 345d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) r200SetTexOffset, 346d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)}; 347d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#endif 348c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 349c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 350c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static const __DRItexOffsetExtension r300texOffsetExtension = { 351c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 352c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) r300SetTexOffset, 353c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)}; 354c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#endif 355c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 356c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)/* Create the device specific screen private data struct. 357c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) */ 358c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)static radeonScreenPtr 359c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)radeonCreateScreen( __DRIscreenPrivate *sPriv ) 360c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles){ 361c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) radeonScreenPtr screen; 362c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 363c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) unsigned char *RADEONMMIO; 364c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int i; 365c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int ret; 366c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) uint32_t temp; 367c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 368c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 369c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 370c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return GL_FALSE; 371c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 372c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 373c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /* Allocate the private area */ 374c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 375c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if ( !screen ) { 376c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) __driUtilMessage("%s: Could not allocate memory for screen structure", 377c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) __FUNCTION__); 378c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return NULL; 379c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 380c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 381c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 382c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 383c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles)#endif 384c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 385c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /* parse information in __driConfigOptions */ 386c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) driParseOptionInfo (&screen->optionCache, 387c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) __driConfigOptions, __driNConfigOptions); 388c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 389c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) /* This is first since which regions we map depends on whether or 390c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) * not we are using a PCI card. 391c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) */ 392c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 393c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) { 394c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) int ret; 395c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 396c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) &screen->gart_buffer_offset); 397c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 398c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (ret) { 399c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) FREE( screen ); 400c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 401c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return NULL; 402c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 403c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 404c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 405c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) &screen->gart_base); 406c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (ret) { 407c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) FREE( screen ); 408c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 409c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return NULL; 410c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 411c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 412c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 413c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) &screen->irq); 414c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if (ret) { 415c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) FREE( screen ); 416c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 417c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return NULL; 418c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) } 419c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 420c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 421c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 422c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 423c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 424c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 425c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 426a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) } 427a3f6a49ab37290eeeb8db0f41ec0f1cb74a68be7Torne (Richard Coles) 428c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->mmio.handle = dri_priv->registerHandle; 429c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) screen->mmio.size = dri_priv->registerSize; 430c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) if ( drmMap( sPriv->fd, 431 screen->mmio.handle, 432 screen->mmio.size, 433 &screen->mmio.map ) ) { 434 FREE( screen ); 435 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 436 return NULL; 437 } 438 439 RADEONMMIO = screen->mmio.map; 440 441 screen->status.handle = dri_priv->statusHandle; 442 screen->status.size = dri_priv->statusSize; 443 if ( drmMap( sPriv->fd, 444 screen->status.handle, 445 screen->status.size, 446 &screen->status.map ) ) { 447 drmUnmap( screen->mmio.map, screen->mmio.size ); 448 FREE( screen ); 449 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 450 return NULL; 451 } 452 screen->scratch = (__volatile__ uint32_t *) 453 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 454 455 screen->buffers = drmMapBufs( sPriv->fd ); 456 if ( !screen->buffers ) { 457 drmUnmap( screen->status.map, screen->status.size ); 458 drmUnmap( screen->mmio.map, screen->mmio.size ); 459 FREE( screen ); 460 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 461 return NULL; 462 } 463 464 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 465 screen->gartTextures.handle = dri_priv->gartTexHandle; 466 screen->gartTextures.size = dri_priv->gartTexMapSize; 467 if ( drmMap( sPriv->fd, 468 screen->gartTextures.handle, 469 screen->gartTextures.size, 470 (drmAddressPtr)&screen->gartTextures.map ) ) { 471 drmUnmapBufs( screen->buffers ); 472 drmUnmap( screen->status.map, screen->status.size ); 473 drmUnmap( screen->mmio.map, screen->mmio.size ); 474 FREE( screen ); 475 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 476 return NULL; 477 } 478 479 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 480 } 481 482 screen->chip_flags = 0; 483 /* XXX: add more chipsets */ 484 switch ( dri_priv->deviceID ) { 485 case PCI_CHIP_RADEON_LY: 486 case PCI_CHIP_RADEON_LZ: 487 case PCI_CHIP_RADEON_QY: 488 case PCI_CHIP_RADEON_QZ: 489 case PCI_CHIP_RN50_515E: 490 case PCI_CHIP_RN50_5969: 491 screen->chip_family = CHIP_FAMILY_RV100; 492 break; 493 494 case PCI_CHIP_RS100_4136: 495 case PCI_CHIP_RS100_4336: 496 screen->chip_family = CHIP_FAMILY_RS100; 497 break; 498 499 case PCI_CHIP_RS200_4137: 500 case PCI_CHIP_RS200_4337: 501 case PCI_CHIP_RS250_4237: 502 case PCI_CHIP_RS250_4437: 503 screen->chip_family = CHIP_FAMILY_RS200; 504 break; 505 506 case PCI_CHIP_RADEON_QD: 507 case PCI_CHIP_RADEON_QE: 508 case PCI_CHIP_RADEON_QF: 509 case PCI_CHIP_RADEON_QG: 510 /* all original radeons (7200) presumably have a stencil op bug */ 511 screen->chip_family = CHIP_FAMILY_R100; 512 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 513 break; 514 515 case PCI_CHIP_RV200_QW: 516 case PCI_CHIP_RV200_QX: 517 case PCI_CHIP_RADEON_LW: 518 case PCI_CHIP_RADEON_LX: 519 screen->chip_family = CHIP_FAMILY_RV200; 520 screen->chip_flags = RADEON_CHIPSET_TCL; 521 break; 522 523 case PCI_CHIP_R200_BB: 524 case PCI_CHIP_R200_BC: 525 case PCI_CHIP_R200_QH: 526 case PCI_CHIP_R200_QL: 527 case PCI_CHIP_R200_QM: 528 screen->chip_family = CHIP_FAMILY_R200; 529 screen->chip_flags = RADEON_CHIPSET_TCL; 530 break; 531 532 case PCI_CHIP_RV250_If: 533 case PCI_CHIP_RV250_Ig: 534 case PCI_CHIP_RV250_Ld: 535 case PCI_CHIP_RV250_Lf: 536 case PCI_CHIP_RV250_Lg: 537 screen->chip_family = CHIP_FAMILY_RV250; 538 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 539 break; 540 541 case PCI_CHIP_RV280_5960: 542 case PCI_CHIP_RV280_5961: 543 case PCI_CHIP_RV280_5962: 544 case PCI_CHIP_RV280_5964: 545 case PCI_CHIP_RV280_5965: 546 case PCI_CHIP_RV280_5C61: 547 case PCI_CHIP_RV280_5C63: 548 screen->chip_family = CHIP_FAMILY_RV280; 549 screen->chip_flags = RADEON_CHIPSET_TCL; 550 break; 551 552 case PCI_CHIP_RS300_5834: 553 case PCI_CHIP_RS300_5835: 554 case PCI_CHIP_RS350_7834: 555 case PCI_CHIP_RS350_7835: 556 screen->chip_family = CHIP_FAMILY_RS300; 557 break; 558 559 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 560 case PCI_CHIP_R300_AD: 561 screen->chip_family = CHIP_FAMILY_RV350; 562 screen->chip_flags = RADEON_CHIPSET_TCL; 563 break; 564 case PCI_CHIP_R300_AE: 565 case PCI_CHIP_R300_AF: 566 case PCI_CHIP_R300_AG: 567 case PCI_CHIP_R300_ND: 568 case PCI_CHIP_R300_NE: 569 case PCI_CHIP_R300_NF: 570 case PCI_CHIP_R300_NG: 571 screen->chip_family = CHIP_FAMILY_R300; 572 screen->chip_flags = RADEON_CHIPSET_TCL; 573 break; 574 575 case PCI_CHIP_RV350_AP: 576 case PCI_CHIP_RV350_AQ: 577 case PCI_CHIP_RV350_AR: 578 case PCI_CHIP_RV350_AS: 579 case PCI_CHIP_RV350_AT: 580 case PCI_CHIP_RV350_AV: 581 case PCI_CHIP_RV350_AU: 582 case PCI_CHIP_RV350_NP: 583 case PCI_CHIP_RV350_NQ: 584 case PCI_CHIP_RV350_NR: 585 case PCI_CHIP_RV350_NS: 586 case PCI_CHIP_RV350_NT: 587 case PCI_CHIP_RV350_NV: 588 screen->chip_family = CHIP_FAMILY_RV350; 589 screen->chip_flags = RADEON_CHIPSET_TCL; 590 break; 591 592 case PCI_CHIP_R350_AH: 593 case PCI_CHIP_R350_AI: 594 case PCI_CHIP_R350_AJ: 595 case PCI_CHIP_R350_AK: 596 case PCI_CHIP_R350_NH: 597 case PCI_CHIP_R350_NI: 598 case PCI_CHIP_R360_NJ: 599 case PCI_CHIP_R350_NK: 600 screen->chip_family = CHIP_FAMILY_R350; 601 screen->chip_flags = RADEON_CHIPSET_TCL; 602 break; 603 604 case PCI_CHIP_RV370_5460: 605 case PCI_CHIP_RV370_5462: 606 case PCI_CHIP_RV370_5464: 607 case PCI_CHIP_RV370_5B60: 608 case PCI_CHIP_RV370_5B62: 609 case PCI_CHIP_RV370_5B63: 610 case PCI_CHIP_RV370_5B64: 611 case PCI_CHIP_RV370_5B65: 612 case PCI_CHIP_RV380_3150: 613 case PCI_CHIP_RV380_3152: 614 case PCI_CHIP_RV380_3154: 615 case PCI_CHIP_RV380_3E50: 616 case PCI_CHIP_RV380_3E54: 617 screen->chip_family = CHIP_FAMILY_RV380; 618 screen->chip_flags = RADEON_CHIPSET_TCL; 619 break; 620 621 case PCI_CHIP_R420_JN: 622 case PCI_CHIP_R420_JH: 623 case PCI_CHIP_R420_JI: 624 case PCI_CHIP_R420_JJ: 625 case PCI_CHIP_R420_JK: 626 case PCI_CHIP_R420_JL: 627 case PCI_CHIP_R420_JM: 628 case PCI_CHIP_R420_JO: 629 case PCI_CHIP_R420_JP: 630 case PCI_CHIP_R420_JT: 631 case PCI_CHIP_R481_4B49: 632 case PCI_CHIP_R481_4B4A: 633 case PCI_CHIP_R481_4B4B: 634 case PCI_CHIP_R481_4B4C: 635 case PCI_CHIP_R423_UH: 636 case PCI_CHIP_R423_UI: 637 case PCI_CHIP_R423_UJ: 638 case PCI_CHIP_R423_UK: 639 case PCI_CHIP_R430_554C: 640 case PCI_CHIP_R430_554D: 641 case PCI_CHIP_R430_554E: 642 case PCI_CHIP_R430_554F: 643 case PCI_CHIP_R423_5550: 644 case PCI_CHIP_R423_UQ: 645 case PCI_CHIP_R423_UR: 646 case PCI_CHIP_R423_UT: 647 case PCI_CHIP_R430_5D48: 648 case PCI_CHIP_R430_5D49: 649 case PCI_CHIP_R430_5D4A: 650 case PCI_CHIP_R480_5D4C: 651 case PCI_CHIP_R480_5D4D: 652 case PCI_CHIP_R480_5D4E: 653 case PCI_CHIP_R480_5D4F: 654 case PCI_CHIP_R480_5D50: 655 case PCI_CHIP_R480_5D52: 656 case PCI_CHIP_R423_5D57: 657 screen->chip_family = CHIP_FAMILY_R420; 658 screen->chip_flags = RADEON_CHIPSET_TCL; 659 break; 660 661 case PCI_CHIP_RV410_5E4C: 662 case PCI_CHIP_RV410_5E4F: 663 case PCI_CHIP_RV410_564A: 664 case PCI_CHIP_RV410_564B: 665 case PCI_CHIP_RV410_564F: 666 case PCI_CHIP_RV410_5652: 667 case PCI_CHIP_RV410_5653: 668 case PCI_CHIP_RV410_5657: 669 case PCI_CHIP_RV410_5E48: 670 case PCI_CHIP_RV410_5E4A: 671 case PCI_CHIP_RV410_5E4B: 672 case PCI_CHIP_RV410_5E4D: 673 screen->chip_family = CHIP_FAMILY_RV410; 674 screen->chip_flags = RADEON_CHIPSET_TCL; 675 break; 676 677 case PCI_CHIP_RS480_5954: 678 case PCI_CHIP_RS480_5955: 679 case PCI_CHIP_RS482_5974: 680 case PCI_CHIP_RS482_5975: 681 case PCI_CHIP_RS400_5A41: 682 case PCI_CHIP_RS400_5A42: 683 case PCI_CHIP_RC410_5A61: 684 case PCI_CHIP_RC410_5A62: 685 screen->chip_family = CHIP_FAMILY_RS400; 686 break; 687 688 case PCI_CHIP_RS690_791E: 689 case PCI_CHIP_RS690_791F: 690 screen->chip_family = CHIP_FAMILY_RS690; 691 break; 692 case PCI_CHIP_RS740_796C: 693 case PCI_CHIP_RS740_796D: 694 case PCI_CHIP_RS740_796E: 695 case PCI_CHIP_RS740_796F: 696 screen->chip_family = CHIP_FAMILY_RS740; 697 break; 698 699 case PCI_CHIP_R520_7100: 700 case PCI_CHIP_R520_7101: 701 case PCI_CHIP_R520_7102: 702 case PCI_CHIP_R520_7103: 703 case PCI_CHIP_R520_7104: 704 case PCI_CHIP_R520_7105: 705 case PCI_CHIP_R520_7106: 706 case PCI_CHIP_R520_7108: 707 case PCI_CHIP_R520_7109: 708 case PCI_CHIP_R520_710A: 709 case PCI_CHIP_R520_710B: 710 case PCI_CHIP_R520_710C: 711 case PCI_CHIP_R520_710E: 712 case PCI_CHIP_R520_710F: 713 screen->chip_family = CHIP_FAMILY_R520; 714 screen->chip_flags = RADEON_CHIPSET_TCL; 715 break; 716 717 case PCI_CHIP_RV515_7140: 718 case PCI_CHIP_RV515_7141: 719 case PCI_CHIP_RV515_7142: 720 case PCI_CHIP_RV515_7143: 721 case PCI_CHIP_RV515_7144: 722 case PCI_CHIP_RV515_7145: 723 case PCI_CHIP_RV515_7146: 724 case PCI_CHIP_RV515_7147: 725 case PCI_CHIP_RV515_7149: 726 case PCI_CHIP_RV515_714A: 727 case PCI_CHIP_RV515_714B: 728 case PCI_CHIP_RV515_714C: 729 case PCI_CHIP_RV515_714D: 730 case PCI_CHIP_RV515_714E: 731 case PCI_CHIP_RV515_714F: 732 case PCI_CHIP_RV515_7151: 733 case PCI_CHIP_RV515_7152: 734 case PCI_CHIP_RV515_7153: 735 case PCI_CHIP_RV515_715E: 736 case PCI_CHIP_RV515_715F: 737 case PCI_CHIP_RV515_7180: 738 case PCI_CHIP_RV515_7181: 739 case PCI_CHIP_RV515_7183: 740 case PCI_CHIP_RV515_7186: 741 case PCI_CHIP_RV515_7187: 742 case PCI_CHIP_RV515_7188: 743 case PCI_CHIP_RV515_718A: 744 case PCI_CHIP_RV515_718B: 745 case PCI_CHIP_RV515_718C: 746 case PCI_CHIP_RV515_718D: 747 case PCI_CHIP_RV515_718F: 748 case PCI_CHIP_RV515_7193: 749 case PCI_CHIP_RV515_7196: 750 case PCI_CHIP_RV515_719B: 751 case PCI_CHIP_RV515_719F: 752 case PCI_CHIP_RV515_7200: 753 case PCI_CHIP_RV515_7210: 754 case PCI_CHIP_RV515_7211: 755 screen->chip_family = CHIP_FAMILY_RV515; 756 screen->chip_flags = RADEON_CHIPSET_TCL; 757 break; 758 759 case PCI_CHIP_RV530_71C0: 760 case PCI_CHIP_RV530_71C1: 761 case PCI_CHIP_RV530_71C2: 762 case PCI_CHIP_RV530_71C3: 763 case PCI_CHIP_RV530_71C4: 764 case PCI_CHIP_RV530_71C5: 765 case PCI_CHIP_RV530_71C6: 766 case PCI_CHIP_RV530_71C7: 767 case PCI_CHIP_RV530_71CD: 768 case PCI_CHIP_RV530_71CE: 769 case PCI_CHIP_RV530_71D2: 770 case PCI_CHIP_RV530_71D4: 771 case PCI_CHIP_RV530_71D5: 772 case PCI_CHIP_RV530_71D6: 773 case PCI_CHIP_RV530_71DA: 774 case PCI_CHIP_RV530_71DE: 775 screen->chip_family = CHIP_FAMILY_RV530; 776 screen->chip_flags = RADEON_CHIPSET_TCL; 777 break; 778 779 case PCI_CHIP_R580_7240: 780 case PCI_CHIP_R580_7243: 781 case PCI_CHIP_R580_7244: 782 case PCI_CHIP_R580_7245: 783 case PCI_CHIP_R580_7246: 784 case PCI_CHIP_R580_7247: 785 case PCI_CHIP_R580_7248: 786 case PCI_CHIP_R580_7249: 787 case PCI_CHIP_R580_724A: 788 case PCI_CHIP_R580_724B: 789 case PCI_CHIP_R580_724C: 790 case PCI_CHIP_R580_724D: 791 case PCI_CHIP_R580_724E: 792 case PCI_CHIP_R580_724F: 793 case PCI_CHIP_R580_7284: 794 screen->chip_family = CHIP_FAMILY_R580; 795 screen->chip_flags = RADEON_CHIPSET_TCL; 796 break; 797 798 case PCI_CHIP_RV570_7280: 799 case PCI_CHIP_RV560_7281: 800 case PCI_CHIP_RV560_7283: 801 case PCI_CHIP_RV560_7287: 802 case PCI_CHIP_RV570_7288: 803 case PCI_CHIP_RV570_7289: 804 case PCI_CHIP_RV570_728B: 805 case PCI_CHIP_RV570_728C: 806 case PCI_CHIP_RV560_7290: 807 case PCI_CHIP_RV560_7291: 808 case PCI_CHIP_RV560_7293: 809 case PCI_CHIP_RV560_7297: 810 screen->chip_family = CHIP_FAMILY_RV560; 811 screen->chip_flags = RADEON_CHIPSET_TCL; 812 break; 813 814 default: 815 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 816 dri_priv->deviceID); 817 return NULL; 818 } 819 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 820 sPriv->ddx_version.minor < 2) { 821 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 822 return NULL; 823 } 824 825 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 826 fprintf(stderr, "R500 support requires a newer drm.\n"); 827 return NULL; 828 } 829 830 if (getenv("R300_NO_TCL")) 831 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 832 833 if (screen->chip_family <= CHIP_FAMILY_RS200) 834 screen->chip_flags |= RADEON_CLASS_R100; 835 else if (screen->chip_family <= CHIP_FAMILY_RV280) 836 screen->chip_flags |= RADEON_CLASS_R200; 837 else 838 screen->chip_flags |= RADEON_CLASS_R300; 839 840 screen->cpp = dri_priv->bpp / 8; 841 screen->AGPMode = dri_priv->AGPMode; 842 843 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 844 &temp); 845 if (ret) { 846 if (screen->chip_family < CHIP_FAMILY_RS690) 847 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 848 else { 849 FREE( screen ); 850 fprintf(stderr, "Unable to get fb location need newer drm\n"); 851 return NULL; 852 } 853 } else { 854 screen->fbLocation = (temp & 0xffff) << 16; 855 } 856 857 if (screen->chip_family >= CHIP_FAMILY_RV515) { 858 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 859 &temp); 860 if (ret) { 861 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 862 switch (screen->chip_family) { 863 case CHIP_FAMILY_R300: 864 case CHIP_FAMILY_R350: 865 screen->num_gb_pipes = 2; 866 break; 867 case CHIP_FAMILY_R420: 868 case CHIP_FAMILY_R520: 869 case CHIP_FAMILY_R580: 870 case CHIP_FAMILY_RV560: 871 case CHIP_FAMILY_RV570: 872 screen->num_gb_pipes = 4; 873 break; 874 case CHIP_FAMILY_RV350: 875 case CHIP_FAMILY_RV515: 876 case CHIP_FAMILY_RV530: 877 case CHIP_FAMILY_RV410: 878 default: 879 screen->num_gb_pipes = 1; 880 break; 881 } 882 } else { 883 screen->num_gb_pipes = temp; 884 } 885 } 886 887 if ( sPriv->drm_version.minor >= 10 ) { 888 drm_radeon_setparam_t sp; 889 890 sp.param = RADEON_SETPARAM_FB_LOCATION; 891 sp.value = screen->fbLocation; 892 893 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 894 &sp, sizeof( sp ) ); 895 } 896 897 screen->frontOffset = dri_priv->frontOffset; 898 screen->frontPitch = dri_priv->frontPitch; 899 screen->backOffset = dri_priv->backOffset; 900 screen->backPitch = dri_priv->backPitch; 901 screen->depthOffset = dri_priv->depthOffset; 902 screen->depthPitch = dri_priv->depthPitch; 903 904 /* Check if ddx has set up a surface reg to cover depth buffer */ 905 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 906 /* these chips don't use tiled z without hyperz. So always pretend 907 we have set up a surface which will cause linear reads/writes */ 908 (IS_R100_CLASS(screen) && 909 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 910 911 if ( dri_priv->textureSize == 0 ) { 912 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 913 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 914 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 915 dri_priv->log2GARTTexGran; 916 } else { 917 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 918 + screen->fbLocation; 919 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 920 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 921 dri_priv->log2TexGran; 922 } 923 924 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 925 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 926 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 927 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 928 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 929 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 930 } else { 931 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 932 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 933 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 934 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 935 dri_priv->log2GARTTexGran; 936 } 937 938 i = 0; 939 screen->extensions[i++] = &driCopySubBufferExtension.base; 940 screen->extensions[i++] = &driFrameTrackingExtension.base; 941 screen->extensions[i++] = &driReadDrawableExtension; 942 943 if ( screen->irq != 0 ) { 944 screen->extensions[i++] = &driSwapControlExtension.base; 945 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 946 } 947 948#if !RADEON_COMMON 949 screen->extensions[i++] = &radeonTexOffsetExtension.base; 950#endif 951 952#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 953 if (IS_R200_CLASS(screen)) 954 screen->extensions[i++] = &r200AllocateExtension.base; 955 956 screen->extensions[i++] = &r200texOffsetExtension.base; 957#endif 958 959#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 960 screen->extensions[i++] = &r300texOffsetExtension.base; 961#endif 962 963 screen->extensions[i++] = NULL; 964 sPriv->extensions = screen->extensions; 965 966 screen->driScreen = sPriv; 967 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 968 return screen; 969} 970 971/* Destroy the device specific screen private data struct. 972 */ 973static void 974radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 975{ 976 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 977 978 if (!screen) 979 return; 980 981 if ( screen->gartTextures.map ) { 982 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 983 } 984 drmUnmapBufs( screen->buffers ); 985 drmUnmap( screen->status.map, screen->status.size ); 986 drmUnmap( screen->mmio.map, screen->mmio.size ); 987 988 /* free all option information */ 989 driDestroyOptionInfo (&screen->optionCache); 990 991 FREE( screen ); 992 sPriv->private = NULL; 993} 994 995 996/* Initialize the driver specific screen private data. 997 */ 998static GLboolean 999radeonInitDriver( __DRIscreenPrivate *sPriv ) 1000{ 1001 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1002 if ( !sPriv->private ) { 1003 radeonDestroyScreen( sPriv ); 1004 return GL_FALSE; 1005 } 1006 1007 return GL_TRUE; 1008} 1009 1010 1011/** 1012 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1013 * 1014 * \todo This function (and its interface) will need to be updated to support 1015 * pbuffers. 1016 */ 1017static GLboolean 1018radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1019 __DRIdrawablePrivate *driDrawPriv, 1020 const __GLcontextModes *mesaVis, 1021 GLboolean isPixmap ) 1022{ 1023 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1024 1025 if (isPixmap) { 1026 return GL_FALSE; /* not implemented */ 1027 } 1028 else { 1029 const GLboolean swDepth = GL_FALSE; 1030 const GLboolean swAlpha = GL_FALSE; 1031 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1032 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1033 mesaVis->depthBits != 24; 1034 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1035 1036 /* front color renderbuffer */ 1037 { 1038 driRenderbuffer *frontRb 1039 = driNewRenderbuffer(GL_RGBA, 1040 driScrnPriv->pFB + screen->frontOffset, 1041 screen->cpp, 1042 screen->frontOffset, screen->frontPitch, 1043 driDrawPriv); 1044 radeonSetSpanFunctions(frontRb, mesaVis); 1045 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); 1046 } 1047 1048 /* back color renderbuffer */ 1049 if (mesaVis->doubleBufferMode) { 1050 driRenderbuffer *backRb 1051 = driNewRenderbuffer(GL_RGBA, 1052 driScrnPriv->pFB + screen->backOffset, 1053 screen->cpp, 1054 screen->backOffset, screen->backPitch, 1055 driDrawPriv); 1056 radeonSetSpanFunctions(backRb, mesaVis); 1057 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); 1058 } 1059 1060 /* depth renderbuffer */ 1061 if (mesaVis->depthBits == 16) { 1062 driRenderbuffer *depthRb 1063 = driNewRenderbuffer(GL_DEPTH_COMPONENT16, 1064 driScrnPriv->pFB + screen->depthOffset, 1065 screen->cpp, 1066 screen->depthOffset, screen->depthPitch, 1067 driDrawPriv); 1068 radeonSetSpanFunctions(depthRb, mesaVis); 1069 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 1070 depthRb->depthHasSurface = screen->depthHasSurface; 1071 } 1072 else if (mesaVis->depthBits == 24) { 1073 driRenderbuffer *depthRb 1074 = driNewRenderbuffer(GL_DEPTH_COMPONENT24, 1075 driScrnPriv->pFB + screen->depthOffset, 1076 screen->cpp, 1077 screen->depthOffset, screen->depthPitch, 1078 driDrawPriv); 1079 radeonSetSpanFunctions(depthRb, mesaVis); 1080 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 1081 depthRb->depthHasSurface = screen->depthHasSurface; 1082 } 1083 1084 /* stencil renderbuffer */ 1085 if (mesaVis->stencilBits > 0 && !swStencil) { 1086 driRenderbuffer *stencilRb 1087 = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, 1088 driScrnPriv->pFB + screen->depthOffset, 1089 screen->cpp, 1090 screen->depthOffset, screen->depthPitch, 1091 driDrawPriv); 1092 radeonSetSpanFunctions(stencilRb, mesaVis); 1093 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); 1094 stencilRb->depthHasSurface = screen->depthHasSurface; 1095 } 1096 1097 _mesa_add_soft_renderbuffers(fb, 1098 GL_FALSE, /* color */ 1099 swDepth, 1100 swStencil, 1101 swAccum, 1102 swAlpha, 1103 GL_FALSE /* aux */); 1104 driDrawPriv->driverPrivate = (void *) fb; 1105 1106 return (driDrawPriv->driverPrivate != NULL); 1107 } 1108} 1109 1110 1111static void 1112radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1113{ 1114 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1115} 1116 1117#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1118/** 1119 * Choose the appropriate CreateContext function based on the chipset. 1120 * Eventually, all drivers will go through this process. 1121 */ 1122static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1123 __DRIcontextPrivate * driContextPriv, 1124 void *sharedContextPriv) 1125{ 1126 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1127 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1128 1129 if (IS_R300_CLASS(screen)) 1130 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1131 return GL_FALSE; 1132} 1133 1134/** 1135 * Choose the appropriate DestroyContext function based on the chipset. 1136 */ 1137static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1138{ 1139 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1140 1141 if (IS_R300_CLASS(radeon->radeonScreen)) 1142 return r300DestroyContext(driContextPriv); 1143} 1144 1145 1146#endif 1147 1148 1149/** 1150 * This is the driver specific part of the createNewScreen entry point. 1151 * 1152 * \todo maybe fold this into intelInitDriver 1153 * 1154 * \return the __GLcontextModes supported by this driver 1155 */ 1156static const __DRIconfig ** 1157radeonInitScreen(__DRIscreenPrivate *psp) 1158{ 1159#if !RADEON_COMMON 1160 static const char *driver_name = "Radeon"; 1161 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1162 static const __DRIversion dri_expected = { 4, 0, 0 }; 1163 static const __DRIversion drm_expected = { 1, 6, 0 }; 1164#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1165 static const char *driver_name = "R200"; 1166 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1167 static const __DRIversion dri_expected = { 4, 0, 0 }; 1168 static const __DRIversion drm_expected = { 1, 6, 0 }; 1169#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1170 static const char *driver_name = "R300"; 1171 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1172 static const __DRIversion dri_expected = { 4, 0, 0 }; 1173 static const __DRIversion drm_expected = { 1, 24, 0 }; 1174#endif 1175 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1176 1177 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1178 &psp->dri_version, & dri_expected, 1179 &psp->ddx_version, & ddx_expected, 1180 &psp->drm_version, & drm_expected ) ) { 1181 return NULL; 1182 } 1183 1184 /* Calling driInitExtensions here, with a NULL context pointer, 1185 * does not actually enable the extensions. It just makes sure 1186 * that all the dispatch offsets for all the extensions that 1187 * *might* be enables are known. This is needed because the 1188 * dispatch offsets need to be known when _mesa_context_create 1189 * is called, but we can't enable the extensions until we have a 1190 * context pointer. 1191 * 1192 * Hello chicken. Hello egg. How are you two today? 1193 */ 1194 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1195#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1196 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1197 driInitSingleExtension( NULL, ARB_vp_extension ); 1198 driInitSingleExtension( NULL, NV_vp_extension ); 1199 driInitSingleExtension( NULL, ATI_fs_extension ); 1200 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1201#elif defined(RADEON_COMMON_FOR_R300) 1202 driInitSingleExtension( NULL, gl_20_extension ); 1203#endif 1204 1205 if (!radeonInitDriver(psp)) 1206 return NULL; 1207 1208 return radeonFillInModes( psp, 1209 dri_priv->bpp, 1210 (dri_priv->bpp == 16) ? 16 : 24, 1211 (dri_priv->bpp == 16) ? 0 : 8, 1212 (dri_priv->backOffset != dri_priv->depthOffset) ); 1213} 1214 1215 1216/** 1217 * Get information about previous buffer swaps. 1218 */ 1219static int 1220getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1221{ 1222#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1223 radeonContextPtr rmesa; 1224#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1225 r200ContextPtr rmesa; 1226#endif 1227 1228 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1229 || (dPriv->driContextPriv->driverPrivate == NULL) 1230 || (sInfo == NULL) ) { 1231 return -1; 1232 } 1233 1234 rmesa = dPriv->driContextPriv->driverPrivate; 1235 sInfo->swap_count = rmesa->swap_count; 1236 sInfo->swap_ust = rmesa->swap_ust; 1237 sInfo->swap_missed_count = rmesa->swap_missed_count; 1238 1239 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1240 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1241 : 0.0; 1242 1243 return 0; 1244} 1245 1246#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1247const struct __DriverAPIRec driDriverAPI = { 1248 .InitScreen = radeonInitScreen, 1249 .DestroyScreen = radeonDestroyScreen, 1250 .CreateContext = radeonCreateContext, 1251 .DestroyContext = radeonDestroyContext, 1252 .CreateBuffer = radeonCreateBuffer, 1253 .DestroyBuffer = radeonDestroyBuffer, 1254 .SwapBuffers = radeonSwapBuffers, 1255 .MakeCurrent = radeonMakeCurrent, 1256 .UnbindContext = radeonUnbindContext, 1257 .GetSwapInfo = getSwapInfo, 1258 .GetDrawableMSC = driDrawableGetMSC32, 1259 .WaitForMSC = driWaitForMSC32, 1260 .WaitForSBC = NULL, 1261 .SwapBuffersMSC = NULL, 1262 .CopySubBuffer = radeonCopySubBuffer, 1263}; 1264#else 1265const struct __DriverAPIRec driDriverAPI = { 1266 .InitScreen = radeonInitScreen, 1267 .DestroyScreen = radeonDestroyScreen, 1268 .CreateContext = r200CreateContext, 1269 .DestroyContext = r200DestroyContext, 1270 .CreateBuffer = radeonCreateBuffer, 1271 .DestroyBuffer = radeonDestroyBuffer, 1272 .SwapBuffers = r200SwapBuffers, 1273 .MakeCurrent = r200MakeCurrent, 1274 .UnbindContext = r200UnbindContext, 1275 .GetSwapInfo = getSwapInfo, 1276 .GetDrawableMSC = driDrawableGetMSC32, 1277 .WaitForMSC = driWaitForMSC32, 1278 .WaitForSBC = NULL, 1279 .SwapBuffersMSC = NULL, 1280 .CopySubBuffer = r200CopySubBuffer, 1281}; 1282#endif 1283