radeon_screen.c revision eb135fe8c16388cd33b424ee3915ae52d20cb3ff 
1/**************************************************************************
2
3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4                     VA Linux Systems Inc., Fremont, California.
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining
9a copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sublicense, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial
18portions of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author  Gareth Hughes <gareth@valinux.com>
36 */
37
38#include <errno.h>
39#include "main/glheader.h"
40#include "main/imports.h"
41#include "main/mtypes.h"
42#include "main/framebuffer.h"
43#include "main/renderbuffer.h"
44#include "main/fbobject.h"
45
46#define STANDALONE_MMIO
47#include "radeon_chipset.h"
48#include "radeon_macros.h"
49#include "radeon_screen.h"
50#include "radeon_common.h"
51#include "radeon_common_context.h"
52#if defined(RADEON_R100)
53#include "radeon_context.h"
54#include "radeon_tex.h"
55#elif defined(RADEON_R200)
56#include "r200_context.h"
57#include "r200_tex.h"
58#endif
59
60#include "utils.h"
61#include "vblank.h"
62
63#include "radeon_bocs_wrapper.h"
64
65#include "GL/internal/dri_interface.h"
66
67/* Radeon configuration
68 */
69#include "xmlpool.h"
70
71#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
72DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
73        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
74        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
75DRI_CONF_OPT_END
76
77#if defined(RADEON_R100)	/* R100 */
78PUBLIC const char __driConfigOptions[] =
79DRI_CONF_BEGIN
80    DRI_CONF_SECTION_PERFORMANCE
81        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
82        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
83        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
84        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
85        DRI_CONF_HYPERZ(false)
86        DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
87    DRI_CONF_SECTION_END
88    DRI_CONF_SECTION_QUALITY
89        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
90        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
91        DRI_CONF_NO_NEG_LOD_BIAS(false)
92        DRI_CONF_FORCE_S3TC_ENABLE(false)
93        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
94        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
95        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
96        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
97    DRI_CONF_SECTION_END
98    DRI_CONF_SECTION_DEBUG
99        DRI_CONF_NO_RAST(false)
100    DRI_CONF_SECTION_END
101DRI_CONF_END;
102static const GLuint __driNConfigOptions = 15;
103
104#elif defined(RADEON_R200)
105
106PUBLIC const char __driConfigOptions[] =
107DRI_CONF_BEGIN
108    DRI_CONF_SECTION_PERFORMANCE
109        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
110        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
111        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
112        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
113        DRI_CONF_HYPERZ(false)
114        DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
115    DRI_CONF_SECTION_END
116    DRI_CONF_SECTION_QUALITY
117        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
118        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
119        DRI_CONF_NO_NEG_LOD_BIAS(false)
120        DRI_CONF_FORCE_S3TC_ENABLE(false)
121        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
122        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
123        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
124        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
125        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
126    DRI_CONF_SECTION_END
127    DRI_CONF_SECTION_DEBUG
128        DRI_CONF_NO_RAST(false)
129    DRI_CONF_SECTION_END
130    DRI_CONF_SECTION_SOFTWARE
131        DRI_CONF_NV_VERTEX_PROGRAM(false)
132    DRI_CONF_SECTION_END
133DRI_CONF_END;
134static const GLuint __driNConfigOptions = 17;
135
136#endif
137
138#ifndef RADEON_INFO_TILE_CONFIG
139#define RADEON_INFO_TILE_CONFIG 0x6
140#endif
141
142static int
143radeonGetParam(__DRIscreen *sPriv, int param, void *value)
144{
145  int ret;
146  drm_radeon_getparam_t gp = { 0 };
147  struct drm_radeon_info info = { 0 };
148
149  if (sPriv->drm_version.major >= 2) {
150      info.value = (uint64_t)(uintptr_t)value;
151      switch (param) {
152      case RADEON_PARAM_DEVICE_ID:
153          info.request = RADEON_INFO_DEVICE_ID;
154          break;
155      case RADEON_PARAM_NUM_GB_PIPES:
156          info.request = RADEON_INFO_NUM_GB_PIPES;
157          break;
158      case RADEON_PARAM_NUM_Z_PIPES:
159          info.request = RADEON_INFO_NUM_Z_PIPES;
160          break;
161      case RADEON_INFO_TILE_CONFIG:
162	  info.request = RADEON_INFO_TILE_CONFIG;
163          break;
164      default:
165          return -EINVAL;
166      }
167      ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
168  } else {
169      gp.param = param;
170      gp.value = value;
171
172      ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
173  }
174  return ret;
175}
176
177#if defined(RADEON_R100)
178static const __DRItexBufferExtension radeonTexBufferExtension = {
179    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
180   radeonSetTexBuffer,
181   radeonSetTexBuffer2,
182};
183#endif
184
185#if defined(RADEON_R200)
186static const __DRItexBufferExtension r200TexBufferExtension = {
187    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
188   r200SetTexBuffer,
189   r200SetTexBuffer2,
190};
191#endif
192
193static void
194radeonDRI2Flush(__DRIdrawable *drawable)
195{
196    radeonContextPtr rmesa;
197
198    rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
199    radeonFlush(rmesa->glCtx);
200}
201
202static const struct __DRI2flushExtensionRec radeonFlushExtension = {
203    { __DRI2_FLUSH, __DRI2_FLUSH_VERSION },
204    radeonDRI2Flush,
205    dri2InvalidateDrawable,
206};
207
208static __DRIimage *
209radeon_create_image_from_name(__DRIscreen *screen,
210                              int width, int height, int format,
211                              int name, int pitch, void *loaderPrivate)
212{
213   __DRIimage *image;
214   radeonScreenPtr radeonScreen = screen->private;
215
216   if (name == 0)
217      return NULL;
218
219   image = CALLOC(sizeof *image);
220   if (image == NULL)
221      return NULL;
222
223   switch (format) {
224   case __DRI_IMAGE_FORMAT_RGB565:
225      image->format = MESA_FORMAT_RGB565;
226      image->internal_format = GL_RGB;
227      image->data_type = GL_UNSIGNED_BYTE;
228      break;
229   case __DRI_IMAGE_FORMAT_XRGB8888:
230      image->format = MESA_FORMAT_XRGB8888;
231      image->internal_format = GL_RGB;
232      image->data_type = GL_UNSIGNED_BYTE;
233      break;
234   case __DRI_IMAGE_FORMAT_ARGB8888:
235      image->format = MESA_FORMAT_ARGB8888;
236      image->internal_format = GL_RGBA;
237      image->data_type = GL_UNSIGNED_BYTE;
238      break;
239   default:
240      free(image);
241      return NULL;
242   }
243
244   image->data = loaderPrivate;
245   image->cpp = _mesa_get_format_bytes(image->format);
246   image->width = width;
247   image->pitch = pitch;
248   image->height = height;
249
250   image->bo = radeon_bo_open(radeonScreen->bom,
251                              (uint32_t)name,
252                              image->pitch * image->height * image->cpp,
253                              0,
254                              RADEON_GEM_DOMAIN_VRAM,
255                              0);
256
257   if (image->bo == NULL) {
258      FREE(image);
259      return NULL;
260   }
261
262   return image;
263}
264
265static __DRIimage *
266radeon_create_image_from_renderbuffer(__DRIcontext *context,
267                                      int renderbuffer, void *loaderPrivate)
268{
269   __DRIimage *image;
270   radeonContextPtr radeon = context->driverPrivate;
271   struct gl_renderbuffer *rb;
272   struct radeon_renderbuffer *rrb;
273
274   rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer);
275   if (!rb) {
276      _mesa_error(radeon->glCtx,
277                  GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
278      return NULL;
279   }
280
281   rrb = radeon_renderbuffer(rb);
282   image = CALLOC(sizeof *image);
283   if (image == NULL)
284      return NULL;
285
286   image->internal_format = rb->InternalFormat;
287   image->format = rb->Format;
288   image->cpp = rrb->cpp;
289   image->data_type = rb->DataType;
290   image->data = loaderPrivate;
291   radeon_bo_ref(rrb->bo);
292   image->bo = rrb->bo;
293
294   image->width = rb->Width;
295   image->height = rb->Height;
296   image->pitch = rrb->pitch / image->cpp;
297
298   return image;
299}
300
301static void
302radeon_destroy_image(__DRIimage *image)
303{
304   radeon_bo_unref(image->bo);
305   FREE(image);
306}
307
308static __DRIimage *
309radeon_create_image(__DRIscreen *screen,
310                    int width, int height, int format,
311                    unsigned int use,
312                    void *loaderPrivate)
313{
314   __DRIimage *image;
315   radeonScreenPtr radeonScreen = screen->private;
316
317   image = CALLOC(sizeof *image);
318   if (image == NULL)
319      return NULL;
320
321   switch (format) {
322   case __DRI_IMAGE_FORMAT_RGB565:
323      image->format = MESA_FORMAT_RGB565;
324      image->internal_format = GL_RGB;
325      image->data_type = GL_UNSIGNED_BYTE;
326      break;
327   case __DRI_IMAGE_FORMAT_XRGB8888:
328      image->format = MESA_FORMAT_XRGB8888;
329      image->internal_format = GL_RGB;
330      image->data_type = GL_UNSIGNED_BYTE;
331      break;
332   case __DRI_IMAGE_FORMAT_ARGB8888:
333      image->format = MESA_FORMAT_ARGB8888;
334      image->internal_format = GL_RGBA;
335      image->data_type = GL_UNSIGNED_BYTE;
336      break;
337   default:
338      free(image);
339      return NULL;
340   }
341
342   image->data = loaderPrivate;
343   image->cpp = _mesa_get_format_bytes(image->format);
344   image->width = width;
345   image->height = height;
346   image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
347
348   image->bo = radeon_bo_open(radeonScreen->bom,
349                              0,
350                              image->pitch * image->height * image->cpp,
351                              0,
352                              RADEON_GEM_DOMAIN_VRAM,
353                              0);
354
355   if (image->bo == NULL) {
356      FREE(image);
357      return NULL;
358   }
359
360   return image;
361}
362
363static GLboolean
364radeon_query_image(__DRIimage *image, int attrib, int *value)
365{
366   switch (attrib) {
367   case __DRI_IMAGE_ATTRIB_STRIDE:
368      *value = image->pitch * image->cpp;
369      return GL_TRUE;
370   case __DRI_IMAGE_ATTRIB_HANDLE:
371      *value = image->bo->handle;
372      return GL_TRUE;
373   case __DRI_IMAGE_ATTRIB_NAME:
374      radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
375      return GL_TRUE;
376   default:
377      return GL_FALSE;
378   }
379}
380
381static struct __DRIimageExtensionRec radeonImageExtension = {
382    { __DRI_IMAGE, __DRI_IMAGE_VERSION },
383   radeon_create_image_from_name,
384   radeon_create_image_from_renderbuffer,
385   radeon_destroy_image,
386   radeon_create_image,
387   radeon_query_image
388};
389
390static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
391{
392   screen->device_id = device_id;
393   screen->chip_flags = 0;
394   switch ( device_id ) {
395   case PCI_CHIP_RN50_515E:
396   case PCI_CHIP_RN50_5969:
397	return -1;
398
399   case PCI_CHIP_RADEON_LY:
400   case PCI_CHIP_RADEON_LZ:
401   case PCI_CHIP_RADEON_QY:
402   case PCI_CHIP_RADEON_QZ:
403      screen->chip_family = CHIP_FAMILY_RV100;
404      break;
405
406   case PCI_CHIP_RS100_4136:
407   case PCI_CHIP_RS100_4336:
408      screen->chip_family = CHIP_FAMILY_RS100;
409      break;
410
411   case PCI_CHIP_RS200_4137:
412   case PCI_CHIP_RS200_4337:
413   case PCI_CHIP_RS250_4237:
414   case PCI_CHIP_RS250_4437:
415      screen->chip_family = CHIP_FAMILY_RS200;
416      break;
417
418   case PCI_CHIP_RADEON_QD:
419   case PCI_CHIP_RADEON_QE:
420   case PCI_CHIP_RADEON_QF:
421   case PCI_CHIP_RADEON_QG:
422      /* all original radeons (7200) presumably have a stencil op bug */
423      screen->chip_family = CHIP_FAMILY_R100;
424      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
425      break;
426
427   case PCI_CHIP_RV200_QW:
428   case PCI_CHIP_RV200_QX:
429   case PCI_CHIP_RADEON_LW:
430   case PCI_CHIP_RADEON_LX:
431      screen->chip_family = CHIP_FAMILY_RV200;
432      screen->chip_flags = RADEON_CHIPSET_TCL;
433      break;
434
435   case PCI_CHIP_R200_BB:
436   case PCI_CHIP_R200_QH:
437   case PCI_CHIP_R200_QL:
438   case PCI_CHIP_R200_QM:
439      screen->chip_family = CHIP_FAMILY_R200;
440      screen->chip_flags = RADEON_CHIPSET_TCL;
441      break;
442
443   case PCI_CHIP_RV250_If:
444   case PCI_CHIP_RV250_Ig:
445   case PCI_CHIP_RV250_Ld:
446   case PCI_CHIP_RV250_Lf:
447   case PCI_CHIP_RV250_Lg:
448      screen->chip_family = CHIP_FAMILY_RV250;
449      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
450      break;
451
452   case PCI_CHIP_RV280_5960:
453   case PCI_CHIP_RV280_5961:
454   case PCI_CHIP_RV280_5962:
455   case PCI_CHIP_RV280_5964:
456   case PCI_CHIP_RV280_5965:
457   case PCI_CHIP_RV280_5C61:
458   case PCI_CHIP_RV280_5C63:
459      screen->chip_family = CHIP_FAMILY_RV280;
460      screen->chip_flags = RADEON_CHIPSET_TCL;
461      break;
462
463   case PCI_CHIP_RS300_5834:
464   case PCI_CHIP_RS300_5835:
465   case PCI_CHIP_RS350_7834:
466   case PCI_CHIP_RS350_7835:
467      screen->chip_family = CHIP_FAMILY_RS300;
468      break;
469
470   case PCI_CHIP_R300_AD:
471   case PCI_CHIP_R300_AE:
472   case PCI_CHIP_R300_AF:
473   case PCI_CHIP_R300_AG:
474   case PCI_CHIP_R300_ND:
475   case PCI_CHIP_R300_NE:
476   case PCI_CHIP_R300_NF:
477   case PCI_CHIP_R300_NG:
478      screen->chip_family = CHIP_FAMILY_R300;
479      screen->chip_flags = RADEON_CHIPSET_TCL;
480      break;
481
482   case PCI_CHIP_RV350_AP:
483   case PCI_CHIP_RV350_AQ:
484   case PCI_CHIP_RV350_AR:
485   case PCI_CHIP_RV350_AS:
486   case PCI_CHIP_RV350_AT:
487   case PCI_CHIP_RV350_AV:
488   case PCI_CHIP_RV350_AU:
489   case PCI_CHIP_RV350_NP:
490   case PCI_CHIP_RV350_NQ:
491   case PCI_CHIP_RV350_NR:
492   case PCI_CHIP_RV350_NS:
493   case PCI_CHIP_RV350_NT:
494   case PCI_CHIP_RV350_NV:
495      screen->chip_family = CHIP_FAMILY_RV350;
496      screen->chip_flags = RADEON_CHIPSET_TCL;
497      break;
498
499   case PCI_CHIP_R350_AH:
500   case PCI_CHIP_R350_AI:
501   case PCI_CHIP_R350_AJ:
502   case PCI_CHIP_R350_AK:
503   case PCI_CHIP_R350_NH:
504   case PCI_CHIP_R350_NI:
505   case PCI_CHIP_R360_NJ:
506   case PCI_CHIP_R350_NK:
507      screen->chip_family = CHIP_FAMILY_R350;
508      screen->chip_flags = RADEON_CHIPSET_TCL;
509      break;
510
511   case PCI_CHIP_RV370_5460:
512   case PCI_CHIP_RV370_5462:
513   case PCI_CHIP_RV370_5464:
514   case PCI_CHIP_RV370_5B60:
515   case PCI_CHIP_RV370_5B62:
516   case PCI_CHIP_RV370_5B63:
517   case PCI_CHIP_RV370_5B64:
518   case PCI_CHIP_RV370_5B65:
519   case PCI_CHIP_RV380_3150:
520   case PCI_CHIP_RV380_3152:
521   case PCI_CHIP_RV380_3154:
522   case PCI_CHIP_RV380_3155:
523   case PCI_CHIP_RV380_3E50:
524   case PCI_CHIP_RV380_3E54:
525      screen->chip_family = CHIP_FAMILY_RV380;
526      screen->chip_flags = RADEON_CHIPSET_TCL;
527      break;
528
529   case PCI_CHIP_R420_JN:
530   case PCI_CHIP_R420_JH:
531   case PCI_CHIP_R420_JI:
532   case PCI_CHIP_R420_JJ:
533   case PCI_CHIP_R420_JK:
534   case PCI_CHIP_R420_JL:
535   case PCI_CHIP_R420_JM:
536   case PCI_CHIP_R420_JO:
537   case PCI_CHIP_R420_JP:
538   case PCI_CHIP_R420_JT:
539   case PCI_CHIP_R481_4B49:
540   case PCI_CHIP_R481_4B4A:
541   case PCI_CHIP_R481_4B4B:
542   case PCI_CHIP_R481_4B4C:
543   case PCI_CHIP_R423_UH:
544   case PCI_CHIP_R423_UI:
545   case PCI_CHIP_R423_UJ:
546   case PCI_CHIP_R423_UK:
547   case PCI_CHIP_R430_554C:
548   case PCI_CHIP_R430_554D:
549   case PCI_CHIP_R430_554E:
550   case PCI_CHIP_R430_554F:
551   case PCI_CHIP_R423_5550:
552   case PCI_CHIP_R423_UQ:
553   case PCI_CHIP_R423_UR:
554   case PCI_CHIP_R423_UT:
555   case PCI_CHIP_R430_5D48:
556   case PCI_CHIP_R430_5D49:
557   case PCI_CHIP_R430_5D4A:
558   case PCI_CHIP_R480_5D4C:
559   case PCI_CHIP_R480_5D4D:
560   case PCI_CHIP_R480_5D4E:
561   case PCI_CHIP_R480_5D4F:
562   case PCI_CHIP_R480_5D50:
563   case PCI_CHIP_R480_5D52:
564   case PCI_CHIP_R423_5D57:
565      screen->chip_family = CHIP_FAMILY_R420;
566      screen->chip_flags = RADEON_CHIPSET_TCL;
567      break;
568
569   case PCI_CHIP_RV410_5E4C:
570   case PCI_CHIP_RV410_5E4F:
571   case PCI_CHIP_RV410_564A:
572   case PCI_CHIP_RV410_564B:
573   case PCI_CHIP_RV410_564F:
574   case PCI_CHIP_RV410_5652:
575   case PCI_CHIP_RV410_5653:
576   case PCI_CHIP_RV410_5657:
577   case PCI_CHIP_RV410_5E48:
578   case PCI_CHIP_RV410_5E4A:
579   case PCI_CHIP_RV410_5E4B:
580   case PCI_CHIP_RV410_5E4D:
581      screen->chip_family = CHIP_FAMILY_RV410;
582      screen->chip_flags = RADEON_CHIPSET_TCL;
583      break;
584
585   case PCI_CHIP_RS480_5954:
586   case PCI_CHIP_RS480_5955:
587   case PCI_CHIP_RS482_5974:
588   case PCI_CHIP_RS482_5975:
589   case PCI_CHIP_RS400_5A41:
590   case PCI_CHIP_RS400_5A42:
591   case PCI_CHIP_RC410_5A61:
592   case PCI_CHIP_RC410_5A62:
593      screen->chip_family = CHIP_FAMILY_RS400;
594      break;
595
596   case PCI_CHIP_RS600_793F:
597   case PCI_CHIP_RS600_7941:
598   case PCI_CHIP_RS600_7942:
599      screen->chip_family = CHIP_FAMILY_RS600;
600      break;
601
602   case PCI_CHIP_RS690_791E:
603   case PCI_CHIP_RS690_791F:
604      screen->chip_family = CHIP_FAMILY_RS690;
605      break;
606   case PCI_CHIP_RS740_796C:
607   case PCI_CHIP_RS740_796D:
608   case PCI_CHIP_RS740_796E:
609   case PCI_CHIP_RS740_796F:
610      screen->chip_family = CHIP_FAMILY_RS740;
611      break;
612
613   case PCI_CHIP_R520_7100:
614   case PCI_CHIP_R520_7101:
615   case PCI_CHIP_R520_7102:
616   case PCI_CHIP_R520_7103:
617   case PCI_CHIP_R520_7104:
618   case PCI_CHIP_R520_7105:
619   case PCI_CHIP_R520_7106:
620   case PCI_CHIP_R520_7108:
621   case PCI_CHIP_R520_7109:
622   case PCI_CHIP_R520_710A:
623   case PCI_CHIP_R520_710B:
624   case PCI_CHIP_R520_710C:
625   case PCI_CHIP_R520_710E:
626   case PCI_CHIP_R520_710F:
627      screen->chip_family = CHIP_FAMILY_R520;
628      screen->chip_flags = RADEON_CHIPSET_TCL;
629      break;
630
631   case PCI_CHIP_RV515_7140:
632   case PCI_CHIP_RV515_7141:
633   case PCI_CHIP_RV515_7142:
634   case PCI_CHIP_RV515_7143:
635   case PCI_CHIP_RV515_7144:
636   case PCI_CHIP_RV515_7145:
637   case PCI_CHIP_RV515_7146:
638   case PCI_CHIP_RV515_7147:
639   case PCI_CHIP_RV515_7149:
640   case PCI_CHIP_RV515_714A:
641   case PCI_CHIP_RV515_714B:
642   case PCI_CHIP_RV515_714C:
643   case PCI_CHIP_RV515_714D:
644   case PCI_CHIP_RV515_714E:
645   case PCI_CHIP_RV515_714F:
646   case PCI_CHIP_RV515_7151:
647   case PCI_CHIP_RV515_7152:
648   case PCI_CHIP_RV515_7153:
649   case PCI_CHIP_RV515_715E:
650   case PCI_CHIP_RV515_715F:
651   case PCI_CHIP_RV515_7180:
652   case PCI_CHIP_RV515_7181:
653   case PCI_CHIP_RV515_7183:
654   case PCI_CHIP_RV515_7186:
655   case PCI_CHIP_RV515_7187:
656   case PCI_CHIP_RV515_7188:
657   case PCI_CHIP_RV515_718A:
658   case PCI_CHIP_RV515_718B:
659   case PCI_CHIP_RV515_718C:
660   case PCI_CHIP_RV515_718D:
661   case PCI_CHIP_RV515_718F:
662   case PCI_CHIP_RV515_7193:
663   case PCI_CHIP_RV515_7196:
664   case PCI_CHIP_RV515_719B:
665   case PCI_CHIP_RV515_719F:
666   case PCI_CHIP_RV515_7200:
667   case PCI_CHIP_RV515_7210:
668   case PCI_CHIP_RV515_7211:
669      screen->chip_family = CHIP_FAMILY_RV515;
670      screen->chip_flags = RADEON_CHIPSET_TCL;
671      break;
672
673   case PCI_CHIP_RV530_71C0:
674   case PCI_CHIP_RV530_71C1:
675   case PCI_CHIP_RV530_71C2:
676   case PCI_CHIP_RV530_71C3:
677   case PCI_CHIP_RV530_71C4:
678   case PCI_CHIP_RV530_71C5:
679   case PCI_CHIP_RV530_71C6:
680   case PCI_CHIP_RV530_71C7:
681   case PCI_CHIP_RV530_71CD:
682   case PCI_CHIP_RV530_71CE:
683   case PCI_CHIP_RV530_71D2:
684   case PCI_CHIP_RV530_71D4:
685   case PCI_CHIP_RV530_71D5:
686   case PCI_CHIP_RV530_71D6:
687   case PCI_CHIP_RV530_71DA:
688   case PCI_CHIP_RV530_71DE:
689      screen->chip_family = CHIP_FAMILY_RV530;
690      screen->chip_flags = RADEON_CHIPSET_TCL;
691      break;
692
693   case PCI_CHIP_R580_7240:
694   case PCI_CHIP_R580_7243:
695   case PCI_CHIP_R580_7244:
696   case PCI_CHIP_R580_7245:
697   case PCI_CHIP_R580_7246:
698   case PCI_CHIP_R580_7247:
699   case PCI_CHIP_R580_7248:
700   case PCI_CHIP_R580_7249:
701   case PCI_CHIP_R580_724A:
702   case PCI_CHIP_R580_724B:
703   case PCI_CHIP_R580_724C:
704   case PCI_CHIP_R580_724D:
705   case PCI_CHIP_R580_724E:
706   case PCI_CHIP_R580_724F:
707   case PCI_CHIP_R580_7284:
708      screen->chip_family = CHIP_FAMILY_R580;
709      screen->chip_flags = RADEON_CHIPSET_TCL;
710      break;
711
712   case PCI_CHIP_RV570_7280:
713   case PCI_CHIP_RV560_7281:
714   case PCI_CHIP_RV560_7283:
715   case PCI_CHIP_RV560_7287:
716   case PCI_CHIP_RV570_7288:
717   case PCI_CHIP_RV570_7289:
718   case PCI_CHIP_RV570_728B:
719   case PCI_CHIP_RV570_728C:
720   case PCI_CHIP_RV560_7290:
721   case PCI_CHIP_RV560_7291:
722   case PCI_CHIP_RV560_7293:
723   case PCI_CHIP_RV560_7297:
724      screen->chip_family = CHIP_FAMILY_RV560;
725      screen->chip_flags = RADEON_CHIPSET_TCL;
726      break;
727
728   case PCI_CHIP_R600_9400:
729   case PCI_CHIP_R600_9401:
730   case PCI_CHIP_R600_9402:
731   case PCI_CHIP_R600_9403:
732   case PCI_CHIP_R600_9405:
733   case PCI_CHIP_R600_940A:
734   case PCI_CHIP_R600_940B:
735   case PCI_CHIP_R600_940F:
736      screen->chip_family = CHIP_FAMILY_R600;
737      screen->chip_flags = RADEON_CHIPSET_TCL;
738      break;
739
740   case PCI_CHIP_RV610_94C0:
741   case PCI_CHIP_RV610_94C1:
742   case PCI_CHIP_RV610_94C3:
743   case PCI_CHIP_RV610_94C4:
744   case PCI_CHIP_RV610_94C5:
745   case PCI_CHIP_RV610_94C6:
746   case PCI_CHIP_RV610_94C7:
747   case PCI_CHIP_RV610_94C8:
748   case PCI_CHIP_RV610_94C9:
749   case PCI_CHIP_RV610_94CB:
750   case PCI_CHIP_RV610_94CC:
751   case PCI_CHIP_RV610_94CD:
752      screen->chip_family = CHIP_FAMILY_RV610;
753      screen->chip_flags = RADEON_CHIPSET_TCL;
754      break;
755
756   case PCI_CHIP_RV630_9580:
757   case PCI_CHIP_RV630_9581:
758   case PCI_CHIP_RV630_9583:
759   case PCI_CHIP_RV630_9586:
760   case PCI_CHIP_RV630_9587:
761   case PCI_CHIP_RV630_9588:
762   case PCI_CHIP_RV630_9589:
763   case PCI_CHIP_RV630_958A:
764   case PCI_CHIP_RV630_958B:
765   case PCI_CHIP_RV630_958C:
766   case PCI_CHIP_RV630_958D:
767   case PCI_CHIP_RV630_958E:
768   case PCI_CHIP_RV630_958F:
769      screen->chip_family = CHIP_FAMILY_RV630;
770      screen->chip_flags = RADEON_CHIPSET_TCL;
771      break;
772
773   case PCI_CHIP_RV670_9500:
774   case PCI_CHIP_RV670_9501:
775   case PCI_CHIP_RV670_9504:
776   case PCI_CHIP_RV670_9505:
777   case PCI_CHIP_RV670_9506:
778   case PCI_CHIP_RV670_9507:
779   case PCI_CHIP_RV670_9508:
780   case PCI_CHIP_RV670_9509:
781   case PCI_CHIP_RV670_950F:
782   case PCI_CHIP_RV670_9511:
783   case PCI_CHIP_RV670_9515:
784   case PCI_CHIP_RV670_9517:
785   case PCI_CHIP_RV670_9519:
786      screen->chip_family = CHIP_FAMILY_RV670;
787      screen->chip_flags = RADEON_CHIPSET_TCL;
788      break;
789
790   case PCI_CHIP_RV620_95C0:
791   case PCI_CHIP_RV620_95C2:
792   case PCI_CHIP_RV620_95C4:
793   case PCI_CHIP_RV620_95C5:
794   case PCI_CHIP_RV620_95C6:
795   case PCI_CHIP_RV620_95C7:
796   case PCI_CHIP_RV620_95C9:
797   case PCI_CHIP_RV620_95CC:
798   case PCI_CHIP_RV620_95CD:
799   case PCI_CHIP_RV620_95CE:
800   case PCI_CHIP_RV620_95CF:
801      screen->chip_family = CHIP_FAMILY_RV620;
802      screen->chip_flags = RADEON_CHIPSET_TCL;
803      break;
804
805   case PCI_CHIP_RV635_9590:
806   case PCI_CHIP_RV635_9591:
807   case PCI_CHIP_RV635_9593:
808   case PCI_CHIP_RV635_9595:
809   case PCI_CHIP_RV635_9596:
810   case PCI_CHIP_RV635_9597:
811   case PCI_CHIP_RV635_9598:
812   case PCI_CHIP_RV635_9599:
813   case PCI_CHIP_RV635_959B:
814      screen->chip_family = CHIP_FAMILY_RV635;
815      screen->chip_flags = RADEON_CHIPSET_TCL;
816      break;
817
818   case PCI_CHIP_RS780_9610:
819   case PCI_CHIP_RS780_9611:
820   case PCI_CHIP_RS780_9612:
821   case PCI_CHIP_RS780_9613:
822   case PCI_CHIP_RS780_9614:
823   case PCI_CHIP_RS780_9615:
824   case PCI_CHIP_RS780_9616:
825      screen->chip_family = CHIP_FAMILY_RS780;
826      screen->chip_flags = RADEON_CHIPSET_TCL;
827      break;
828   case PCI_CHIP_RS880_9710:
829   case PCI_CHIP_RS880_9711:
830   case PCI_CHIP_RS880_9712:
831   case PCI_CHIP_RS880_9713:
832   case PCI_CHIP_RS880_9714:
833   case PCI_CHIP_RS880_9715:
834      screen->chip_family = CHIP_FAMILY_RS880;
835      screen->chip_flags = RADEON_CHIPSET_TCL;
836      break;
837
838   case PCI_CHIP_RV770_9440:
839   case PCI_CHIP_RV770_9441:
840   case PCI_CHIP_RV770_9442:
841   case PCI_CHIP_RV770_9443:
842   case PCI_CHIP_RV770_9444:
843   case PCI_CHIP_RV770_9446:
844   case PCI_CHIP_RV770_944A:
845   case PCI_CHIP_RV770_944B:
846   case PCI_CHIP_RV770_944C:
847   case PCI_CHIP_RV770_944E:
848   case PCI_CHIP_RV770_9450:
849   case PCI_CHIP_RV770_9452:
850   case PCI_CHIP_RV770_9456:
851   case PCI_CHIP_RV770_945A:
852   case PCI_CHIP_RV770_945B:
853   case PCI_CHIP_RV770_945E:
854   case PCI_CHIP_RV790_9460:
855   case PCI_CHIP_RV790_9462:
856   case PCI_CHIP_RV770_946A:
857   case PCI_CHIP_RV770_946B:
858   case PCI_CHIP_RV770_947A:
859   case PCI_CHIP_RV770_947B:
860      screen->chip_family = CHIP_FAMILY_RV770;
861      screen->chip_flags = RADEON_CHIPSET_TCL;
862      break;
863
864   case PCI_CHIP_RV730_9480:
865   case PCI_CHIP_RV730_9487:
866   case PCI_CHIP_RV730_9488:
867   case PCI_CHIP_RV730_9489:
868   case PCI_CHIP_RV730_948A:
869   case PCI_CHIP_RV730_948F:
870   case PCI_CHIP_RV730_9490:
871   case PCI_CHIP_RV730_9491:
872   case PCI_CHIP_RV730_9495:
873   case PCI_CHIP_RV730_9498:
874   case PCI_CHIP_RV730_949C:
875   case PCI_CHIP_RV730_949E:
876   case PCI_CHIP_RV730_949F:
877      screen->chip_family = CHIP_FAMILY_RV730;
878      screen->chip_flags = RADEON_CHIPSET_TCL;
879      break;
880
881   case PCI_CHIP_RV710_9540:
882   case PCI_CHIP_RV710_9541:
883   case PCI_CHIP_RV710_9542:
884   case PCI_CHIP_RV710_954E:
885   case PCI_CHIP_RV710_954F:
886   case PCI_CHIP_RV710_9552:
887   case PCI_CHIP_RV710_9553:
888   case PCI_CHIP_RV710_9555:
889   case PCI_CHIP_RV710_9557:
890   case PCI_CHIP_RV710_955F:
891      screen->chip_family = CHIP_FAMILY_RV710;
892      screen->chip_flags = RADEON_CHIPSET_TCL;
893      break;
894
895   case PCI_CHIP_RV740_94A0:
896   case PCI_CHIP_RV740_94A1:
897   case PCI_CHIP_RV740_94A3:
898   case PCI_CHIP_RV740_94B1:
899   case PCI_CHIP_RV740_94B3:
900   case PCI_CHIP_RV740_94B4:
901   case PCI_CHIP_RV740_94B5:
902   case PCI_CHIP_RV740_94B9:
903      screen->chip_family = CHIP_FAMILY_RV740;
904      screen->chip_flags = RADEON_CHIPSET_TCL;
905      break;
906
907    case PCI_CHIP_CEDAR_68E0:
908    case PCI_CHIP_CEDAR_68E1:
909    case PCI_CHIP_CEDAR_68E4:
910    case PCI_CHIP_CEDAR_68E5:
911    case PCI_CHIP_CEDAR_68E8:
912    case PCI_CHIP_CEDAR_68E9:
913    case PCI_CHIP_CEDAR_68F1:
914    case PCI_CHIP_CEDAR_68F2:
915    case PCI_CHIP_CEDAR_68F8:
916    case PCI_CHIP_CEDAR_68F9:
917    case PCI_CHIP_CEDAR_68FE:
918       screen->chip_family = CHIP_FAMILY_CEDAR;
919       screen->chip_flags = RADEON_CHIPSET_TCL;
920       break;
921
922    case PCI_CHIP_REDWOOD_68C0:
923    case PCI_CHIP_REDWOOD_68C1:
924    case PCI_CHIP_REDWOOD_68C8:
925    case PCI_CHIP_REDWOOD_68C9:
926    case PCI_CHIP_REDWOOD_68D8:
927    case PCI_CHIP_REDWOOD_68D9:
928    case PCI_CHIP_REDWOOD_68DA:
929    case PCI_CHIP_REDWOOD_68DE:
930       screen->chip_family = CHIP_FAMILY_REDWOOD;
931       screen->chip_flags = RADEON_CHIPSET_TCL;
932       break;
933
934    case PCI_CHIP_JUNIPER_68A0:
935    case PCI_CHIP_JUNIPER_68A1:
936    case PCI_CHIP_JUNIPER_68A8:
937    case PCI_CHIP_JUNIPER_68A9:
938    case PCI_CHIP_JUNIPER_68B0:
939    case PCI_CHIP_JUNIPER_68B8:
940    case PCI_CHIP_JUNIPER_68B9:
941    case PCI_CHIP_JUNIPER_68BA:
942    case PCI_CHIP_JUNIPER_68BE:
943    case PCI_CHIP_JUNIPER_68BF:
944       screen->chip_family = CHIP_FAMILY_JUNIPER;
945       screen->chip_flags = RADEON_CHIPSET_TCL;
946       break;
947
948    case PCI_CHIP_CYPRESS_6880:
949    case PCI_CHIP_CYPRESS_6888:
950    case PCI_CHIP_CYPRESS_6889:
951    case PCI_CHIP_CYPRESS_688A:
952    case PCI_CHIP_CYPRESS_6898:
953    case PCI_CHIP_CYPRESS_6899:
954    case PCI_CHIP_CYPRESS_689B:
955    case PCI_CHIP_CYPRESS_689E:
956       screen->chip_family = CHIP_FAMILY_CYPRESS;
957       screen->chip_flags = RADEON_CHIPSET_TCL;
958       break;
959
960    case PCI_CHIP_HEMLOCK_689C:
961    case PCI_CHIP_HEMLOCK_689D:
962       screen->chip_family = CHIP_FAMILY_HEMLOCK;
963       screen->chip_flags = RADEON_CHIPSET_TCL;
964       break;
965
966    case PCI_CHIP_PALM_9802:
967    case PCI_CHIP_PALM_9803:
968    case PCI_CHIP_PALM_9804:
969    case PCI_CHIP_PALM_9805:
970    case PCI_CHIP_PALM_9806:
971    case PCI_CHIP_PALM_9807:
972       screen->chip_family = CHIP_FAMILY_PALM;
973       screen->chip_flags = RADEON_CHIPSET_TCL;
974       break;
975
976    case PCI_CHIP_SUMO_9640:
977    case PCI_CHIP_SUMO_9641:
978    case PCI_CHIP_SUMO_9647:
979    case PCI_CHIP_SUMO_9648:
980    case PCI_CHIP_SUMO_964A:
981    case PCI_CHIP_SUMO_964E:
982    case PCI_CHIP_SUMO_964F:
983       screen->chip_family = CHIP_FAMILY_SUMO;
984       screen->chip_flags = RADEON_CHIPSET_TCL;
985       break;
986
987    case PCI_CHIP_SUMO2_9642:
988    case PCI_CHIP_SUMO2_9643:
989    case PCI_CHIP_SUMO2_9644:
990    case PCI_CHIP_SUMO2_9645:
991       screen->chip_family = CHIP_FAMILY_SUMO2;
992       screen->chip_flags = RADEON_CHIPSET_TCL;
993       break;
994
995   case PCI_CHIP_BARTS_6720:
996   case PCI_CHIP_BARTS_6721:
997   case PCI_CHIP_BARTS_6722:
998   case PCI_CHIP_BARTS_6723:
999   case PCI_CHIP_BARTS_6724:
1000   case PCI_CHIP_BARTS_6725:
1001   case PCI_CHIP_BARTS_6726:
1002   case PCI_CHIP_BARTS_6727:
1003   case PCI_CHIP_BARTS_6728:
1004   case PCI_CHIP_BARTS_6729:
1005   case PCI_CHIP_BARTS_6738:
1006   case PCI_CHIP_BARTS_6739:
1007   case PCI_CHIP_BARTS_673E:
1008       screen->chip_family = CHIP_FAMILY_BARTS;
1009       screen->chip_flags = RADEON_CHIPSET_TCL;
1010       break;
1011
1012   case PCI_CHIP_TURKS_6740:
1013   case PCI_CHIP_TURKS_6741:
1014   case PCI_CHIP_TURKS_6742:
1015   case PCI_CHIP_TURKS_6743:
1016   case PCI_CHIP_TURKS_6744:
1017   case PCI_CHIP_TURKS_6745:
1018   case PCI_CHIP_TURKS_6746:
1019   case PCI_CHIP_TURKS_6747:
1020   case PCI_CHIP_TURKS_6748:
1021   case PCI_CHIP_TURKS_6749:
1022   case PCI_CHIP_TURKS_6750:
1023   case PCI_CHIP_TURKS_6758:
1024   case PCI_CHIP_TURKS_6759:
1025   case PCI_CHIP_TURKS_675F:
1026       screen->chip_family = CHIP_FAMILY_TURKS;
1027       screen->chip_flags = RADEON_CHIPSET_TCL;
1028       break;
1029
1030   case PCI_CHIP_CAICOS_6760:
1031   case PCI_CHIP_CAICOS_6761:
1032   case PCI_CHIP_CAICOS_6762:
1033   case PCI_CHIP_CAICOS_6763:
1034   case PCI_CHIP_CAICOS_6764:
1035   case PCI_CHIP_CAICOS_6765:
1036   case PCI_CHIP_CAICOS_6766:
1037   case PCI_CHIP_CAICOS_6767:
1038   case PCI_CHIP_CAICOS_6768:
1039   case PCI_CHIP_CAICOS_6770:
1040   case PCI_CHIP_CAICOS_6778:
1041   case PCI_CHIP_CAICOS_6779:
1042       screen->chip_family = CHIP_FAMILY_CAICOS;
1043       screen->chip_flags = RADEON_CHIPSET_TCL;
1044       break;
1045
1046   default:
1047      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
1048	      device_id);
1049      return -1;
1050   }
1051
1052   return 0;
1053}
1054
1055static radeonScreenPtr
1056radeonCreateScreen2(__DRIscreen *sPriv)
1057{
1058   radeonScreenPtr screen;
1059   int i;
1060   int ret;
1061   uint32_t device_id = 0;
1062   uint32_t temp = 0;
1063
1064   /* Allocate the private area */
1065   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1066   if ( !screen ) {
1067      __driUtilMessage("%s: Could not allocate memory for screen structure",
1068		       __FUNCTION__);
1069      fprintf(stderr, "leaving here\n");
1070      return NULL;
1071   }
1072
1073   radeon_init_debug();
1074
1075   /* parse information in __driConfigOptions */
1076   driParseOptionInfo (&screen->optionCache,
1077		       __driConfigOptions, __driNConfigOptions);
1078
1079   screen->chip_flags = 0;
1080
1081   /* if we have kms we can support all of these */
1082   screen->drmSupportsCubeMapsR200 = 1;
1083   screen->drmSupportsBlendColor = 1;
1084   screen->drmSupportsTriPerf = 1;
1085   screen->drmSupportsFragShader = 1;
1086   screen->drmSupportsPointSprites = 1;
1087   screen->drmSupportsCubeMapsR100 = 1;
1088   screen->drmSupportsVertexProgram = 1;
1089   screen->drmSupportsOcclusionQueries = 1;
1090   screen->irq = 1;
1091
1092   ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1093   if (ret) {
1094     FREE( screen );
1095     fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1096     return NULL;
1097   }
1098
1099   ret = radeon_set_screen_flags(screen, device_id);
1100   if (ret == -1)
1101     return NULL;
1102
1103   if (getenv("R300_NO_TCL"))
1104	   screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1105
1106   if (screen->chip_family <= CHIP_FAMILY_RS200)
1107	   screen->chip_flags |= RADEON_CLASS_R100;
1108   else if (screen->chip_family <= CHIP_FAMILY_RV280)
1109	   screen->chip_flags |= RADEON_CLASS_R200;
1110   else if (screen->chip_family <= CHIP_FAMILY_RV570)
1111	   screen->chip_flags |= RADEON_CLASS_R300;
1112   else
1113	   screen->chip_flags |= RADEON_CLASS_R600;
1114
1115   /* r6xx+ tiling, default group bytes */
1116   if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1117	   screen->group_bytes = 512;
1118   else
1119	   screen->group_bytes = 256;
1120   if (IS_R600_CLASS(screen)) {
1121	   if ((sPriv->drm_version.minor >= 6) &&
1122	       (screen->chip_family < CHIP_FAMILY_CEDAR)) {
1123		   ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1124		   if (ret)
1125			   fprintf(stderr, "failed to get tiling info\n");
1126		   else {
1127			   screen->tile_config = temp;
1128			   screen->r7xx_bank_op = 0;
1129			   switch ((screen->tile_config & 0xe) >> 1) {
1130			   case 0:
1131				   screen->num_channels = 1;
1132				   break;
1133			   case 1:
1134				   screen->num_channels = 2;
1135				   break;
1136			   case 2:
1137				   screen->num_channels = 4;
1138				   break;
1139			   case 3:
1140				   screen->num_channels = 8;
1141				   break;
1142			   default:
1143				   fprintf(stderr, "bad channels\n");
1144				   break;
1145			   }
1146			   switch ((screen->tile_config & 0x30) >> 4) {
1147			   case 0:
1148				   screen->num_banks = 4;
1149				   break;
1150			   case 1:
1151				   screen->num_banks = 8;
1152				   break;
1153			   default:
1154				   fprintf(stderr, "bad banks\n");
1155				   break;
1156			   }
1157			   switch ((screen->tile_config & 0xc0) >> 6) {
1158			   case 0:
1159				   screen->group_bytes = 256;
1160				   break;
1161			   case 1:
1162				   screen->group_bytes = 512;
1163				   break;
1164			   default:
1165				   fprintf(stderr, "bad group_bytes\n");
1166				   break;
1167			   }
1168		   }
1169	   } else if ((sPriv->drm_version.minor >= 7) &&
1170		      (screen->chip_family >= CHIP_FAMILY_CEDAR)) {
1171		   ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1172		   if (ret)
1173			   fprintf(stderr, "failed to get tiling info\n");
1174		   else {
1175			   screen->tile_config = temp;
1176			   screen->r7xx_bank_op = 0;
1177			   switch (screen->tile_config & 0xf) {
1178			   case 0:
1179				   screen->num_channels = 1;
1180				   break;
1181			   case 1:
1182				   screen->num_channels = 2;
1183				   break;
1184			   case 2:
1185				   screen->num_channels = 4;
1186				   break;
1187			   case 3:
1188				   screen->num_channels = 8;
1189				   break;
1190			   default:
1191				   fprintf(stderr, "bad channels\n");
1192				   break;
1193			   }
1194			   switch ((screen->tile_config & 0xf0) >> 4) {
1195			   case 0:
1196				   screen->num_banks = 4;
1197				   break;
1198			   case 1:
1199				   screen->num_banks = 8;
1200				   break;
1201			   case 2:
1202				   screen->num_banks = 16;
1203				   break;
1204			   default:
1205				   fprintf(stderr, "bad banks\n");
1206				   break;
1207			   }
1208			   switch ((screen->tile_config & 0xf00) >> 8) {
1209			   case 0:
1210				   screen->group_bytes = 256;
1211				   break;
1212			   case 1:
1213				   screen->group_bytes = 512;
1214				   break;
1215			   default:
1216				   fprintf(stderr, "bad group_bytes\n");
1217				   break;
1218			   }
1219		   }
1220	   }
1221   }
1222
1223   if (IS_R300_CLASS(screen)) {
1224       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1225       if (ret) {
1226	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1227	   switch (screen->chip_family) {
1228	   case CHIP_FAMILY_R300:
1229	   case CHIP_FAMILY_R350:
1230	       screen->num_gb_pipes = 2;
1231	       break;
1232	   case CHIP_FAMILY_R420:
1233	   case CHIP_FAMILY_R520:
1234	   case CHIP_FAMILY_R580:
1235	   case CHIP_FAMILY_RV560:
1236	   case CHIP_FAMILY_RV570:
1237	       screen->num_gb_pipes = 4;
1238	       break;
1239	   case CHIP_FAMILY_RV350:
1240	   case CHIP_FAMILY_RV515:
1241	   case CHIP_FAMILY_RV530:
1242	   case CHIP_FAMILY_RV410:
1243	   default:
1244	       screen->num_gb_pipes = 1;
1245	       break;
1246	   }
1247       } else {
1248	   screen->num_gb_pipes = temp;
1249       }
1250
1251       /* pipe overrides */
1252       switch (device_id) {
1253       case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1254       case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1255       case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1256       case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1257	   screen->num_gb_pipes = 1;
1258	   break;
1259       default:
1260	   break;
1261       }
1262
1263       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1264       if (ret)
1265	       screen->num_z_pipes = 2;
1266       else
1267	       screen->num_z_pipes = temp;
1268
1269   }
1270
1271   i = 0;
1272   screen->extensions[i++] = &driCopySubBufferExtension.base;
1273   screen->extensions[i++] = &driReadDrawableExtension;
1274   screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1275
1276   if ( screen->irq != 0 ) {
1277       screen->extensions[i++] = &driSwapControlExtension.base;
1278       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1279   }
1280
1281#if defined(RADEON_R100)
1282   screen->extensions[i++] = &radeonTexBufferExtension.base;
1283#endif
1284
1285#if defined(RADEON_R200)
1286   screen->extensions[i++] = &r200TexBufferExtension.base;
1287#endif
1288
1289   screen->extensions[i++] = &radeonFlushExtension.base;
1290   screen->extensions[i++] = &radeonImageExtension.base;
1291
1292   screen->extensions[i++] = NULL;
1293   sPriv->extensions = screen->extensions;
1294
1295   screen->driScreen = sPriv;
1296   screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1297   if (screen->bom == NULL) {
1298       free(screen);
1299       return NULL;
1300   }
1301   return screen;
1302}
1303
1304/* Destroy the device specific screen private data struct.
1305 */
1306static void
1307radeonDestroyScreen( __DRIscreen *sPriv )
1308{
1309    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1310
1311    if (!screen)
1312        return;
1313
1314#ifdef RADEON_BO_TRACK
1315    radeon_tracker_print(&screen->bom->tracker, stderr);
1316#endif
1317    radeon_bo_manager_gem_dtor(screen->bom);
1318
1319    /* free all option information */
1320    driDestroyOptionInfo (&screen->optionCache);
1321
1322    FREE( screen );
1323    sPriv->private = NULL;
1324}
1325
1326
1327/* Initialize the driver specific screen private data.
1328 */
1329static GLboolean
1330radeonInitDriver( __DRIscreen *sPriv )
1331{
1332   assert(sPriv->dri2.enabled);
1333
1334    sPriv->private = (void *) radeonCreateScreen2( sPriv );
1335    if ( !sPriv->private ) {
1336        radeonDestroyScreen( sPriv );
1337        return GL_FALSE;
1338    }
1339
1340    return GL_TRUE;
1341}
1342
1343
1344
1345/**
1346 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1347 *
1348 * \todo This function (and its interface) will need to be updated to support
1349 * pbuffers.
1350 */
1351static GLboolean
1352radeonCreateBuffer( __DRIscreen *driScrnPriv,
1353                    __DRIdrawable *driDrawPriv,
1354                    const struct gl_config *mesaVis,
1355                    GLboolean isPixmap )
1356{
1357    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1358
1359    const GLboolean swDepth = GL_FALSE;
1360    const GLboolean swAlpha = GL_FALSE;
1361    const GLboolean swAccum = mesaVis->accumRedBits > 0;
1362    const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1363	mesaVis->depthBits != 24;
1364    gl_format rgbFormat;
1365    struct radeon_framebuffer *rfb;
1366
1367    if (isPixmap)
1368      return GL_FALSE; /* not implemented */
1369
1370    rfb = CALLOC_STRUCT(radeon_framebuffer);
1371    if (!rfb)
1372      return GL_FALSE;
1373
1374    _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1375
1376    if (mesaVis->redBits == 5)
1377        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1378    else if (mesaVis->alphaBits == 0)
1379        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1380    else
1381        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1382
1383    /* front color renderbuffer */
1384    rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1385    _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1386    rfb->color_rb[0]->has_surface = 1;
1387
1388    /* back color renderbuffer */
1389    if (mesaVis->doubleBufferMode) {
1390      rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1391	_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1392	rfb->color_rb[1]->has_surface = 1;
1393    }
1394
1395    if (mesaVis->depthBits == 24) {
1396      if (mesaVis->stencilBits == 8) {
1397	struct radeon_renderbuffer *depthStencilRb =
1398           radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1399	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1400	_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1401	depthStencilRb->has_surface = screen->depthHasSurface;
1402      } else {
1403	/* depth renderbuffer */
1404	struct radeon_renderbuffer *depth =
1405           radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1406	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1407	depth->has_surface = screen->depthHasSurface;
1408      }
1409    } else if (mesaVis->depthBits == 16) {
1410        /* just 16-bit depth buffer, no hw stencil */
1411	struct radeon_renderbuffer *depth =
1412           radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1413	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1414	depth->has_surface = screen->depthHasSurface;
1415    }
1416
1417    _mesa_add_soft_renderbuffers(&rfb->base,
1418	    GL_FALSE, /* color */
1419	    swDepth,
1420	    swStencil,
1421	    swAccum,
1422	    swAlpha,
1423	    GL_FALSE /* aux */);
1424    driDrawPriv->driverPrivate = (void *) rfb;
1425
1426    return (driDrawPriv->driverPrivate != NULL);
1427}
1428
1429
1430static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1431{
1432	struct radeon_renderbuffer *rb;
1433
1434	rb = rfb->color_rb[0];
1435	if (rb && rb->bo) {
1436		radeon_bo_unref(rb->bo);
1437		rb->bo = NULL;
1438	}
1439	rb = rfb->color_rb[1];
1440	if (rb && rb->bo) {
1441		radeon_bo_unref(rb->bo);
1442		rb->bo = NULL;
1443	}
1444	rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1445	if (rb && rb->bo) {
1446		radeon_bo_unref(rb->bo);
1447		rb->bo = NULL;
1448	}
1449}
1450
1451void
1452radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1453{
1454    struct radeon_framebuffer *rfb;
1455    if (!driDrawPriv)
1456	return;
1457
1458    rfb = (void*)driDrawPriv->driverPrivate;
1459    if (!rfb)
1460	return;
1461    radeon_cleanup_renderbuffers(rfb);
1462    _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1463}
1464
1465#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1466
1467/**
1468 * This is the driver specific part of the createNewScreen entry point.
1469 * Called when using DRI2.
1470 *
1471 * \return the struct gl_config supported by this driver
1472 */
1473static const
1474__DRIconfig **radeonInitScreen2(__DRIscreen *psp)
1475{
1476   GLenum fb_format[3];
1477   GLenum fb_type[3];
1478   /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1479    * support pageflipping at all.
1480    */
1481   static const GLenum back_buffer_modes[] = {
1482     GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1483   };
1484   uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1485   int color;
1486   __DRIconfig **configs = NULL;
1487
1488   if (!radeonInitDriver(psp)) {
1489       return NULL;
1490    }
1491   depth_bits[0] = 0;
1492   stencil_bits[0] = 0;
1493   depth_bits[1] = 16;
1494   stencil_bits[1] = 0;
1495   depth_bits[2] = 24;
1496   stencil_bits[2] = 0;
1497   depth_bits[3] = 24;
1498   stencil_bits[3] = 8;
1499
1500   msaa_samples_array[0] = 0;
1501
1502   fb_format[0] = GL_RGB;
1503   fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1504
1505   fb_format[1] = GL_BGR;
1506   fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1507
1508   fb_format[2] = GL_BGRA;
1509   fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1510
1511   for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1512      __DRIconfig **new_configs;
1513
1514      new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1515				     depth_bits,
1516				     stencil_bits,
1517				     ARRAY_SIZE(depth_bits),
1518				     back_buffer_modes,
1519				     ARRAY_SIZE(back_buffer_modes),
1520				     msaa_samples_array,
1521				     ARRAY_SIZE(msaa_samples_array),
1522				     GL_TRUE);
1523      if (configs == NULL)
1524	 configs = new_configs;
1525      else
1526	 configs = driConcatConfigs(configs, new_configs);
1527   }
1528
1529   if (configs == NULL) {
1530      fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1531              __LINE__);
1532      return NULL;
1533   }
1534
1535   return (const __DRIconfig **)configs;
1536}
1537
1538const struct __DriverAPIRec driDriverAPI = {
1539   .DestroyScreen   = radeonDestroyScreen,
1540#if defined(RADEON_R200)
1541   .CreateContext   = r200CreateContext,
1542   .DestroyContext  = r200DestroyContext,
1543#else
1544   .CreateContext   = r100CreateContext,
1545   .DestroyContext  = radeonDestroyContext,
1546#endif
1547   .CreateBuffer    = radeonCreateBuffer,
1548   .DestroyBuffer   = radeonDestroyBuffer,
1549   .MakeCurrent     = radeonMakeCurrent,
1550   .UnbindContext   = radeonUnbindContext,
1551    /* DRI2 */
1552   .InitScreen2     = radeonInitScreen2,
1553};
1554
1555/* This is the table of extensions that the loader will dlsym() for. */
1556PUBLIC const __DRIextension *__driDriverExtensions[] = {
1557    &driCoreExtension.base,
1558    &driLegacyExtension.base,
1559    &driDRI2Extension.base,
1560    NULL
1561};
1562