radeon_screen.c revision f68a61d88398fe8eb3eb41b929dcb4483354a81e
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_buffer.h" 50#include "common_misc.h" 51#if !RADEON_COMMON 52#include "radeon_context.h" 53#include "radeon_span.h" 54#include "radeon_tex.h" 55#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 56#include "r200_context.h" 57#include "r200_ioctl.h" 58#include "r200_span.h" 59#include "r200_tex.h" 60#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 61#include "r300_context.h" 62#include "r300_fragprog.h" 63#include "r300_tex.h" 64#include "radeon_span.h" 65#endif 66 67#include "utils.h" 68#include "vblank.h" 69#include "drirenderbuffer.h" 70 71#include "GL/internal/dri_interface.h" 72 73/* Radeon configuration 74 */ 75#include "xmlpool.h" 76#include "radeon_bo_legacy.h" 77#include "radeon_bo_gem.h" 78 79#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 80DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 81 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 82 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 83DRI_CONF_OPT_END 84 85#if !RADEON_COMMON /* R100 */ 86PUBLIC const char __driConfigOptions[] = 87DRI_CONF_BEGIN 88 DRI_CONF_SECTION_PERFORMANCE 89 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 90 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 91 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 92 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 93 DRI_CONF_HYPERZ(false) 94 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 95 DRI_CONF_SECTION_END 96 DRI_CONF_SECTION_QUALITY 97 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 98 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 99 DRI_CONF_NO_NEG_LOD_BIAS(false) 100 DRI_CONF_FORCE_S3TC_ENABLE(false) 101 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 102 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 103 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 104 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 105 DRI_CONF_SECTION_END 106 DRI_CONF_SECTION_DEBUG 107 DRI_CONF_NO_RAST(false) 108 DRI_CONF_SECTION_END 109DRI_CONF_END; 110static const GLuint __driNConfigOptions = 15; 111 112#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 113 114PUBLIC const char __driConfigOptions[] = 115DRI_CONF_BEGIN 116 DRI_CONF_SECTION_PERFORMANCE 117 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 118 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 119 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 120 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 121 DRI_CONF_HYPERZ(false) 122 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 123 DRI_CONF_SECTION_END 124 DRI_CONF_SECTION_QUALITY 125 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 126 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 127 DRI_CONF_NO_NEG_LOD_BIAS(false) 128 DRI_CONF_FORCE_S3TC_ENABLE(false) 129 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 130 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 131 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 132 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 133 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 134 DRI_CONF_SECTION_END 135 DRI_CONF_SECTION_DEBUG 136 DRI_CONF_NO_RAST(false) 137 DRI_CONF_SECTION_END 138 DRI_CONF_SECTION_SOFTWARE 139 DRI_CONF_NV_VERTEX_PROGRAM(false) 140 DRI_CONF_SECTION_END 141DRI_CONF_END; 142static const GLuint __driNConfigOptions = 17; 143 144extern const struct dri_extension blend_extensions[]; 145extern const struct dri_extension ARB_vp_extension[]; 146extern const struct dri_extension NV_vp_extension[]; 147extern const struct dri_extension ATI_fs_extension[]; 148extern const struct dri_extension point_extensions[]; 149 150#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 151 152/* TODO: integrate these into xmlpool.h! */ 153#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 154DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 155 DRI_CONF_DESC(en,"Number of texture image units") \ 156 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 157DRI_CONF_OPT_END 158 159#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 160DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 161 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 162 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 163DRI_CONF_OPT_END 164 165 166 167#define DRI_CONF_DISABLE_S3TC(def) \ 168DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 169 DRI_CONF_DESC(en,"Disable S3TC compression") \ 170DRI_CONF_OPT_END 171 172#define DRI_CONF_DISABLE_FALLBACK(def) \ 173DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 174 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 175DRI_CONF_OPT_END 176 177#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 178DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 179 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 180DRI_CONF_OPT_END 181 182#define DRI_CONF_FP_OPTIMIZATION(def) \ 183DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 184 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 185 DRI_CONF_ENUM(0,"Optimize for Speed") \ 186 DRI_CONF_ENUM(1,"Optimize for Quality") \ 187 DRI_CONF_DESC_END \ 188DRI_CONF_OPT_END 189 190PUBLIC const char __driConfigOptions[] = 191DRI_CONF_BEGIN 192 DRI_CONF_SECTION_PERFORMANCE 193 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 194 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 195 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 196 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 197 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 198 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 199 DRI_CONF_DISABLE_FALLBACK(true) 200 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 201 DRI_CONF_SECTION_END 202 DRI_CONF_SECTION_QUALITY 203 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 204 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 205 DRI_CONF_FORCE_S3TC_ENABLE(false) 206 DRI_CONF_DISABLE_S3TC(false) 207 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 208 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 209 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 210 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 211 DRI_CONF_SECTION_END 212 DRI_CONF_SECTION_DEBUG 213 DRI_CONF_NO_RAST(false) 214 DRI_CONF_SECTION_END 215DRI_CONF_END; 216static const GLuint __driNConfigOptions = 17; 217 218#ifndef RADEON_DEBUG 219 220static const struct dri_debug_control debug_control[] = { 221 {"fall", DEBUG_FALLBACKS}, 222 {"tex", DEBUG_TEXTURE}, 223 {"ioctl", DEBUG_IOCTL}, 224 {"prim", DEBUG_PRIMS}, 225 {"vert", DEBUG_VERTS}, 226 {"state", DEBUG_STATE}, 227 {"code", DEBUG_CODEGEN}, 228 {"vfmt", DEBUG_VFMT}, 229 {"vtxf", DEBUG_VFMT}, 230 {"verb", DEBUG_VERBOSE}, 231 {"dri", DEBUG_DRI}, 232 {"dma", DEBUG_DMA}, 233 {"san", DEBUG_SANITY}, 234 {"sync", DEBUG_SYNC}, 235 {"pix", DEBUG_PIXEL}, 236 {"mem", DEBUG_MEMORY}, 237 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 238 {NULL, 0} 239}; 240#endif /* RADEON_DEBUG */ 241 242#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 243 244extern const struct dri_extension card_extensions[]; 245 246static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 247 248static int 249radeonGetParam(int fd, int param, void *value) 250{ 251 int ret; 252 drm_radeon_getparam_t gp; 253 254 gp.param = param; 255 gp.value = value; 256 257 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 258 return ret; 259} 260 261static const __DRIconfig ** 262radeonFillInModes( __DRIscreenPrivate *psp, 263 unsigned pixel_bits, unsigned depth_bits, 264 unsigned stencil_bits, GLboolean have_back_buffer ) 265{ 266 __DRIconfig **configs; 267 __GLcontextModes *m; 268 unsigned depth_buffer_factor; 269 unsigned back_buffer_factor; 270 GLenum fb_format; 271 GLenum fb_type; 272 int i; 273 274 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 275 * enough to add support. Basically, if a context is created with an 276 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 277 * will never be used. 278 */ 279 static const GLenum back_buffer_modes[] = { 280 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 281 }; 282 283 uint8_t depth_bits_array[2]; 284 uint8_t stencil_bits_array[2]; 285 286 287 depth_bits_array[0] = depth_bits; 288 depth_bits_array[1] = depth_bits; 289 290 /* Just like with the accumulation buffer, always provide some modes 291 * with a stencil buffer. It will be a sw fallback, but some apps won't 292 * care about that. 293 */ 294 stencil_bits_array[0] = 0; 295 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 296 297 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 298 back_buffer_factor = (have_back_buffer) ? 2 : 1; 299 300 if ( pixel_bits == 16 ) { 301 fb_format = GL_RGB; 302 fb_type = GL_UNSIGNED_SHORT_5_6_5; 303 } 304 else { 305 fb_format = GL_BGRA; 306 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 307 } 308 309 configs = driCreateConfigs(fb_format, fb_type, 310 depth_bits_array, stencil_bits_array, 311 depth_buffer_factor, 312 back_buffer_modes, back_buffer_factor); 313 if (configs == NULL) { 314 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 315 __func__, __LINE__ ); 316 return NULL; 317 } 318 319 /* Mark the visual as slow if there are "fake" stencil bits. 320 */ 321 for (i = 0; configs[i]; i++) { 322 m = &configs[i]->modes; 323 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 324 m->visualRating = GLX_SLOW_CONFIG; 325 } 326 } 327 328 return (const __DRIconfig **) configs; 329} 330 331#if !RADEON_COMMON 332static const __DRItexOffsetExtension radeonTexOffsetExtension = { 333 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 334 radeonSetTexOffset, 335}; 336#endif 337 338#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 339static const __DRIallocateExtension r200AllocateExtension = { 340 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 341 r200AllocateMemoryMESA, 342 r200FreeMemoryMESA, 343 r200GetMemoryOffsetMESA 344}; 345 346static const __DRItexOffsetExtension r200texOffsetExtension = { 347 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 348 r200SetTexOffset, 349}; 350#endif 351 352#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 353static const __DRItexOffsetExtension r300texOffsetExtension = { 354 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 355 r300SetTexOffset, 356}; 357 358void r300SetTexBuffer(__DRIcontext *pDRICtx, 359 GLint target, 360 __DRIdrawable *dPriv); 361static const __DRItexBufferExtension r300TexBufferExtension = { 362 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 363 r300SetTexBuffer, 364}; 365#endif 366 367int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 368{ 369 screen->chip_flags = 0; 370 switch ( device_id ) { 371 case PCI_CHIP_RADEON_LY: 372 case PCI_CHIP_RADEON_LZ: 373 case PCI_CHIP_RADEON_QY: 374 case PCI_CHIP_RADEON_QZ: 375 case PCI_CHIP_RN50_515E: 376 case PCI_CHIP_RN50_5969: 377 screen->chip_family = CHIP_FAMILY_RV100; 378 break; 379 380 case PCI_CHIP_RS100_4136: 381 case PCI_CHIP_RS100_4336: 382 screen->chip_family = CHIP_FAMILY_RS100; 383 break; 384 385 case PCI_CHIP_RS200_4137: 386 case PCI_CHIP_RS200_4337: 387 case PCI_CHIP_RS250_4237: 388 case PCI_CHIP_RS250_4437: 389 screen->chip_family = CHIP_FAMILY_RS200; 390 break; 391 392 case PCI_CHIP_RADEON_QD: 393 case PCI_CHIP_RADEON_QE: 394 case PCI_CHIP_RADEON_QF: 395 case PCI_CHIP_RADEON_QG: 396 /* all original radeons (7200) presumably have a stencil op bug */ 397 screen->chip_family = CHIP_FAMILY_R100; 398 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 399 break; 400 401 case PCI_CHIP_RV200_QW: 402 case PCI_CHIP_RV200_QX: 403 case PCI_CHIP_RADEON_LW: 404 case PCI_CHIP_RADEON_LX: 405 screen->chip_family = CHIP_FAMILY_RV200; 406 screen->chip_flags = RADEON_CHIPSET_TCL; 407 break; 408 409 case PCI_CHIP_R200_BB: 410 case PCI_CHIP_R200_BC: 411 case PCI_CHIP_R200_QH: 412 case PCI_CHIP_R200_QL: 413 case PCI_CHIP_R200_QM: 414 screen->chip_family = CHIP_FAMILY_R200; 415 screen->chip_flags = RADEON_CHIPSET_TCL; 416 break; 417 418 case PCI_CHIP_RV250_If: 419 case PCI_CHIP_RV250_Ig: 420 case PCI_CHIP_RV250_Ld: 421 case PCI_CHIP_RV250_Lf: 422 case PCI_CHIP_RV250_Lg: 423 screen->chip_family = CHIP_FAMILY_RV250; 424 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 425 break; 426 427 case PCI_CHIP_RV280_5960: 428 case PCI_CHIP_RV280_5961: 429 case PCI_CHIP_RV280_5962: 430 case PCI_CHIP_RV280_5964: 431 case PCI_CHIP_RV280_5965: 432 case PCI_CHIP_RV280_5C61: 433 case PCI_CHIP_RV280_5C63: 434 screen->chip_family = CHIP_FAMILY_RV280; 435 screen->chip_flags = RADEON_CHIPSET_TCL; 436 break; 437 438 case PCI_CHIP_RS300_5834: 439 case PCI_CHIP_RS300_5835: 440 case PCI_CHIP_RS350_7834: 441 case PCI_CHIP_RS350_7835: 442 screen->chip_family = CHIP_FAMILY_RS300; 443 break; 444 445 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 446 case PCI_CHIP_R300_AD: 447 screen->chip_family = CHIP_FAMILY_RV350; 448 screen->chip_flags = RADEON_CHIPSET_TCL; 449 break; 450 case PCI_CHIP_R300_AE: 451 case PCI_CHIP_R300_AF: 452 case PCI_CHIP_R300_AG: 453 case PCI_CHIP_R300_ND: 454 case PCI_CHIP_R300_NE: 455 case PCI_CHIP_R300_NF: 456 case PCI_CHIP_R300_NG: 457 screen->chip_family = CHIP_FAMILY_R300; 458 screen->chip_flags = RADEON_CHIPSET_TCL; 459 break; 460 461 case PCI_CHIP_RV350_AP: 462 case PCI_CHIP_RV350_AQ: 463 case PCI_CHIP_RV350_AR: 464 case PCI_CHIP_RV350_AS: 465 case PCI_CHIP_RV350_AT: 466 case PCI_CHIP_RV350_AV: 467 case PCI_CHIP_RV350_AU: 468 case PCI_CHIP_RV350_NP: 469 case PCI_CHIP_RV350_NQ: 470 case PCI_CHIP_RV350_NR: 471 case PCI_CHIP_RV350_NS: 472 case PCI_CHIP_RV350_NT: 473 case PCI_CHIP_RV350_NV: 474 screen->chip_family = CHIP_FAMILY_RV350; 475 screen->chip_flags = RADEON_CHIPSET_TCL; 476 break; 477 478 case PCI_CHIP_R350_AH: 479 case PCI_CHIP_R350_AI: 480 case PCI_CHIP_R350_AJ: 481 case PCI_CHIP_R350_AK: 482 case PCI_CHIP_R350_NH: 483 case PCI_CHIP_R350_NI: 484 case PCI_CHIP_R360_NJ: 485 case PCI_CHIP_R350_NK: 486 screen->chip_family = CHIP_FAMILY_R350; 487 screen->chip_flags = RADEON_CHIPSET_TCL; 488 break; 489 490 case PCI_CHIP_RV370_5460: 491 case PCI_CHIP_RV370_5462: 492 case PCI_CHIP_RV370_5464: 493 case PCI_CHIP_RV370_5B60: 494 case PCI_CHIP_RV370_5B62: 495 case PCI_CHIP_RV370_5B63: 496 case PCI_CHIP_RV370_5B64: 497 case PCI_CHIP_RV370_5B65: 498 case PCI_CHIP_RV380_3150: 499 case PCI_CHIP_RV380_3152: 500 case PCI_CHIP_RV380_3154: 501 case PCI_CHIP_RV380_3E50: 502 case PCI_CHIP_RV380_3E54: 503 screen->chip_family = CHIP_FAMILY_RV380; 504 screen->chip_flags = RADEON_CHIPSET_TCL; 505 break; 506 507 case PCI_CHIP_R420_JN: 508 case PCI_CHIP_R420_JH: 509 case PCI_CHIP_R420_JI: 510 case PCI_CHIP_R420_JJ: 511 case PCI_CHIP_R420_JK: 512 case PCI_CHIP_R420_JL: 513 case PCI_CHIP_R420_JM: 514 case PCI_CHIP_R420_JO: 515 case PCI_CHIP_R420_JP: 516 case PCI_CHIP_R420_JT: 517 case PCI_CHIP_R481_4B49: 518 case PCI_CHIP_R481_4B4A: 519 case PCI_CHIP_R481_4B4B: 520 case PCI_CHIP_R481_4B4C: 521 case PCI_CHIP_R423_UH: 522 case PCI_CHIP_R423_UI: 523 case PCI_CHIP_R423_UJ: 524 case PCI_CHIP_R423_UK: 525 case PCI_CHIP_R430_554C: 526 case PCI_CHIP_R430_554D: 527 case PCI_CHIP_R430_554E: 528 case PCI_CHIP_R430_554F: 529 case PCI_CHIP_R423_5550: 530 case PCI_CHIP_R423_UQ: 531 case PCI_CHIP_R423_UR: 532 case PCI_CHIP_R423_UT: 533 case PCI_CHIP_R430_5D48: 534 case PCI_CHIP_R430_5D49: 535 case PCI_CHIP_R430_5D4A: 536 case PCI_CHIP_R480_5D4C: 537 case PCI_CHIP_R480_5D4D: 538 case PCI_CHIP_R480_5D4E: 539 case PCI_CHIP_R480_5D4F: 540 case PCI_CHIP_R480_5D50: 541 case PCI_CHIP_R480_5D52: 542 case PCI_CHIP_R423_5D57: 543 screen->chip_family = CHIP_FAMILY_R420; 544 screen->chip_flags = RADEON_CHIPSET_TCL; 545 break; 546 547 case PCI_CHIP_RV410_5E4C: 548 case PCI_CHIP_RV410_5E4F: 549 case PCI_CHIP_RV410_564A: 550 case PCI_CHIP_RV410_564B: 551 case PCI_CHIP_RV410_564F: 552 case PCI_CHIP_RV410_5652: 553 case PCI_CHIP_RV410_5653: 554 case PCI_CHIP_RV410_5657: 555 case PCI_CHIP_RV410_5E48: 556 case PCI_CHIP_RV410_5E4A: 557 case PCI_CHIP_RV410_5E4B: 558 case PCI_CHIP_RV410_5E4D: 559 screen->chip_family = CHIP_FAMILY_RV410; 560 screen->chip_flags = RADEON_CHIPSET_TCL; 561 break; 562 563 case PCI_CHIP_RS480_5954: 564 case PCI_CHIP_RS480_5955: 565 case PCI_CHIP_RS482_5974: 566 case PCI_CHIP_RS482_5975: 567 case PCI_CHIP_RS400_5A41: 568 case PCI_CHIP_RS400_5A42: 569 case PCI_CHIP_RC410_5A61: 570 case PCI_CHIP_RC410_5A62: 571 screen->chip_family = CHIP_FAMILY_RS400; 572 break; 573 574 case PCI_CHIP_RS690_791E: 575 case PCI_CHIP_RS690_791F: 576 screen->chip_family = CHIP_FAMILY_RS690; 577 break; 578 case PCI_CHIP_RS740_796C: 579 case PCI_CHIP_RS740_796D: 580 case PCI_CHIP_RS740_796E: 581 case PCI_CHIP_RS740_796F: 582 screen->chip_family = CHIP_FAMILY_RS740; 583 break; 584 585 case PCI_CHIP_R520_7100: 586 case PCI_CHIP_R520_7101: 587 case PCI_CHIP_R520_7102: 588 case PCI_CHIP_R520_7103: 589 case PCI_CHIP_R520_7104: 590 case PCI_CHIP_R520_7105: 591 case PCI_CHIP_R520_7106: 592 case PCI_CHIP_R520_7108: 593 case PCI_CHIP_R520_7109: 594 case PCI_CHIP_R520_710A: 595 case PCI_CHIP_R520_710B: 596 case PCI_CHIP_R520_710C: 597 case PCI_CHIP_R520_710E: 598 case PCI_CHIP_R520_710F: 599 screen->chip_family = CHIP_FAMILY_R520; 600 screen->chip_flags = RADEON_CHIPSET_TCL; 601 break; 602 603 case PCI_CHIP_RV515_7140: 604 case PCI_CHIP_RV515_7141: 605 case PCI_CHIP_RV515_7142: 606 case PCI_CHIP_RV515_7143: 607 case PCI_CHIP_RV515_7144: 608 case PCI_CHIP_RV515_7145: 609 case PCI_CHIP_RV515_7146: 610 case PCI_CHIP_RV515_7147: 611 case PCI_CHIP_RV515_7149: 612 case PCI_CHIP_RV515_714A: 613 case PCI_CHIP_RV515_714B: 614 case PCI_CHIP_RV515_714C: 615 case PCI_CHIP_RV515_714D: 616 case PCI_CHIP_RV515_714E: 617 case PCI_CHIP_RV515_714F: 618 case PCI_CHIP_RV515_7151: 619 case PCI_CHIP_RV515_7152: 620 case PCI_CHIP_RV515_7153: 621 case PCI_CHIP_RV515_715E: 622 case PCI_CHIP_RV515_715F: 623 case PCI_CHIP_RV515_7180: 624 case PCI_CHIP_RV515_7181: 625 case PCI_CHIP_RV515_7183: 626 case PCI_CHIP_RV515_7186: 627 case PCI_CHIP_RV515_7187: 628 case PCI_CHIP_RV515_7188: 629 case PCI_CHIP_RV515_718A: 630 case PCI_CHIP_RV515_718B: 631 case PCI_CHIP_RV515_718C: 632 case PCI_CHIP_RV515_718D: 633 case PCI_CHIP_RV515_718F: 634 case PCI_CHIP_RV515_7193: 635 case PCI_CHIP_RV515_7196: 636 case PCI_CHIP_RV515_719B: 637 case PCI_CHIP_RV515_719F: 638 case PCI_CHIP_RV515_7200: 639 case PCI_CHIP_RV515_7210: 640 case PCI_CHIP_RV515_7211: 641 screen->chip_family = CHIP_FAMILY_RV515; 642 screen->chip_flags = RADEON_CHIPSET_TCL; 643 break; 644 645 case PCI_CHIP_RV530_71C0: 646 case PCI_CHIP_RV530_71C1: 647 case PCI_CHIP_RV530_71C2: 648 case PCI_CHIP_RV530_71C3: 649 case PCI_CHIP_RV530_71C4: 650 case PCI_CHIP_RV530_71C5: 651 case PCI_CHIP_RV530_71C6: 652 case PCI_CHIP_RV530_71C7: 653 case PCI_CHIP_RV530_71CD: 654 case PCI_CHIP_RV530_71CE: 655 case PCI_CHIP_RV530_71D2: 656 case PCI_CHIP_RV530_71D4: 657 case PCI_CHIP_RV530_71D5: 658 case PCI_CHIP_RV530_71D6: 659 case PCI_CHIP_RV530_71DA: 660 case PCI_CHIP_RV530_71DE: 661 screen->chip_family = CHIP_FAMILY_RV530; 662 screen->chip_flags = RADEON_CHIPSET_TCL; 663 break; 664 665 case PCI_CHIP_R580_7240: 666 case PCI_CHIP_R580_7243: 667 case PCI_CHIP_R580_7244: 668 case PCI_CHIP_R580_7245: 669 case PCI_CHIP_R580_7246: 670 case PCI_CHIP_R580_7247: 671 case PCI_CHIP_R580_7248: 672 case PCI_CHIP_R580_7249: 673 case PCI_CHIP_R580_724A: 674 case PCI_CHIP_R580_724B: 675 case PCI_CHIP_R580_724C: 676 case PCI_CHIP_R580_724D: 677 case PCI_CHIP_R580_724E: 678 case PCI_CHIP_R580_724F: 679 case PCI_CHIP_R580_7284: 680 screen->chip_family = CHIP_FAMILY_R580; 681 screen->chip_flags = RADEON_CHIPSET_TCL; 682 break; 683 684 case PCI_CHIP_RV570_7280: 685 case PCI_CHIP_RV560_7281: 686 case PCI_CHIP_RV560_7283: 687 case PCI_CHIP_RV560_7287: 688 case PCI_CHIP_RV570_7288: 689 case PCI_CHIP_RV570_7289: 690 case PCI_CHIP_RV570_728B: 691 case PCI_CHIP_RV570_728C: 692 case PCI_CHIP_RV560_7290: 693 case PCI_CHIP_RV560_7291: 694 case PCI_CHIP_RV560_7293: 695 case PCI_CHIP_RV560_7297: 696 screen->chip_family = CHIP_FAMILY_RV560; 697 screen->chip_flags = RADEON_CHIPSET_TCL; 698 break; 699 700 default: 701 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 702 device_id); 703 return -1; 704 } 705 706 return 0; 707} 708 709 710/* Create the device specific screen private data struct. 711 */ 712static radeonScreenPtr 713radeonCreateScreen( __DRIscreenPrivate *sPriv ) 714{ 715 radeonScreenPtr screen; 716 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 717 unsigned char *RADEONMMIO = NULL; 718 int i; 719 int ret; 720 uint32_t temp; 721 722 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 723 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 724 return GL_FALSE; 725 } 726 727 /* Allocate the private area */ 728 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 729 if ( !screen ) { 730 __driUtilMessage("%s: Could not allocate memory for screen structure", 731 __FUNCTION__); 732 return NULL; 733 } 734 735#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 736 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 737#endif 738 739 /* parse information in __driConfigOptions */ 740 driParseOptionInfo (&screen->optionCache, 741 __driConfigOptions, __driNConfigOptions); 742 743 /* This is first since which regions we map depends on whether or 744 * not we are using a PCI card. 745 */ 746 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 747 { 748 int ret; 749 750#ifdef RADEON_PARAM_KERNEL_MM 751 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, 752 &screen->kernel_mm); 753 754 if (ret && ret != -EINVAL) { 755 FREE( screen ); 756 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 757 return NULL; 758 } 759 760 if (ret == -EINVAL) 761 screen->kernel_mm = 0; 762#endif 763 764 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 765 &screen->gart_buffer_offset); 766 767 if (ret) { 768 FREE( screen ); 769 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 770 return NULL; 771 } 772 773 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 774 &screen->gart_base); 775 if (ret) { 776 FREE( screen ); 777 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 778 return NULL; 779 } 780 781 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 782 &screen->irq); 783 if (ret) { 784 FREE( screen ); 785 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 786 return NULL; 787 } 788 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 789 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 790 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 791 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 792 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 793 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 794 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 795 } 796 797 if (!screen->kernel_mm) { 798 screen->mmio.handle = dri_priv->registerHandle; 799 screen->mmio.size = dri_priv->registerSize; 800 if ( drmMap( sPriv->fd, 801 screen->mmio.handle, 802 screen->mmio.size, 803 &screen->mmio.map ) ) { 804 FREE( screen ); 805 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 806 return NULL; 807 } 808 809 RADEONMMIO = screen->mmio.map; 810 811 screen->status.handle = dri_priv->statusHandle; 812 screen->status.size = dri_priv->statusSize; 813 if ( drmMap( sPriv->fd, 814 screen->status.handle, 815 screen->status.size, 816 &screen->status.map ) ) { 817 drmUnmap( screen->mmio.map, screen->mmio.size ); 818 FREE( screen ); 819 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 820 return NULL; 821 } 822 screen->scratch = (__volatile__ uint32_t *) 823 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 824 825 screen->buffers = drmMapBufs( sPriv->fd ); 826 if ( !screen->buffers ) { 827 drmUnmap( screen->status.map, screen->status.size ); 828 drmUnmap( screen->mmio.map, screen->mmio.size ); 829 FREE( screen ); 830 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 831 return NULL; 832 } 833 834 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 835 screen->gartTextures.handle = dri_priv->gartTexHandle; 836 screen->gartTextures.size = dri_priv->gartTexMapSize; 837 if ( drmMap( sPriv->fd, 838 screen->gartTextures.handle, 839 screen->gartTextures.size, 840 (drmAddressPtr)&screen->gartTextures.map ) ) { 841 drmUnmapBufs( screen->buffers ); 842 drmUnmap( screen->status.map, screen->status.size ); 843 drmUnmap( screen->mmio.map, screen->mmio.size ); 844 FREE( screen ); 845 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 846 return NULL; 847 } 848 849 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 850 } 851 } 852 853 854 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 855 if (ret == -1) 856 return NULL; 857 858 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 859 sPriv->ddx_version.minor < 2) { 860 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 861 return NULL; 862 } 863 864 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 865 fprintf(stderr, "R500 support requires a newer drm.\n"); 866 return NULL; 867 } 868 869 if (getenv("R300_NO_TCL")) 870 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 871 872 if (screen->chip_family <= CHIP_FAMILY_RS200) 873 screen->chip_flags |= RADEON_CLASS_R100; 874 else if (screen->chip_family <= CHIP_FAMILY_RV280) 875 screen->chip_flags |= RADEON_CLASS_R200; 876 else 877 screen->chip_flags |= RADEON_CLASS_R300; 878 879 screen->cpp = dri_priv->bpp / 8; 880 screen->AGPMode = dri_priv->AGPMode; 881 882 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 883 &temp); 884 if (ret) { 885 if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm) 886 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 887 else { 888 FREE( screen ); 889 fprintf(stderr, "Unable to get fb location need newer drm\n"); 890 return NULL; 891 } 892 } else { 893 screen->fbLocation = (temp & 0xffff) << 16; 894 } 895 896 if (screen->chip_family >= CHIP_FAMILY_RV515) { 897 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 898 &temp); 899 if (ret) { 900 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 901 switch (screen->chip_family) { 902 case CHIP_FAMILY_R300: 903 case CHIP_FAMILY_R350: 904 screen->num_gb_pipes = 2; 905 break; 906 case CHIP_FAMILY_R420: 907 case CHIP_FAMILY_R520: 908 case CHIP_FAMILY_R580: 909 case CHIP_FAMILY_RV560: 910 case CHIP_FAMILY_RV570: 911 screen->num_gb_pipes = 4; 912 break; 913 case CHIP_FAMILY_RV350: 914 case CHIP_FAMILY_RV515: 915 case CHIP_FAMILY_RV530: 916 case CHIP_FAMILY_RV410: 917 default: 918 screen->num_gb_pipes = 1; 919 break; 920 } 921 } else { 922 screen->num_gb_pipes = temp; 923 } 924 } 925 926 if ( sPriv->drm_version.minor >= 10 ) { 927 drm_radeon_setparam_t sp; 928 929 sp.param = RADEON_SETPARAM_FB_LOCATION; 930 sp.value = screen->fbLocation; 931 932 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 933 &sp, sizeof( sp ) ); 934 } 935 936 screen->frontOffset = dri_priv->frontOffset; 937 screen->frontPitch = dri_priv->frontPitch; 938 screen->backOffset = dri_priv->backOffset; 939 screen->backPitch = dri_priv->backPitch; 940 screen->depthOffset = dri_priv->depthOffset; 941 screen->depthPitch = dri_priv->depthPitch; 942 943 /* Check if ddx has set up a surface reg to cover depth buffer */ 944 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 945 /* these chips don't use tiled z without hyperz. So always pretend 946 we have set up a surface which will cause linear reads/writes */ 947 (IS_R100_CLASS(screen) && 948 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 949 950 if ( dri_priv->textureSize == 0 ) { 951 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 952 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 953 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 954 dri_priv->log2GARTTexGran; 955 } else { 956 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 957 + screen->fbLocation; 958 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 959 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 960 dri_priv->log2TexGran; 961 } 962 963 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 964 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 965 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 966 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 967 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 968 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 969 } else { 970 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 971 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 972 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 973 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 974 dri_priv->log2GARTTexGran; 975 } 976 977 i = 0; 978 screen->extensions[i++] = &driCopySubBufferExtension.base; 979 screen->extensions[i++] = &driFrameTrackingExtension.base; 980 screen->extensions[i++] = &driReadDrawableExtension; 981 982 if ( screen->irq != 0 ) { 983 screen->extensions[i++] = &driSwapControlExtension.base; 984 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 985 } 986 987#if !RADEON_COMMON 988 screen->extensions[i++] = &radeonTexOffsetExtension.base; 989#endif 990 991#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 992 if (IS_R200_CLASS(screen)) 993 screen->extensions[i++] = &r200AllocateExtension.base; 994 995 screen->extensions[i++] = &r200texOffsetExtension.base; 996#endif 997 998#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 999 //screen->extensions[i++] = &r300texOffsetExtension.base; 1000#endif 1001 1002 screen->extensions[i++] = NULL; 1003 sPriv->extensions = screen->extensions; 1004 1005 screen->driScreen = sPriv; 1006 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1007 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1008 screen->sarea_priv_offset); 1009 1010 if (screen->kernel_mm) 1011 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1012 else 1013 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1014 if (screen->bom == NULL) { 1015 free(screen); 1016 return NULL; 1017 } 1018 1019 return screen; 1020} 1021 1022static radeonScreenPtr 1023radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1024{ 1025 radeonScreenPtr screen; 1026 int i; 1027 int ret; 1028 uint32_t device_id; 1029 1030 /* Allocate the private area */ 1031 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1032 if ( !screen ) { 1033 __driUtilMessage("%s: Could not allocate memory for screen structure", 1034 __FUNCTION__); 1035 fprintf(stderr, "leaving here\n"); 1036 return NULL; 1037 } 1038 1039#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1040 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1041#endif 1042 1043 /* parse information in __driConfigOptions */ 1044 driParseOptionInfo (&screen->optionCache, 1045 __driConfigOptions, __driNConfigOptions); 1046 1047 screen->kernel_mm = 1; 1048 screen->chip_flags = 0; 1049 1050 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 1051 &screen->irq); 1052 1053 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, 1054 &device_id); 1055 if (ret) { 1056 FREE( screen ); 1057 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1058 return NULL; 1059 } 1060 1061 ret = radeon_set_screen_flags(screen, device_id); 1062 if (ret == -1) 1063 return NULL; 1064 1065 if (screen->chip_family <= CHIP_FAMILY_RS200) 1066 screen->chip_flags |= RADEON_CLASS_R100; 1067 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1068 screen->chip_flags |= RADEON_CLASS_R200; 1069 else 1070 screen->chip_flags |= RADEON_CLASS_R300; 1071 1072 i = 0; 1073 screen->extensions[i++] = &driCopySubBufferExtension.base; 1074 screen->extensions[i++] = &driFrameTrackingExtension.base; 1075 screen->extensions[i++] = &driReadDrawableExtension; 1076 1077 if ( screen->irq != 0 ) { 1078 screen->extensions[i++] = &driSwapControlExtension.base; 1079 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1080 } 1081 1082#if !RADEON_COMMON 1083 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1084#endif 1085 1086#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1087 if (IS_R200_CLASS(screen)) 1088 screen->extensions[i++] = &r200AllocateExtension.base; 1089 1090 screen->extensions[i++] = &r200texOffsetExtension.base; 1091#endif 1092 1093#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1094 screen->extensions[i++] = &r300texOffsetExtension.base; 1095 screen->extensions[i++] = &r300TexBufferExtension.base; 1096#endif 1097 1098 screen->extensions[i++] = NULL; 1099 sPriv->extensions = screen->extensions; 1100 1101 screen->driScreen = sPriv; 1102 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1103 if (screen->bom == NULL) { 1104 free(screen); 1105 return NULL; 1106 } 1107 return screen; 1108} 1109 1110/* Destroy the device specific screen private data struct. 1111 */ 1112static void 1113radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1114{ 1115 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1116 1117 if (!screen) 1118 return; 1119 1120 if (screen->kernel_mm) { 1121 radeon_tracker_print(&screen->bom->tracker, stderr); 1122 radeon_bo_manager_gem_dtor(screen->bom); 1123 } else { 1124 radeon_bo_manager_legacy_dtor(screen->bom); 1125 1126 if ( screen->gartTextures.map ) { 1127 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1128 } 1129 drmUnmapBufs( screen->buffers ); 1130 drmUnmap( screen->status.map, screen->status.size ); 1131 drmUnmap( screen->mmio.map, screen->mmio.size ); 1132 } 1133 1134 /* free all option information */ 1135 driDestroyOptionInfo (&screen->optionCache); 1136 1137 FREE( screen ); 1138 sPriv->private = NULL; 1139} 1140 1141 1142/* Initialize the driver specific screen private data. 1143 */ 1144static GLboolean 1145radeonInitDriver( __DRIscreenPrivate *sPriv ) 1146{ 1147 if (sPriv->dri2.enabled) { 1148 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1149 } else { 1150 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1151 } 1152 if ( !sPriv->private ) { 1153 radeonDestroyScreen( sPriv ); 1154 return GL_FALSE; 1155 } 1156 1157 return GL_TRUE; 1158} 1159 1160static GLboolean 1161radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, 1162 GLenum intFormat, GLuint w, GLuint h) 1163{ 1164 rb->Width = w; 1165 rb->Height = h; 1166 rb->_ActualFormat = intFormat; 1167 1168 return GL_TRUE; 1169} 1170 1171 1172static struct radeon_renderbuffer * 1173radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) 1174{ 1175 struct radeon_renderbuffer *ret; 1176 1177 ret = CALLOC_STRUCT(radeon_renderbuffer); 1178 if (!ret) 1179 return NULL; 1180 1181 _mesa_init_renderbuffer(&ret->base, 0); 1182 1183 /* XXX format junk */ 1184 switch (format) { 1185 case GL_RGB5: 1186 ret->base._ActualFormat = GL_RGB5; 1187 ret->base._BaseFormat = GL_RGBA; 1188 ret->base.RedBits = 5; 1189 ret->base.GreenBits = 6; 1190 ret->base.BlueBits = 5; 1191 ret->base.DataType = GL_UNSIGNED_BYTE; 1192 break; 1193 case GL_RGBA8: 1194 ret->base._ActualFormat = GL_RGBA8; 1195 ret->base._BaseFormat = GL_RGBA; 1196 ret->base.RedBits = 8; 1197 ret->base.GreenBits = 8; 1198 ret->base.BlueBits = 8; 1199 ret->base.AlphaBits = 8; 1200 ret->base.DataType = GL_UNSIGNED_BYTE; 1201 break; 1202 case GL_STENCIL_INDEX8_EXT: 1203 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; 1204 ret->base._BaseFormat = GL_STENCIL_INDEX; 1205 ret->base.StencilBits = 8; 1206 ret->base.DataType = GL_UNSIGNED_BYTE; 1207 break; 1208 case GL_DEPTH_COMPONENT16: 1209 ret->base._ActualFormat = GL_DEPTH_COMPONENT16; 1210 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1211 ret->base.DepthBits = 16; 1212 ret->base.DataType = GL_UNSIGNED_SHORT; 1213 break; 1214 case GL_DEPTH_COMPONENT24: 1215 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1216 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1217 ret->base.DepthBits = 24; 1218 ret->base.DataType = GL_UNSIGNED_INT; 1219 break; 1220 case GL_DEPTH24_STENCIL8_EXT: 1221 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1222 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; 1223 ret->base.DepthBits = 24; 1224 ret->base.StencilBits = 8; 1225 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; 1226 break; 1227 default: 1228 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); 1229 _mesa_delete_renderbuffer(&ret->base); 1230 return NULL; 1231 } 1232 1233 ret->dPriv = driDrawPriv; 1234 ret->base.InternalFormat = format; 1235 1236 ret->base.AllocStorage = radeon_alloc_window_storage; 1237 1238 radeonSetSpanFunctions(ret); 1239 1240 ret->bo = NULL; 1241 return ret; 1242} 1243 1244/** 1245 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1246 * 1247 * \todo This function (and its interface) will need to be updated to support 1248 * pbuffers. 1249 */ 1250static GLboolean 1251radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1252 __DRIdrawablePrivate *driDrawPriv, 1253 const __GLcontextModes *mesaVis, 1254 GLboolean isPixmap ) 1255{ 1256 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1257 1258 const GLboolean swDepth = GL_FALSE; 1259 const GLboolean swAlpha = GL_FALSE; 1260 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1261 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1262 mesaVis->depthBits != 24; 1263 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); 1264 GLenum depthFormat = GL_NONE; 1265 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1266 1267 if (mesaVis->depthBits == 16) 1268 depthFormat = GL_DEPTH_COMPONENT16; 1269 else if (mesaVis->depthBits == 24) 1270 depthFormat = GL_DEPTH_COMPONENT24; 1271 1272 /* front color renderbuffer */ 1273 { 1274 struct radeon_renderbuffer *front = 1275 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1276 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); 1277 front->has_surface = 1; 1278 } 1279 1280 /* back color renderbuffer */ 1281 if (mesaVis->doubleBufferMode) { 1282 struct radeon_renderbuffer *back = 1283 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1284 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); 1285 back->has_surface = 1; 1286 } 1287 1288 /* depth renderbuffer */ 1289 if (depthFormat != GL_NONE) { 1290 struct radeon_renderbuffer *depth = 1291 radeon_create_renderbuffer(depthFormat, driDrawPriv); 1292 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); 1293 depth->has_surface = screen->depthHasSurface; 1294 } 1295 1296 /* stencil renderbuffer */ 1297 if (mesaVis->stencilBits > 0 && !swStencil) { 1298 struct radeon_renderbuffer *stencil = 1299 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); 1300 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); 1301 stencil->has_surface = screen->depthHasSurface; 1302 } 1303 1304 _mesa_add_soft_renderbuffers(fb, 1305 GL_FALSE, /* color */ 1306 swDepth, 1307 swStencil, 1308 swAccum, 1309 swAlpha, 1310 GL_FALSE /* aux */); 1311 driDrawPriv->driverPrivate = (void *) fb; 1312 1313 return (driDrawPriv->driverPrivate != NULL); 1314} 1315 1316static void 1317radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1318{ 1319 struct radeon_renderbuffer *rb; 1320 GLframebuffer *fb; 1321 1322 fb = (void*)driDrawPriv->driverPrivate; 1323 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; 1324 if (rb && rb->bo) { 1325 radeon_bo_unref(rb->bo); 1326 rb->bo = NULL; 1327 } 1328 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 1329 if (rb && rb->bo) { 1330 radeon_bo_unref(rb->bo); 1331 rb->bo = NULL; 1332 } 1333 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; 1334 if (rb && rb->bo) { 1335 radeon_bo_unref(rb->bo); 1336 rb->bo = NULL; 1337 } 1338 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1339} 1340 1341#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1342/** 1343 * Choose the appropriate CreateContext function based on the chipset. 1344 * Eventually, all drivers will go through this process. 1345 */ 1346static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1347 __DRIcontextPrivate * driContextPriv, 1348 void *sharedContextPriv) 1349{ 1350 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1351 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1352 1353 if (IS_R300_CLASS(screen)) 1354 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1355 return GL_FALSE; 1356} 1357 1358/** 1359 * Choose the appropriate DestroyContext function based on the chipset. 1360 */ 1361static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1362{ 1363 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1364 1365 if (IS_R300_CLASS(radeon->radeonScreen)) 1366 return r300DestroyContext(driContextPriv); 1367} 1368 1369 1370#endif 1371 1372/** 1373 * This is the driver specific part of the createNewScreen entry point. 1374 * 1375 * \todo maybe fold this into intelInitDriver 1376 * 1377 * \return the __GLcontextModes supported by this driver 1378 */ 1379static const __DRIconfig ** 1380radeonInitScreen(__DRIscreenPrivate *psp) 1381{ 1382#if !RADEON_COMMON 1383 static const char *driver_name = "Radeon"; 1384 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1385 static const __DRIversion dri_expected = { 4, 0, 0 }; 1386 static const __DRIversion drm_expected = { 1, 6, 0 }; 1387#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1388 static const char *driver_name = "R200"; 1389 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1390 static const __DRIversion dri_expected = { 4, 0, 0 }; 1391 static const __DRIversion drm_expected = { 1, 6, 0 }; 1392#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1393 static const char *driver_name = "R300"; 1394 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1395 static const __DRIversion dri_expected = { 4, 0, 0 }; 1396 static const __DRIversion drm_expected = { 1, 24, 0 }; 1397#endif 1398 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1399 1400 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1401 &psp->dri_version, & dri_expected, 1402 &psp->ddx_version, & ddx_expected, 1403 &psp->drm_version, & drm_expected ) ) { 1404 return NULL; 1405 } 1406 1407 /* Calling driInitExtensions here, with a NULL context pointer, 1408 * does not actually enable the extensions. It just makes sure 1409 * that all the dispatch offsets for all the extensions that 1410 * *might* be enables are known. This is needed because the 1411 * dispatch offsets need to be known when _mesa_context_create 1412 * is called, but we can't enable the extensions until we have a 1413 * context pointer. 1414 * 1415 * Hello chicken. Hello egg. How are you two today? 1416 */ 1417 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1418#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1419 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1420 driInitSingleExtension( NULL, ARB_vp_extension ); 1421 driInitSingleExtension( NULL, NV_vp_extension ); 1422 driInitSingleExtension( NULL, ATI_fs_extension ); 1423 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1424#endif 1425 1426 if (!radeonInitDriver(psp)) 1427 return NULL; 1428 1429 /* for now fill in all modes */ 1430 return radeonFillInModes( psp, 1431 dri_priv->bpp, 1432 (dri_priv->bpp == 16) ? 16 : 24, 1433 (dri_priv->bpp == 16) ? 0 : 8, 1); 1434} 1435 1436/** 1437 * This is the driver specific part of the createNewScreen entry point. 1438 * Called when using DRI2. 1439 * 1440 * \return the __GLcontextModes supported by this driver 1441 */ 1442static const 1443__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1444{ 1445 /* Calling driInitExtensions here, with a NULL context pointer, 1446 * does not actually enable the extensions. It just makes sure 1447 * that all the dispatch offsets for all the extensions that 1448 * *might* be enables are known. This is needed because the 1449 * dispatch offsets need to be known when _mesa_context_create 1450 * is called, but we can't enable the extensions until we have a 1451 * context pointer. 1452 * 1453 * Hello chicken. Hello egg. How are you two today? 1454 */ 1455 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1456#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1457 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1458 driInitSingleExtension( NULL, ARB_vp_extension ); 1459 driInitSingleExtension( NULL, NV_vp_extension ); 1460 driInitSingleExtension( NULL, ATI_fs_extension ); 1461 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1462#endif 1463 1464 if (!radeonInitDriver(psp)) { 1465 return NULL; 1466 } 1467 1468 /* for now fill in all modes */ 1469 return radeonFillInModes( psp, 24, 24, 8, 1); 1470} 1471 1472/** 1473 * Get information about previous buffer swaps. 1474 */ 1475static int 1476getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1477{ 1478 radeonContextPtr rmesa; 1479 1480 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1481 || (dPriv->driContextPriv->driverPrivate == NULL) 1482 || (sInfo == NULL) ) { 1483 return -1; 1484 } 1485 1486 rmesa = dPriv->driContextPriv->driverPrivate; 1487 sInfo->swap_count = rmesa->swap_count; 1488 sInfo->swap_ust = rmesa->swap_ust; 1489 sInfo->swap_missed_count = rmesa->swap_missed_count; 1490 1491 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1492 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1493 : 0.0; 1494 1495 return 0; 1496} 1497 1498#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1499const struct __DriverAPIRec driDriverAPI = { 1500 .InitScreen = radeonInitScreen, 1501 .DestroyScreen = radeonDestroyScreen, 1502 .CreateContext = radeonCreateContext, 1503 .DestroyContext = radeonDestroyContext, 1504 .CreateBuffer = radeonCreateBuffer, 1505 .DestroyBuffer = radeonDestroyBuffer, 1506 .SwapBuffers = radeonSwapBuffers, 1507 .MakeCurrent = radeonMakeCurrent, 1508 .UnbindContext = radeonUnbindContext, 1509 .GetSwapInfo = getSwapInfo, 1510 .GetDrawableMSC = driDrawableGetMSC32, 1511 .WaitForMSC = driWaitForMSC32, 1512 .WaitForSBC = NULL, 1513 .SwapBuffersMSC = NULL, 1514 .CopySubBuffer = radeonCopySubBuffer, 1515 /* DRI2 */ 1516 .InitScreen2 = radeonInitScreen2, 1517}; 1518#else 1519const struct __DriverAPIRec driDriverAPI = { 1520 .InitScreen = radeonInitScreen, 1521 .DestroyScreen = radeonDestroyScreen, 1522 .CreateContext = r200CreateContext, 1523 .DestroyContext = r200DestroyContext, 1524 .CreateBuffer = radeonCreateBuffer, 1525 .DestroyBuffer = radeonDestroyBuffer, 1526 .SwapBuffers = radeonSwapBuffers, 1527 .MakeCurrent = radeonMakeCurrent, 1528 .UnbindContext = r200UnbindContext, 1529 .GetSwapInfo = getSwapInfo, 1530 .GetDrawableMSC = driDrawableGetMSC32, 1531 .WaitForMSC = driWaitForMSC32, 1532 .WaitForSBC = NULL, 1533 .SwapBuffersMSC = NULL, 1534 .CopySubBuffer = radeonCopySubBuffer, 1535}; 1536#endif 1537 1538