radeon_cmdbuf.h revision 23d3559bd4ece1fcab5513ebdaa38600d6654374 
1#ifndef COMMON_CMDBUF_H
2#define COMMON_CMDBUF_H
3
4#include "radeon_cs.h"
5
6void rcommonEnsureCmdBufSpace(radeonContextPtr rmesa, int dwords, const char *caller);
7int rcommonFlushCmdBuf(radeonContextPtr rmesa, const char *caller);
8int rcommonFlushCmdBufLocked(radeonContextPtr rmesa, const char *caller);
9void rcommonInitCmdBuf(radeonContextPtr rmesa);
10void rcommonDestroyCmdBuf(radeonContextPtr rmesa);
11
12void rcommonBeginBatch(radeonContextPtr rmesa,
13		       int n,
14		       int dostate,
15		       const char *file,
16		       const char *function,
17		       int line);
18
19#define RADEON_CP_PACKET3_NOP                       0xC0001000
20#define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
21#define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
22#define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
23#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
24#define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
25#define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
26#define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
27#define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
28#define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
29#define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
30#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
31#define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
32#define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
33#define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
34#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
35#define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
36#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
37#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
38#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
39#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
40
41#define CP_PACKET2  (2 << 30)
42#define CP_PACKET0(reg, n)	(RADEON_CP_PACKET0 | ((n)<<16) | ((reg)>>2))
43#define CP_PACKET0_ONE(reg, n)	(RADEON_CP_PACKET0 | RADEON_CP_PACKET0_ONE_REG_WR | ((n)<<16) | ((reg)>>2))
44#define CP_PACKET3( pkt, n )						\
45	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
46
47/**
48 * Every function writing to the command buffer needs to declare this
49 * to get the necessary local variables.
50 */
51#define BATCH_LOCALS(rmesa) \
52	const radeonContextPtr b_l_rmesa = rmesa
53
54/**
55 * Prepare writing n dwords to the command buffer,
56 * including producing any necessary state emits on buffer wraparound.
57 */
58#define BEGIN_BATCH(n) rcommonBeginBatch(b_l_rmesa, n, 1, __FILE__, __FUNCTION__, __LINE__)
59
60/**
61 * Same as BEGIN_BATCH, but do not cause automatic state emits.
62 */
63#define BEGIN_BATCH_NO_AUTOSTATE(n) rcommonBeginBatch(b_l_rmesa, n, 0, __FILE__, __FUNCTION__, __LINE__)
64
65/**
66 * Write one dword to the command buffer.
67 */
68#define OUT_BATCH(data) \
69	do { \
70        radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, data);\
71	} while(0)
72
73/**
74 * Write a relocated dword to the command buffer.
75 */
76#define OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) 	\
77	do { 							\
78        if (0 && offset) {					\
79            fprintf(stderr, "(%s:%s:%d) offset : %d\n",		\
80            __FILE__, __FUNCTION__, __LINE__, offset);		\
81        }							\
82        radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset);	\
83        radeon_cs_write_reloc(b_l_rmesa->cmdbuf.cs, 		\
84                              bo, rd, wd, flags);		\
85	if (!b_l_rmesa->radeonScreen->kernel_mm) 		\
86		b_l_rmesa->cmdbuf.cs->section_cdw += 2;		\
87	} while(0)
88
89
90/**
91 * Write n dwords from ptr to the command buffer.
92 */
93#define OUT_BATCH_TABLE(ptr,n) \
94	do { \
95		int _i; \
96        for (_i=0; _i < n; _i++) {\
97            radeon_cs_write_dword(b_l_rmesa->cmdbuf.cs, ptr[_i]);\
98        }\
99	} while(0)
100
101/**
102 * Finish writing dwords to the command buffer.
103 * The number of (direct or indirect) OUT_BATCH calls between the previous
104 * BEGIN_BATCH and END_BATCH must match the number specified at BEGIN_BATCH time.
105 */
106#define END_BATCH() \
107	do { \
108        radeon_cs_end(b_l_rmesa->cmdbuf.cs, __FILE__, __FUNCTION__, __LINE__);\
109	} while(0)
110
111/**
112 * After the last END_BATCH() of rendering, this indicates that flushing
113 * the command buffer now is okay.
114 */
115#define COMMIT_BATCH() \
116	do { \
117	} while(0)
118
119
120/** Single register write to command buffer; requires 2 dwords. */
121#define OUT_BATCH_REGVAL(reg, val) \
122	OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), 1)); \
123	OUT_BATCH((val))
124
125/** Continuous register range write to command buffer; requires 1 dword,
126 * expects count dwords afterwards for register contents. */
127#define OUT_BATCH_REGSEQ(reg, count) \
128	OUT_BATCH(cmdpacket0(b_l_rmesa->radeonScreen, (reg), (count)));
129
130/** Write a 32 bit float to the ring; requires 1 dword. */
131#define OUT_BATCH_FLOAT32(f) \
132	OUT_BATCH(radeonPackFloat32((f)));
133
134
135/* Fire the buffered vertices no matter what.
136 */
137static INLINE void radeon_firevertices(radeonContextPtr radeon)
138{
139   if (radeon->cmdbuf.cs->cdw || radeon->dma.flush )
140      radeonFlush(radeon->glCtx);
141}
142
143#endif
144