radeon_common_context.h revision 1fcb321e2fa1903b815b099e59bd85aac823850a 
1
2#ifndef COMMON_CONTEXT_H
3#define COMMON_CONTEXT_H
4
5#include "main/mm.h"
6#include "math/m_vector.h"
7#include "texmem.h"
8#include "tnl/t_context.h"
9#include "main/colormac.h"
10
11#include "radeon_screen.h"
12#include "radeon_drm.h"
13#include "dri_util.h"
14#include "tnl/t_vertex.h"
15
16#include "dri_metaops.h"
17struct radeon_context;
18
19#include "radeon_bocs_wrapper.h"
20
21/* This union is used to avoid warnings/miscompilation
22   with float to uint32_t casts due to strict-aliasing */
23typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;
24
25struct radeon_context;
26typedef struct radeon_context radeonContextRec;
27typedef struct radeon_context *radeonContextPtr;
28
29
30#define TEX_0   0x1
31#define TEX_1   0x2
32#define TEX_2   0x4
33#define TEX_3	0x8
34#define TEX_4	0x10
35#define TEX_5	0x20
36
37/* Rasterizing fallbacks */
38/* See correponding strings in r200_swtcl.c */
39#define RADEON_FALLBACK_TEXTURE		0x0001
40#define RADEON_FALLBACK_DRAW_BUFFER	0x0002
41#define RADEON_FALLBACK_STENCIL		0x0004
42#define RADEON_FALLBACK_RENDER_MODE	0x0008
43#define RADEON_FALLBACK_BLEND_EQ	0x0010
44#define RADEON_FALLBACK_BLEND_FUNC	0x0020
45#define RADEON_FALLBACK_DISABLE 	0x0040
46#define RADEON_FALLBACK_BORDER_MODE	0x0080
47#define RADEON_FALLBACK_DEPTH_BUFFER	0x0100
48#define RADEON_FALLBACK_STENCIL_BUFFER  0x0200
49
50#define R200_FALLBACK_TEXTURE           0x01
51#define R200_FALLBACK_DRAW_BUFFER       0x02
52#define R200_FALLBACK_STENCIL           0x04
53#define R200_FALLBACK_RENDER_MODE       0x08
54#define R200_FALLBACK_DISABLE           0x10
55#define R200_FALLBACK_BORDER_MODE       0x20
56
57#define RADEON_TCL_FALLBACK_RASTER            0x1 /* rasterization */
58#define RADEON_TCL_FALLBACK_UNFILLED          0x2 /* unfilled tris */
59#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE     0x4 /* twoside tris */
60#define RADEON_TCL_FALLBACK_MATERIAL          0x8 /* material in vb */
61#define RADEON_TCL_FALLBACK_TEXGEN_0          0x10 /* texgen, unit 0 */
62#define RADEON_TCL_FALLBACK_TEXGEN_1          0x20 /* texgen, unit 1 */
63#define RADEON_TCL_FALLBACK_TEXGEN_2          0x40 /* texgen, unit 2 */
64#define RADEON_TCL_FALLBACK_TCL_DISABLE       0x80 /* user disable */
65#define RADEON_TCL_FALLBACK_FOGCOORDSPEC      0x100 /* fogcoord, sep. spec light */
66
67/* The blit width for texture uploads
68 */
69#define BLIT_WIDTH_BYTES 1024
70
71/* Use the templated vertex format:
72 */
73#define COLOR_IS_RGBA
74#define TAG(x) radeon##x
75#include "tnl_dd/t_dd_vertex.h"
76#undef TAG
77
78#define RADEON_RB_CLASS 0xdeadbeef
79
80struct radeon_renderbuffer
81{
82	struct gl_renderbuffer base;
83	struct radeon_bo *bo;
84	unsigned int cpp;
85	/* unsigned int offset; */
86	unsigned int pitch;
87
88	uint32_t draw_offset; /* FBO */
89	/* boo Xorg 6.8.2 compat */
90	int has_surface;
91
92	GLuint pf_pending;  /**< sequence number of pending flip */
93	GLuint vbl_pending;   /**< vblank sequence number of pending flip */
94	__DRIdrawablePrivate *dPriv;
95};
96
97struct radeon_framebuffer
98{
99	struct gl_framebuffer base;
100
101	struct radeon_renderbuffer *color_rb[2];
102
103	GLuint vbl_waited;
104
105	/* buffer swap */
106	int64_t swap_ust;
107	int64_t swap_missed_ust;
108
109	GLuint swap_count;
110	GLuint swap_missed_count;
111
112	/* Drawable page flipping state */
113	GLboolean pf_active;
114	GLint pf_current_page;
115	GLint pf_num_pages;
116
117};
118
119
120struct radeon_colorbuffer_state {
121	GLuint clear;
122	int roundEnable;
123	struct gl_renderbuffer *rb;
124	uint32_t draw_offset; /* offset into color renderbuffer - FBOs */
125};
126
127struct radeon_depthbuffer_state {
128	GLuint clear;
129	struct gl_renderbuffer *rb;
130};
131
132struct radeon_scissor_state {
133	drm_clip_rect_t rect;
134	GLboolean enabled;
135
136	GLuint numClipRects;	/* Cliprects active */
137	GLuint numAllocedClipRects;	/* Cliprects available */
138	drm_clip_rect_t *pClipRects;
139};
140
141struct radeon_stencilbuffer_state {
142	GLuint clear;		/* rb3d_stencilrefmask value */
143};
144
145struct radeon_stipple_state {
146	GLuint mask[32];
147};
148
149struct radeon_state_atom {
150	struct radeon_state_atom *next, *prev;
151	const char *name;	/* for debug */
152	int cmd_size;		/* size in bytes */
153        GLuint idx;
154	GLuint is_tcl;
155        GLuint *cmd;		/* one or more cmd's */
156	GLuint *lastcmd;		/* one or more cmd's */
157	GLboolean dirty;	/* dirty-mark in emit_state_list */
158        int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */
159        void (*emit) (GLcontext *, struct radeon_state_atom *atom);
160};
161
162struct radeon_hw_state {
163  	/* Head of the linked list of state atoms. */
164	struct radeon_state_atom atomlist;
165	int max_state_size;	/* Number of bytes necessary for a full state emit. */
166	GLboolean is_dirty, all_dirty;
167};
168
169
170/* Texture related */
171typedef struct _radeon_texture_image radeon_texture_image;
172
173struct _radeon_texture_image {
174	struct gl_texture_image base;
175
176	/**
177	 * If mt != 0, the image is stored in hardware format in the
178	 * given mipmap tree. In this case, base.Data may point into the
179	 * mapping of the buffer object that contains the mipmap tree.
180	 *
181	 * If mt == 0, the image is stored in normal memory pointed to
182	 * by base.Data.
183	 */
184	struct _radeon_mipmap_tree *mt;
185	struct radeon_bo *bo;
186
187	int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */
188	int mtface; /** if mt != 0, this is the image's face in the mipmap tree */
189};
190
191
192static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)
193{
194	return (radeon_texture_image*)image;
195}
196
197
198typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;
199
200#define RADEON_TXO_MICRO_TILE               (1 << 3)
201
202/* Texture object in locally shared texture space.
203 */
204struct radeon_tex_obj {
205	struct gl_texture_object base;
206	struct _radeon_mipmap_tree *mt;
207
208	/**
209	 * This is true if we've verified that the mipmap tree above is complete
210	 * and so on.
211	 */
212	GLboolean validated;
213
214	GLuint override_offset;
215	GLboolean image_override; /* Image overridden by GLX_EXT_tfp */
216	GLuint tile_bits;	/* hw texture tile bits used on this texture */
217        struct radeon_bo *bo;
218
219	GLuint pp_txfilter;	/* hardware register values */
220	GLuint pp_txformat;
221	GLuint pp_txformat_x;
222	GLuint pp_txsize;	/* npot only */
223	GLuint pp_txpitch;	/* npot only */
224	GLuint pp_border_color;
225	GLuint pp_cubic_faces;	/* cube face 1,2,3,4 log2 sizes */
226
227        GLuint pp_txfilter_1;	/*  r300 */
228
229	/* r700 texture states */
230	GLuint SQ_TEX_RESOURCE0;
231	GLuint SQ_TEX_RESOURCE1;
232	GLuint SQ_TEX_RESOURCE2;
233	GLuint SQ_TEX_RESOURCE3;
234	GLuint SQ_TEX_RESOURCE4;
235	GLuint SQ_TEX_RESOURCE5;
236	GLuint SQ_TEX_RESOURCE6;
237
238	GLuint SQ_TEX_SAMPLER0;
239	GLuint SQ_TEX_SAMPLER1;
240	GLuint SQ_TEX_SAMPLER2;
241
242	GLuint TD_PS_SAMPLER0_BORDER_RED;
243	GLuint TD_PS_SAMPLER0_BORDER_GREEN;
244	GLuint TD_PS_SAMPLER0_BORDER_BLUE;
245	GLuint TD_PS_SAMPLER0_BORDER_ALPHA;
246
247	GLboolean border_fallback;
248
249
250};
251
252static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)
253{
254	return (radeonTexObj*)texObj;
255}
256
257/* Need refcounting on dma buffers:
258 */
259struct radeon_dma_buffer {
260	int refcount;		/* the number of retained regions in buf */
261	drmBufPtr buf;
262};
263
264struct radeon_aos {
265	struct radeon_bo *bo; /** Buffer object where vertex data is stored */
266	int offset; /** Offset into buffer object, in bytes */
267	int components; /** Number of components per vertex */
268	int stride; /** Stride in dwords (may be 0 for repeating) */
269	int count; /** Number of vertices */
270};
271
272struct radeon_dma {
273        /* Active dma region.  Allocations for vertices and retained
274         * regions come from here.  Also used for emitting random vertices,
275         * these may be flushed by calling flush_current();
276         */
277        struct radeon_bo *current; /** Buffer that DMA memory is allocated from */
278        int current_used; /** Number of bytes allocated and forgotten about */
279        int current_vertexptr; /** End of active vertex region */
280
281        /**
282         * If current_vertexptr != current_used then flush must be non-zero.
283         * flush must be called before non-active vertex allocations can be
284         * performed.
285         */
286        void (*flush) (GLcontext *);
287
288        /* Number of "in-flight" DMA buffers, i.e. the number of buffers
289         * for which a DISCARD command is currently queued in the command buffer
290.
291         */
292        GLuint nr_released_bufs;
293};
294
295/* radeon_swtcl.c
296 */
297struct radeon_swtcl_info {
298
299	GLuint RenderIndex;
300	GLuint vertex_size;
301	GLubyte *verts;
302
303	/* Fallback rasterization functions
304	 */
305	GLuint hw_primitive;
306	GLenum render_primitive;
307	GLuint numverts;
308
309	struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
310	GLuint vertex_attr_count;
311
312};
313
314#define RADEON_MAX_AOS_ARRAYS		16
315struct radeon_tcl_info {
316	struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];
317	GLuint aos_count;
318	struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */
319	int elt_dma_offset; /** Offset into this buffer object, in bytes */
320};
321
322struct radeon_ioctl {
323	GLuint vertex_offset;
324        struct radeon_bo *bo;
325	GLuint vertex_size;
326};
327
328#define RADEON_MAX_PRIMS 64
329
330struct radeon_prim {
331	GLuint start;
332	GLuint end;
333	GLuint prim;
334};
335
336static INLINE GLuint radeonPackColor(GLuint cpp,
337                                     GLubyte r, GLubyte g,
338                                     GLubyte b, GLubyte a)
339{
340	switch (cpp) {
341	case 2:
342		return PACK_COLOR_565(r, g, b);
343	case 4:
344		return PACK_COLOR_8888(a, r, g, b);
345	default:
346		return 0;
347	}
348}
349
350#define MAX_CMD_BUF_SZ (16*1024)
351
352#define MAX_DMA_BUF_SZ (64*1024)
353
354struct radeon_store {
355	GLuint statenr;
356	GLuint primnr;
357	char cmd_buf[MAX_CMD_BUF_SZ];
358	int cmd_used;
359	int elts_start;
360};
361
362struct radeon_dri_mirror {
363	__DRIcontextPrivate *context;	/* DRI context */
364	__DRIscreenPrivate *screen;	/* DRI screen */
365
366	drm_context_t hwContext;
367	drm_hw_lock_t *hwLock;
368	int fd;
369	int drmMinor;
370};
371
372#define DEBUG_TEXTURE	0x001
373#define DEBUG_STATE	0x002
374#define DEBUG_IOCTL	0x004
375#define DEBUG_PRIMS	0x008
376#define DEBUG_VERTS	0x010
377#define DEBUG_FALLBACKS	0x020
378#define DEBUG_VFMT	0x040
379#define DEBUG_CODEGEN	0x080
380#define DEBUG_VERBOSE	0x100
381#define DEBUG_DRI       0x200
382#define DEBUG_DMA       0x400
383#define DEBUG_SANITY    0x800
384#define DEBUG_SYNC      0x1000
385#define DEBUG_PIXEL     0x2000
386#define DEBUG_MEMORY    0x4000
387
388
389typedef void (*radeon_tri_func) (radeonContextPtr,
390				 radeonVertex *,
391				 radeonVertex *, radeonVertex *);
392
393typedef void (*radeon_line_func) (radeonContextPtr,
394				  radeonVertex *, radeonVertex *);
395
396typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);
397
398#define RADEON_MAX_BOS 32
399struct radeon_state {
400	struct radeon_colorbuffer_state color;
401	struct radeon_depthbuffer_state depth;
402	struct radeon_scissor_state scissor;
403	struct radeon_stencilbuffer_state stencil;
404
405	struct radeon_cs_space_check bos[RADEON_MAX_BOS];
406	int validated_bo_count;
407};
408
409/**
410 * This structure holds the command buffer while it is being constructed.
411 *
412 * The first batch of commands in the buffer is always the state that needs
413 * to be re-emitted when the context is lost. This batch can be skipped
414 * otherwise.
415 */
416struct radeon_cmdbuf {
417	struct radeon_cs_manager    *csm;
418	struct radeon_cs            *cs;
419	int size; /** # of dwords total */
420	unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */
421};
422
423struct radeon_context {
424   GLcontext *glCtx;
425   radeonScreenPtr radeonScreen;	/* Screen private DRI data */
426
427   /* Texture object bookkeeping
428    */
429   int                   texture_depth;
430   float                 initialMaxAnisotropy;
431   uint32_t              texture_row_align;
432   uint32_t              texture_rect_row_align;
433   uint32_t              texture_compressed_row_align;
434
435  struct radeon_dma dma;
436  struct radeon_hw_state hw;
437   /* Rasterization and vertex state:
438    */
439   GLuint TclFallback;
440   GLuint Fallback;
441   GLuint NewGLState;
442   DECLARE_RENDERINPUTS(tnl_index_bitset);	/* index of bits for last tnl_install_attrs */
443
444   /* Drawable, cliprect and scissor information */
445   GLuint numClipRects;	/* Cliprects for the draw buffer */
446   drm_clip_rect_t *pClipRects;
447   unsigned int lastStamp;
448   drm_radeon_sarea_t *sarea;	/* Private SAREA data */
449
450   /* Mirrors of some DRI state */
451   struct radeon_dri_mirror dri;
452
453   /* Busy waiting */
454   GLuint do_usleeps;
455   GLuint do_irqs;
456   GLuint irqsEmitted;
457   drm_radeon_irq_wait_t iw;
458
459   /* Derived state - for r300 only */
460   struct radeon_state state;
461
462   struct radeon_swtcl_info swtcl;
463   struct radeon_tcl_info tcl;
464   /* Configuration cache
465    */
466   driOptionCache optionCache;
467
468   struct radeon_cmdbuf cmdbuf;
469
470  drm_clip_rect_t fboRect;
471  GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */
472  GLboolean front_cliprects;
473
474   /**
475    * Set if rendering has occured to the drawable's front buffer.
476    *
477    * This is used in the DRI2 case to detect that glFlush should also copy
478    * the contents of the fake front buffer to the real front buffer.
479    */
480   GLboolean front_buffer_dirty;
481
482   /**
483    * Track whether front-buffer rendering is currently enabled
484    *
485    * A separate flag is used to track this in order to support MRT more
486    * easily.
487    */
488   GLboolean is_front_buffer_rendering;
489
490   /**
491    * Track whether front-buffer is the current read target.
492    *
493    * This is closely associated with is_front_buffer_rendering, but may
494    * be set separately.  The DRI2 fake front buffer must be referenced
495    * either way.
496    */
497   GLboolean is_front_buffer_reading;
498
499   struct dri_metaops meta;
500
501   struct {
502	   void (*get_lock)(radeonContextPtr radeon);
503	   void (*update_viewport_offset)(GLcontext *ctx);
504	   void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);
505	   void (*swtcl_flush)(GLcontext *ctx, uint32_t offset);
506	   void (*pre_emit_atoms)(radeonContextPtr rmesa);
507	   void (*pre_emit_state)(radeonContextPtr rmesa);
508	   void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode);
509	   void (*free_context)(GLcontext *ctx);
510   } vtbl;
511};
512
513#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
514
515static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon)
516{
517	return radeon->dri.context->driDrawablePriv;
518}
519
520static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon)
521{
522	return radeon->dri.context->driReadablePriv;
523}
524
525
526/**
527 * This function takes a float and packs it into a uint32_t
528 */
529static INLINE uint32_t radeonPackFloat32(float fl)
530{
531	union {
532		float fl;
533		uint32_t u;
534	} u;
535
536	u.fl = fl;
537	return u.u;
538}
539
540/* This is probably wrong for some values, I need to test this
541 * some more.  Range checking would be a good idea also..
542 *
543 * But it works for most things.  I'll fix it later if someone
544 * else with a better clue doesn't
545 */
546static INLINE uint32_t radeonPackFloat24(float f)
547{
548	float mantissa;
549	int exponent;
550	uint32_t float24 = 0;
551
552	if (f == 0.0)
553		return 0;
554
555	mantissa = frexpf(f, &exponent);
556
557	/* Handle -ve */
558	if (mantissa < 0) {
559		float24 |= (1 << 23);
560		mantissa = mantissa * -1.0;
561	}
562	/* Handle exponent, bias of 63 */
563	exponent += 62;
564	float24 |= (exponent << 16);
565	/* Kill 7 LSB of mantissa */
566	float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;
567
568	return float24;
569}
570
571GLboolean radeonInitContext(radeonContextPtr radeon,
572			    struct dd_function_table* functions,
573			    const __GLcontextModes * glVisual,
574			    __DRIcontextPrivate * driContextPriv,
575			    void *sharedContextPrivate);
576
577void radeonCleanupContext(radeonContextPtr radeon);
578GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv);
579void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable);
580GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
581			    __DRIdrawablePrivate * driDrawPriv,
582			    __DRIdrawablePrivate * driReadPriv);
583extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv);
584
585/* ================================================================
586 * Debugging:
587 */
588#define DO_DEBUG		1
589
590#if DO_DEBUG
591extern int RADEON_DEBUG;
592#else
593#define RADEON_DEBUG		0
594#endif
595
596#ifndef HAVE_LIBDRM_RADEON
597#ifndef RADEON_DEBUG_BO
598#define RADEON_DEBUG_BO 1
599#endif
600#endif
601
602#endif
603