radeon_common_context.h revision f6f0e117a45a64464e49290ebc9f75b9a976070a
1 2#ifndef COMMON_CONTEXT_H 3#define COMMON_CONTEXT_H 4 5#include "main/mm.h" 6#include "math/m_vector.h" 7#include "texmem.h" 8#include "tnl/t_context.h" 9#include "main/colormac.h" 10 11#include "radeon_screen.h" 12#include "radeon_drm.h" 13#include "dri_util.h" 14#include "tnl/t_vertex.h" 15 16#include "dri_metaops.h" 17struct radeon_context; 18 19#include "radeon_bocs_wrapper.h" 20 21/* This union is used to avoid warnings/miscompilation 22 with float to uint32_t casts due to strict-aliasing */ 23typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; 24 25struct radeon_context; 26typedef struct radeon_context radeonContextRec; 27typedef struct radeon_context *radeonContextPtr; 28 29 30#define TEX_0 0x1 31#define TEX_1 0x2 32#define TEX_2 0x4 33#define TEX_3 0x8 34#define TEX_4 0x10 35#define TEX_5 0x20 36 37/* Rasterizing fallbacks */ 38/* See correponding strings in r200_swtcl.c */ 39#define RADEON_FALLBACK_TEXTURE 0x0001 40#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 41#define RADEON_FALLBACK_STENCIL 0x0004 42#define RADEON_FALLBACK_RENDER_MODE 0x0008 43#define RADEON_FALLBACK_BLEND_EQ 0x0010 44#define RADEON_FALLBACK_BLEND_FUNC 0x0020 45#define RADEON_FALLBACK_DISABLE 0x0040 46#define RADEON_FALLBACK_BORDER_MODE 0x0080 47#define RADEON_FALLBACK_DEPTH_BUFFER 0x0100 48#define RADEON_FALLBACK_STENCIL_BUFFER 0x0200 49 50#define R200_FALLBACK_TEXTURE 0x01 51#define R200_FALLBACK_DRAW_BUFFER 0x02 52#define R200_FALLBACK_STENCIL 0x04 53#define R200_FALLBACK_RENDER_MODE 0x08 54#define R200_FALLBACK_DISABLE 0x10 55#define R200_FALLBACK_BORDER_MODE 0x20 56 57#define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */ 58#define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ 59#define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ 60#define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ 61#define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ 62#define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ 63#define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ 64#define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */ 65#define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */ 66 67/* The blit width for texture uploads 68 */ 69#define BLIT_WIDTH_BYTES 1024 70 71/* Use the templated vertex format: 72 */ 73#define COLOR_IS_RGBA 74#define TAG(x) radeon##x 75#include "tnl_dd/t_dd_vertex.h" 76#undef TAG 77 78#define RADEON_RB_CLASS 0xdeadbeef 79 80struct radeon_renderbuffer 81{ 82 struct gl_renderbuffer base; 83 struct radeon_bo *bo; 84 unsigned int cpp; 85 /* unsigned int offset; */ 86 unsigned int pitch; 87 88 uint32_t draw_offset; /* FBO */ 89 /* boo Xorg 6.8.2 compat */ 90 int has_surface; 91 92 GLuint pf_pending; /**< sequence number of pending flip */ 93 GLuint vbl_pending; /**< vblank sequence number of pending flip */ 94 __DRIdrawablePrivate *dPriv; 95}; 96 97struct radeon_framebuffer 98{ 99 struct gl_framebuffer base; 100 101 struct radeon_renderbuffer *color_rb[2]; 102 103 GLuint vbl_waited; 104 105 /* buffer swap */ 106 int64_t swap_ust; 107 int64_t swap_missed_ust; 108 109 GLuint swap_count; 110 GLuint swap_missed_count; 111 112 /* Drawable page flipping state */ 113 GLboolean pf_active; 114 GLint pf_current_page; 115 GLint pf_num_pages; 116 117}; 118 119 120struct radeon_colorbuffer_state { 121 GLuint clear; 122 int roundEnable; 123 struct gl_renderbuffer *rb; 124 uint32_t draw_offset; /* offset into color renderbuffer - FBOs */ 125}; 126 127struct radeon_depthbuffer_state { 128 GLuint clear; 129 struct gl_renderbuffer *rb; 130}; 131 132struct radeon_scissor_state { 133 drm_clip_rect_t rect; 134 GLboolean enabled; 135 136 GLuint numClipRects; /* Cliprects active */ 137 GLuint numAllocedClipRects; /* Cliprects available */ 138 drm_clip_rect_t *pClipRects; 139}; 140 141struct radeon_stencilbuffer_state { 142 GLuint clear; /* rb3d_stencilrefmask value */ 143}; 144 145struct radeon_stipple_state { 146 GLuint mask[32]; 147}; 148 149struct radeon_state_atom { 150 struct radeon_state_atom *next, *prev; 151 const char *name; /* for debug */ 152 int cmd_size; /* size in bytes */ 153 GLuint idx; 154 GLuint is_tcl; 155 GLuint *cmd; /* one or more cmd's */ 156 GLuint *lastcmd; /* one or more cmd's */ 157 GLboolean dirty; /* dirty-mark in emit_state_list */ 158 int (*check) (GLcontext *, struct radeon_state_atom *atom); /* is this state active? */ 159 void (*emit) (GLcontext *, struct radeon_state_atom *atom); 160}; 161 162struct radeon_hw_state { 163 /* Head of the linked list of state atoms. */ 164 struct radeon_state_atom atomlist; 165 int max_state_size; /* Number of bytes necessary for a full state emit. */ 166 GLboolean is_dirty, all_dirty; 167}; 168 169 170/* Texture related */ 171typedef struct _radeon_texture_image radeon_texture_image; 172 173struct _radeon_texture_image { 174 struct gl_texture_image base; 175 176 /** 177 * If mt != 0, the image is stored in hardware format in the 178 * given mipmap tree. In this case, base.Data may point into the 179 * mapping of the buffer object that contains the mipmap tree. 180 * 181 * If mt == 0, the image is stored in normal memory pointed to 182 * by base.Data. 183 */ 184 struct _radeon_mipmap_tree *mt; 185 struct radeon_bo *bo; 186 187 int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */ 188 int mtface; /** if mt != 0, this is the image's face in the mipmap tree */ 189}; 190 191 192static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image) 193{ 194 return (radeon_texture_image*)image; 195} 196 197 198typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 199 200#define RADEON_TXO_MICRO_TILE (1 << 3) 201 202/* Texture object in locally shared texture space. 203 */ 204struct radeon_tex_obj { 205 struct gl_texture_object base; 206 struct _radeon_mipmap_tree *mt; 207 208 /** 209 * This is true if we've verified that the mipmap tree above is complete 210 * and so on. 211 */ 212 GLboolean validated; 213 214 GLuint override_offset; 215 GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ 216 GLuint tile_bits; /* hw texture tile bits used on this texture */ 217 struct radeon_bo *bo; 218 219 GLuint pp_txfilter; /* hardware register values */ 220 GLuint pp_txformat; 221 GLuint pp_txformat_x; 222 GLuint pp_txsize; /* npot only */ 223 GLuint pp_txpitch; /* npot only */ 224 GLuint pp_border_color; 225 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 226 227 GLuint pp_txfilter_1; /* r300 */ 228 229 GLboolean border_fallback; 230 231 232}; 233 234static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj) 235{ 236 return (radeonTexObj*)texObj; 237} 238 239/* Need refcounting on dma buffers: 240 */ 241struct radeon_dma_buffer { 242 int refcount; /* the number of retained regions in buf */ 243 drmBufPtr buf; 244}; 245 246struct radeon_aos { 247 struct radeon_bo *bo; /** Buffer object where vertex data is stored */ 248 int offset; /** Offset into buffer object, in bytes */ 249 int components; /** Number of components per vertex */ 250 int stride; /** Stride in dwords (may be 0 for repeating) */ 251 int count; /** Number of vertices */ 252}; 253 254struct radeon_dma { 255 /* Active dma region. Allocations for vertices and retained 256 * regions come from here. Also used for emitting random vertices, 257 * these may be flushed by calling flush_current(); 258 */ 259 struct radeon_bo *current; /** Buffer that DMA memory is allocated from */ 260 int current_used; /** Number of bytes allocated and forgotten about */ 261 int current_vertexptr; /** End of active vertex region */ 262 263 /** 264 * If current_vertexptr != current_used then flush must be non-zero. 265 * flush must be called before non-active vertex allocations can be 266 * performed. 267 */ 268 void (*flush) (GLcontext *); 269 270 /* Number of "in-flight" DMA buffers, i.e. the number of buffers 271 * for which a DISCARD command is currently queued in the command buffer 272. 273 */ 274 GLuint nr_released_bufs; 275}; 276 277/* radeon_swtcl.c 278 */ 279struct radeon_swtcl_info { 280 281 GLuint RenderIndex; 282 GLuint vertex_size; 283 GLubyte *verts; 284 285 /* Fallback rasterization functions 286 */ 287 GLuint hw_primitive; 288 GLenum render_primitive; 289 GLuint numverts; 290 291 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 292 GLuint vertex_attr_count; 293 294}; 295 296#define RADEON_MAX_AOS_ARRAYS 16 297struct radeon_tcl_info { 298 struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS]; 299 GLuint aos_count; 300 struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */ 301 int elt_dma_offset; /** Offset into this buffer object, in bytes */ 302}; 303 304struct radeon_ioctl { 305 GLuint vertex_offset; 306 struct radeon_bo *bo; 307 GLuint vertex_size; 308}; 309 310#define RADEON_MAX_PRIMS 64 311 312struct radeon_prim { 313 GLuint start; 314 GLuint end; 315 GLuint prim; 316}; 317 318static INLINE GLuint radeonPackColor(GLuint cpp, 319 GLubyte r, GLubyte g, 320 GLubyte b, GLubyte a) 321{ 322 switch (cpp) { 323 case 2: 324 return PACK_COLOR_565(r, g, b); 325 case 4: 326 return PACK_COLOR_8888(a, r, g, b); 327 default: 328 return 0; 329 } 330} 331 332#define MAX_CMD_BUF_SZ (16*1024) 333 334#define MAX_DMA_BUF_SZ (64*1024) 335 336struct radeon_store { 337 GLuint statenr; 338 GLuint primnr; 339 char cmd_buf[MAX_CMD_BUF_SZ]; 340 int cmd_used; 341 int elts_start; 342}; 343 344struct radeon_dri_mirror { 345 __DRIcontextPrivate *context; /* DRI context */ 346 __DRIscreenPrivate *screen; /* DRI screen */ 347 348 drm_context_t hwContext; 349 drm_hw_lock_t *hwLock; 350 int fd; 351 int drmMinor; 352}; 353 354#define DEBUG_TEXTURE 0x001 355#define DEBUG_STATE 0x002 356#define DEBUG_IOCTL 0x004 357#define DEBUG_PRIMS 0x008 358#define DEBUG_VERTS 0x010 359#define DEBUG_FALLBACKS 0x020 360#define DEBUG_VFMT 0x040 361#define DEBUG_CODEGEN 0x080 362#define DEBUG_VERBOSE 0x100 363#define DEBUG_DRI 0x200 364#define DEBUG_DMA 0x400 365#define DEBUG_SANITY 0x800 366#define DEBUG_SYNC 0x1000 367#define DEBUG_PIXEL 0x2000 368#define DEBUG_MEMORY 0x4000 369 370 371typedef void (*radeon_tri_func) (radeonContextPtr, 372 radeonVertex *, 373 radeonVertex *, radeonVertex *); 374 375typedef void (*radeon_line_func) (radeonContextPtr, 376 radeonVertex *, radeonVertex *); 377 378typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); 379 380#define RADEON_MAX_BOS 32 381struct radeon_state { 382 struct radeon_colorbuffer_state color; 383 struct radeon_depthbuffer_state depth; 384 struct radeon_scissor_state scissor; 385 struct radeon_stencilbuffer_state stencil; 386 387 struct radeon_cs_space_check bos[RADEON_MAX_BOS]; 388 int validated_bo_count; 389}; 390 391/** 392 * This structure holds the command buffer while it is being constructed. 393 * 394 * The first batch of commands in the buffer is always the state that needs 395 * to be re-emitted when the context is lost. This batch can be skipped 396 * otherwise. 397 */ 398struct radeon_cmdbuf { 399 struct radeon_cs_manager *csm; 400 struct radeon_cs *cs; 401 int size; /** # of dwords total */ 402 unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */ 403}; 404 405struct radeon_context { 406 GLcontext *glCtx; 407 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 408 409 /* Texture object bookkeeping 410 */ 411 int texture_depth; 412 float initialMaxAnisotropy; 413 uint32_t texture_row_align; 414 415 struct radeon_dma dma; 416 struct radeon_hw_state hw; 417 /* Rasterization and vertex state: 418 */ 419 GLuint TclFallback; 420 GLuint Fallback; 421 GLuint NewGLState; 422 DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ 423 424 /* Drawable, cliprect and scissor information */ 425 GLuint numClipRects; /* Cliprects for the draw buffer */ 426 drm_clip_rect_t *pClipRects; 427 unsigned int lastStamp; 428 GLboolean lost_context; 429 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 430 431 /* Mirrors of some DRI state */ 432 struct radeon_dri_mirror dri; 433 434 /* Busy waiting */ 435 GLuint do_usleeps; 436 GLuint do_irqs; 437 GLuint irqsEmitted; 438 drm_radeon_irq_wait_t iw; 439 440 /* Derived state - for r300 only */ 441 struct radeon_state state; 442 443 struct radeon_swtcl_info swtcl; 444 struct radeon_tcl_info tcl; 445 /* Configuration cache 446 */ 447 driOptionCache optionCache; 448 449 struct radeon_cmdbuf cmdbuf; 450 451 drm_clip_rect_t fboRect; 452 GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */ 453 GLboolean front_cliprects; 454 455 /** 456 * Set if rendering has occured to the drawable's front buffer. 457 * 458 * This is used in the DRI2 case to detect that glFlush should also copy 459 * the contents of the fake front buffer to the real front buffer. 460 */ 461 GLboolean front_buffer_dirty; 462 463 /** 464 * Track whether front-buffer rendering is currently enabled 465 * 466 * A separate flag is used to track this in order to support MRT more 467 * easily. 468 */ 469 GLboolean is_front_buffer_rendering; 470 471 /** 472 * Track whether front-buffer is the current read target. 473 * 474 * This is closely associated with is_front_buffer_rendering, but may 475 * be set separately. The DRI2 fake front buffer must be referenced 476 * either way. 477 */ 478 GLboolean is_front_buffer_reading; 479 480 struct dri_metaops meta; 481 482 struct { 483 void (*get_lock)(radeonContextPtr radeon); 484 void (*update_viewport_offset)(GLcontext *ctx); 485 void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa); 486 void (*swtcl_flush)(GLcontext *ctx, uint32_t offset); 487 void (*pre_emit_atoms)(radeonContextPtr rmesa); 488 void (*pre_emit_state)(radeonContextPtr rmesa); 489 void (*fallback)(GLcontext *ctx, GLuint bit, GLboolean mode); 490 void (*free_context)(GLcontext *ctx); 491 } vtbl; 492}; 493 494#define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) 495 496static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon) 497{ 498 return radeon->dri.context->driDrawablePriv; 499} 500 501static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon) 502{ 503 return radeon->dri.context->driReadablePriv; 504} 505 506 507/** 508 * This function takes a float and packs it into a uint32_t 509 */ 510static INLINE uint32_t radeonPackFloat32(float fl) 511{ 512 union { 513 float fl; 514 uint32_t u; 515 } u; 516 517 u.fl = fl; 518 return u.u; 519} 520 521/* This is probably wrong for some values, I need to test this 522 * some more. Range checking would be a good idea also.. 523 * 524 * But it works for most things. I'll fix it later if someone 525 * else with a better clue doesn't 526 */ 527static INLINE uint32_t radeonPackFloat24(float f) 528{ 529 float mantissa; 530 int exponent; 531 uint32_t float24 = 0; 532 533 if (f == 0.0) 534 return 0; 535 536 mantissa = frexpf(f, &exponent); 537 538 /* Handle -ve */ 539 if (mantissa < 0) { 540 float24 |= (1 << 23); 541 mantissa = mantissa * -1.0; 542 } 543 /* Handle exponent, bias of 63 */ 544 exponent += 62; 545 float24 |= (exponent << 16); 546 /* Kill 7 LSB of mantissa */ 547 float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7; 548 549 return float24; 550} 551 552GLboolean radeonInitContext(radeonContextPtr radeon, 553 struct dd_function_table* functions, 554 const __GLcontextModes * glVisual, 555 __DRIcontextPrivate * driContextPriv, 556 void *sharedContextPrivate); 557 558void radeonCleanupContext(radeonContextPtr radeon); 559GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); 560void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable); 561GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, 562 __DRIdrawablePrivate * driDrawPriv, 563 __DRIdrawablePrivate * driReadPriv); 564extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); 565 566/* ================================================================ 567 * Debugging: 568 */ 569#define DO_DEBUG 1 570 571#if DO_DEBUG 572extern int RADEON_DEBUG; 573#else 574#define RADEON_DEBUG 0 575#endif 576 577#endif 578