radeon_context.c revision 150ed2e43d5541556d282cae728cebeec692e07a 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/*
32 * Authors:
33 *   Kevin E. Martin <martin@valinux.com>
34 *   Gareth Hughes <gareth@valinux.com>
35 *   Keith Whitwell <keith@tungstengraphics.com>
36 */
37
38#include "glheader.h"
39#include "api_arrayelt.h"
40#include "context.h"
41#include "simple_list.h"
42#include "imports.h"
43#include "matrix.h"
44#include "extensions.h"
45
46#include "swrast/swrast.h"
47#include "swrast_setup/swrast_setup.h"
48#include "array_cache/acache.h"
49
50#include "tnl/tnl.h"
51#include "tnl/t_pipeline.h"
52
53#include "drivers/common/driverfuncs.h"
54
55#include "radeon_context.h"
56#include "radeon_ioctl.h"
57#include "radeon_state.h"
58#include "radeon_span.h"
59#include "radeon_tex.h"
60#include "radeon_swtcl.h"
61#include "radeon_tcl.h"
62#include "radeon_vtxfmt.h"
63#include "radeon_maos.h"
64
65#define DRIVER_DATE	"20041207"
66
67#include "vblank.h"
68#include "utils.h"
69#include "xmlpool.h" /* for symbolic values of enum-type options */
70#ifndef RADEON_DEBUG
71int RADEON_DEBUG = (0);
72#endif
73
74
75/* Return the width and height of the given buffer.
76 */
77static void radeonGetBufferSize( GLframebuffer *buffer,
78				 GLuint *width, GLuint *height )
79{
80   GET_CURRENT_CONTEXT(ctx);
81   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
82
83   LOCK_HARDWARE( rmesa );
84   *width  = rmesa->dri.drawable->w;
85   *height = rmesa->dri.drawable->h;
86   UNLOCK_HARDWARE( rmesa );
87}
88
89/* Return various strings for glGetString().
90 */
91static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name )
92{
93   radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
94   static char buffer[128];
95   unsigned   offset;
96   GLuint agp_mode = rmesa->radeonScreen->IsPCI ? 0 :
97      rmesa->radeonScreen->AGPMode;
98
99   switch ( name ) {
100   case GL_VENDOR:
101      return (GLubyte *)"Tungsten Graphics, Inc.";
102
103   case GL_RENDERER:
104      offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE,
105				     agp_mode );
106
107      sprintf( & buffer[ offset ], " %sTCL",
108	       !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
109	       ? "" : "NO-" );
110
111      return (GLubyte *)buffer;
112
113   default:
114      return NULL;
115   }
116}
117
118
119/* Extension strings exported by the R100 driver.
120 */
121static const char * const card_extensions[] =
122{
123    "GL_ARB_multisample",
124    "GL_ARB_multitexture",
125    "GL_ARB_texture_border_clamp",
126    "GL_ARB_texture_compression",
127    "GL_ARB_texture_env_add",
128    "GL_ARB_texture_env_combine",
129    "GL_ARB_texture_env_crossbar",
130    "GL_ARB_texture_env_dot3",
131    "GL_ARB_texture_mirrored_repeat",
132    "GL_EXT_blend_logic_op",
133    "GL_EXT_blend_subtract",
134    "GL_EXT_secondary_color",
135    "GL_EXT_stencil_wrap",
136    "GL_EXT_texture_edge_clamp",
137    "GL_EXT_texture_env_combine",
138    "GL_EXT_texture_env_dot3",
139    "GL_EXT_texture_filter_anisotropic",
140    "GL_EXT_texture_lod_bias",
141    "GL_EXT_texture_mirror_clamp",
142    "GL_ATI_texture_env_combine3",
143    "GL_ATI_texture_mirror_once",
144    "GL_MESA_ycbcr_texture",
145    "GL_NV_blend_square",
146    "GL_SGIS_generate_mipmap",
147    NULL
148};
149
150extern const struct tnl_pipeline_stage _radeon_texrect_stage;
151extern const struct tnl_pipeline_stage _radeon_render_stage;
152extern const struct tnl_pipeline_stage _radeon_tcl_stage;
153
154static const struct tnl_pipeline_stage *radeon_pipeline[] = {
155
156   /* Try and go straight to t&l
157    */
158   &_radeon_tcl_stage,
159
160   /* Catch any t&l fallbacks
161    */
162   &_tnl_vertex_transform_stage,
163   &_tnl_normal_transform_stage,
164   &_tnl_lighting_stage,
165   &_tnl_fog_coordinate_stage,
166   &_tnl_texgen_stage,
167   &_tnl_texture_transform_stage,
168
169   /* Scale texture rectangle to 0..1.
170    */
171   &_radeon_texrect_stage,
172
173   &_radeon_render_stage,
174   &_tnl_render_stage,		/* FALLBACK:  */
175   0,
176};
177
178
179
180/* Initialize the driver's misc functions.
181 */
182static void radeonInitDriverFuncs( struct dd_function_table *functions )
183{
184    functions->GetBufferSize	= radeonGetBufferSize;
185    functions->ResizeBuffers	= _swrast_alloc_buffers;
186    functions->GetString	= radeonGetString;
187}
188
189static const struct dri_debug_control debug_control[] =
190{
191    { "fall",  DEBUG_FALLBACKS },
192    { "tex",   DEBUG_TEXTURE },
193    { "ioctl", DEBUG_IOCTL },
194    { "prim",  DEBUG_PRIMS },
195    { "vert",  DEBUG_VERTS },
196    { "state", DEBUG_STATE },
197    { "code",  DEBUG_CODEGEN },
198    { "vfmt",  DEBUG_VFMT },
199    { "vtxf",  DEBUG_VFMT },
200    { "verb",  DEBUG_VERBOSE },
201    { "dri",   DEBUG_DRI },
202    { "dma",   DEBUG_DMA },
203    { "san",   DEBUG_SANITY },
204    { "sync",  DEBUG_SYNC },
205    { NULL,    0 }
206};
207
208
209static int
210get_ust_nop( int64_t * ust )
211{
212   *ust = 1;
213   return 0;
214}
215
216
217/* Create the device specific context.
218 */
219GLboolean
220radeonCreateContext( const __GLcontextModes *glVisual,
221                     __DRIcontextPrivate *driContextPriv,
222                     void *sharedContextPrivate)
223{
224   __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
225   radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private);
226   struct dd_function_table functions;
227   radeonContextPtr rmesa;
228   GLcontext *ctx, *shareCtx;
229   int i;
230   int tcl_mode, fthrottle_mode;
231
232   assert(glVisual);
233   assert(driContextPriv);
234   assert(screen);
235
236   /* Allocate the Radeon context */
237   rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) );
238   if ( !rmesa )
239      return GL_FALSE;
240
241   /* Parse configuration files.
242    * Do this here so that initialMaxAnisotropy is set before we create
243    * the default textures.
244    */
245   driParseConfigFiles (&rmesa->optionCache, &screen->optionCache,
246			screen->driScreen->myNum, "radeon");
247   rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
248                                                 "def_max_anisotropy");
249
250   if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
251      if ( sPriv->drmMinor < 13 )
252	 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
253			  "disabling.\n",sPriv->drmMinor );
254      else
255	 rmesa->using_hyperz = GL_TRUE;
256   }
257
258   /* Init default driver functions then plug in our Radeon-specific functions
259    * (the texture functions are especially important)
260    */
261   _mesa_init_driver_functions( &functions );
262   radeonInitDriverFuncs( &functions );
263   radeonInitTextureFuncs( &functions );
264
265   /* Allocate the Mesa context */
266   if (sharedContextPrivate)
267      shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx;
268   else
269      shareCtx = NULL;
270   rmesa->glCtx = _mesa_create_context(glVisual, shareCtx,
271                                       &functions, (void *) rmesa);
272   if (!rmesa->glCtx) {
273      FREE(rmesa);
274      return GL_FALSE;
275   }
276   driContextPriv->driverPrivate = rmesa;
277
278   /* Init radeon context data */
279   rmesa->dri.context = driContextPriv;
280   rmesa->dri.screen = sPriv;
281   rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */
282   rmesa->dri.hwContext = driContextPriv->hHWContext;
283   rmesa->dri.hwLock = &sPriv->pSAREA->lock;
284   rmesa->dri.fd = sPriv->fd;
285   rmesa->dri.drmMinor = sPriv->drmMinor;
286
287   rmesa->radeonScreen = screen;
288   rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
289				       screen->sarea_priv_offset);
290
291
292   rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address;
293
294   (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) );
295   make_empty_list( & rmesa->swapped );
296
297   rmesa->nr_heaps = screen->numTexHeaps;
298   for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
299      rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa,
300	    screen->texSize[i],
301	    12,
302	    RADEON_NR_TEX_REGIONS,
303	    (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
304	    & rmesa->sarea->tex_age[i],
305	    & rmesa->swapped,
306	    sizeof( radeonTexObj ),
307	    (destroy_texture_object_t *) radeonDestroyTexObj );
308
309      driSetTextureSwapCounterLocation( rmesa->texture_heaps[i],
310					& rmesa->c_textureSwaps );
311   }
312   rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache,
313					   "texture_depth");
314   if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
315      rmesa->texture_depth = ( screen->cpp == 4 ) ?
316	 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
317
318   rmesa->swtcl.RenderIndex = ~0;
319   rmesa->hw.all_dirty = GL_TRUE;
320
321   /* Set the maximum texture size small enough that we can guarentee that
322    * all texture units can bind a maximal texture and have them both in
323    * texturable memory at once.
324    */
325
326   ctx = rmesa->glCtx;
327   ctx->Const.MaxTextureUnits = 2;
328   ctx->Const.MaxTextureImageUnits = 2;
329   ctx->Const.MaxTextureCoordUnits = 2;
330
331   driCalculateMaxTextureLevels( rmesa->texture_heaps,
332				 rmesa->nr_heaps,
333				 & ctx->Const,
334				 4,
335				 11, /* max 2D texture size is 2048x2048 */
336				 0,  /* 3D textures unsupported. */
337				 0,  /* cube textures unsupported. */
338				 11, /* max rect texture size is 2048x2048. */
339				 12,
340				 GL_FALSE );
341
342   ctx->Const.MaxTextureMaxAnisotropy = 16.0;
343
344   /* No wide points.
345    */
346   ctx->Const.MinPointSize = 1.0;
347   ctx->Const.MinPointSizeAA = 1.0;
348   ctx->Const.MaxPointSize = 1.0;
349   ctx->Const.MaxPointSizeAA = 1.0;
350
351   ctx->Const.MinLineWidth = 1.0;
352   ctx->Const.MinLineWidthAA = 1.0;
353   ctx->Const.MaxLineWidth = 10.0;
354   ctx->Const.MaxLineWidthAA = 10.0;
355   ctx->Const.LineWidthGranularity = 0.0625;
356
357   /* Set maxlocksize (and hence vb size) small enough to avoid
358    * fallbacks in radeon_tcl.c.  ie. guarentee that all vertices can
359    * fit in a single dma buffer for indexed rendering of quad strips,
360    * etc.
361    */
362   ctx->Const.MaxArrayLockSize =
363      MIN2( ctx->Const.MaxArrayLockSize,
364 	    RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE );
365
366   rmesa->boxes = 0;
367
368   /* Initialize the software rasterizer and helper modules.
369    */
370   _swrast_CreateContext( ctx );
371   _ac_CreateContext( ctx );
372   _tnl_CreateContext( ctx );
373   _swsetup_CreateContext( ctx );
374   _ae_create_context( ctx );
375
376   /* Install the customized pipeline:
377    */
378   _tnl_destroy_pipeline( ctx );
379   _tnl_install_pipeline( ctx, radeon_pipeline );
380   ctx->Driver.FlushVertices = radeonFlushVertices;
381
382   /* Try and keep materials and vertices separate:
383    */
384   _tnl_isolate_materials( ctx, GL_TRUE );
385
386
387/*     _mesa_allow_light_in_model( ctx, GL_FALSE ); */
388
389   /* Try and keep materials and vertices separate:
390    */
391   _tnl_isolate_materials( ctx, GL_TRUE );
392
393
394   /* Configure swrast and T&L to match hardware characteristics:
395    */
396   _swrast_allow_pixel_fog( ctx, GL_FALSE );
397   _swrast_allow_vertex_fog( ctx, GL_TRUE );
398   _tnl_allow_pixel_fog( ctx, GL_FALSE );
399   _tnl_allow_vertex_fog( ctx, GL_TRUE );
400
401
402   _math_matrix_ctr( &rmesa->TexGenMatrix[0] );
403   _math_matrix_ctr( &rmesa->TexGenMatrix[1] );
404   _math_matrix_ctr( &rmesa->tmpmat );
405   _math_matrix_set_identity( &rmesa->TexGenMatrix[0] );
406   _math_matrix_set_identity( &rmesa->TexGenMatrix[1] );
407   _math_matrix_set_identity( &rmesa->tmpmat );
408
409   driInitExtensions( ctx, card_extensions, GL_TRUE );
410   if (rmesa->glCtx->Mesa_DXTn) {
411      _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
412      _mesa_enable_extension( ctx, "GL_S3_s3tc" );
413   }
414   else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) {
415      _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" );
416   }
417
418   if (rmesa->dri.drmMinor >= 9)
419      _mesa_enable_extension( ctx, "GL_NV_texture_rectangle");
420
421   /* XXX these should really go right after _mesa_init_driver_functions() */
422   radeonInitIoctlFuncs( ctx );
423   radeonInitStateFuncs( ctx );
424   radeonInitSpanFuncs( ctx );
425   radeonInitState( rmesa );
426   radeonInitSwtcl( ctx );
427
428   _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0,
429			 ctx->Const.MaxArrayLockSize, 32 );
430
431   fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode");
432   rmesa->iw.irq_seq = -1;
433   rmesa->irqsEmitted = 0;
434   rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 &&
435		     fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
436
437   rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
438
439   rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0)
440       ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ;
441
442   rmesa->get_ust = (PFNGLXGETUSTPROC) glXGetProcAddress( (const GLubyte *) "__glXGetUST" );
443   if ( rmesa->get_ust == NULL ) {
444      rmesa->get_ust = get_ust_nop;
445   }
446   (*rmesa->get_ust)( & rmesa->swap_ust );
447
448
449#if DO_DEBUG
450   RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ),
451				       debug_control );
452#endif
453
454   tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
455   if (driQueryOptionb(&rmesa->optionCache, "no_rast")) {
456      fprintf(stderr, "disabling 3D acceleration\n");
457      FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
458   } else if (tcl_mode == DRI_CONF_TCL_SW ||
459	      !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
460      if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
461	 rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL;
462	 fprintf(stderr, "Disabling HW TCL support\n");
463      }
464      TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
465   }
466
467   if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
468      if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
469	 radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
470
471      _tnl_need_dlist_norm_lengths( ctx, GL_FALSE );
472   }
473   return GL_TRUE;
474}
475
476
477/* Destroy the device specific context.
478 */
479/* Destroy the Mesa and driver specific context data.
480 */
481void radeonDestroyContext( __DRIcontextPrivate *driContextPriv )
482{
483   GET_CURRENT_CONTEXT(ctx);
484   radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
485   radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
486
487   /* check if we're deleting the currently bound context */
488   if (rmesa == current) {
489      RADEON_FIREVERTICES( rmesa );
490      _mesa_make_current2(NULL, NULL, NULL);
491   }
492
493   /* Free radeon context resources */
494   assert(rmesa); /* should never be null */
495   if ( rmesa ) {
496      GLboolean   release_texture_heaps;
497
498
499      release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1);
500      _swsetup_DestroyContext( rmesa->glCtx );
501      _tnl_DestroyContext( rmesa->glCtx );
502      _ac_DestroyContext( rmesa->glCtx );
503      _swrast_DestroyContext( rmesa->glCtx );
504
505      radeonDestroySwtcl( rmesa->glCtx );
506      radeonReleaseArrays( rmesa->glCtx, ~0 );
507      if (rmesa->dma.current.buf) {
508	 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ );
509	 radeonFlushCmdBuf( rmesa, __FUNCTION__ );
510      }
511
512      if (!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)) {
513	 int tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode");
514	 if (tcl_mode >= DRI_CONF_TCL_VTXFMT)
515	    radeonVtxfmtDestroy( rmesa->glCtx );
516      }
517
518      /* free the Mesa context */
519      rmesa->glCtx->DriverCtx = NULL;
520      _mesa_destroy_context( rmesa->glCtx );
521
522      _mesa_vector4f_free( &rmesa->tcl.ObjClean );
523
524      if (rmesa->state.scissor.pClipRects) {
525	 FREE(rmesa->state.scissor.pClipRects);
526	 rmesa->state.scissor.pClipRects = 0;
527      }
528
529      if ( release_texture_heaps ) {
530         /* This share group is about to go away, free our private
531          * texture object data.
532          */
533         int i;
534
535         for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
536	    driDestroyTextureHeap( rmesa->texture_heaps[ i ] );
537	    rmesa->texture_heaps[ i ] = NULL;
538         }
539
540	 assert( is_empty_list( & rmesa->swapped ) );
541      }
542
543      /* free the option cache */
544      driDestroyOptionCache (&rmesa->optionCache);
545
546      FREE( rmesa );
547   }
548}
549
550
551
552
553void
554radeonSwapBuffers( __DRIdrawablePrivate *dPriv )
555{
556
557   if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) {
558      radeonContextPtr rmesa;
559      GLcontext *ctx;
560      rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate;
561      ctx = rmesa->glCtx;
562      if (ctx->Visual.doubleBufferMode) {
563         _mesa_notifySwapBuffers( ctx );  /* flush pending rendering comands */
564
565         if ( rmesa->doPageFlip ) {
566            radeonPageFlip( dPriv );
567         }
568         else {
569            radeonCopyBuffer( dPriv );
570         }
571      }
572   }
573   else {
574      /* XXX this shouldn't be an error but we can't handle it for now */
575      _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__);
576   }
577}
578
579
580/* Force the context `c' to be the current context and associate with it
581 * buffer `b'.
582 */
583GLboolean
584radeonMakeCurrent( __DRIcontextPrivate *driContextPriv,
585                   __DRIdrawablePrivate *driDrawPriv,
586                   __DRIdrawablePrivate *driReadPriv )
587{
588   if ( driContextPriv ) {
589      radeonContextPtr newCtx =
590	 (radeonContextPtr) driContextPriv->driverPrivate;
591
592      if (RADEON_DEBUG & DEBUG_DRI)
593	 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx);
594
595      if ( newCtx->dri.drawable != driDrawPriv ) {
596	 driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags );
597	 newCtx->dri.drawable = driDrawPriv;
598	 radeonUpdateWindow( newCtx->glCtx );
599	 radeonUpdateViewportOffset( newCtx->glCtx );
600      }
601
602      _mesa_make_current2( newCtx->glCtx,
603			   (GLframebuffer *) driDrawPriv->driverPrivate,
604			   (GLframebuffer *) driReadPriv->driverPrivate );
605
606      if (newCtx->vb.enabled)
607	 radeonVtxfmtMakeCurrent( newCtx->glCtx );
608
609   } else {
610      if (RADEON_DEBUG & DEBUG_DRI)
611	 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
612      _mesa_make_current( 0, 0 );
613   }
614
615   if (RADEON_DEBUG & DEBUG_DRI)
616      fprintf(stderr, "End %s\n", __FUNCTION__);
617   return GL_TRUE;
618}
619
620/* Force the context `c' to be unbound from its buffer.
621 */
622GLboolean
623radeonUnbindContext( __DRIcontextPrivate *driContextPriv )
624{
625   radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate;
626
627   if (RADEON_DEBUG & DEBUG_DRI)
628      fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx);
629
630   return GL_TRUE;
631}
632