radeon_context.c revision 2d61d301171620efe624d83a5457f4094eb49cba
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.c,v 1.9 2003/09/24 02:43:12 dawes Exp $ */ 2/************************************************************************** 3 4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 5 VA Linux Systems Inc., Fremont, California. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29**************************************************************************/ 30 31/* 32 * Authors: 33 * Kevin E. Martin <martin@valinux.com> 34 * Gareth Hughes <gareth@valinux.com> 35 * Keith Whitwell <keith@tungstengraphics.com> 36 */ 37 38#include "glheader.h" 39#include "api_arrayelt.h" 40#include "context.h" 41#include "simple_list.h" 42#include "imports.h" 43#include "matrix.h" 44#include "extensions.h" 45#include "framebuffer.h" 46 47#include "swrast/swrast.h" 48#include "swrast_setup/swrast_setup.h" 49#include "array_cache/acache.h" 50 51#include "tnl/tnl.h" 52#include "tnl/t_pipeline.h" 53 54#include "drivers/common/driverfuncs.h" 55 56#include "radeon_context.h" 57#include "radeon_ioctl.h" 58#include "radeon_state.h" 59#include "radeon_span.h" 60#include "radeon_tex.h" 61#include "radeon_swtcl.h" 62#include "radeon_tcl.h" 63#include "radeon_vtxfmt.h" 64#include "radeon_maos.h" 65 66#define need_GL_ARB_multisample 67#define need_GL_ARB_texture_compression 68#define need_GL_EXT_blend_minmax 69#define need_GL_EXT_fog_coord 70#define need_GL_EXT_secondary_color 71#include "extension_helper.h" 72 73#define DRIVER_DATE "20051013" 74 75#include "vblank.h" 76#include "utils.h" 77#include "xmlpool.h" /* for symbolic values of enum-type options */ 78#ifndef RADEON_DEBUG 79int RADEON_DEBUG = (0); 80#endif 81 82 83/* Return the width and height of the given buffer. 84 */ 85static void radeonGetBufferSize( GLframebuffer *buffer, 86 GLuint *width, GLuint *height ) 87{ 88 GET_CURRENT_CONTEXT(ctx); 89 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 90 91 LOCK_HARDWARE( rmesa ); 92 *width = rmesa->dri.drawable->w; 93 *height = rmesa->dri.drawable->h; 94 95 UNLOCK_HARDWARE( rmesa ); 96} 97 98/* Return various strings for glGetString(). 99 */ 100static const GLubyte *radeonGetString( GLcontext *ctx, GLenum name ) 101{ 102 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 103 static char buffer[128]; 104 unsigned offset; 105 GLuint agp_mode = rmesa->radeonScreen->IsPCI ? 0 : 106 rmesa->radeonScreen->AGPMode; 107 108 switch ( name ) { 109 case GL_VENDOR: 110 return (GLubyte *)"Tungsten Graphics, Inc."; 111 112 case GL_RENDERER: 113 offset = driGetRendererString( buffer, "Radeon", DRIVER_DATE, 114 agp_mode ); 115 116 sprintf( & buffer[ offset ], " %sTCL", 117 !(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE) 118 ? "" : "NO-" ); 119 120 return (GLubyte *)buffer; 121 122 default: 123 return NULL; 124 } 125} 126 127 128/* Extension strings exported by the R100 driver. 129 */ 130const struct dri_extension card_extensions[] = 131{ 132 { "GL_ARB_multisample", GL_ARB_multisample_functions }, 133 { "GL_ARB_multitexture", NULL }, 134 { "GL_ARB_texture_border_clamp", NULL }, 135 { "GL_ARB_texture_compression", GL_ARB_texture_compression_functions }, 136 { "GL_ARB_texture_env_add", NULL }, 137 { "GL_ARB_texture_env_combine", NULL }, 138 { "GL_ARB_texture_env_crossbar", NULL }, 139 { "GL_ARB_texture_env_dot3", NULL }, 140 { "GL_ARB_texture_mirrored_repeat", NULL }, 141 { "GL_EXT_blend_logic_op", NULL }, 142 { "GL_EXT_blend_subtract", GL_EXT_blend_minmax_functions }, 143 { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, 144 { "GL_EXT_secondary_color", GL_EXT_secondary_color_functions }, 145 { "GL_EXT_stencil_wrap", NULL }, 146 { "GL_EXT_texture_edge_clamp", NULL }, 147 { "GL_EXT_texture_env_combine", NULL }, 148 { "GL_EXT_texture_env_dot3", NULL }, 149 { "GL_EXT_texture_filter_anisotropic", NULL }, 150 { "GL_EXT_texture_lod_bias", NULL }, 151 { "GL_EXT_texture_mirror_clamp", NULL }, 152 { "GL_ATI_texture_env_combine3", NULL }, 153 { "GL_ATI_texture_mirror_once", NULL }, 154 { "GL_MESA_ycbcr_texture", NULL }, 155 { "GL_NV_blend_square", NULL }, 156 { "GL_SGIS_generate_mipmap", NULL }, 157 { NULL, NULL } 158}; 159 160extern const struct tnl_pipeline_stage _radeon_texrect_stage; 161extern const struct tnl_pipeline_stage _radeon_render_stage; 162extern const struct tnl_pipeline_stage _radeon_tcl_stage; 163 164static const struct tnl_pipeline_stage *radeon_pipeline[] = { 165 166 /* Try and go straight to t&l 167 */ 168 &_radeon_tcl_stage, 169 170 /* Catch any t&l fallbacks 171 */ 172 &_tnl_vertex_transform_stage, 173 &_tnl_normal_transform_stage, 174 &_tnl_lighting_stage, 175 &_tnl_fog_coordinate_stage, 176 &_tnl_texgen_stage, 177 &_tnl_texture_transform_stage, 178 179 /* Scale texture rectangle to 0..1. 180 */ 181 &_radeon_texrect_stage, 182 183 &_radeon_render_stage, 184 &_tnl_render_stage, /* FALLBACK: */ 185 NULL, 186}; 187 188 189 190/* Initialize the driver's misc functions. 191 */ 192static void radeonInitDriverFuncs( struct dd_function_table *functions ) 193{ 194 functions->GetBufferSize = radeonGetBufferSize; 195 functions->ResizeBuffers = _mesa_resize_framebuffer; 196 functions->GetString = radeonGetString; 197} 198 199static const struct dri_debug_control debug_control[] = 200{ 201 { "fall", DEBUG_FALLBACKS }, 202 { "tex", DEBUG_TEXTURE }, 203 { "ioctl", DEBUG_IOCTL }, 204 { "prim", DEBUG_PRIMS }, 205 { "vert", DEBUG_VERTS }, 206 { "state", DEBUG_STATE }, 207 { "code", DEBUG_CODEGEN }, 208 { "vfmt", DEBUG_VFMT }, 209 { "vtxf", DEBUG_VFMT }, 210 { "verb", DEBUG_VERBOSE }, 211 { "dri", DEBUG_DRI }, 212 { "dma", DEBUG_DMA }, 213 { "san", DEBUG_SANITY }, 214 { "sync", DEBUG_SYNC }, 215 { NULL, 0 } 216}; 217 218 219/* Create the device specific context. 220 */ 221GLboolean 222radeonCreateContext( const __GLcontextModes *glVisual, 223 __DRIcontextPrivate *driContextPriv, 224 void *sharedContextPrivate) 225{ 226 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 227 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); 228 struct dd_function_table functions; 229 radeonContextPtr rmesa; 230 GLcontext *ctx, *shareCtx; 231 int i; 232 int tcl_mode, fthrottle_mode; 233 234 assert(glVisual); 235 assert(driContextPriv); 236 assert(screen); 237 238 /* Allocate the Radeon context */ 239 rmesa = (radeonContextPtr) CALLOC( sizeof(*rmesa) ); 240 if ( !rmesa ) 241 return GL_FALSE; 242 243 /* init exp fog table data */ 244 radeonInitStaticFogData(); 245 246 /* Parse configuration files. 247 * Do this here so that initialMaxAnisotropy is set before we create 248 * the default textures. 249 */ 250 driParseConfigFiles (&rmesa->optionCache, &screen->optionCache, 251 screen->driScreen->myNum, "radeon"); 252 rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache, 253 "def_max_anisotropy"); 254 255 if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) { 256 if ( sPriv->drmMinor < 13 ) 257 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " 258 "disabling.\n",sPriv->drmMinor ); 259 else 260 rmesa->using_hyperz = GL_TRUE; 261 } 262 263 if ( sPriv->drmMinor >= 15 ) 264 rmesa->texmicrotile = GL_TRUE; 265 266 /* Init default driver functions then plug in our Radeon-specific functions 267 * (the texture functions are especially important) 268 */ 269 _mesa_init_driver_functions( &functions ); 270 radeonInitDriverFuncs( &functions ); 271 radeonInitTextureFuncs( &functions ); 272 273 /* Allocate the Mesa context */ 274 if (sharedContextPrivate) 275 shareCtx = ((radeonContextPtr) sharedContextPrivate)->glCtx; 276 else 277 shareCtx = NULL; 278 rmesa->glCtx = _mesa_create_context(glVisual, shareCtx, 279 &functions, (void *) rmesa); 280 if (!rmesa->glCtx) { 281 FREE(rmesa); 282 return GL_FALSE; 283 } 284 driContextPriv->driverPrivate = rmesa; 285 286 /* Init radeon context data */ 287 rmesa->dri.context = driContextPriv; 288 rmesa->dri.screen = sPriv; 289 rmesa->dri.drawable = NULL; /* Set by XMesaMakeCurrent */ 290 rmesa->dri.hwContext = driContextPriv->hHWContext; 291 rmesa->dri.hwLock = &sPriv->pSAREA->lock; 292 rmesa->dri.fd = sPriv->fd; 293 rmesa->dri.drmMinor = sPriv->drmMinor; 294 295 rmesa->radeonScreen = screen; 296 rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA + 297 screen->sarea_priv_offset); 298 299 300 rmesa->dma.buf0_address = rmesa->radeonScreen->buffers->list[0].address; 301 302 (void) memset( rmesa->texture_heaps, 0, sizeof( rmesa->texture_heaps ) ); 303 make_empty_list( & rmesa->swapped ); 304 305 rmesa->nr_heaps = screen->numTexHeaps; 306 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { 307 rmesa->texture_heaps[i] = driCreateTextureHeap( i, rmesa, 308 screen->texSize[i], 309 12, 310 RADEON_NR_TEX_REGIONS, 311 (drmTextureRegionPtr)rmesa->sarea->tex_list[i], 312 & rmesa->sarea->tex_age[i], 313 & rmesa->swapped, 314 sizeof( radeonTexObj ), 315 (destroy_texture_object_t *) radeonDestroyTexObj ); 316 317 driSetTextureSwapCounterLocation( rmesa->texture_heaps[i], 318 & rmesa->c_textureSwaps ); 319 } 320 rmesa->texture_depth = driQueryOptioni (&rmesa->optionCache, 321 "texture_depth"); 322 if (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB) 323 rmesa->texture_depth = ( screen->cpp == 4 ) ? 324 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16; 325 326 rmesa->swtcl.RenderIndex = ~0; 327 rmesa->hw.all_dirty = GL_TRUE; 328 329 /* Set the maximum texture size small enough that we can guarentee that 330 * all texture units can bind a maximal texture and have them both in 331 * texturable memory at once. 332 */ 333 334 ctx = rmesa->glCtx; 335 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->optionCache, 336 "texture_units"); 337 ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits; 338 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; 339 340 driCalculateMaxTextureLevels( rmesa->texture_heaps, 341 rmesa->nr_heaps, 342 & ctx->Const, 343 4, 344 11, /* max 2D texture size is 2048x2048 */ 345 0, /* 3D textures unsupported. */ 346 9, /* \todo: max cube texture size seems to be 512x512(x6) */ 347 11, /* max rect texture size is 2048x2048. */ 348 12, 349 GL_FALSE ); 350 351 /* adjust max texture size a bit. Hack, but I really want to use larger textures 352 which will work just fine in 99.999999% of all cases, especially with texture compression... */ 353 if (driQueryOptionb( &rmesa->optionCache, "texture_level_hack" )) 354 { 355 if (ctx->Const.MaxTextureLevels < 12) ctx->Const.MaxTextureLevels += 1; 356 } 357 358 ctx->Const.MaxTextureMaxAnisotropy = 16.0; 359 360 /* No wide points. 361 */ 362 ctx->Const.MinPointSize = 1.0; 363 ctx->Const.MinPointSizeAA = 1.0; 364 ctx->Const.MaxPointSize = 1.0; 365 ctx->Const.MaxPointSizeAA = 1.0; 366 367 ctx->Const.MinLineWidth = 1.0; 368 ctx->Const.MinLineWidthAA = 1.0; 369 ctx->Const.MaxLineWidth = 10.0; 370 ctx->Const.MaxLineWidthAA = 10.0; 371 ctx->Const.LineWidthGranularity = 0.0625; 372 373 /* Set maxlocksize (and hence vb size) small enough to avoid 374 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can 375 * fit in a single dma buffer for indexed rendering of quad strips, 376 * etc. 377 */ 378 ctx->Const.MaxArrayLockSize = 379 MIN2( ctx->Const.MaxArrayLockSize, 380 RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE ); 381 382 rmesa->boxes = 0; 383 384 /* Initialize the software rasterizer and helper modules. 385 */ 386 _swrast_CreateContext( ctx ); 387 _ac_CreateContext( ctx ); 388 _tnl_CreateContext( ctx ); 389 _swsetup_CreateContext( ctx ); 390 _ae_create_context( ctx ); 391 392 /* Install the customized pipeline: 393 */ 394 _tnl_destroy_pipeline( ctx ); 395 _tnl_install_pipeline( ctx, radeon_pipeline ); 396 ctx->Driver.FlushVertices = radeonFlushVertices; 397 398 /* Try and keep materials and vertices separate: 399 */ 400 _tnl_isolate_materials( ctx, GL_TRUE ); 401 402/* _mesa_allow_light_in_model( ctx, GL_FALSE ); */ 403 404 /* Configure swrast and T&L to match hardware characteristics: 405 */ 406 _swrast_allow_pixel_fog( ctx, GL_FALSE ); 407 _swrast_allow_vertex_fog( ctx, GL_TRUE ); 408 _tnl_allow_pixel_fog( ctx, GL_FALSE ); 409 _tnl_allow_vertex_fog( ctx, GL_TRUE ); 410 411 412 for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) { 413 _math_matrix_ctr( &rmesa->TexGenMatrix[i] ); 414 _math_matrix_ctr( &rmesa->tmpmat[i] ); 415 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] ); 416 _math_matrix_set_identity( &rmesa->tmpmat[i] ); 417 } 418 419 driInitExtensions( ctx, card_extensions, GL_TRUE ); 420 if (rmesa->radeonScreen->drmSupportsCubeMaps) 421 _mesa_enable_extension( ctx, "GL_ARB_texture_cube_map" ); 422 if (rmesa->glCtx->Mesa_DXTn) { 423 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); 424 _mesa_enable_extension( ctx, "GL_S3_s3tc" ); 425 } 426 else if (driQueryOptionb (&rmesa->optionCache, "force_s3tc_enable")) { 427 _mesa_enable_extension( ctx, "GL_EXT_texture_compression_s3tc" ); 428 } 429 430 if (rmesa->dri.drmMinor >= 9) 431 _mesa_enable_extension( ctx, "GL_NV_texture_rectangle"); 432 433 /* XXX these should really go right after _mesa_init_driver_functions() */ 434 radeonInitIoctlFuncs( ctx ); 435 radeonInitStateFuncs( ctx ); 436 radeonInitSpanFuncs( ctx ); 437 radeonInitState( rmesa ); 438 radeonInitSwtcl( ctx ); 439 440 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, 441 ctx->Const.MaxArrayLockSize, 32 ); 442 443 fthrottle_mode = driQueryOptioni(&rmesa->optionCache, "fthrottle_mode"); 444 rmesa->iw.irq_seq = -1; 445 rmesa->irqsEmitted = 0; 446 rmesa->do_irqs = (rmesa->radeonScreen->irq != 0 && 447 fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS); 448 449 rmesa->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); 450 451 rmesa->vblank_flags = (rmesa->radeonScreen->irq != 0) 452 ? driGetDefaultVBlankFlags(&rmesa->optionCache) : VBLANK_FLAG_NO_IRQ; 453 454 (*dri_interface->getUST)( & rmesa->swap_ust ); 455 456 457#if DO_DEBUG 458 RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ), 459 debug_control ); 460#endif 461 462 tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode"); 463 if (driQueryOptionb(&rmesa->optionCache, "no_rast")) { 464 fprintf(stderr, "disabling 3D acceleration\n"); 465 FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1); 466 } else if (tcl_mode == DRI_CONF_TCL_SW || 467 !(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) { 468 if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) { 469 rmesa->radeonScreen->chipset &= ~RADEON_CHIPSET_TCL; 470 fprintf(stderr, "Disabling HW TCL support\n"); 471 } 472 TCL_FALLBACK(rmesa->glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); 473 } 474 475 if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) { 476 if (tcl_mode >= DRI_CONF_TCL_VTXFMT) 477 radeonVtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN ); 478 479 _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); 480 } 481 return GL_TRUE; 482} 483 484 485/* Destroy the device specific context. 486 */ 487/* Destroy the Mesa and driver specific context data. 488 */ 489void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ) 490{ 491 GET_CURRENT_CONTEXT(ctx); 492 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate; 493 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL; 494 495 /* check if we're deleting the currently bound context */ 496 if (rmesa == current) { 497 RADEON_FIREVERTICES( rmesa ); 498 _mesa_make_current(NULL, NULL, NULL); 499 } 500 501 /* Free radeon context resources */ 502 assert(rmesa); /* should never be null */ 503 if ( rmesa ) { 504 GLboolean release_texture_heaps; 505 506 507 release_texture_heaps = (rmesa->glCtx->Shared->RefCount == 1); 508 _swsetup_DestroyContext( rmesa->glCtx ); 509 _tnl_DestroyContext( rmesa->glCtx ); 510 _ac_DestroyContext( rmesa->glCtx ); 511 _swrast_DestroyContext( rmesa->glCtx ); 512 513 radeonDestroySwtcl( rmesa->glCtx ); 514 radeonReleaseArrays( rmesa->glCtx, ~0 ); 515 if (rmesa->dma.current.buf) { 516 radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); 517 radeonFlushCmdBuf( rmesa, __FUNCTION__ ); 518 } 519 520 if (!(rmesa->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)) { 521 int tcl_mode = driQueryOptioni(&rmesa->optionCache, "tcl_mode"); 522 if (tcl_mode >= DRI_CONF_TCL_VTXFMT) 523 radeonVtxfmtDestroy( rmesa->glCtx ); 524 } 525 526 /* free the Mesa context */ 527 rmesa->glCtx->DriverCtx = NULL; 528 _mesa_destroy_context( rmesa->glCtx ); 529 530 _mesa_vector4f_free( &rmesa->tcl.ObjClean ); 531 532 if (rmesa->state.scissor.pClipRects) { 533 FREE(rmesa->state.scissor.pClipRects); 534 rmesa->state.scissor.pClipRects = NULL; 535 } 536 537 if ( release_texture_heaps ) { 538 /* This share group is about to go away, free our private 539 * texture object data. 540 */ 541 int i; 542 543 for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) { 544 driDestroyTextureHeap( rmesa->texture_heaps[ i ] ); 545 rmesa->texture_heaps[ i ] = NULL; 546 } 547 548 assert( is_empty_list( & rmesa->swapped ) ); 549 } 550 551 /* free the option cache */ 552 driDestroyOptionCache (&rmesa->optionCache); 553 554 FREE( rmesa ); 555 } 556} 557 558 559 560 561void 562radeonSwapBuffers( __DRIdrawablePrivate *dPriv ) 563{ 564 565 if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { 566 radeonContextPtr rmesa; 567 GLcontext *ctx; 568 rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; 569 ctx = rmesa->glCtx; 570 if (ctx->Visual.doubleBufferMode) { 571 _mesa_notifySwapBuffers( ctx ); /* flush pending rendering comands */ 572 573 if ( rmesa->doPageFlip ) { 574 radeonPageFlip( dPriv ); 575 } 576 else { 577 radeonCopyBuffer( dPriv ); 578 } 579 } 580 } 581 else { 582 /* XXX this shouldn't be an error but we can't handle it for now */ 583 _mesa_problem(NULL, "%s: drawable has no context!", __FUNCTION__); 584 } 585} 586 587 588/* Make context `c' the current context and bind it to the given 589 * drawing and reading surfaces. 590 */ 591GLboolean 592radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, 593 __DRIdrawablePrivate *driDrawPriv, 594 __DRIdrawablePrivate *driReadPriv ) 595{ 596 if ( driContextPriv ) { 597 radeonContextPtr newCtx = 598 (radeonContextPtr) driContextPriv->driverPrivate; 599 600 if (RADEON_DEBUG & DEBUG_DRI) 601 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) newCtx->glCtx); 602 603 if ( newCtx->dri.drawable != driDrawPriv ) { 604 /* XXX we may need to validate the drawable here!!! */ 605 driDrawableInitVBlank( driDrawPriv, newCtx->vblank_flags ); 606 newCtx->dri.drawable = driDrawPriv; 607 radeonUpdateWindow( newCtx->glCtx ); 608 radeonUpdateViewportOffset( newCtx->glCtx ); 609 } 610 611 _mesa_make_current( newCtx->glCtx, 612 (GLframebuffer *) driDrawPriv->driverPrivate, 613 (GLframebuffer *) driReadPriv->driverPrivate ); 614 615 if (newCtx->vb.enabled) 616 radeonVtxfmtMakeCurrent( newCtx->glCtx ); 617 618 } else { 619 if (RADEON_DEBUG & DEBUG_DRI) 620 fprintf(stderr, "%s ctx is null\n", __FUNCTION__); 621 _mesa_make_current( NULL, NULL, NULL ); 622 } 623 624 if (RADEON_DEBUG & DEBUG_DRI) 625 fprintf(stderr, "End %s\n", __FUNCTION__); 626 return GL_TRUE; 627} 628 629/* Force the context `c' to be unbound from its buffer. 630 */ 631GLboolean 632radeonUnbindContext( __DRIcontextPrivate *driContextPriv ) 633{ 634 radeonContextPtr rmesa = (radeonContextPtr) driContextPriv->driverPrivate; 635 636 if (RADEON_DEBUG & DEBUG_DRI) 637 fprintf(stderr, "%s ctx %p\n", __FUNCTION__, (void *) rmesa->glCtx); 638 639 return GL_TRUE; 640} 641