radeon_context.c revision 9c1b41879aab2ff7386c547a2ccce7686c018cf5
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/* 31 * Authors: 32 * Kevin E. Martin <martin@valinux.com> 33 * Gareth Hughes <gareth@valinux.com> 34 * Keith Whitwell <keith@tungstengraphics.com> 35 */ 36 37#include <stdbool.h> 38#include "main/glheader.h" 39#include "main/api_arrayelt.h" 40#include "main/context.h" 41#include "main/simple_list.h" 42#include "main/imports.h" 43#include "main/extensions.h" 44#include "main/mfeatures.h" 45#include "main/version.h" 46 47#include "swrast/swrast.h" 48#include "swrast_setup/swrast_setup.h" 49#include "vbo/vbo.h" 50 51#include "tnl/tnl.h" 52#include "tnl/t_pipeline.h" 53 54#include "drivers/common/driverfuncs.h" 55 56#include "radeon_common.h" 57#include "radeon_context.h" 58#include "radeon_ioctl.h" 59#include "radeon_state.h" 60#include "radeon_span.h" 61#include "radeon_tex.h" 62#include "radeon_swtcl.h" 63#include "radeon_tcl.h" 64#include "radeon_queryobj.h" 65#include "radeon_blit.h" 66#include "radeon_fog.h" 67 68#include "utils.h" 69#include "xmlpool.h" /* for symbolic values of enum-type options */ 70 71extern const struct tnl_pipeline_stage _radeon_render_stage; 72extern const struct tnl_pipeline_stage _radeon_tcl_stage; 73 74static const struct tnl_pipeline_stage *radeon_pipeline[] = { 75 76 /* Try and go straight to t&l 77 */ 78 &_radeon_tcl_stage, 79 80 /* Catch any t&l fallbacks 81 */ 82 &_tnl_vertex_transform_stage, 83 &_tnl_normal_transform_stage, 84 &_tnl_lighting_stage, 85 &_tnl_fog_coordinate_stage, 86 &_tnl_texgen_stage, 87 &_tnl_texture_transform_stage, 88 89 &_radeon_render_stage, 90 &_tnl_render_stage, /* FALLBACK: */ 91 NULL, 92}; 93 94static void r100_get_lock(radeonContextPtr radeon) 95{ 96 r100ContextPtr rmesa = (r100ContextPtr)radeon; 97 drm_radeon_sarea_t *sarea = radeon->sarea; 98 99 RADEON_STATECHANGE(rmesa, ctx); 100 if (rmesa->radeon.sarea->tiling_enabled) { 101 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= 102 RADEON_COLOR_TILE_ENABLE; 103 } else { 104 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] &= 105 ~RADEON_COLOR_TILE_ENABLE; 106 } 107 108 if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) { 109 sarea->ctx_owner = rmesa->radeon.dri.hwContext; 110 } 111} 112 113static void r100_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa) 114{ 115} 116 117static void r100_vtbl_pre_emit_state(radeonContextPtr radeon) 118{ 119 r100ContextPtr rmesa = (r100ContextPtr)radeon; 120 121 /* r100 always needs to emit ZBS to avoid TCL lockups */ 122 rmesa->hw.zbs.dirty = 1; 123 radeon->hw.is_dirty = 1; 124} 125 126static void r100_vtbl_free_context(struct gl_context *ctx) 127{ 128 r100ContextPtr rmesa = R100_CONTEXT(ctx); 129 _mesa_vector4f_free( &rmesa->tcl.ObjClean ); 130} 131 132static void r100_emit_query_finish(radeonContextPtr radeon) 133{ 134 BATCH_LOCALS(radeon); 135 struct radeon_query_object *query = radeon->query.current; 136 137 BEGIN_BATCH_NO_AUTOSTATE(4); 138 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); 139 OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); 140 END_BATCH(); 141 query->curr_offset += sizeof(uint32_t); 142 assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); 143 query->emitted_begin = GL_FALSE; 144} 145 146static void r100_init_vtbl(radeonContextPtr radeon) 147{ 148 radeon->vtbl.get_lock = r100_get_lock; 149 radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset; 150 radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header; 151 radeon->vtbl.swtcl_flush = r100_swtcl_flush; 152 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; 153 radeon->vtbl.fallback = radeonFallback; 154 radeon->vtbl.free_context = r100_vtbl_free_context; 155 radeon->vtbl.emit_query_finish = r100_emit_query_finish; 156 radeon->vtbl.check_blit = r100_check_blit; 157 radeon->vtbl.blit = r100_blit; 158 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; 159} 160 161/* Create the device specific context. 162 */ 163GLboolean 164r100CreateContext( gl_api api, 165 const struct gl_config *glVisual, 166 __DRIcontext *driContextPriv, 167 unsigned major_version, 168 unsigned minor_version, 169 uint32_t flags, 170 unsigned *error, 171 void *sharedContextPrivate) 172{ 173 __DRIscreen *sPriv = driContextPriv->driScreenPriv; 174 radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate); 175 struct dd_function_table functions; 176 r100ContextPtr rmesa; 177 struct gl_context *ctx; 178 int i; 179 int tcl_mode, fthrottle_mode; 180 181 /* API and flag filtering is handled in dri2CreateContextAttribs. 182 */ 183 (void) api; 184 (void) flags; 185 186 assert(glVisual); 187 assert(driContextPriv); 188 assert(screen); 189 190 /* Allocate the Radeon context */ 191 rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) ); 192 if ( !rmesa ) { 193 *error = __DRI_CTX_ERROR_NO_MEMORY; 194 return GL_FALSE; 195 } 196 197 rmesa->radeon.radeonScreen = screen; 198 r100_init_vtbl(&rmesa->radeon); 199 200 /* init exp fog table data */ 201 radeonInitStaticFogData(); 202 203 /* Parse configuration files. 204 * Do this here so that initialMaxAnisotropy is set before we create 205 * the default textures. 206 */ 207 driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, 208 screen->driScreen->myNum, "radeon"); 209 rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache, 210 "def_max_anisotropy"); 211 212 if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) { 213 if ( sPriv->drm_version.minor < 13 ) 214 fprintf( stderr, "DRM version 1.%d too old to support HyperZ, " 215 "disabling.\n", sPriv->drm_version.minor ); 216 else 217 rmesa->using_hyperz = GL_TRUE; 218 } 219 220 if ( sPriv->drm_version.minor >= 15 ) 221 rmesa->texmicrotile = GL_TRUE; 222 223 /* Init default driver functions then plug in our Radeon-specific functions 224 * (the texture functions are especially important) 225 */ 226 _mesa_init_driver_functions( &functions ); 227 radeonInitTextureFuncs( &rmesa->radeon, &functions ); 228 radeonInitQueryObjFunctions(&functions); 229 230 if (!radeonInitContext(&rmesa->radeon, &functions, 231 glVisual, driContextPriv, 232 sharedContextPrivate)) { 233 FREE(rmesa); 234 *error = __DRI_CTX_ERROR_NO_MEMORY; 235 return GL_FALSE; 236 } 237 238 rmesa->radeon.swtcl.RenderIndex = ~0; 239 rmesa->radeon.hw.all_dirty = GL_TRUE; 240 241 /* Set the maximum texture size small enough that we can guarentee that 242 * all texture units can bind a maximal texture and have all of them in 243 * texturable memory at once. Depending on the allow_large_textures driconf 244 * setting allow larger textures. 245 */ 246 247 ctx = rmesa->radeon.glCtx; 248 ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache, 249 "texture_units"); 250 ctx->Const.MaxTextureImageUnits = ctx->Const.MaxTextureUnits; 251 ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; 252 ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits; 253 254 ctx->Const.StripTextureBorder = GL_TRUE; 255 256 i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures"); 257 258 /* FIXME: When no memory manager is available we should set this 259 * to some reasonable value based on texture memory pool size */ 260 ctx->Const.MaxTextureLevels = 12; 261 ctx->Const.Max3DTextureLevels = 9; 262 ctx->Const.MaxCubeTextureLevels = 12; 263 ctx->Const.MaxTextureRectSize = 2048; 264 265 ctx->Const.MaxTextureMaxAnisotropy = 16.0; 266 267 /* No wide points. 268 */ 269 ctx->Const.MinPointSize = 1.0; 270 ctx->Const.MinPointSizeAA = 1.0; 271 ctx->Const.MaxPointSize = 1.0; 272 ctx->Const.MaxPointSizeAA = 1.0; 273 274 ctx->Const.MinLineWidth = 1.0; 275 ctx->Const.MinLineWidthAA = 1.0; 276 ctx->Const.MaxLineWidth = 10.0; 277 ctx->Const.MaxLineWidthAA = 10.0; 278 ctx->Const.LineWidthGranularity = 0.0625; 279 280 /* Set maxlocksize (and hence vb size) small enough to avoid 281 * fallbacks in radeon_tcl.c. ie. guarentee that all vertices can 282 * fit in a single dma buffer for indexed rendering of quad strips, 283 * etc. 284 */ 285 ctx->Const.MaxArrayLockSize = 286 MIN2( ctx->Const.MaxArrayLockSize, 287 RADEON_BUFFER_SIZE / RADEON_MAX_TCL_VERTSIZE ); 288 289 rmesa->boxes = 0; 290 291 ctx->Const.MaxDrawBuffers = 1; 292 ctx->Const.MaxColorAttachments = 1; 293 ctx->Const.MaxRenderbufferSize = 2048; 294 295 _mesa_set_mvp_with_dp4( ctx, GL_TRUE ); 296 297 /* Initialize the software rasterizer and helper modules. 298 */ 299 _swrast_CreateContext( ctx ); 300 _vbo_CreateContext( ctx ); 301 _tnl_CreateContext( ctx ); 302 _swsetup_CreateContext( ctx ); 303 _ae_create_context( ctx ); 304 305 /* Install the customized pipeline: 306 */ 307 _tnl_destroy_pipeline( ctx ); 308 _tnl_install_pipeline( ctx, radeon_pipeline ); 309 310 /* Try and keep materials and vertices separate: 311 */ 312/* _tnl_isolate_materials( ctx, GL_TRUE ); */ 313 314 /* Configure swrast and T&L to match hardware characteristics: 315 */ 316 _swrast_allow_pixel_fog( ctx, GL_FALSE ); 317 _swrast_allow_vertex_fog( ctx, GL_TRUE ); 318 _tnl_allow_pixel_fog( ctx, GL_FALSE ); 319 _tnl_allow_vertex_fog( ctx, GL_TRUE ); 320 321 322 for ( i = 0 ; i < RADEON_MAX_TEXTURE_UNITS ; i++ ) { 323 _math_matrix_ctr( &rmesa->TexGenMatrix[i] ); 324 _math_matrix_ctr( &rmesa->tmpmat[i] ); 325 _math_matrix_set_identity( &rmesa->TexGenMatrix[i] ); 326 _math_matrix_set_identity( &rmesa->tmpmat[i] ); 327 } 328 329 ctx->Extensions.ARB_texture_border_clamp = true; 330 ctx->Extensions.ARB_texture_env_combine = true; 331 ctx->Extensions.ARB_texture_env_crossbar = true; 332 ctx->Extensions.ARB_texture_env_dot3 = true; 333 ctx->Extensions.EXT_fog_coord = true; 334 ctx->Extensions.EXT_packed_depth_stencil = true; 335 ctx->Extensions.EXT_secondary_color = true; 336 ctx->Extensions.EXT_texture_env_dot3 = true; 337 ctx->Extensions.EXT_texture_filter_anisotropic = true; 338 ctx->Extensions.EXT_texture_mirror_clamp = true; 339 ctx->Extensions.ATI_texture_env_combine3 = true; 340 ctx->Extensions.ATI_texture_mirror_once = true; 341 ctx->Extensions.MESA_ycbcr_texture = true; 342 ctx->Extensions.NV_blend_square = true; 343#if FEATURE_OES_EGL_image 344 ctx->Extensions.OES_EGL_image = true; 345#endif 346 347 ctx->Extensions.EXT_framebuffer_object = true; 348 349 ctx->Extensions.ARB_texture_cube_map = true; 350 351 if (rmesa->radeon.glCtx->Mesa_DXTn) { 352 ctx->Extensions.EXT_texture_compression_s3tc = true; 353 ctx->Extensions.S3_s3tc = true; 354 } 355 else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) { 356 ctx->Extensions.EXT_texture_compression_s3tc = true; 357 } 358 359 ctx->Extensions.NV_texture_rectangle = true; 360 ctx->Extensions.ARB_occlusion_query = true; 361 362 /* XXX these should really go right after _mesa_init_driver_functions() */ 363 radeon_fbo_init(&rmesa->radeon); 364 radeonInitSpanFuncs( ctx ); 365 radeonInitIoctlFuncs( ctx ); 366 radeonInitStateFuncs( ctx ); 367 radeonInitState( rmesa ); 368 radeonInitSwtcl( ctx ); 369 370 _mesa_vector4f_alloc( &rmesa->tcl.ObjClean, 0, 371 ctx->Const.MaxArrayLockSize, 32 ); 372 373 fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode"); 374 rmesa->radeon.iw.irq_seq = -1; 375 rmesa->radeon.irqsEmitted = 0; 376 rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 && 377 fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS); 378 379 rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS); 380 381 382#if DO_DEBUG 383 RADEON_DEBUG = driParseDebugString( getenv( "RADEON_DEBUG" ), 384 debug_control ); 385#endif 386 387 tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode"); 388 if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) { 389 fprintf(stderr, "disabling 3D acceleration\n"); 390 FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1); 391 } else if (tcl_mode == DRI_CONF_TCL_SW || 392 !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { 393 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 394 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; 395 fprintf(stderr, "Disabling HW TCL support\n"); 396 } 397 TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1); 398 } 399 400 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 401/* _tnl_need_dlist_norm_lengths( ctx, GL_FALSE ); */ 402 } 403 404 _mesa_compute_version(ctx); 405 if (ctx->Version < major_version * 10 + minor_version) { 406 radeonDestroyContext(driContextPriv); 407 *error = __DRI_CTX_ERROR_BAD_VERSION; 408 return GL_FALSE; 409 } 410 411 *error = __DRI_CTX_ERROR_SUCCESS; 412 return GL_TRUE; 413} 414