radeon_context.h revision 30daa7529331057ecb470efb500152e9c4aa1ae5
15df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */ 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/************************************************************************** 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul VA Linux Systems Inc., Fremont, California. 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulAll Rights Reserved. 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulPermission is hereby granted, free of charge, to any person obtaining 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paula copy of this software and associated documentation files (the 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul"Software"), to deal in the Software without restriction, including 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulwithout limitation the rights to use, copy, modify, merge, publish, 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Pauldistribute, sublicense, and/or sell copies of the Software, and to 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulpermit persons to whom the Software is furnished to do so, subject to 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulthe following conditions: 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulThe above copyright notice and this permission notice (including the 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulnext paragraph) shall be included in all copies or substantial 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulportions of the Software. 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul**************************************************************************/ 305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* 325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Authors: 335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Kevin E. Martin <martin@valinux.com> 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Gareth Hughes <gareth@valinux.com> 355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Keith Whitwell <keith@tungstengraphics.com> 365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#ifndef __RADEON_CONTEXT_H__ 395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define __RADEON_CONTEXT_H__ 405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 418a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt#include "tnl/t_vertex.h" 425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "dri_util.h" 436ddfdff659196cf4eeb0e5fed70ddd1ced0d16fcJon Smirl#include "drm.h" 446ddfdff659196cf4eeb0e5fed70ddd1ced0d16fcJon Smirl#include "radeon_drm.h" 455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "texmem.h" 465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "macros.h" 485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "mtypes.h" 495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "colormac.h" 505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_context; 525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paultypedef struct radeon_context radeonContextRec; 535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paultypedef struct radeon_context *radeonContextPtr; 545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_lock.h" 565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_screen.h" 575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "mm.h" 585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5957c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell#include "math/m_vector.h" 6057c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell 615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Flags for software fallback cases */ 625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* See correponding strings in radeon_swtcl.c */ 635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_TEXTURE 0x0001 645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_STENCIL 0x0004 665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_RENDER_MODE 0x0008 675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_BLEND_EQ 0x0010 685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_BLEND_FUNC 0x0020 695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_DISABLE 0x0040 705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_FALLBACK_BORDER_MODE 0x0080 715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* The blit width for texture uploads 735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define BLIT_WIDTH_BYTES 1024 755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Use the templated vertex format: 775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define COLOR_IS_RGBA 795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TAG(x) radeon##x 805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "tnl_dd/t_dd_vertex.h" 815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#undef TAG 825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paultypedef void (*radeon_tri_func)( radeonContextPtr, 845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonVertex *, 855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonVertex *, 865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonVertex * ); 875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paultypedef void (*radeon_line_func)( radeonContextPtr, 895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonVertex *, 905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonVertex * ); 915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paultypedef void (*radeon_point_func)( radeonContextPtr, 935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonVertex * ); 945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_colorbuffer_state { 975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint clear; 9899ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane int roundEnable; 995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_depthbuffer_state { 1035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint clear; 1045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLfloat scale; 1055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_scissor_state { 108ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t rect; 1095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean enabled; 1105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint numClipRects; /* Cliprects active */ 1125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint numAllocedClipRects; /* Cliprects available */ 113ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *pClipRects; 1145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_stencilbuffer_state { 1175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean hwBuffer; 1185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint clear; /* rb3d_stencilrefmask value */ 1195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_stipple_state { 1225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint mask[32]; 1235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12530daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ 12630daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger#define RADEON_ST_BIT(unit) \ 12730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) 1285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12930daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger#define RADEON_Q_BIT(unit) \ 13030daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) 1315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_0 0x1 1335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_1 0x2 13430daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger#define TEX_2 0x4 13530daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger#define TEX_ALL 0x7 1365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paultypedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 1385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Texture object in locally shared texture space. 1405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 1415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_tex_obj { 1425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul driTextureObject base; 1435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint bufAddr; /* Offset to start of locally 1455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul shared texture block */ 1465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint dirty_state; /* Flags (1 per texunit) for 1485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul whether or not this texobj 1495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul has dirty hardware state 1505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (pp_*) that needs to be 1515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul brought into the 1525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul texunit. */ 1535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 154ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; 1555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Six, for the cube faces */ 1565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_txfilter; /* hardware register values */ 1585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_txformat; 1595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_txoffset; /* Image location in texmem. 1605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul All cube faces follow. */ 1615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_txsize; /* npot only */ 1625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_txpitch; /* npot only */ 1635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_border_color; 1645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 1655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean border_fallback; 1674837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger 1684837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger GLuint tile_bits; /* hw texture tile bits used on this texture */ 1695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_texture_env_state { 1735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonTexObjPtr texobj; 1745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLenum format; 1755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLenum envMode; 1765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_texture_state { 1795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 1805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_state_atom { 1845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom *next, *prev; 1855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const char *name; /* for debug */ 1865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int cmd_size; /* size in bytes */ 1875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint is_tcl; 1885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int *cmd; /* one or more cmd's */ 1895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int *lastcmd; /* one or more cmd's */ 19022d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling GLboolean dirty; /* dirty-mark in emit_state_list */ 1915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean (*check)( GLcontext * ); /* is this state active? */ 1925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 1934837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger 1945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Trying to keep these relatively short as the variables are becoming 1975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * extravagently long. Drop the driver name prefix off the front of 1985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * everything - I think we know which driver we're in by now, and keep the 1995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * prefix to 3 letters unless absolutely impossible. 2005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 2015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_CMD_0 0 2035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_PP_MISC 1 2045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_PP_FOG_COLOR 2 2055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RE_SOLID_COLOR 3 2065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_BLENDCNTL 4 2075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_DEPTHOFFSET 5 2085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_DEPTHPITCH 6 2095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_ZSTENCILCNTL 7 2105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_CMD_1 8 2115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_PP_CNTL 9 2125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_CNTL 10 2135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_COLOROFFSET 11 2145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_CMD_2 12 2155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_RB3D_COLORPITCH 13 2165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define CTX_STATE_SIZE 14 2175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SET_CMD_0 0 2195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SET_SE_CNTL 1 2205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SET_SE_COORDFMT 2 2215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SET_CMD_1 3 2225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SET_SE_CNTL_STATUS 4 2235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SET_STATE_SIZE 5 2245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIN_CMD_0 0 2265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIN_RE_LINE_PATTERN 1 2275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIN_RE_LINE_STATE 2 2285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIN_CMD_1 3 2295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIN_SE_LINE_WIDTH 4 2305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIN_STATE_SIZE 5 2315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSK_CMD_0 0 2335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSK_RB3D_STENCILREFMASK 1 2345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSK_RB3D_ROPCNTL 2 2355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSK_RB3D_PLANEMASK 3 2365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSK_STATE_SIZE 4 2375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_CMD_0 0 2395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_SE_VPORT_XSCALE 1 2405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_SE_VPORT_XOFFSET 2 2415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_SE_VPORT_YSCALE 3 2425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_SE_VPORT_YOFFSET 4 2435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_SE_VPORT_ZSCALE 5 2445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_SE_VPORT_ZOFFSET 6 2455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VPT_STATE_SIZE 7 2465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSC_CMD_0 0 2485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSC_RE_MISC 1 2495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MSC_STATE_SIZE 2 2505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_CMD_0 0 2525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_TXFILTER 1 2535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_TXFORMAT 2 2545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_TXOFFSET 3 2555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_TXCBLEND 4 2565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_TXABLEND 5 2575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_TFACTOR 6 2585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_CMD_1 7 2595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_PP_BORDER_COLOR 8 2605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TEX_STATE_SIZE 9 2615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TXR_CMD_0 0 /* rectangle textures */ 2635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 2645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 2655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TXR_STATE_SIZE 3 2665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define ZBS_CMD_0 0 2685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define ZBS_SE_ZBIAS_FACTOR 1 2695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define ZBS_SE_ZBIAS_CONSTANT 2 2705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define ZBS_STATE_SIZE 3 2715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_CMD_0 0 2735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_OUTPUT_VTXFMT 1 2745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_OUTPUT_VTXSEL 2 2755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_MATRIX_SELECT_0 3 2765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_MATRIX_SELECT_1 4 2775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_UCP_VERT_BLEND_CTL 5 2785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_TEXTURE_PROC_CTL 6 2795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_LIGHT_MODEL_CTL 7 2805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_PER_LIGHT_CTL_0 8 2815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_PER_LIGHT_CTL_1 9 2825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_PER_LIGHT_CTL_2 10 2835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_PER_LIGHT_CTL_3 11 2845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define TCL_STATE_SIZE 12 2855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_CMD_0 0 2875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_EMMISSIVE_RED 1 2885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_EMMISSIVE_GREEN 2 2895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_EMMISSIVE_BLUE 3 2905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_EMMISSIVE_ALPHA 4 2915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_AMBIENT_RED 5 2925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_AMBIENT_GREEN 6 2935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_AMBIENT_BLUE 7 2945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_AMBIENT_ALPHA 8 2955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_DIFFUSE_RED 9 2965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_DIFFUSE_GREEN 10 2975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_DIFFUSE_BLUE 11 2985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_DIFFUSE_ALPHA 12 2995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_SPECULAR_RED 13 3005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_SPECULAR_GREEN 14 3015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_SPECULAR_BLUE 15 3025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_SPECULAR_ALPHA 16 3035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_SHININESS 17 3045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MTL_STATE_SIZE 18 3055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VTX_CMD_0 0 3075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VTX_SE_COORD_FMT 1 3085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define VTX_STATE_SIZE 2 3095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MAT_CMD_0 0 3115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MAT_ELT_0 1 3125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define MAT_STATE_SIZE 17 3135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GRD_CMD_0 0 3155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GRD_VERT_GUARD_CLIP_ADJ 1 3165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GRD_VERT_GUARD_DISCARD_ADJ 2 3175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GRD_HORZ_GUARD_CLIP_ADJ 3 3185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GRD_HORZ_GUARD_DISCARD_ADJ 4 3195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GRD_STATE_SIZE 5 3205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* position changes frequently when lighting in modelpos - separate 3225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * out to new state item? 3235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_CMD_0 0 3255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_AMBIENT_RED 1 3265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_AMBIENT_GREEN 2 3275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_AMBIENT_BLUE 3 3285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_AMBIENT_ALPHA 4 3295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIFFUSE_RED 5 3305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIFFUSE_GREEN 6 3315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIFFUSE_BLUE 7 3325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIFFUSE_ALPHA 8 3335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPECULAR_RED 9 3345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPECULAR_GREEN 10 3355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPECULAR_BLUE 11 3365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPECULAR_ALPHA 12 3375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_POSITION_X 13 3385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_POSITION_Y 14 3395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_POSITION_Z 15 3405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_POSITION_W 16 3415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIRECTION_X 17 3425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIRECTION_Y 18 3435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIRECTION_Z 19 3445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_DIRECTION_W 20 3455d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_QUADRATIC 21 3465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_ATTEN_LINEAR 22 3475d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST 23 3485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_ATTEN_XXX 24 3495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_CMD_1 25 3505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPOT_DCD 26 3515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPOT_EXPONENT 27 3525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPOT_CUTOFF 28 3535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_SPECULAR_THRESH 29 3545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_RANGE_CUTOFF 30 /* ? */ 3555d00e131d8a264498b8d050c3eded093ee5c42f2Michel Dänzer#define LIT_ATTEN_CONST_INV 31 3565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define LIT_STATE_SIZE 32 3575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Fog 3595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define FOG_CMD_0 0 3615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define FOG_R 1 3625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define FOG_C 2 3635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define FOG_D 3 3645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define FOG_PAD 4 3655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define FOG_STATE_SIZE 5 3665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* UCP 3685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define UCP_CMD_0 0 3705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define UCP_X 1 3715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define UCP_Y 2 3725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define UCP_Z 3 3735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define UCP_W 4 3745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define UCP_STATE_SIZE 5 3755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* GLT - Global ambient 3775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GLT_CMD_0 0 3795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GLT_RED 1 3805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GLT_GREEN 2 3815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GLT_BLUE 3 3825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GLT_ALPHA 4 3835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define GLT_STATE_SIZE 5 3845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* EYE 3865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define EYE_CMD_0 0 3885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define EYE_X 1 3895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define EYE_Y 2 3905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define EYE_Z 3 3915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define EYE_RESCALE_FACTOR 4 3925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define EYE_STATE_SIZE 5 3935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SHN_CMD_0 0 3955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SHN_SHININESS 1 3965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define SHN_STATE_SIZE 2 3975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_hw_state { 4035562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt /* Head of the linked list of state atoms. */ 4045562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt struct radeon_state_atom atomlist; 4055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Hardware state, stored as cmdbuf commands: 4075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * -- Need to doublebuffer for 4085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * - eliding noop statechange loops? (except line stipple count) 4095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 4105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom ctx; 4115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom set; 4125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom lin; 4135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom msk; 4145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom vpt; 4155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom tcl; 4165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom msc; 41730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger struct radeon_state_atom tex[3]; 4185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom zbs; 4195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom mtl; 42030daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger struct radeon_state_atom mat[6]; 4215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 4225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom ucp[6]; 4235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom eye; /* eye pos */ 4245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom grd; /* guard band clipping */ 4255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom fog; 4265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state_atom glt; 42730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger struct radeon_state_atom txr[3]; /* for NPOT */ 4286f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt 4296f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt int max_state_size; /* Number of bytes necessary for a full state emit. */ 4305562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt GLboolean is_dirty, all_dirty; 4315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 4325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_state { 4345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Derived state for internal purposes: 4355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 4365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_colorbuffer_state color; 4375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_depthbuffer_state depth; 4385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_scissor_state scissor; 4395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_stencilbuffer_state stencil; 4405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_stipple_state stipple; 4415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_texture_state texture; 4425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 4435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Need refcounting on dma buffers: 4465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 4475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_dma_buffer { 4485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int refcount; /* the number of retained regions in buf */ 4495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmBufPtr buf; 4505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 4515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 452bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 4535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (rvb)->address - rmesa->dma.buf0_address + \ 4545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (rvb)->start) 4555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* A retained region, eg vertices for indexed vertices. 4575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 4585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_dma_region { 4595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_buffer *buf; 4605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul char *address; /* == buf->address */ 4615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int start, end, ptr; /* offsets from start of buf */ 4625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int aos_start; 4635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int aos_stride; 4645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int aos_size; 4655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 4665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_dma { 4695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Active dma region. Allocations for vertices and retained 4705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * regions come from here. Also used for emitting random vertices, 4715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * these may be flushed by calling flush_current(); 4725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 4735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region current; 4745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul void (*flush)( radeonContextPtr ); 4765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul char *buf0_address; /* start of buf[0], for index calcs */ 4785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint nr_released_bufs; /* flush after so many buffers released */ 4795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 4805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_dri_mirror { 4825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIcontextPrivate *context; /* DRI context */ 4835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIscreenPrivate *screen; /* DRI screen */ 4845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */ 4855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 486c06b25594e5effe34a90c067e1a3da0f61cf2b13Ian Romanick drm_context_t hwContext; 487ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_hw_lock_t *hwLock; 4885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int fd; 4895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int drmMinor; 4905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 4915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_CMD_BUF_SZ (8*1024) 4945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_store { 4965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint statenr; 4975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint primnr; 4985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul char cmd_buf[RADEON_CMD_BUF_SZ]; 4995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int cmd_used; 5005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int elts_start; 5015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 5025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* radeon_tcl.c 5055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_tcl_info { 5075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format; 5085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint last_offset; 5095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint hw_primitive; 5105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 51157c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell /* Temporary for cases where incoming vertex data is incompatible 51257c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell * with maos code. 51357c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell */ 51457c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell GLvector4f ObjClean; 51557c9814b9e87924696df4c741861c29d4236d1ebKeith Whitwell 5165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region *aos_components[8]; 5175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint nr_aos_components; 5185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint *Elts; 5205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region indexed_verts; 5225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region obj; 5235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region rgba; 5245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region spec; 5255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region fog; 5265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 5275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region norm; 5285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 5295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* radeon_swtcl.c 5325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_swtcl_info { 5345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint RenderIndex; 5355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_size; 5365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format; 5378a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt 5388a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 5398a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt GLuint vertex_attr_count; 5408a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt 5415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLubyte *verts; 5425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Fallback rasterization functions 5445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeon_point_func draw_point; 5465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeon_line_func draw_line; 5475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeon_tri_func draw_tri; 5485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint hw_primitive; 5505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLenum render_primitive; 5515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint numverts; 5525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5538a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt /** 5548a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt * Offset of the 4UB color data within a hardware (swtcl) vertex. 5558a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt */ 5568a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt GLuint coloroffset; 5578a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt 5588a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt /** 5598a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 5608a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt */ 5618a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt GLuint specoffset; 5628a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt 5638a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt GLboolean needproj; 5648a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt 5655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region indexed_verts; 5665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 5675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_ioctl { 5705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_offset; 5715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_size; 5725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 5735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_MAX_PRIMS 64 5775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Want to keep a cache of these around. Each is parameterized by 5805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * only a single value which has only a small range. Only expect a 5815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * few, so just rescan the list each time? 5825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 5835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct dynfn { 5845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *next, *prev; 5855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int key; 5865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul char *code; 5875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 5885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct dfn_lists { 5905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Vertex2f; 5915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Vertex2fv; 5925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Vertex3f; 5935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Vertex3fv; 5945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color4ub; 5955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color4ubv; 5965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color3ub; 5975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color3ubv; 5985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color4f; 5995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color4fv; 6005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color3f; 6015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Color3fv; 6025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn SecondaryColor3ubEXT; 6035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn SecondaryColor3ubvEXT; 6045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn SecondaryColor3fEXT; 6055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn SecondaryColor3fvEXT; 6065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Normal3f; 6075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn Normal3fv; 6085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn TexCoord2f; 6095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn TexCoord2fv; 6105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn TexCoord1f; 6115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn TexCoord1fv; 6125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn MultiTexCoord2fARB; 6135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn MultiTexCoord2fvARB; 6145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn MultiTexCoord1fARB; 6155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn MultiTexCoord1fvARB; 6165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 6175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct dfn_generators { 6195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Vertex2f)( GLcontext *, int ); 6205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Vertex2fv)( GLcontext *, int ); 6215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Vertex3f)( GLcontext *, int ); 6225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Vertex3fv)( GLcontext *, int ); 6235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color4ub)( GLcontext *, int ); 6245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color4ubv)( GLcontext *, int ); 6255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color3ub)( GLcontext *, int ); 6265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color3ubv)( GLcontext *, int ); 6275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color4f)( GLcontext *, int ); 6285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color4fv)( GLcontext *, int ); 6295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color3f)( GLcontext *, int ); 6305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Color3fv)( GLcontext *, int ); 6315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int ); 6325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int ); 6335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int ); 6345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int ); 6355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Normal3f)( GLcontext *, int ); 6365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*Normal3fv)( GLcontext *, int ); 6375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*TexCoord2f)( GLcontext *, int ); 6385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*TexCoord2fv)( GLcontext *, int ); 6395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*TexCoord1f)( GLcontext *, int ); 6405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*TexCoord1fv)( GLcontext *, int ); 6415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int ); 6425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int ); 6435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int ); 6445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int ); 6455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 6465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_prim { 6505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint start; 6515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint end; 6525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint prim; 6535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 6545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 65530daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger/* A maximum total of 20 elements per vertex: 3 floats for position, 3 65630daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger * floats for normal, 4 floats for color, 4 bytes for secondary color, 65730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger * 3 floats for each texture unit (9 floats total). 65830daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger * 65930daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger * The position data is never actually stored here, so 3 elements could be 66030daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger * trimmed out of the buffer. This number is only valid for vtxfmt! 66130daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger */ 66230daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger#define RADEON_MAX_VERTEX_SIZE 20 66330daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger 6645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_vbinfo { 6655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint counter, initial_counter; 6665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint *dmaptr; 6675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul void (*notify)( void ); 6685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint vertex_size; 6695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 67030daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger union { float f; int i; radeon_color_t color; } vertex[RADEON_MAX_VERTEX_SIZE]; 6715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLfloat *normalptr; 6735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLfloat *floatcolorptr; 6745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeon_color_t *colorptr; 6755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLfloat *floatspecptr; 6765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeon_color_t *specptr; 67730daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheidegger GLfloat *texcoordptr[4]; /* 3 (TMU) + 1 for radeon_vtxfmt_c.c when GL_TEXTURE3 */ 6785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ 6805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint primflags; 6815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */ 6825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean installed; 6835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean fell_back; 6845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean recheck; 6855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint nrverts; 6865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format; 6875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint installed_vertex_format; 6895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint installed_color_3f_sz; 6905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_prim primlist[RADEON_MAX_PRIMS]; 6925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int nrprims; 6935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dfn_lists dfn_cache; 6955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct dfn_generators codegen; 6965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLvertexformat vtxfmt; 6975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 6985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstruct radeon_context { 7035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLcontext *glCtx; /* Mesa context */ 7045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Driver and hardware state management 7065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_hw_state hw; 7085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_state state; 7095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Texture object bookkeeping 7115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul unsigned nr_heaps; 7135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 7145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul driTextureObject swapped; 715d907a75498360fb96ec2314bb0abb105be74d500Alan Hourihane int texture_depth; 716d3fd7ba8af15bead2f770d68a893449adeb11397Brian Paul float initialMaxAnisotropy; 7175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Rasterization and vertex state: 7195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint TclFallback; 7215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint Fallback; 7225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint NewGLState; 7238a1df968627de01d04f3d692fd81108ba6492c18Eric Anholt GLuint tnl_index; /* index of bits for last tnl_install_attrs */ 7245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Vertex buffers 7265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_ioctl ioctl; 7285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma dma; 7295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_store store; 7307a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt /* A full state emit as of the first state emit in the main store, in case 7317a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt * the context is lost. 7327a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt */ 7337a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt struct radeon_store backup_store; 7345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Page flipping 7365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint doPageFlip; 7385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Busy waiting 7405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint do_usleeps; 7425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint do_irqs; 7435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint irqsEmitted; 744ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_irq_wait_t iw; 7455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Drawable, cliprect and scissor information 7475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint numClipRects; /* Cliprects for the draw buffer */ 749ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *pClipRects; 7505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul unsigned int lastStamp; 7515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean lost_context; 7527a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt GLboolean save_on_next_emit; 7535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonScreenPtr radeonScreen; /* Screen private DRI data */ 754ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_sarea_t *sarea; /* Private SAREA data */ 7555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* TCL stuff 7575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 7595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 7605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 7615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint TexGenEnabled; 762a3c8de2fa7fba22647e5b3e8cfb05c85d1a5a980Roland Scheidegger GLuint NeedTexMatrix; 763a3c8de2fa7fba22647e5b3e8cfb05c85d1a5a980Roland Scheidegger GLuint TexMatColSwap; 764a3c8de2fa7fba22647e5b3e8cfb05c85d1a5a980Roland Scheidegger GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; 7655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint last_ReallyEnabled; 7665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* VBI 7685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vbl_seq; 7705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vblank_flags; 7715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 772afa446db83ecf5dcb38ce46648fb12911628de32Ian Romanick int64_t swap_ust; 773afa446db83ecf5dcb38ce46648fb12911628de32Ian Romanick int64_t swap_missed_ust; 7745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint swap_count; 7765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint swap_missed_count; 7775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* radeon_tcl.c 7805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_tcl_info tcl; 7825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* radeon_swtcl.c 7845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_swtcl_info swtcl; 7865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* radeon_vtxfmt.c 7885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_vbinfo vb; 7905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Mirrors of some DRI state 7925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dri_mirror dri; 7945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 795bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl /* Configuration cache 796bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl */ 797bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl driOptionCache optionCache; 798bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 799b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger GLboolean using_hyperz; 8004837ea30208d002bc36a836d2117f826d40c8bfaRoland Scheidegger GLboolean texmicrotile; 801b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger 8025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Performance counters 8035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint boxes; /* Draw performance boxes */ 8055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint hardwareWentIdle; 8065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint c_clears; 8075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint c_drawWaits; 8085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint c_textureSwaps; 8095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint c_textureBytes; 8105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint c_vertexBuffers; 8115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 8125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 8145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic __inline GLuint radeonPackColor( GLuint cpp, 8175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLubyte r, GLubyte g, 8185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLubyte b, GLubyte a ) 8195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 8205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul switch ( cpp ) { 8215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case 2: 8225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return PACK_COLOR_565( r, g, b ); 8235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case 4: 8245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return PACK_COLOR_8888( a, r, g, b ); 8255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul default: 8265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return 0; 8275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_OLD_PACKETS 1 8315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ); 8345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern GLboolean radeonCreateContext(const __GLcontextModes *glVisual, 8355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIcontextPrivate *driContextPriv, 8365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul void *sharedContextPrivate); 8375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv ); 8385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, 8395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIdrawablePrivate *driDrawPriv, 8405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIdrawablePrivate *driReadPriv ); 8415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv ); 8425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ================================================================ 8445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Debugging: 8455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DO_DEBUG 1 8475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if DO_DEBUG 8495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern int RADEON_DEBUG; 8505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 8515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_DEBUG 0 8525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 8535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_TEXTURE 0x001 8555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_STATE 0x002 8565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_IOCTL 0x004 8575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_PRIMS 0x008 8585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_VERTS 0x010 8595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_FALLBACKS 0x020 8605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_VFMT 0x040 8615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_CODEGEN 0x080 8625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_VERBOSE 0x100 8635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_DRI 0x200 8645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_DMA 0x400 8655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define DEBUG_SANITY 0x800 866150ed2e43d5541556d282cae728cebeec692e07aDave Airlie#define DEBUG_SYNC 0x1000 8675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif /* __RADEON_CONTEXT_H__ */ 869