radeon_context.h revision 4637235183b80963536f2364e4d50fcb894886dd
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 6 7The Weather Channel (TM) funded Tungsten Graphics to develop the 8initial release of the Radeon 8500 driver under the XFree86 license. 9This notice must be preserved. 10 11All Rights Reserved. 12 13Permission is hereby granted, free of charge, to any person obtaining 14a copy of this software and associated documentation files (the 15"Software"), to deal in the Software without restriction, including 16without limitation the rights to use, copy, modify, merge, publish, 17distribute, sublicense, and/or sell copies of the Software, and to 18permit persons to whom the Software is furnished to do so, subject to 19the following conditions: 20 21The above copyright notice and this permission notice (including the 22next paragraph) shall be included in all copies or substantial 23portions of the Software. 24 25THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 33**************************************************************************/ 34 35/* 36 * Authors: 37 * Gareth Hughes <gareth@valinux.com> 38 * Keith Whitwell <keith@tungstengraphics.com> 39 * Kevin E. Martin <martin@valinux.com> 40 * Nicolai Haehnle <prefect_@gmx.net> 41 */ 42 43#ifndef __RADEON_CONTEXT_H__ 44#define __RADEON_CONTEXT_H__ 45 46#include "tnl/t_vertex.h" 47#include "dri_util.h" 48#include "drm.h" 49#include "radeon_drm.h" 50#include "texmem.h" 51#include "main/macros.h" 52#include "main/mtypes.h" 53#include "main/colormac.h" 54#include "radeon_screen.h" 55 56#include "common_context.h" 57 58 59struct r100_context; 60typedef struct r100_context r100ContextRec; 61typedef struct r100_context *r100ContextPtr; 62 63#include "radeon_lock.h" 64 65 66 67#define R100_TEX_ALL 0x7 68 69/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ 70#define RADEON_ST_BIT(unit) \ 71(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) 72 73#define RADEON_Q_BIT(unit) \ 74(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) 75 76struct radeon_texture_env_state { 77 radeonTexObjPtr texobj; 78 GLenum format; 79 GLenum envMode; 80}; 81 82struct radeon_texture_state { 83 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 84}; 85 86/* Trying to keep these relatively short as the variables are becoming 87 * extravagently long. Drop the driver name prefix off the front of 88 * everything - I think we know which driver we're in by now, and keep the 89 * prefix to 3 letters unless absolutely impossible. 90 */ 91 92#define CTX_CMD_0 0 93#define CTX_PP_MISC 1 94#define CTX_PP_FOG_COLOR 2 95#define CTX_RE_SOLID_COLOR 3 96#define CTX_RB3D_BLENDCNTL 4 97#define CTX_RB3D_DEPTHOFFSET 5 98#define CTX_RB3D_DEPTHPITCH 6 99#define CTX_RB3D_ZSTENCILCNTL 7 100#define CTX_CMD_1 8 101#define CTX_PP_CNTL 9 102#define CTX_RB3D_CNTL 10 103#define CTX_RB3D_COLOROFFSET 11 104#define CTX_CMD_2 12 105#define CTX_RB3D_COLORPITCH 13 106#define CTX_STATE_SIZE 14 107 108#define SET_CMD_0 0 109#define SET_SE_CNTL 1 110#define SET_SE_COORDFMT 2 111#define SET_CMD_1 3 112#define SET_SE_CNTL_STATUS 4 113#define SET_STATE_SIZE 5 114 115#define LIN_CMD_0 0 116#define LIN_RE_LINE_PATTERN 1 117#define LIN_RE_LINE_STATE 2 118#define LIN_CMD_1 3 119#define LIN_SE_LINE_WIDTH 4 120#define LIN_STATE_SIZE 5 121 122#define MSK_CMD_0 0 123#define MSK_RB3D_STENCILREFMASK 1 124#define MSK_RB3D_ROPCNTL 2 125#define MSK_RB3D_PLANEMASK 3 126#define MSK_STATE_SIZE 4 127 128#define VPT_CMD_0 0 129#define VPT_SE_VPORT_XSCALE 1 130#define VPT_SE_VPORT_XOFFSET 2 131#define VPT_SE_VPORT_YSCALE 3 132#define VPT_SE_VPORT_YOFFSET 4 133#define VPT_SE_VPORT_ZSCALE 5 134#define VPT_SE_VPORT_ZOFFSET 6 135#define VPT_STATE_SIZE 7 136 137#define MSC_CMD_0 0 138#define MSC_RE_MISC 1 139#define MSC_STATE_SIZE 2 140 141#define TEX_CMD_0 0 142#define TEX_PP_TXFILTER 1 143#define TEX_PP_TXFORMAT 2 144#define TEX_PP_TXOFFSET 3 145#define TEX_PP_TXCBLEND 4 146#define TEX_PP_TXABLEND 5 147#define TEX_PP_TFACTOR 6 148#define TEX_CMD_1 7 149#define TEX_PP_BORDER_COLOR 8 150#define TEX_STATE_SIZE 9 151 152#define TXR_CMD_0 0 /* rectangle textures */ 153#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 154#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 155#define TXR_STATE_SIZE 3 156 157#define CUBE_CMD_0 0 158#define CUBE_PP_CUBIC_FACES 1 159#define CUBE_CMD_1 2 160#define CUBE_PP_CUBIC_OFFSET_0 3 161#define CUBE_PP_CUBIC_OFFSET_1 4 162#define CUBE_PP_CUBIC_OFFSET_2 5 163#define CUBE_PP_CUBIC_OFFSET_3 6 164#define CUBE_PP_CUBIC_OFFSET_4 7 165#define CUBE_STATE_SIZE 8 166 167#define ZBS_CMD_0 0 168#define ZBS_SE_ZBIAS_FACTOR 1 169#define ZBS_SE_ZBIAS_CONSTANT 2 170#define ZBS_STATE_SIZE 3 171 172#define TCL_CMD_0 0 173#define TCL_OUTPUT_VTXFMT 1 174#define TCL_OUTPUT_VTXSEL 2 175#define TCL_MATRIX_SELECT_0 3 176#define TCL_MATRIX_SELECT_1 4 177#define TCL_UCP_VERT_BLEND_CTL 5 178#define TCL_TEXTURE_PROC_CTL 6 179#define TCL_LIGHT_MODEL_CTL 7 180#define TCL_PER_LIGHT_CTL_0 8 181#define TCL_PER_LIGHT_CTL_1 9 182#define TCL_PER_LIGHT_CTL_2 10 183#define TCL_PER_LIGHT_CTL_3 11 184#define TCL_STATE_SIZE 12 185 186#define MTL_CMD_0 0 187#define MTL_EMMISSIVE_RED 1 188#define MTL_EMMISSIVE_GREEN 2 189#define MTL_EMMISSIVE_BLUE 3 190#define MTL_EMMISSIVE_ALPHA 4 191#define MTL_AMBIENT_RED 5 192#define MTL_AMBIENT_GREEN 6 193#define MTL_AMBIENT_BLUE 7 194#define MTL_AMBIENT_ALPHA 8 195#define MTL_DIFFUSE_RED 9 196#define MTL_DIFFUSE_GREEN 10 197#define MTL_DIFFUSE_BLUE 11 198#define MTL_DIFFUSE_ALPHA 12 199#define MTL_SPECULAR_RED 13 200#define MTL_SPECULAR_GREEN 14 201#define MTL_SPECULAR_BLUE 15 202#define MTL_SPECULAR_ALPHA 16 203#define MTL_SHININESS 17 204#define MTL_STATE_SIZE 18 205 206#define VTX_CMD_0 0 207#define VTX_SE_COORD_FMT 1 208#define VTX_STATE_SIZE 2 209 210#define MAT_CMD_0 0 211#define MAT_ELT_0 1 212#define MAT_STATE_SIZE 17 213 214#define GRD_CMD_0 0 215#define GRD_VERT_GUARD_CLIP_ADJ 1 216#define GRD_VERT_GUARD_DISCARD_ADJ 2 217#define GRD_HORZ_GUARD_CLIP_ADJ 3 218#define GRD_HORZ_GUARD_DISCARD_ADJ 4 219#define GRD_STATE_SIZE 5 220 221/* position changes frequently when lighting in modelpos - separate 222 * out to new state item? 223 */ 224#define LIT_CMD_0 0 225#define LIT_AMBIENT_RED 1 226#define LIT_AMBIENT_GREEN 2 227#define LIT_AMBIENT_BLUE 3 228#define LIT_AMBIENT_ALPHA 4 229#define LIT_DIFFUSE_RED 5 230#define LIT_DIFFUSE_GREEN 6 231#define LIT_DIFFUSE_BLUE 7 232#define LIT_DIFFUSE_ALPHA 8 233#define LIT_SPECULAR_RED 9 234#define LIT_SPECULAR_GREEN 10 235#define LIT_SPECULAR_BLUE 11 236#define LIT_SPECULAR_ALPHA 12 237#define LIT_POSITION_X 13 238#define LIT_POSITION_Y 14 239#define LIT_POSITION_Z 15 240#define LIT_POSITION_W 16 241#define LIT_DIRECTION_X 17 242#define LIT_DIRECTION_Y 18 243#define LIT_DIRECTION_Z 19 244#define LIT_DIRECTION_W 20 245#define LIT_ATTEN_QUADRATIC 21 246#define LIT_ATTEN_LINEAR 22 247#define LIT_ATTEN_CONST 23 248#define LIT_ATTEN_XXX 24 249#define LIT_CMD_1 25 250#define LIT_SPOT_DCD 26 251#define LIT_SPOT_EXPONENT 27 252#define LIT_SPOT_CUTOFF 28 253#define LIT_SPECULAR_THRESH 29 254#define LIT_RANGE_CUTOFF 30 /* ? */ 255#define LIT_ATTEN_CONST_INV 31 256#define LIT_STATE_SIZE 32 257 258/* Fog 259 */ 260#define FOG_CMD_0 0 261#define FOG_R 1 262#define FOG_C 2 263#define FOG_D 3 264#define FOG_PAD 4 265#define FOG_STATE_SIZE 5 266 267/* UCP 268 */ 269#define UCP_CMD_0 0 270#define UCP_X 1 271#define UCP_Y 2 272#define UCP_Z 3 273#define UCP_W 4 274#define UCP_STATE_SIZE 5 275 276/* GLT - Global ambient 277 */ 278#define GLT_CMD_0 0 279#define GLT_RED 1 280#define GLT_GREEN 2 281#define GLT_BLUE 3 282#define GLT_ALPHA 4 283#define GLT_STATE_SIZE 5 284 285/* EYE 286 */ 287#define EYE_CMD_0 0 288#define EYE_X 1 289#define EYE_Y 2 290#define EYE_Z 3 291#define EYE_RESCALE_FACTOR 4 292#define EYE_STATE_SIZE 5 293 294#define SHN_CMD_0 0 295#define SHN_SHININESS 1 296#define SHN_STATE_SIZE 2 297 298struct radeon_hw_state { 299 /* Head of the linked list of state atoms. */ 300 struct radeon_state_atom atomlist; 301 302 /* Hardware state, stored as cmdbuf commands: 303 * -- Need to doublebuffer for 304 * - eliding noop statechange loops? (except line stipple count) 305 */ 306 struct radeon_state_atom ctx; 307 struct radeon_state_atom set; 308 struct radeon_state_atom lin; 309 struct radeon_state_atom msk; 310 struct radeon_state_atom vpt; 311 struct radeon_state_atom tcl; 312 struct radeon_state_atom msc; 313 struct radeon_state_atom tex[3]; 314 struct radeon_state_atom cube[3]; 315 struct radeon_state_atom zbs; 316 struct radeon_state_atom mtl; 317 struct radeon_state_atom mat[6]; 318 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 319 struct radeon_state_atom ucp[6]; 320 struct radeon_state_atom eye; /* eye pos */ 321 struct radeon_state_atom grd; /* guard band clipping */ 322 struct radeon_state_atom fog; 323 struct radeon_state_atom glt; 324 struct radeon_state_atom txr[3]; /* for NPOT */ 325 326 int max_state_size; /* Number of bytes necessary for a full state emit. */ 327 GLboolean is_dirty, all_dirty; 328}; 329 330 331struct radeon_state { 332 struct radeon_colorbuffer_state color; 333 struct radeon_depthbuffer_state depth; 334 struct radeon_scissor_state scissor; 335 struct radeon_stencilbuffer_state stencil; 336 struct radeon_stipple_state stipple; 337 struct radeon_texture_state texture; 338}; 339 340#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ 341 (rvb)->address - rmesa->dma.buf0_address + \ 342 (rvb)->start) 343 344 345#define RADEON_CMD_BUF_SZ (8*1024) 346 347/* radeon_tcl.c 348 */ 349struct radeon_tcl_info { 350 GLuint vertex_format; 351 GLuint hw_primitive; 352 353 /* Temporary for cases where incoming vertex data is incompatible 354 * with maos code. 355 */ 356 GLvector4f ObjClean; 357 358 struct radeon_dma_region *aos_components[8]; 359 GLuint nr_aos_components; 360 361 GLuint *Elts; 362 363 struct radeon_dma_region indexed_verts; 364 struct radeon_dma_region obj; 365 struct radeon_dma_region rgba; 366 struct radeon_dma_region spec; 367 struct radeon_dma_region fog; 368 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 369 struct radeon_dma_region norm; 370}; 371 372/* radeon_swtcl.c 373 */ 374struct radeon_swtcl_info { 375 GLuint RenderIndex; 376 GLuint vertex_size; 377 GLuint vertex_format; 378 379 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 380 GLuint vertex_attr_count; 381 382 GLubyte *verts; 383 384 /* Fallback rasterization functions 385 */ 386 radeon_point_func draw_point; 387 radeon_line_func draw_line; 388 radeon_tri_func draw_tri; 389 390 GLuint hw_primitive; 391 GLenum render_primitive; 392 GLuint numverts; 393 394 /** 395 * Offset of the 4UB color data within a hardware (swtcl) vertex. 396 */ 397 GLuint coloroffset; 398 399 /** 400 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 401 */ 402 GLuint specoffset; 403 404 GLboolean needproj; 405 406 struct radeon_dma_region indexed_verts; 407}; 408 409 410 411/* A maximum total of 20 elements per vertex: 3 floats for position, 3 412 * floats for normal, 4 floats for color, 4 bytes for secondary color, 413 * 3 floats for each texture unit (9 floats total). 414 * 415 * The position data is never actually stored here, so 3 elements could be 416 * trimmed out of the buffer. This number is only valid for vtxfmt! 417 */ 418#define RADEON_MAX_VERTEX_SIZE 20 419 420struct r100_context { 421 struct radeon_context radeon; 422 423 /* Driver and hardware state management 424 */ 425 struct radeon_hw_state hw; 426 struct radeon_state state; 427 428 /* Vertex buffers 429 */ 430 struct radeon_ioctl ioctl; 431 struct radeon_dma dma; 432 struct radeon_store store; 433 /* A full state emit as of the first state emit in the main store, in case 434 * the context is lost. 435 */ 436 struct radeon_store backup_store; 437 438 /* TCL stuff 439 */ 440 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 441 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 442 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 443 GLuint TexGenEnabled; 444 GLuint NeedTexMatrix; 445 GLuint TexMatColSwap; 446 GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; 447 GLuint last_ReallyEnabled; 448 449 /* radeon_tcl.c 450 */ 451 struct radeon_tcl_info tcl; 452 453 /* radeon_swtcl.c 454 */ 455 struct radeon_swtcl_info swtcl; 456 457 GLboolean using_hyperz; 458 GLboolean texmicrotile; 459 460 /* Performance counters 461 */ 462 GLuint boxes; /* Draw performance boxes */ 463 GLuint hardwareWentIdle; 464 GLuint c_clears; 465 GLuint c_drawWaits; 466 GLuint c_textureSwaps; 467 GLuint c_textureBytes; 468 GLuint c_vertexBuffers; 469 470 GLboolean save_on_next_emit; 471}; 472 473#define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) 474 475 476#define RADEON_OLD_PACKETS 1 477 478extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); 479extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 480 __DRIcontextPrivate * driContextPriv, 481 void *sharedContextPrivate); 482extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); 483extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, 484 int x, int y, int w, int h); 485extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, 486 __DRIdrawablePrivate * driDrawPriv, 487 __DRIdrawablePrivate * driReadPriv); 488extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); 489 490/* ================================================================ 491 * Debugging: 492 */ 493#define DO_DEBUG 1 494 495#if DO_DEBUG 496extern int RADEON_DEBUG; 497#else 498#define RADEON_DEBUG 0 499#endif 500 501#endif /* __RADEON_CONTEXT_H__ */ 502