radeon_context.h revision 23295cf8e84495af86f62395d32b3116261927e8
1cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.com/************************************************************************** 2cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.com 38cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.com VA Linux Systems Inc., Fremont, California. 5cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.comCopyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 6cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.com 78cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comThe Weather Channel (TM) funded Tungsten Graphics to develop the 8cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.cominitial release of the Radeon 8500 driver under the XFree86 license. 98cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comThis notice must be preserved. 10cf2cfa174ca878c144e17e9fc60ca8e9070d7dededisonn@google.com 118cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comAll Rights Reserved. 128cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 138cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comPermission is hereby granted, free of charge, to any person obtaining 148cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.coma copy of this software and associated documentation files (the 158cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com"Software"), to deal in the Software without restriction, including 168cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comwithout limitation the rights to use, copy, modify, merge, publish, 178cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comdistribute, sublicense, and/or sell copies of the Software, and to 188cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.compermit persons to whom the Software is furnished to do so, subject to 198cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comthe following conditions: 208cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 218cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comThe above copyright notice and this permission notice (including the 228cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comnext paragraph) shall be included in all copies or substantial 238cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comportions of the Software. 248cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 258cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 268cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 278cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 288cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 298cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 308cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 318cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.comWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 328cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 338cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com**************************************************************************/ 348cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 358cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com/* 368cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com * Authors: 378cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com * Gareth Hughes <gareth@valinux.com> 388cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com * Keith Whitwell <keith@tungstengraphics.com> 398cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com * Kevin E. Martin <martin@valinux.com> 408cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com * Nicolai Haehnle <prefect_@gmx.net> 418cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com */ 428cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 438cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com#ifndef __RADEON_CONTEXT_H__ 448cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com#define __RADEON_CONTEXT_H__ 458cee797901763ab0922eb9ef484cfdcbc94bee54edisonn@google.com 46#include "tnl/t_vertex.h" 47#include "dri_util.h" 48#include "drm.h" 49#include "radeon_drm.h" 50#include "texmem.h" 51#include "main/macros.h" 52#include "main/mtypes.h" 53#include "main/colormac.h" 54#include "radeon_screen.h" 55 56#include "common_context.h" 57#include "common_misc.h" 58 59 60struct r100_context; 61typedef struct r100_context r100ContextRec; 62typedef struct r100_context *r100ContextPtr; 63 64#include "radeon_lock.h" 65 66 67 68#define R100_TEX_ALL 0x7 69 70/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ 71#define RADEON_ST_BIT(unit) \ 72(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) 73 74#define RADEON_Q_BIT(unit) \ 75(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) 76 77struct radeon_texture_env_state { 78 radeonTexObjPtr texobj; 79 GLenum format; 80 GLenum envMode; 81}; 82 83struct radeon_texture_state { 84 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 85}; 86 87/* Trying to keep these relatively short as the variables are becoming 88 * extravagently long. Drop the driver name prefix off the front of 89 * everything - I think we know which driver we're in by now, and keep the 90 * prefix to 3 letters unless absolutely impossible. 91 */ 92 93#define CTX_CMD_0 0 94#define CTX_PP_MISC 1 95#define CTX_PP_FOG_COLOR 2 96#define CTX_RE_SOLID_COLOR 3 97#define CTX_RB3D_BLENDCNTL 4 98#define CTX_RB3D_DEPTHOFFSET 5 99#define CTX_RB3D_DEPTHPITCH 6 100#define CTX_RB3D_ZSTENCILCNTL 7 101#define CTX_CMD_1 8 102#define CTX_PP_CNTL 9 103#define CTX_RB3D_CNTL 10 104#define CTX_RB3D_COLOROFFSET 11 105#define CTX_CMD_2 12 106#define CTX_RB3D_COLORPITCH 13 107#define CTX_STATE_SIZE 14 108 109#define SET_CMD_0 0 110#define SET_SE_CNTL 1 111#define SET_SE_COORDFMT 2 112#define SET_CMD_1 3 113#define SET_SE_CNTL_STATUS 4 114#define SET_STATE_SIZE 5 115 116#define LIN_CMD_0 0 117#define LIN_RE_LINE_PATTERN 1 118#define LIN_RE_LINE_STATE 2 119#define LIN_CMD_1 3 120#define LIN_SE_LINE_WIDTH 4 121#define LIN_STATE_SIZE 5 122 123#define MSK_CMD_0 0 124#define MSK_RB3D_STENCILREFMASK 1 125#define MSK_RB3D_ROPCNTL 2 126#define MSK_RB3D_PLANEMASK 3 127#define MSK_STATE_SIZE 4 128 129#define VPT_CMD_0 0 130#define VPT_SE_VPORT_XSCALE 1 131#define VPT_SE_VPORT_XOFFSET 2 132#define VPT_SE_VPORT_YSCALE 3 133#define VPT_SE_VPORT_YOFFSET 4 134#define VPT_SE_VPORT_ZSCALE 5 135#define VPT_SE_VPORT_ZOFFSET 6 136#define VPT_STATE_SIZE 7 137 138#define MSC_CMD_0 0 139#define MSC_RE_MISC 1 140#define MSC_STATE_SIZE 2 141 142#define TEX_CMD_0 0 143#define TEX_PP_TXFILTER 1 144#define TEX_PP_TXFORMAT 2 145#define TEX_PP_TXOFFSET 3 146#define TEX_PP_TXCBLEND 4 147#define TEX_PP_TXABLEND 5 148#define TEX_PP_TFACTOR 6 149#define TEX_CMD_1 7 150#define TEX_PP_BORDER_COLOR 8 151#define TEX_STATE_SIZE 9 152 153#define TXR_CMD_0 0 /* rectangle textures */ 154#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 155#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 156#define TXR_STATE_SIZE 3 157 158#define CUBE_CMD_0 0 159#define CUBE_PP_CUBIC_FACES 1 160#define CUBE_CMD_1 2 161#define CUBE_PP_CUBIC_OFFSET_0 3 162#define CUBE_PP_CUBIC_OFFSET_1 4 163#define CUBE_PP_CUBIC_OFFSET_2 5 164#define CUBE_PP_CUBIC_OFFSET_3 6 165#define CUBE_PP_CUBIC_OFFSET_4 7 166#define CUBE_STATE_SIZE 8 167 168#define ZBS_CMD_0 0 169#define ZBS_SE_ZBIAS_FACTOR 1 170#define ZBS_SE_ZBIAS_CONSTANT 2 171#define ZBS_STATE_SIZE 3 172 173#define TCL_CMD_0 0 174#define TCL_OUTPUT_VTXFMT 1 175#define TCL_OUTPUT_VTXSEL 2 176#define TCL_MATRIX_SELECT_0 3 177#define TCL_MATRIX_SELECT_1 4 178#define TCL_UCP_VERT_BLEND_CTL 5 179#define TCL_TEXTURE_PROC_CTL 6 180#define TCL_LIGHT_MODEL_CTL 7 181#define TCL_PER_LIGHT_CTL_0 8 182#define TCL_PER_LIGHT_CTL_1 9 183#define TCL_PER_LIGHT_CTL_2 10 184#define TCL_PER_LIGHT_CTL_3 11 185#define TCL_STATE_SIZE 12 186 187#define MTL_CMD_0 0 188#define MTL_EMMISSIVE_RED 1 189#define MTL_EMMISSIVE_GREEN 2 190#define MTL_EMMISSIVE_BLUE 3 191#define MTL_EMMISSIVE_ALPHA 4 192#define MTL_AMBIENT_RED 5 193#define MTL_AMBIENT_GREEN 6 194#define MTL_AMBIENT_BLUE 7 195#define MTL_AMBIENT_ALPHA 8 196#define MTL_DIFFUSE_RED 9 197#define MTL_DIFFUSE_GREEN 10 198#define MTL_DIFFUSE_BLUE 11 199#define MTL_DIFFUSE_ALPHA 12 200#define MTL_SPECULAR_RED 13 201#define MTL_SPECULAR_GREEN 14 202#define MTL_SPECULAR_BLUE 15 203#define MTL_SPECULAR_ALPHA 16 204#define MTL_SHININESS 17 205#define MTL_STATE_SIZE 18 206 207#define VTX_CMD_0 0 208#define VTX_SE_COORD_FMT 1 209#define VTX_STATE_SIZE 2 210 211#define MAT_CMD_0 0 212#define MAT_ELT_0 1 213#define MAT_STATE_SIZE 17 214 215#define GRD_CMD_0 0 216#define GRD_VERT_GUARD_CLIP_ADJ 1 217#define GRD_VERT_GUARD_DISCARD_ADJ 2 218#define GRD_HORZ_GUARD_CLIP_ADJ 3 219#define GRD_HORZ_GUARD_DISCARD_ADJ 4 220#define GRD_STATE_SIZE 5 221 222/* position changes frequently when lighting in modelpos - separate 223 * out to new state item? 224 */ 225#define LIT_CMD_0 0 226#define LIT_AMBIENT_RED 1 227#define LIT_AMBIENT_GREEN 2 228#define LIT_AMBIENT_BLUE 3 229#define LIT_AMBIENT_ALPHA 4 230#define LIT_DIFFUSE_RED 5 231#define LIT_DIFFUSE_GREEN 6 232#define LIT_DIFFUSE_BLUE 7 233#define LIT_DIFFUSE_ALPHA 8 234#define LIT_SPECULAR_RED 9 235#define LIT_SPECULAR_GREEN 10 236#define LIT_SPECULAR_BLUE 11 237#define LIT_SPECULAR_ALPHA 12 238#define LIT_POSITION_X 13 239#define LIT_POSITION_Y 14 240#define LIT_POSITION_Z 15 241#define LIT_POSITION_W 16 242#define LIT_DIRECTION_X 17 243#define LIT_DIRECTION_Y 18 244#define LIT_DIRECTION_Z 19 245#define LIT_DIRECTION_W 20 246#define LIT_ATTEN_QUADRATIC 21 247#define LIT_ATTEN_LINEAR 22 248#define LIT_ATTEN_CONST 23 249#define LIT_ATTEN_XXX 24 250#define LIT_CMD_1 25 251#define LIT_SPOT_DCD 26 252#define LIT_SPOT_EXPONENT 27 253#define LIT_SPOT_CUTOFF 28 254#define LIT_SPECULAR_THRESH 29 255#define LIT_RANGE_CUTOFF 30 /* ? */ 256#define LIT_ATTEN_CONST_INV 31 257#define LIT_STATE_SIZE 32 258 259/* Fog 260 */ 261#define FOG_CMD_0 0 262#define FOG_R 1 263#define FOG_C 2 264#define FOG_D 3 265#define FOG_PAD 4 266#define FOG_STATE_SIZE 5 267 268/* UCP 269 */ 270#define UCP_CMD_0 0 271#define UCP_X 1 272#define UCP_Y 2 273#define UCP_Z 3 274#define UCP_W 4 275#define UCP_STATE_SIZE 5 276 277/* GLT - Global ambient 278 */ 279#define GLT_CMD_0 0 280#define GLT_RED 1 281#define GLT_GREEN 2 282#define GLT_BLUE 3 283#define GLT_ALPHA 4 284#define GLT_STATE_SIZE 5 285 286/* EYE 287 */ 288#define EYE_CMD_0 0 289#define EYE_X 1 290#define EYE_Y 2 291#define EYE_Z 3 292#define EYE_RESCALE_FACTOR 4 293#define EYE_STATE_SIZE 5 294 295#define SHN_CMD_0 0 296#define SHN_SHININESS 1 297#define SHN_STATE_SIZE 2 298 299struct radeon_hw_state { 300 /* Head of the linked list of state atoms. */ 301 struct radeon_state_atom atomlist; 302 303 /* Hardware state, stored as cmdbuf commands: 304 * -- Need to doublebuffer for 305 * - eliding noop statechange loops? (except line stipple count) 306 */ 307 struct radeon_state_atom ctx; 308 struct radeon_state_atom set; 309 struct radeon_state_atom lin; 310 struct radeon_state_atom msk; 311 struct radeon_state_atom vpt; 312 struct radeon_state_atom tcl; 313 struct radeon_state_atom msc; 314 struct radeon_state_atom tex[3]; 315 struct radeon_state_atom cube[3]; 316 struct radeon_state_atom zbs; 317 struct radeon_state_atom mtl; 318 struct radeon_state_atom mat[6]; 319 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 320 struct radeon_state_atom ucp[6]; 321 struct radeon_state_atom eye; /* eye pos */ 322 struct radeon_state_atom grd; /* guard band clipping */ 323 struct radeon_state_atom fog; 324 struct radeon_state_atom glt; 325 struct radeon_state_atom txr[3]; /* for NPOT */ 326 327 int max_state_size; /* Number of bytes necessary for a full state emit. */ 328 GLboolean is_dirty, all_dirty; 329}; 330 331 332struct r100_state { 333 struct radeon_stipple_state stipple; 334 struct radeon_texture_state texture; 335}; 336 337#define GET_START(rvb) (rmesa->radeon.radeonScreen->gart_buffer_offset + \ 338 (rvb)->address - rmesa->dma.buf0_address + \ 339 (rvb)->start) 340 341 342#define RADEON_CMD_BUF_SZ (8*1024) 343 344/* radeon_tcl.c 345 */ 346struct radeon_tcl_info { 347 GLuint vertex_format; 348 GLuint hw_primitive; 349 350 /* Temporary for cases where incoming vertex data is incompatible 351 * with maos code. 352 */ 353 GLvector4f ObjClean; 354 355 struct radeon_dma_region *aos_components[8]; 356 GLuint nr_aos_components; 357 358 GLuint *Elts; 359 360 struct radeon_dma_region indexed_verts; 361 struct radeon_dma_region obj; 362 struct radeon_dma_region rgba; 363 struct radeon_dma_region spec; 364 struct radeon_dma_region fog; 365 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 366 struct radeon_dma_region norm; 367}; 368 369/* radeon_swtcl.c 370 */ 371struct radeon_swtcl_info { 372 GLuint RenderIndex; 373 GLuint vertex_size; 374 GLuint vertex_format; 375 376 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 377 GLuint vertex_attr_count; 378 379 GLubyte *verts; 380 381 /* Fallback rasterization functions 382 */ 383 radeon_point_func draw_point; 384 radeon_line_func draw_line; 385 radeon_tri_func draw_tri; 386 387 GLuint hw_primitive; 388 GLenum render_primitive; 389 GLuint numverts; 390 391 /** 392 * Offset of the 4UB color data within a hardware (swtcl) vertex. 393 */ 394 GLuint coloroffset; 395 396 /** 397 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 398 */ 399 GLuint specoffset; 400 401 GLboolean needproj; 402 403 struct radeon_dma_region indexed_verts; 404}; 405 406 407 408/* A maximum total of 20 elements per vertex: 3 floats for position, 3 409 * floats for normal, 4 floats for color, 4 bytes for secondary color, 410 * 3 floats for each texture unit (9 floats total). 411 * 412 * The position data is never actually stored here, so 3 elements could be 413 * trimmed out of the buffer. This number is only valid for vtxfmt! 414 */ 415#define RADEON_MAX_VERTEX_SIZE 20 416 417struct r100_context { 418 struct radeon_context radeon; 419 420 /* Driver and hardware state management 421 */ 422 struct radeon_hw_state hw; 423 struct r100_state state; 424 425 /* Vertex buffers 426 */ 427 struct radeon_ioctl ioctl; 428 struct radeon_dma dma; 429 struct radeon_store store; 430 /* A full state emit as of the first state emit in the main store, in case 431 * the context is lost. 432 */ 433 struct radeon_store backup_store; 434 435 /* TCL stuff 436 */ 437 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 438 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 439 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 440 GLuint TexGenEnabled; 441 GLuint NeedTexMatrix; 442 GLuint TexMatColSwap; 443 GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; 444 GLuint last_ReallyEnabled; 445 446 /* radeon_tcl.c 447 */ 448 struct radeon_tcl_info tcl; 449 450 /* radeon_swtcl.c 451 */ 452 struct radeon_swtcl_info swtcl; 453 454 GLboolean using_hyperz; 455 GLboolean texmicrotile; 456 457 /* Performance counters 458 */ 459 GLuint boxes; /* Draw performance boxes */ 460 GLuint hardwareWentIdle; 461 GLuint c_clears; 462 GLuint c_drawWaits; 463 GLuint c_textureSwaps; 464 GLuint c_textureBytes; 465 GLuint c_vertexBuffers; 466 467 GLboolean save_on_next_emit; 468}; 469 470#define R100_CONTEXT(ctx) ((r100ContextPtr)(ctx->DriverCtx)) 471 472 473#define RADEON_OLD_PACKETS 1 474 475extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); 476extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 477 __DRIcontextPrivate * driContextPriv, 478 void *sharedContextPrivate); 479extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, 480 __DRIdrawablePrivate * driDrawPriv, 481 __DRIdrawablePrivate * driReadPriv); 482extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); 483 484 485 486#endif /* __RADEON_CONTEXT_H__ */ 487