radeon_context.h revision 3beaff1e3cf227c493badfc55a69381c778b2ff7
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */ 2/************************************************************************** 3 4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 5 VA Linux Systems Inc., Fremont, California. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29**************************************************************************/ 30 31/* 32 * Authors: 33 * Kevin E. Martin <martin@valinux.com> 34 * Gareth Hughes <gareth@valinux.com> 35 * Keith Whitwell <keith@tungstengraphics.com> 36 */ 37 38#ifndef __RADEON_CONTEXT_H__ 39#define __RADEON_CONTEXT_H__ 40 41#include "tnl/t_vertex.h" 42#include "dri_util.h" 43#include "drm.h" 44#include "radeon_drm.h" 45#include "texmem.h" 46 47#include "macros.h" 48#include "mtypes.h" 49#include "colormac.h" 50 51struct radeon_context; 52typedef struct radeon_context radeonContextRec; 53typedef struct radeon_context *radeonContextPtr; 54 55/* This union is used to avoid warnings/miscompilation 56 with float to uint32_t casts due to strict-aliasing */ 57typedef union { GLfloat f; uint32_t ui32; } float_ui32_type; 58 59#include "radeon_lock.h" 60#include "radeon_screen.h" 61#include "mm.h" 62 63#include "math/m_vector.h" 64 65/* Flags for software fallback cases */ 66/* See correponding strings in radeon_swtcl.c */ 67#define RADEON_FALLBACK_TEXTURE 0x0001 68#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 69#define RADEON_FALLBACK_STENCIL 0x0004 70#define RADEON_FALLBACK_RENDER_MODE 0x0008 71#define RADEON_FALLBACK_BLEND_EQ 0x0010 72#define RADEON_FALLBACK_BLEND_FUNC 0x0020 73#define RADEON_FALLBACK_DISABLE 0x0040 74#define RADEON_FALLBACK_BORDER_MODE 0x0080 75 76/* The blit width for texture uploads 77 */ 78#define BLIT_WIDTH_BYTES 1024 79 80/* Use the templated vertex format: 81 */ 82#define COLOR_IS_RGBA 83#define TAG(x) radeon##x 84#include "tnl_dd/t_dd_vertex.h" 85#undef TAG 86 87typedef void (*radeon_tri_func)( radeonContextPtr, 88 radeonVertex *, 89 radeonVertex *, 90 radeonVertex * ); 91 92typedef void (*radeon_line_func)( radeonContextPtr, 93 radeonVertex *, 94 radeonVertex * ); 95 96typedef void (*radeon_point_func)( radeonContextPtr, 97 radeonVertex * ); 98 99 100struct radeon_colorbuffer_state { 101 GLuint clear; 102 int roundEnable; 103}; 104 105 106struct radeon_depthbuffer_state { 107 GLuint clear; 108 GLfloat scale; 109}; 110 111struct radeon_scissor_state { 112 drm_clip_rect_t rect; 113 GLboolean enabled; 114 115 GLuint numClipRects; /* Cliprects active */ 116 GLuint numAllocedClipRects; /* Cliprects available */ 117 drm_clip_rect_t *pClipRects; 118}; 119 120struct radeon_stencilbuffer_state { 121 GLboolean hwBuffer; 122 GLuint clear; /* rb3d_stencilrefmask value */ 123}; 124 125struct radeon_stipple_state { 126 GLuint mask[32]; 127}; 128 129/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ 130#define RADEON_ST_BIT(unit) \ 131(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) 132 133#define RADEON_Q_BIT(unit) \ 134(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) 135 136#define TEX_0 0x1 137#define TEX_1 0x2 138#define TEX_2 0x4 139#define TEX_ALL 0x7 140 141typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 142 143/* Texture object in locally shared texture space. 144 */ 145struct radeon_tex_obj { 146 driTextureObject base; 147 148 GLuint bufAddr; /* Offset to start of locally 149 shared texture block */ 150 151 GLuint dirty_state; /* Flags (1 per texunit) for 152 whether or not this texobj 153 has dirty hardware state 154 (pp_*) that needs to be 155 brought into the 156 texunit. */ 157 158 drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; 159 /* Six, for the cube faces */ 160 161 GLuint pp_txfilter; /* hardware register values */ 162 GLuint pp_txformat; 163 GLuint pp_txoffset; /* Image location in texmem. 164 All cube faces follow. */ 165 GLuint pp_txsize; /* npot only */ 166 GLuint pp_txpitch; /* npot only */ 167 GLuint pp_border_color; 168 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 169 170 GLboolean border_fallback; 171 172 GLuint tile_bits; /* hw texture tile bits used on this texture */ 173}; 174 175 176struct radeon_texture_env_state { 177 radeonTexObjPtr texobj; 178 GLenum format; 179 GLenum envMode; 180}; 181 182struct radeon_texture_state { 183 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 184}; 185 186 187struct radeon_state_atom { 188 struct radeon_state_atom *next, *prev; 189 const char *name; /* for debug */ 190 int cmd_size; /* size in bytes */ 191 GLuint is_tcl; 192 int *cmd; /* one or more cmd's */ 193 int *lastcmd; /* one or more cmd's */ 194 GLboolean dirty; /* dirty-mark in emit_state_list */ 195 GLboolean (*check)( GLcontext * ); /* is this state active? */ 196}; 197 198 199 200/* Trying to keep these relatively short as the variables are becoming 201 * extravagently long. Drop the driver name prefix off the front of 202 * everything - I think we know which driver we're in by now, and keep the 203 * prefix to 3 letters unless absolutely impossible. 204 */ 205 206#define CTX_CMD_0 0 207#define CTX_PP_MISC 1 208#define CTX_PP_FOG_COLOR 2 209#define CTX_RE_SOLID_COLOR 3 210#define CTX_RB3D_BLENDCNTL 4 211#define CTX_RB3D_DEPTHOFFSET 5 212#define CTX_RB3D_DEPTHPITCH 6 213#define CTX_RB3D_ZSTENCILCNTL 7 214#define CTX_CMD_1 8 215#define CTX_PP_CNTL 9 216#define CTX_RB3D_CNTL 10 217#define CTX_RB3D_COLOROFFSET 11 218#define CTX_CMD_2 12 219#define CTX_RB3D_COLORPITCH 13 220#define CTX_STATE_SIZE 14 221 222#define SET_CMD_0 0 223#define SET_SE_CNTL 1 224#define SET_SE_COORDFMT 2 225#define SET_CMD_1 3 226#define SET_SE_CNTL_STATUS 4 227#define SET_STATE_SIZE 5 228 229#define LIN_CMD_0 0 230#define LIN_RE_LINE_PATTERN 1 231#define LIN_RE_LINE_STATE 2 232#define LIN_CMD_1 3 233#define LIN_SE_LINE_WIDTH 4 234#define LIN_STATE_SIZE 5 235 236#define MSK_CMD_0 0 237#define MSK_RB3D_STENCILREFMASK 1 238#define MSK_RB3D_ROPCNTL 2 239#define MSK_RB3D_PLANEMASK 3 240#define MSK_STATE_SIZE 4 241 242#define VPT_CMD_0 0 243#define VPT_SE_VPORT_XSCALE 1 244#define VPT_SE_VPORT_XOFFSET 2 245#define VPT_SE_VPORT_YSCALE 3 246#define VPT_SE_VPORT_YOFFSET 4 247#define VPT_SE_VPORT_ZSCALE 5 248#define VPT_SE_VPORT_ZOFFSET 6 249#define VPT_STATE_SIZE 7 250 251#define MSC_CMD_0 0 252#define MSC_RE_MISC 1 253#define MSC_STATE_SIZE 2 254 255#define TEX_CMD_0 0 256#define TEX_PP_TXFILTER 1 257#define TEX_PP_TXFORMAT 2 258#define TEX_PP_TXOFFSET 3 259#define TEX_PP_TXCBLEND 4 260#define TEX_PP_TXABLEND 5 261#define TEX_PP_TFACTOR 6 262#define TEX_CMD_1 7 263#define TEX_PP_BORDER_COLOR 8 264#define TEX_STATE_SIZE 9 265 266#define TXR_CMD_0 0 /* rectangle textures */ 267#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 268#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 269#define TXR_STATE_SIZE 3 270 271#define CUBE_CMD_0 0 272#define CUBE_PP_CUBIC_FACES 1 273#define CUBE_CMD_1 2 274#define CUBE_PP_CUBIC_OFFSET_0 3 275#define CUBE_PP_CUBIC_OFFSET_1 4 276#define CUBE_PP_CUBIC_OFFSET_2 5 277#define CUBE_PP_CUBIC_OFFSET_3 6 278#define CUBE_PP_CUBIC_OFFSET_4 7 279#define CUBE_STATE_SIZE 8 280 281#define ZBS_CMD_0 0 282#define ZBS_SE_ZBIAS_FACTOR 1 283#define ZBS_SE_ZBIAS_CONSTANT 2 284#define ZBS_STATE_SIZE 3 285 286#define TCL_CMD_0 0 287#define TCL_OUTPUT_VTXFMT 1 288#define TCL_OUTPUT_VTXSEL 2 289#define TCL_MATRIX_SELECT_0 3 290#define TCL_MATRIX_SELECT_1 4 291#define TCL_UCP_VERT_BLEND_CTL 5 292#define TCL_TEXTURE_PROC_CTL 6 293#define TCL_LIGHT_MODEL_CTL 7 294#define TCL_PER_LIGHT_CTL_0 8 295#define TCL_PER_LIGHT_CTL_1 9 296#define TCL_PER_LIGHT_CTL_2 10 297#define TCL_PER_LIGHT_CTL_3 11 298#define TCL_STATE_SIZE 12 299 300#define MTL_CMD_0 0 301#define MTL_EMMISSIVE_RED 1 302#define MTL_EMMISSIVE_GREEN 2 303#define MTL_EMMISSIVE_BLUE 3 304#define MTL_EMMISSIVE_ALPHA 4 305#define MTL_AMBIENT_RED 5 306#define MTL_AMBIENT_GREEN 6 307#define MTL_AMBIENT_BLUE 7 308#define MTL_AMBIENT_ALPHA 8 309#define MTL_DIFFUSE_RED 9 310#define MTL_DIFFUSE_GREEN 10 311#define MTL_DIFFUSE_BLUE 11 312#define MTL_DIFFUSE_ALPHA 12 313#define MTL_SPECULAR_RED 13 314#define MTL_SPECULAR_GREEN 14 315#define MTL_SPECULAR_BLUE 15 316#define MTL_SPECULAR_ALPHA 16 317#define MTL_SHININESS 17 318#define MTL_STATE_SIZE 18 319 320#define VTX_CMD_0 0 321#define VTX_SE_COORD_FMT 1 322#define VTX_STATE_SIZE 2 323 324#define MAT_CMD_0 0 325#define MAT_ELT_0 1 326#define MAT_STATE_SIZE 17 327 328#define GRD_CMD_0 0 329#define GRD_VERT_GUARD_CLIP_ADJ 1 330#define GRD_VERT_GUARD_DISCARD_ADJ 2 331#define GRD_HORZ_GUARD_CLIP_ADJ 3 332#define GRD_HORZ_GUARD_DISCARD_ADJ 4 333#define GRD_STATE_SIZE 5 334 335/* position changes frequently when lighting in modelpos - separate 336 * out to new state item? 337 */ 338#define LIT_CMD_0 0 339#define LIT_AMBIENT_RED 1 340#define LIT_AMBIENT_GREEN 2 341#define LIT_AMBIENT_BLUE 3 342#define LIT_AMBIENT_ALPHA 4 343#define LIT_DIFFUSE_RED 5 344#define LIT_DIFFUSE_GREEN 6 345#define LIT_DIFFUSE_BLUE 7 346#define LIT_DIFFUSE_ALPHA 8 347#define LIT_SPECULAR_RED 9 348#define LIT_SPECULAR_GREEN 10 349#define LIT_SPECULAR_BLUE 11 350#define LIT_SPECULAR_ALPHA 12 351#define LIT_POSITION_X 13 352#define LIT_POSITION_Y 14 353#define LIT_POSITION_Z 15 354#define LIT_POSITION_W 16 355#define LIT_DIRECTION_X 17 356#define LIT_DIRECTION_Y 18 357#define LIT_DIRECTION_Z 19 358#define LIT_DIRECTION_W 20 359#define LIT_ATTEN_QUADRATIC 21 360#define LIT_ATTEN_LINEAR 22 361#define LIT_ATTEN_CONST 23 362#define LIT_ATTEN_XXX 24 363#define LIT_CMD_1 25 364#define LIT_SPOT_DCD 26 365#define LIT_SPOT_EXPONENT 27 366#define LIT_SPOT_CUTOFF 28 367#define LIT_SPECULAR_THRESH 29 368#define LIT_RANGE_CUTOFF 30 /* ? */ 369#define LIT_ATTEN_CONST_INV 31 370#define LIT_STATE_SIZE 32 371 372/* Fog 373 */ 374#define FOG_CMD_0 0 375#define FOG_R 1 376#define FOG_C 2 377#define FOG_D 3 378#define FOG_PAD 4 379#define FOG_STATE_SIZE 5 380 381/* UCP 382 */ 383#define UCP_CMD_0 0 384#define UCP_X 1 385#define UCP_Y 2 386#define UCP_Z 3 387#define UCP_W 4 388#define UCP_STATE_SIZE 5 389 390/* GLT - Global ambient 391 */ 392#define GLT_CMD_0 0 393#define GLT_RED 1 394#define GLT_GREEN 2 395#define GLT_BLUE 3 396#define GLT_ALPHA 4 397#define GLT_STATE_SIZE 5 398 399/* EYE 400 */ 401#define EYE_CMD_0 0 402#define EYE_X 1 403#define EYE_Y 2 404#define EYE_Z 3 405#define EYE_RESCALE_FACTOR 4 406#define EYE_STATE_SIZE 5 407 408#define SHN_CMD_0 0 409#define SHN_SHININESS 1 410#define SHN_STATE_SIZE 2 411 412 413 414 415 416struct radeon_hw_state { 417 /* Head of the linked list of state atoms. */ 418 struct radeon_state_atom atomlist; 419 420 /* Hardware state, stored as cmdbuf commands: 421 * -- Need to doublebuffer for 422 * - eliding noop statechange loops? (except line stipple count) 423 */ 424 struct radeon_state_atom ctx; 425 struct radeon_state_atom set; 426 struct radeon_state_atom lin; 427 struct radeon_state_atom msk; 428 struct radeon_state_atom vpt; 429 struct radeon_state_atom tcl; 430 struct radeon_state_atom msc; 431 struct radeon_state_atom tex[3]; 432 struct radeon_state_atom cube[3]; 433 struct radeon_state_atom zbs; 434 struct radeon_state_atom mtl; 435 struct radeon_state_atom mat[6]; 436 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 437 struct radeon_state_atom ucp[6]; 438 struct radeon_state_atom eye; /* eye pos */ 439 struct radeon_state_atom grd; /* guard band clipping */ 440 struct radeon_state_atom fog; 441 struct radeon_state_atom glt; 442 struct radeon_state_atom txr[3]; /* for NPOT */ 443 444 int max_state_size; /* Number of bytes necessary for a full state emit. */ 445 GLboolean is_dirty, all_dirty; 446}; 447 448struct radeon_state { 449 /* Derived state for internal purposes: 450 */ 451 struct radeon_colorbuffer_state color; 452 struct radeon_depthbuffer_state depth; 453 struct radeon_scissor_state scissor; 454 struct radeon_stencilbuffer_state stencil; 455 struct radeon_stipple_state stipple; 456 struct radeon_texture_state texture; 457}; 458 459 460/* Need refcounting on dma buffers: 461 */ 462struct radeon_dma_buffer { 463 int refcount; /* the number of retained regions in buf */ 464 drmBufPtr buf; 465}; 466 467#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 468 (rvb)->address - rmesa->dma.buf0_address + \ 469 (rvb)->start) 470 471/* A retained region, eg vertices for indexed vertices. 472 */ 473struct radeon_dma_region { 474 struct radeon_dma_buffer *buf; 475 char *address; /* == buf->address */ 476 int start, end, ptr; /* offsets from start of buf */ 477 int aos_start; 478 int aos_stride; 479 int aos_size; 480}; 481 482 483struct radeon_dma { 484 /* Active dma region. Allocations for vertices and retained 485 * regions come from here. Also used for emitting random vertices, 486 * these may be flushed by calling flush_current(); 487 */ 488 struct radeon_dma_region current; 489 490 void (*flush)( radeonContextPtr ); 491 492 char *buf0_address; /* start of buf[0], for index calcs */ 493 GLuint nr_released_bufs; /* flush after so many buffers released */ 494}; 495 496struct radeon_dri_mirror { 497 __DRIcontextPrivate *context; /* DRI context */ 498 __DRIscreenPrivate *screen; /* DRI screen */ 499 500 /** 501 * DRI drawable bound to this context for drawing. 502 */ 503 __DRIdrawablePrivate *drawable; 504 505 /** 506 * DRI drawable bound to this context for reading. 507 */ 508 __DRIdrawablePrivate *readable; 509 510 drm_context_t hwContext; 511 drm_hw_lock_t *hwLock; 512 int fd; 513 int drmMinor; 514}; 515 516 517#define RADEON_CMD_BUF_SZ (8*1024) 518 519struct radeon_store { 520 GLuint statenr; 521 GLuint primnr; 522 char cmd_buf[RADEON_CMD_BUF_SZ]; 523 int cmd_used; 524 int elts_start; 525}; 526 527 528/* radeon_tcl.c 529 */ 530struct radeon_tcl_info { 531 GLuint vertex_format; 532 GLint last_offset; 533 GLuint hw_primitive; 534 535 /* Temporary for cases where incoming vertex data is incompatible 536 * with maos code. 537 */ 538 GLvector4f ObjClean; 539 540 struct radeon_dma_region *aos_components[8]; 541 GLuint nr_aos_components; 542 543 GLuint *Elts; 544 545 struct radeon_dma_region indexed_verts; 546 struct radeon_dma_region obj; 547 struct radeon_dma_region rgba; 548 struct radeon_dma_region spec; 549 struct radeon_dma_region fog; 550 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 551 struct radeon_dma_region norm; 552}; 553 554 555/* radeon_swtcl.c 556 */ 557struct radeon_swtcl_info { 558 GLuint RenderIndex; 559 GLuint vertex_size; 560 GLuint vertex_format; 561 562 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 563 GLuint vertex_attr_count; 564 565 GLubyte *verts; 566 567 /* Fallback rasterization functions 568 */ 569 radeon_point_func draw_point; 570 radeon_line_func draw_line; 571 radeon_tri_func draw_tri; 572 573 GLuint hw_primitive; 574 GLenum render_primitive; 575 GLuint numverts; 576 577 /** 578 * Offset of the 4UB color data within a hardware (swtcl) vertex. 579 */ 580 GLuint coloroffset; 581 582 /** 583 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 584 */ 585 GLuint specoffset; 586 587 GLboolean needproj; 588 589 struct radeon_dma_region indexed_verts; 590}; 591 592 593struct radeon_ioctl { 594 GLuint vertex_offset; 595 GLuint vertex_size; 596}; 597 598 599 600#define RADEON_MAX_PRIMS 64 601 602 603/* Want to keep a cache of these around. Each is parameterized by 604 * only a single value which has only a small range. Only expect a 605 * few, so just rescan the list each time? 606 */ 607struct dynfn { 608 struct dynfn *next, *prev; 609 int key; 610 char *code; 611}; 612 613struct dfn_lists { 614 struct dynfn Vertex2f; 615 struct dynfn Vertex2fv; 616 struct dynfn Vertex3f; 617 struct dynfn Vertex3fv; 618 struct dynfn Color4ub; 619 struct dynfn Color4ubv; 620 struct dynfn Color3ub; 621 struct dynfn Color3ubv; 622 struct dynfn Color4f; 623 struct dynfn Color4fv; 624 struct dynfn Color3f; 625 struct dynfn Color3fv; 626 struct dynfn SecondaryColor3ubEXT; 627 struct dynfn SecondaryColor3ubvEXT; 628 struct dynfn SecondaryColor3fEXT; 629 struct dynfn SecondaryColor3fvEXT; 630 struct dynfn Normal3f; 631 struct dynfn Normal3fv; 632 struct dynfn TexCoord2f; 633 struct dynfn TexCoord2fv; 634 struct dynfn TexCoord1f; 635 struct dynfn TexCoord1fv; 636 struct dynfn MultiTexCoord2fARB; 637 struct dynfn MultiTexCoord2fvARB; 638 struct dynfn MultiTexCoord1fARB; 639 struct dynfn MultiTexCoord1fvARB; 640}; 641 642struct dfn_generators { 643 struct dynfn *(*Vertex2f)( GLcontext *, int ); 644 struct dynfn *(*Vertex2fv)( GLcontext *, int ); 645 struct dynfn *(*Vertex3f)( GLcontext *, int ); 646 struct dynfn *(*Vertex3fv)( GLcontext *, int ); 647 struct dynfn *(*Color4ub)( GLcontext *, int ); 648 struct dynfn *(*Color4ubv)( GLcontext *, int ); 649 struct dynfn *(*Color3ub)( GLcontext *, int ); 650 struct dynfn *(*Color3ubv)( GLcontext *, int ); 651 struct dynfn *(*Color4f)( GLcontext *, int ); 652 struct dynfn *(*Color4fv)( GLcontext *, int ); 653 struct dynfn *(*Color3f)( GLcontext *, int ); 654 struct dynfn *(*Color3fv)( GLcontext *, int ); 655 struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int ); 656 struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int ); 657 struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int ); 658 struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int ); 659 struct dynfn *(*Normal3f)( GLcontext *, int ); 660 struct dynfn *(*Normal3fv)( GLcontext *, int ); 661 struct dynfn *(*TexCoord2f)( GLcontext *, int ); 662 struct dynfn *(*TexCoord2fv)( GLcontext *, int ); 663 struct dynfn *(*TexCoord1f)( GLcontext *, int ); 664 struct dynfn *(*TexCoord1fv)( GLcontext *, int ); 665 struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int ); 666 struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int ); 667 struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int ); 668 struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int ); 669}; 670 671 672 673struct radeon_prim { 674 GLuint start; 675 GLuint end; 676 GLuint prim; 677}; 678 679/* A maximum total of 20 elements per vertex: 3 floats for position, 3 680 * floats for normal, 4 floats for color, 4 bytes for secondary color, 681 * 3 floats for each texture unit (9 floats total). 682 * 683 * The position data is never actually stored here, so 3 elements could be 684 * trimmed out of the buffer. This number is only valid for vtxfmt! 685 */ 686#define RADEON_MAX_VERTEX_SIZE 20 687 688struct radeon_vbinfo { 689 GLint counter, initial_counter; 690 GLint *dmaptr; 691 void (*notify)( void ); 692 GLint vertex_size; 693 694 union { float f; int i; radeon_color_t color; } vertex[RADEON_MAX_VERTEX_SIZE]; 695 696 GLfloat *normalptr; 697 GLfloat *floatcolorptr; 698 radeon_color_t *colorptr; 699 GLfloat *floatspecptr; 700 radeon_color_t *specptr; 701 GLfloat *texcoordptr[4]; /* 3 (TMU) + 1 for radeon_vtxfmt_c.c when GL_TEXTURE3 */ 702 703 GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ 704 GLuint primflags; 705 GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */ 706 GLboolean installed; 707 GLboolean fell_back; 708 GLboolean recheck; 709 GLint nrverts; 710 GLuint vertex_format; 711 712 GLuint installed_vertex_format; 713 GLuint installed_color_3f_sz; 714 715 struct radeon_prim primlist[RADEON_MAX_PRIMS]; 716 int nrprims; 717 718 struct dfn_lists dfn_cache; 719 struct dfn_generators codegen; 720 GLvertexformat vtxfmt; 721}; 722 723 724 725 726struct radeon_context { 727 GLcontext *glCtx; /* Mesa context */ 728 729 /* Driver and hardware state management 730 */ 731 struct radeon_hw_state hw; 732 struct radeon_state state; 733 734 /* Texture object bookkeeping 735 */ 736 unsigned nr_heaps; 737 driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 738 driTextureObject swapped; 739 int texture_depth; 740 float initialMaxAnisotropy; 741 742 /* Rasterization and vertex state: 743 */ 744 GLuint TclFallback; 745 GLuint Fallback; 746 GLuint NewGLState; 747 DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ 748 749 /* Vertex buffers 750 */ 751 struct radeon_ioctl ioctl; 752 struct radeon_dma dma; 753 struct radeon_store store; 754 /* A full state emit as of the first state emit in the main store, in case 755 * the context is lost. 756 */ 757 struct radeon_store backup_store; 758 759 /* Page flipping 760 */ 761 GLuint doPageFlip; 762 763 /* Busy waiting 764 */ 765 GLuint do_usleeps; 766 GLuint do_irqs; 767 GLuint irqsEmitted; 768 drm_radeon_irq_wait_t iw; 769 770 /* Drawable, cliprect and scissor information 771 */ 772 GLuint numClipRects; /* Cliprects for the draw buffer */ 773 drm_clip_rect_t *pClipRects; 774 unsigned int lastStamp; 775 GLboolean lost_context; 776 GLboolean save_on_next_emit; 777 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 778 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 779 780 /* TCL stuff 781 */ 782 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 783 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 784 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 785 GLuint TexGenEnabled; 786 GLuint NeedTexMatrix; 787 GLuint TexMatColSwap; 788 GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; 789 GLuint last_ReallyEnabled; 790 791 /* VBI 792 */ 793 GLuint vbl_seq; 794 GLuint vblank_flags; 795 796 int64_t swap_ust; 797 int64_t swap_missed_ust; 798 799 GLuint swap_count; 800 GLuint swap_missed_count; 801 802 803 /* radeon_tcl.c 804 */ 805 struct radeon_tcl_info tcl; 806 807 /* radeon_swtcl.c 808 */ 809 struct radeon_swtcl_info swtcl; 810 811 /* radeon_vtxfmt.c 812 */ 813 struct radeon_vbinfo vb; 814 815 /* Mirrors of some DRI state 816 */ 817 struct radeon_dri_mirror dri; 818 819 /* Configuration cache 820 */ 821 driOptionCache optionCache; 822 823 GLboolean using_hyperz; 824 GLboolean texmicrotile; 825 826 /* Performance counters 827 */ 828 GLuint boxes; /* Draw performance boxes */ 829 GLuint hardwareWentIdle; 830 GLuint c_clears; 831 GLuint c_drawWaits; 832 GLuint c_textureSwaps; 833 GLuint c_textureBytes; 834 GLuint c_vertexBuffers; 835}; 836 837#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 838 839 840static __inline GLuint radeonPackColor( GLuint cpp, 841 GLubyte r, GLubyte g, 842 GLubyte b, GLubyte a ) 843{ 844 switch ( cpp ) { 845 case 2: 846 return PACK_COLOR_565( r, g, b ); 847 case 4: 848 return PACK_COLOR_8888( a, r, g, b ); 849 default: 850 return 0; 851 } 852} 853 854#define RADEON_OLD_PACKETS 1 855 856 857extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ); 858extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual, 859 __DRIcontextPrivate *driContextPriv, 860 void *sharedContextPrivate); 861extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv ); 862extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, 863 int x, int y, int w, int h); 864extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, 865 __DRIdrawablePrivate *driDrawPriv, 866 __DRIdrawablePrivate *driReadPriv ); 867extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv ); 868 869/* ================================================================ 870 * Debugging: 871 */ 872#define DO_DEBUG 1 873 874#if DO_DEBUG 875extern int RADEON_DEBUG; 876#else 877#define RADEON_DEBUG 0 878#endif 879 880#define DEBUG_TEXTURE 0x001 881#define DEBUG_STATE 0x002 882#define DEBUG_IOCTL 0x004 883#define DEBUG_PRIMS 0x008 884#define DEBUG_VERTS 0x010 885#define DEBUG_FALLBACKS 0x020 886#define DEBUG_VFMT 0x040 887#define DEBUG_CODEGEN 0x080 888#define DEBUG_VERBOSE 0x100 889#define DEBUG_DRI 0x200 890#define DEBUG_DMA 0x400 891#define DEBUG_SANITY 0x800 892#define DEBUG_SYNC 0x1000 893 894#endif /* __RADEON_CONTEXT_H__ */ 895