radeon_context.h revision 5e600209f4908ece2ba8b7f880e1d7e950d2cfb4
1e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/************************************************************************** 2e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 3e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher VA Linux Systems Inc., Fremont, California. 5e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherCopyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 6e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 7e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherThe Weather Channel (TM) funded Tungsten Graphics to develop the 8e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherinitial release of the Radeon 8500 driver under the XFree86 license. 9e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherThis notice must be preserved. 10e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 11e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherAll Rights Reserved. 12e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 13e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherPermission is hereby granted, free of charge, to any person obtaining 14e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchera copy of this software and associated documentation files (the 15e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher"Software"), to deal in the Software without restriction, including 16e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherwithout limitation the rights to use, copy, modify, merge, publish, 17e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherdistribute, sublicense, and/or sell copies of the Software, and to 18e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherpermit persons to whom the Software is furnished to do so, subject to 19e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherthe following conditions: 20e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 21e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherThe above copyright notice and this permission notice (including the 22e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchernext paragraph) shall be included in all copies or substantial 23e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherportions of the Software. 24e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 25e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31e6869a8f59d779ff4d5a0984c86d80db7078496Marc BoucherWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 33e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher**************************************************************************/ 34e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 35e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/* 36e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher * Authors: 37e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher * Gareth Hughes <gareth@valinux.com> 38e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher * Keith Whitwell <keith@tungstengraphics.com> 39e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher * Kevin E. Martin <martin@valinux.com> 40e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher * Nicolai Haehnle <prefect_@gmx.net> 41e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher */ 42e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 43e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#ifndef __RADEON_CONTEXT_H__ 44e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define __RADEON_CONTEXT_H__ 45e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 46e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "tnl/t_vertex.h" 47e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "dri_util.h" 48e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "drm.h" 49e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "radeon_drm.h" 50e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "texmem.h" 51e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 52e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "macros.h" 53e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "mtypes.h" 54e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "colormac.h" 55e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 56e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherstruct radeon_context; 57e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchertypedef struct radeon_context radeonContextRec; 58e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchertypedef struct radeon_context *radeonContextPtr; 59e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 60e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/* This union is used to avoid warnings/miscompilation 61e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher with float to uint32_t casts due to strict-aliasing */ 62e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchertypedef union { 63e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher GLfloat f; 64e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher uint32_t ui32; 65e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher} float_ui32_type; 66e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 67e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "radeon_lock.h" 68e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "radeon_screen.h" 69e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "mm.h" 70e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 71e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "math/m_vector.h" 72e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 73e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define TEX_0 0x1 74e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define TEX_1 0x2 75e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define TEX_2 0x4 76e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define TEX_ALL 0x7 77e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 78e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/* Rasterizing fallbacks */ 79e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/* See correponding strings in r200_swtcl.c */ 80e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_TEXTURE 0x0001 81e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 82e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_STENCIL 0x0004 83e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_RENDER_MODE 0x0008 84e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_BLEND_EQ 0x0010 85e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_BLEND_FUNC 0x0020 86e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_DISABLE 0x0040 87e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define RADEON_FALLBACK_BORDER_MODE 0x0080 88e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 89e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/* The blit width for texture uploads 90e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher */ 91e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define BLIT_WIDTH_BYTES 1024 92e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 93e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher/* Use the templated vertex format: 94e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher */ 95e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define COLOR_IS_RGBA 96e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#define TAG(x) radeon##x 97e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#include "tnl_dd/t_dd_vertex.h" 98e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher#undef TAG 99e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 100e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchertypedef void (*radeon_tri_func) (radeonContextPtr, 101e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher radeonVertex *, 102e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher radeonVertex *, radeonVertex *); 103e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 104e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchertypedef void (*radeon_line_func) (radeonContextPtr, 105e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher radeonVertex *, radeonVertex *); 106e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 107e6869a8f59d779ff4d5a0984c86d80db7078496Marc Bouchertypedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); 108e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 109e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherstruct radeon_colorbuffer_state { 110e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher GLuint clear; 111e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher int roundEnable; 112e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher}; 113e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 114e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherstruct radeon_depthbuffer_state { 115e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher GLuint clear; 116e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher GLfloat scale; 117e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher}; 118e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 119e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucherstruct radeon_scissor_state { 120e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher drm_clip_rect_t rect; 121e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher GLboolean enabled; 122e6869a8f59d779ff4d5a0984c86d80db7078496Marc Boucher 123 GLuint numClipRects; /* Cliprects active */ 124 GLuint numAllocedClipRects; /* Cliprects available */ 125 drm_clip_rect_t *pClipRects; 126}; 127 128struct radeon_stencilbuffer_state { 129 GLboolean hwBuffer; 130 GLuint clear; /* rb3d_stencilrefmask value */ 131}; 132 133struct radeon_stipple_state { 134 GLuint mask[32]; 135}; 136 137/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ 138#define RADEON_ST_BIT(unit) \ 139(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) 140 141#define RADEON_Q_BIT(unit) \ 142(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) 143 144typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 145 146/* Texture object in locally shared texture space. 147 */ 148struct radeon_tex_obj { 149 driTextureObject base; 150 151 GLuint bufAddr; /* Offset to start of locally 152 shared texture block */ 153 154 GLuint dirty_state; /* Flags (1 per texunit) for 155 whether or not this texobj 156 has dirty hardware state 157 (pp_*) that needs to be 158 brought into the 159 texunit. */ 160 161 drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; 162 /* Six, for the cube faces */ 163 164 GLboolean image_override; /* Image overridden by GLX_EXT_tfp */ 165 166 GLuint pp_txfilter; /* hardware register values */ 167 GLuint pp_txformat; 168 GLuint pp_txoffset; /* Image location in texmem. 169 All cube faces follow. */ 170 GLuint pp_txsize; /* npot only */ 171 GLuint pp_txpitch; /* npot only */ 172 GLuint pp_border_color; 173 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 174 175 GLboolean border_fallback; 176 177 GLuint tile_bits; /* hw texture tile bits used on this texture */ 178}; 179 180struct radeon_texture_env_state { 181 radeonTexObjPtr texobj; 182 GLenum format; 183 GLenum envMode; 184}; 185 186struct radeon_texture_state { 187 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 188}; 189 190struct radeon_state_atom { 191 struct radeon_state_atom *next, *prev; 192 const char *name; /* for debug */ 193 int cmd_size; /* size in bytes */ 194 GLuint is_tcl; 195 int *cmd; /* one or more cmd's */ 196 int *lastcmd; /* one or more cmd's */ 197 GLboolean dirty; /* dirty-mark in emit_state_list */ 198 GLboolean(*check) (GLcontext *); /* is this state active? */ 199}; 200 201/* Trying to keep these relatively short as the variables are becoming 202 * extravagently long. Drop the driver name prefix off the front of 203 * everything - I think we know which driver we're in by now, and keep the 204 * prefix to 3 letters unless absolutely impossible. 205 */ 206 207#define CTX_CMD_0 0 208#define CTX_PP_MISC 1 209#define CTX_PP_FOG_COLOR 2 210#define CTX_RE_SOLID_COLOR 3 211#define CTX_RB3D_BLENDCNTL 4 212#define CTX_RB3D_DEPTHOFFSET 5 213#define CTX_RB3D_DEPTHPITCH 6 214#define CTX_RB3D_ZSTENCILCNTL 7 215#define CTX_CMD_1 8 216#define CTX_PP_CNTL 9 217#define CTX_RB3D_CNTL 10 218#define CTX_RB3D_COLOROFFSET 11 219#define CTX_CMD_2 12 220#define CTX_RB3D_COLORPITCH 13 221#define CTX_STATE_SIZE 14 222 223#define SET_CMD_0 0 224#define SET_SE_CNTL 1 225#define SET_SE_COORDFMT 2 226#define SET_CMD_1 3 227#define SET_SE_CNTL_STATUS 4 228#define SET_STATE_SIZE 5 229 230#define LIN_CMD_0 0 231#define LIN_RE_LINE_PATTERN 1 232#define LIN_RE_LINE_STATE 2 233#define LIN_CMD_1 3 234#define LIN_SE_LINE_WIDTH 4 235#define LIN_STATE_SIZE 5 236 237#define MSK_CMD_0 0 238#define MSK_RB3D_STENCILREFMASK 1 239#define MSK_RB3D_ROPCNTL 2 240#define MSK_RB3D_PLANEMASK 3 241#define MSK_STATE_SIZE 4 242 243#define VPT_CMD_0 0 244#define VPT_SE_VPORT_XSCALE 1 245#define VPT_SE_VPORT_XOFFSET 2 246#define VPT_SE_VPORT_YSCALE 3 247#define VPT_SE_VPORT_YOFFSET 4 248#define VPT_SE_VPORT_ZSCALE 5 249#define VPT_SE_VPORT_ZOFFSET 6 250#define VPT_STATE_SIZE 7 251 252#define MSC_CMD_0 0 253#define MSC_RE_MISC 1 254#define MSC_STATE_SIZE 2 255 256#define TEX_CMD_0 0 257#define TEX_PP_TXFILTER 1 258#define TEX_PP_TXFORMAT 2 259#define TEX_PP_TXOFFSET 3 260#define TEX_PP_TXCBLEND 4 261#define TEX_PP_TXABLEND 5 262#define TEX_PP_TFACTOR 6 263#define TEX_CMD_1 7 264#define TEX_PP_BORDER_COLOR 8 265#define TEX_STATE_SIZE 9 266 267#define TXR_CMD_0 0 /* rectangle textures */ 268#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 269#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 270#define TXR_STATE_SIZE 3 271 272#define CUBE_CMD_0 0 273#define CUBE_PP_CUBIC_FACES 1 274#define CUBE_CMD_1 2 275#define CUBE_PP_CUBIC_OFFSET_0 3 276#define CUBE_PP_CUBIC_OFFSET_1 4 277#define CUBE_PP_CUBIC_OFFSET_2 5 278#define CUBE_PP_CUBIC_OFFSET_3 6 279#define CUBE_PP_CUBIC_OFFSET_4 7 280#define CUBE_STATE_SIZE 8 281 282#define ZBS_CMD_0 0 283#define ZBS_SE_ZBIAS_FACTOR 1 284#define ZBS_SE_ZBIAS_CONSTANT 2 285#define ZBS_STATE_SIZE 3 286 287#define TCL_CMD_0 0 288#define TCL_OUTPUT_VTXFMT 1 289#define TCL_OUTPUT_VTXSEL 2 290#define TCL_MATRIX_SELECT_0 3 291#define TCL_MATRIX_SELECT_1 4 292#define TCL_UCP_VERT_BLEND_CTL 5 293#define TCL_TEXTURE_PROC_CTL 6 294#define TCL_LIGHT_MODEL_CTL 7 295#define TCL_PER_LIGHT_CTL_0 8 296#define TCL_PER_LIGHT_CTL_1 9 297#define TCL_PER_LIGHT_CTL_2 10 298#define TCL_PER_LIGHT_CTL_3 11 299#define TCL_STATE_SIZE 12 300 301#define MTL_CMD_0 0 302#define MTL_EMMISSIVE_RED 1 303#define MTL_EMMISSIVE_GREEN 2 304#define MTL_EMMISSIVE_BLUE 3 305#define MTL_EMMISSIVE_ALPHA 4 306#define MTL_AMBIENT_RED 5 307#define MTL_AMBIENT_GREEN 6 308#define MTL_AMBIENT_BLUE 7 309#define MTL_AMBIENT_ALPHA 8 310#define MTL_DIFFUSE_RED 9 311#define MTL_DIFFUSE_GREEN 10 312#define MTL_DIFFUSE_BLUE 11 313#define MTL_DIFFUSE_ALPHA 12 314#define MTL_SPECULAR_RED 13 315#define MTL_SPECULAR_GREEN 14 316#define MTL_SPECULAR_BLUE 15 317#define MTL_SPECULAR_ALPHA 16 318#define MTL_SHININESS 17 319#define MTL_STATE_SIZE 18 320 321#define VTX_CMD_0 0 322#define VTX_SE_COORD_FMT 1 323#define VTX_STATE_SIZE 2 324 325#define MAT_CMD_0 0 326#define MAT_ELT_0 1 327#define MAT_STATE_SIZE 17 328 329#define GRD_CMD_0 0 330#define GRD_VERT_GUARD_CLIP_ADJ 1 331#define GRD_VERT_GUARD_DISCARD_ADJ 2 332#define GRD_HORZ_GUARD_CLIP_ADJ 3 333#define GRD_HORZ_GUARD_DISCARD_ADJ 4 334#define GRD_STATE_SIZE 5 335 336/* position changes frequently when lighting in modelpos - separate 337 * out to new state item? 338 */ 339#define LIT_CMD_0 0 340#define LIT_AMBIENT_RED 1 341#define LIT_AMBIENT_GREEN 2 342#define LIT_AMBIENT_BLUE 3 343#define LIT_AMBIENT_ALPHA 4 344#define LIT_DIFFUSE_RED 5 345#define LIT_DIFFUSE_GREEN 6 346#define LIT_DIFFUSE_BLUE 7 347#define LIT_DIFFUSE_ALPHA 8 348#define LIT_SPECULAR_RED 9 349#define LIT_SPECULAR_GREEN 10 350#define LIT_SPECULAR_BLUE 11 351#define LIT_SPECULAR_ALPHA 12 352#define LIT_POSITION_X 13 353#define LIT_POSITION_Y 14 354#define LIT_POSITION_Z 15 355#define LIT_POSITION_W 16 356#define LIT_DIRECTION_X 17 357#define LIT_DIRECTION_Y 18 358#define LIT_DIRECTION_Z 19 359#define LIT_DIRECTION_W 20 360#define LIT_ATTEN_QUADRATIC 21 361#define LIT_ATTEN_LINEAR 22 362#define LIT_ATTEN_CONST 23 363#define LIT_ATTEN_XXX 24 364#define LIT_CMD_1 25 365#define LIT_SPOT_DCD 26 366#define LIT_SPOT_EXPONENT 27 367#define LIT_SPOT_CUTOFF 28 368#define LIT_SPECULAR_THRESH 29 369#define LIT_RANGE_CUTOFF 30 /* ? */ 370#define LIT_ATTEN_CONST_INV 31 371#define LIT_STATE_SIZE 32 372 373/* Fog 374 */ 375#define FOG_CMD_0 0 376#define FOG_R 1 377#define FOG_C 2 378#define FOG_D 3 379#define FOG_PAD 4 380#define FOG_STATE_SIZE 5 381 382/* UCP 383 */ 384#define UCP_CMD_0 0 385#define UCP_X 1 386#define UCP_Y 2 387#define UCP_Z 3 388#define UCP_W 4 389#define UCP_STATE_SIZE 5 390 391/* GLT - Global ambient 392 */ 393#define GLT_CMD_0 0 394#define GLT_RED 1 395#define GLT_GREEN 2 396#define GLT_BLUE 3 397#define GLT_ALPHA 4 398#define GLT_STATE_SIZE 5 399 400/* EYE 401 */ 402#define EYE_CMD_0 0 403#define EYE_X 1 404#define EYE_Y 2 405#define EYE_Z 3 406#define EYE_RESCALE_FACTOR 4 407#define EYE_STATE_SIZE 5 408 409#define SHN_CMD_0 0 410#define SHN_SHININESS 1 411#define SHN_STATE_SIZE 2 412 413struct radeon_hw_state { 414 /* Head of the linked list of state atoms. */ 415 struct radeon_state_atom atomlist; 416 417 /* Hardware state, stored as cmdbuf commands: 418 * -- Need to doublebuffer for 419 * - eliding noop statechange loops? (except line stipple count) 420 */ 421 struct radeon_state_atom ctx; 422 struct radeon_state_atom set; 423 struct radeon_state_atom lin; 424 struct radeon_state_atom msk; 425 struct radeon_state_atom vpt; 426 struct radeon_state_atom tcl; 427 struct radeon_state_atom msc; 428 struct radeon_state_atom tex[3]; 429 struct radeon_state_atom cube[3]; 430 struct radeon_state_atom zbs; 431 struct radeon_state_atom mtl; 432 struct radeon_state_atom mat[6]; 433 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 434 struct radeon_state_atom ucp[6]; 435 struct radeon_state_atom eye; /* eye pos */ 436 struct radeon_state_atom grd; /* guard band clipping */ 437 struct radeon_state_atom fog; 438 struct radeon_state_atom glt; 439 struct radeon_state_atom txr[3]; /* for NPOT */ 440 441 int max_state_size; /* Number of bytes necessary for a full state emit. */ 442 GLboolean is_dirty, all_dirty; 443}; 444 445struct radeon_state { 446 /* Derived state for internal purposes: 447 */ 448 struct radeon_colorbuffer_state color; 449 struct radeon_depthbuffer_state depth; 450 struct radeon_scissor_state scissor; 451 struct radeon_stencilbuffer_state stencil; 452 struct radeon_stipple_state stipple; 453 struct radeon_texture_state texture; 454}; 455 456/* Need refcounting on dma buffers: 457 */ 458struct radeon_dma_buffer { 459 int refcount; /* the number of retained regions in buf */ 460 drmBufPtr buf; 461}; 462 463#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 464 (rvb)->address - rmesa->dma.buf0_address + \ 465 (rvb)->start) 466 467/* A retained region, eg vertices for indexed vertices. 468 */ 469struct radeon_dma_region { 470 struct radeon_dma_buffer *buf; 471 char *address; /* == buf->address */ 472 int start, end, ptr; /* offsets from start of buf */ 473 int aos_start; 474 int aos_stride; 475 int aos_size; 476}; 477 478struct radeon_dma { 479 /* Active dma region. Allocations for vertices and retained 480 * regions come from here. Also used for emitting random vertices, 481 * these may be flushed by calling flush_current(); 482 */ 483 struct radeon_dma_region current; 484 485 void (*flush) (radeonContextPtr); 486 487 char *buf0_address; /* start of buf[0], for index calcs */ 488 GLuint nr_released_bufs; /* flush after so many buffers released */ 489}; 490 491struct radeon_dri_mirror { 492 __DRIcontextPrivate *context; /* DRI context */ 493 __DRIscreenPrivate *screen; /* DRI screen */ 494 495 /** 496 * DRI drawable bound to this context for drawing. 497 */ 498 __DRIdrawablePrivate *drawable; 499 500 /** 501 * DRI drawable bound to this context for reading. 502 */ 503 __DRIdrawablePrivate *readable; 504 505 drm_context_t hwContext; 506 drm_hw_lock_t *hwLock; 507 int fd; 508 int drmMinor; 509}; 510 511#define RADEON_CMD_BUF_SZ (8*1024) 512 513struct radeon_store { 514 GLuint statenr; 515 GLuint primnr; 516 char cmd_buf[RADEON_CMD_BUF_SZ]; 517 int cmd_used; 518 int elts_start; 519}; 520 521/* radeon_tcl.c 522 */ 523struct radeon_tcl_info { 524 GLuint vertex_format; 525 GLuint hw_primitive; 526 527 /* Temporary for cases where incoming vertex data is incompatible 528 * with maos code. 529 */ 530 GLvector4f ObjClean; 531 532 struct radeon_dma_region *aos_components[8]; 533 GLuint nr_aos_components; 534 535 GLuint *Elts; 536 537 struct radeon_dma_region indexed_verts; 538 struct radeon_dma_region obj; 539 struct radeon_dma_region rgba; 540 struct radeon_dma_region spec; 541 struct radeon_dma_region fog; 542 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 543 struct radeon_dma_region norm; 544}; 545 546/* radeon_swtcl.c 547 */ 548struct radeon_swtcl_info { 549 GLuint RenderIndex; 550 GLuint vertex_size; 551 GLuint vertex_format; 552 553 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 554 GLuint vertex_attr_count; 555 556 GLubyte *verts; 557 558 /* Fallback rasterization functions 559 */ 560 radeon_point_func draw_point; 561 radeon_line_func draw_line; 562 radeon_tri_func draw_tri; 563 564 GLuint hw_primitive; 565 GLenum render_primitive; 566 GLuint numverts; 567 568 /** 569 * Offset of the 4UB color data within a hardware (swtcl) vertex. 570 */ 571 GLuint coloroffset; 572 573 /** 574 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 575 */ 576 GLuint specoffset; 577 578 GLboolean needproj; 579 580 struct radeon_dma_region indexed_verts; 581}; 582 583struct radeon_ioctl { 584 GLuint vertex_offset; 585 GLuint vertex_size; 586}; 587 588#define RADEON_MAX_PRIMS 64 589 590struct radeon_prim { 591 GLuint start; 592 GLuint end; 593 GLuint prim; 594}; 595 596/* A maximum total of 20 elements per vertex: 3 floats for position, 3 597 * floats for normal, 4 floats for color, 4 bytes for secondary color, 598 * 3 floats for each texture unit (9 floats total). 599 * 600 * The position data is never actually stored here, so 3 elements could be 601 * trimmed out of the buffer. This number is only valid for vtxfmt! 602 */ 603#define RADEON_MAX_VERTEX_SIZE 20 604 605struct radeon_context { 606 GLcontext *glCtx; /* Mesa context */ 607 608 /* Driver and hardware state management 609 */ 610 struct radeon_hw_state hw; 611 struct radeon_state state; 612 613 /* Texture object bookkeeping 614 */ 615 unsigned nr_heaps; 616 driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS]; 617 driTextureObject swapped; 618 int texture_depth; 619 float initialMaxAnisotropy; 620 621 /* Rasterization and vertex state: 622 */ 623 GLuint TclFallback; 624 GLuint Fallback; 625 GLuint NewGLState; 626 DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ 627 628 /* Vertex buffers 629 */ 630 struct radeon_ioctl ioctl; 631 struct radeon_dma dma; 632 struct radeon_store store; 633 /* A full state emit as of the first state emit in the main store, in case 634 * the context is lost. 635 */ 636 struct radeon_store backup_store; 637 638 /* Page flipping 639 */ 640 GLuint doPageFlip; 641 642 /* Busy waiting 643 */ 644 GLuint do_usleeps; 645 GLuint do_irqs; 646 GLuint irqsEmitted; 647 drm_radeon_irq_wait_t iw; 648 649 /* Drawable, cliprect and scissor information 650 */ 651 GLuint numClipRects; /* Cliprects for the draw buffer */ 652 drm_clip_rect_t *pClipRects; 653 unsigned int lastStamp; 654 GLboolean lost_context; 655 GLboolean save_on_next_emit; 656 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 657 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 658 659 /* TCL stuff 660 */ 661 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 662 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 663 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 664 GLuint TexGenEnabled; 665 GLuint NeedTexMatrix; 666 GLuint TexMatColSwap; 667 GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; 668 GLuint last_ReallyEnabled; 669 670 /* VBI 671 */ 672 int64_t swap_ust; 673 int64_t swap_missed_ust; 674 675 GLuint swap_count; 676 GLuint swap_missed_count; 677 678 /* radeon_tcl.c 679 */ 680 struct radeon_tcl_info tcl; 681 682 /* radeon_swtcl.c 683 */ 684 struct radeon_swtcl_info swtcl; 685 686 /* Mirrors of some DRI state 687 */ 688 struct radeon_dri_mirror dri; 689 690 /* Configuration cache 691 */ 692 driOptionCache optionCache; 693 694 GLboolean using_hyperz; 695 GLboolean texmicrotile; 696 697 /* Performance counters 698 */ 699 GLuint boxes; /* Draw performance boxes */ 700 GLuint hardwareWentIdle; 701 GLuint c_clears; 702 GLuint c_drawWaits; 703 GLuint c_textureSwaps; 704 GLuint c_textureBytes; 705 GLuint c_vertexBuffers; 706}; 707 708#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 709 710static INLINE GLuint radeonPackColor(GLuint cpp, 711 GLubyte r, GLubyte g, 712 GLubyte b, GLubyte a) 713{ 714 switch (cpp) { 715 case 2: 716 return PACK_COLOR_565(r, g, b); 717 case 4: 718 return PACK_COLOR_8888(a, r, g, b); 719 default: 720 return 0; 721 } 722} 723 724#define RADEON_OLD_PACKETS 1 725 726extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); 727extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 728 __DRIcontextPrivate * driContextPriv, 729 void *sharedContextPrivate); 730extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); 731extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, 732 int x, int y, int w, int h); 733extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, 734 __DRIdrawablePrivate * driDrawPriv, 735 __DRIdrawablePrivate * driReadPriv); 736extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); 737 738/* ================================================================ 739 * Debugging: 740 */ 741#define DO_DEBUG 1 742 743#if DO_DEBUG 744extern int RADEON_DEBUG; 745#else 746#define RADEON_DEBUG 0 747#endif 748 749#define DEBUG_TEXTURE 0x0001 750#define DEBUG_STATE 0x0002 751#define DEBUG_IOCTL 0x0004 752#define DEBUG_PRIMS 0x0008 753#define DEBUG_VERTS 0x0010 754#define DEBUG_FALLBACKS 0x0020 755#define DEBUG_VFMT 0x0040 756#define DEBUG_CODEGEN 0x0080 757#define DEBUG_VERBOSE 0x0100 758#define DEBUG_DRI 0x0200 759#define DEBUG_DMA 0x0400 760#define DEBUG_SANITY 0x0800 761#define DEBUG_SYNC 0x1000 762 763#endif /* __RADEON_CONTEXT_H__ */ 764