radeon_context.h revision 692ca82116485a9c6191e5265c5b369d5b4f82f3
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 6 7The Weather Channel (TM) funded Tungsten Graphics to develop the 8initial release of the Radeon 8500 driver under the XFree86 license. 9This notice must be preserved. 10 11All Rights Reserved. 12 13Permission is hereby granted, free of charge, to any person obtaining 14a copy of this software and associated documentation files (the 15"Software"), to deal in the Software without restriction, including 16without limitation the rights to use, copy, modify, merge, publish, 17distribute, sublicense, and/or sell copies of the Software, and to 18permit persons to whom the Software is furnished to do so, subject to 19the following conditions: 20 21The above copyright notice and this permission notice (including the 22next paragraph) shall be included in all copies or substantial 23portions of the Software. 24 25THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 33**************************************************************************/ 34 35/* 36 * Authors: 37 * Gareth Hughes <gareth@valinux.com> 38 * Keith Whitwell <keith@tungstengraphics.com> 39 * Kevin E. Martin <martin@valinux.com> 40 * Nicolai Haehnle <prefect_@gmx.net> 41 */ 42 43#ifndef __RADEON_CONTEXT_H__ 44#define __RADEON_CONTEXT_H__ 45 46#include "tnl/t_vertex.h" 47#include "dri_util.h" 48#include "drm.h" 49#include "radeon_drm.h" 50#include "texmem.h" 51 52#include "main/macros.h" 53#include "main/mtypes.h" 54#include "main/colormac.h" 55 56struct radeon_context; 57typedef struct radeon_context radeonContextRec; 58typedef struct radeon_context *radeonContextPtr; 59 60#include "radeon_lock.h" 61#include "radeon_screen.h" 62 63#include "common_context.h" 64 65#define R100_TEX_ALL 0x7 66 67typedef void (*radeon_tri_func) (radeonContextPtr, 68 radeonVertex *, 69 radeonVertex *, radeonVertex *); 70 71typedef void (*radeon_line_func) (radeonContextPtr, 72 radeonVertex *, radeonVertex *); 73 74typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); 75 76 77 78/* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ 79#define RADEON_ST_BIT(unit) \ 80(unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) 81 82#define RADEON_Q_BIT(unit) \ 83(unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) 84 85struct radeon_texture_env_state { 86 radeonTexObjPtr texobj; 87 GLenum format; 88 GLenum envMode; 89}; 90 91struct radeon_texture_state { 92 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 93}; 94 95/* Trying to keep these relatively short as the variables are becoming 96 * extravagently long. Drop the driver name prefix off the front of 97 * everything - I think we know which driver we're in by now, and keep the 98 * prefix to 3 letters unless absolutely impossible. 99 */ 100 101#define CTX_CMD_0 0 102#define CTX_PP_MISC 1 103#define CTX_PP_FOG_COLOR 2 104#define CTX_RE_SOLID_COLOR 3 105#define CTX_RB3D_BLENDCNTL 4 106#define CTX_RB3D_DEPTHOFFSET 5 107#define CTX_RB3D_DEPTHPITCH 6 108#define CTX_RB3D_ZSTENCILCNTL 7 109#define CTX_CMD_1 8 110#define CTX_PP_CNTL 9 111#define CTX_RB3D_CNTL 10 112#define CTX_RB3D_COLOROFFSET 11 113#define CTX_CMD_2 12 114#define CTX_RB3D_COLORPITCH 13 115#define CTX_STATE_SIZE 14 116 117#define SET_CMD_0 0 118#define SET_SE_CNTL 1 119#define SET_SE_COORDFMT 2 120#define SET_CMD_1 3 121#define SET_SE_CNTL_STATUS 4 122#define SET_STATE_SIZE 5 123 124#define LIN_CMD_0 0 125#define LIN_RE_LINE_PATTERN 1 126#define LIN_RE_LINE_STATE 2 127#define LIN_CMD_1 3 128#define LIN_SE_LINE_WIDTH 4 129#define LIN_STATE_SIZE 5 130 131#define MSK_CMD_0 0 132#define MSK_RB3D_STENCILREFMASK 1 133#define MSK_RB3D_ROPCNTL 2 134#define MSK_RB3D_PLANEMASK 3 135#define MSK_STATE_SIZE 4 136 137#define VPT_CMD_0 0 138#define VPT_SE_VPORT_XSCALE 1 139#define VPT_SE_VPORT_XOFFSET 2 140#define VPT_SE_VPORT_YSCALE 3 141#define VPT_SE_VPORT_YOFFSET 4 142#define VPT_SE_VPORT_ZSCALE 5 143#define VPT_SE_VPORT_ZOFFSET 6 144#define VPT_STATE_SIZE 7 145 146#define MSC_CMD_0 0 147#define MSC_RE_MISC 1 148#define MSC_STATE_SIZE 2 149 150#define TEX_CMD_0 0 151#define TEX_PP_TXFILTER 1 152#define TEX_PP_TXFORMAT 2 153#define TEX_PP_TXOFFSET 3 154#define TEX_PP_TXCBLEND 4 155#define TEX_PP_TXABLEND 5 156#define TEX_PP_TFACTOR 6 157#define TEX_CMD_1 7 158#define TEX_PP_BORDER_COLOR 8 159#define TEX_STATE_SIZE 9 160 161#define TXR_CMD_0 0 /* rectangle textures */ 162#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 163#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 164#define TXR_STATE_SIZE 3 165 166#define CUBE_CMD_0 0 167#define CUBE_PP_CUBIC_FACES 1 168#define CUBE_CMD_1 2 169#define CUBE_PP_CUBIC_OFFSET_0 3 170#define CUBE_PP_CUBIC_OFFSET_1 4 171#define CUBE_PP_CUBIC_OFFSET_2 5 172#define CUBE_PP_CUBIC_OFFSET_3 6 173#define CUBE_PP_CUBIC_OFFSET_4 7 174#define CUBE_STATE_SIZE 8 175 176#define ZBS_CMD_0 0 177#define ZBS_SE_ZBIAS_FACTOR 1 178#define ZBS_SE_ZBIAS_CONSTANT 2 179#define ZBS_STATE_SIZE 3 180 181#define TCL_CMD_0 0 182#define TCL_OUTPUT_VTXFMT 1 183#define TCL_OUTPUT_VTXSEL 2 184#define TCL_MATRIX_SELECT_0 3 185#define TCL_MATRIX_SELECT_1 4 186#define TCL_UCP_VERT_BLEND_CTL 5 187#define TCL_TEXTURE_PROC_CTL 6 188#define TCL_LIGHT_MODEL_CTL 7 189#define TCL_PER_LIGHT_CTL_0 8 190#define TCL_PER_LIGHT_CTL_1 9 191#define TCL_PER_LIGHT_CTL_2 10 192#define TCL_PER_LIGHT_CTL_3 11 193#define TCL_STATE_SIZE 12 194 195#define MTL_CMD_0 0 196#define MTL_EMMISSIVE_RED 1 197#define MTL_EMMISSIVE_GREEN 2 198#define MTL_EMMISSIVE_BLUE 3 199#define MTL_EMMISSIVE_ALPHA 4 200#define MTL_AMBIENT_RED 5 201#define MTL_AMBIENT_GREEN 6 202#define MTL_AMBIENT_BLUE 7 203#define MTL_AMBIENT_ALPHA 8 204#define MTL_DIFFUSE_RED 9 205#define MTL_DIFFUSE_GREEN 10 206#define MTL_DIFFUSE_BLUE 11 207#define MTL_DIFFUSE_ALPHA 12 208#define MTL_SPECULAR_RED 13 209#define MTL_SPECULAR_GREEN 14 210#define MTL_SPECULAR_BLUE 15 211#define MTL_SPECULAR_ALPHA 16 212#define MTL_SHININESS 17 213#define MTL_STATE_SIZE 18 214 215#define VTX_CMD_0 0 216#define VTX_SE_COORD_FMT 1 217#define VTX_STATE_SIZE 2 218 219#define MAT_CMD_0 0 220#define MAT_ELT_0 1 221#define MAT_STATE_SIZE 17 222 223#define GRD_CMD_0 0 224#define GRD_VERT_GUARD_CLIP_ADJ 1 225#define GRD_VERT_GUARD_DISCARD_ADJ 2 226#define GRD_HORZ_GUARD_CLIP_ADJ 3 227#define GRD_HORZ_GUARD_DISCARD_ADJ 4 228#define GRD_STATE_SIZE 5 229 230/* position changes frequently when lighting in modelpos - separate 231 * out to new state item? 232 */ 233#define LIT_CMD_0 0 234#define LIT_AMBIENT_RED 1 235#define LIT_AMBIENT_GREEN 2 236#define LIT_AMBIENT_BLUE 3 237#define LIT_AMBIENT_ALPHA 4 238#define LIT_DIFFUSE_RED 5 239#define LIT_DIFFUSE_GREEN 6 240#define LIT_DIFFUSE_BLUE 7 241#define LIT_DIFFUSE_ALPHA 8 242#define LIT_SPECULAR_RED 9 243#define LIT_SPECULAR_GREEN 10 244#define LIT_SPECULAR_BLUE 11 245#define LIT_SPECULAR_ALPHA 12 246#define LIT_POSITION_X 13 247#define LIT_POSITION_Y 14 248#define LIT_POSITION_Z 15 249#define LIT_POSITION_W 16 250#define LIT_DIRECTION_X 17 251#define LIT_DIRECTION_Y 18 252#define LIT_DIRECTION_Z 19 253#define LIT_DIRECTION_W 20 254#define LIT_ATTEN_QUADRATIC 21 255#define LIT_ATTEN_LINEAR 22 256#define LIT_ATTEN_CONST 23 257#define LIT_ATTEN_XXX 24 258#define LIT_CMD_1 25 259#define LIT_SPOT_DCD 26 260#define LIT_SPOT_EXPONENT 27 261#define LIT_SPOT_CUTOFF 28 262#define LIT_SPECULAR_THRESH 29 263#define LIT_RANGE_CUTOFF 30 /* ? */ 264#define LIT_ATTEN_CONST_INV 31 265#define LIT_STATE_SIZE 32 266 267/* Fog 268 */ 269#define FOG_CMD_0 0 270#define FOG_R 1 271#define FOG_C 2 272#define FOG_D 3 273#define FOG_PAD 4 274#define FOG_STATE_SIZE 5 275 276/* UCP 277 */ 278#define UCP_CMD_0 0 279#define UCP_X 1 280#define UCP_Y 2 281#define UCP_Z 3 282#define UCP_W 4 283#define UCP_STATE_SIZE 5 284 285/* GLT - Global ambient 286 */ 287#define GLT_CMD_0 0 288#define GLT_RED 1 289#define GLT_GREEN 2 290#define GLT_BLUE 3 291#define GLT_ALPHA 4 292#define GLT_STATE_SIZE 5 293 294/* EYE 295 */ 296#define EYE_CMD_0 0 297#define EYE_X 1 298#define EYE_Y 2 299#define EYE_Z 3 300#define EYE_RESCALE_FACTOR 4 301#define EYE_STATE_SIZE 5 302 303#define SHN_CMD_0 0 304#define SHN_SHININESS 1 305#define SHN_STATE_SIZE 2 306 307struct radeon_hw_state { 308 /* Head of the linked list of state atoms. */ 309 struct radeon_state_atom atomlist; 310 311 /* Hardware state, stored as cmdbuf commands: 312 * -- Need to doublebuffer for 313 * - eliding noop statechange loops? (except line stipple count) 314 */ 315 struct radeon_state_atom ctx; 316 struct radeon_state_atom set; 317 struct radeon_state_atom lin; 318 struct radeon_state_atom msk; 319 struct radeon_state_atom vpt; 320 struct radeon_state_atom tcl; 321 struct radeon_state_atom msc; 322 struct radeon_state_atom tex[3]; 323 struct radeon_state_atom cube[3]; 324 struct radeon_state_atom zbs; 325 struct radeon_state_atom mtl; 326 struct radeon_state_atom mat[6]; 327 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 328 struct radeon_state_atom ucp[6]; 329 struct radeon_state_atom eye; /* eye pos */ 330 struct radeon_state_atom grd; /* guard band clipping */ 331 struct radeon_state_atom fog; 332 struct radeon_state_atom glt; 333 struct radeon_state_atom txr[3]; /* for NPOT */ 334 335 int max_state_size; /* Number of bytes necessary for a full state emit. */ 336 GLboolean is_dirty, all_dirty; 337}; 338 339struct radeon_state { 340 /* Derived state for internal purposes: 341 */ 342 struct radeon_colorbuffer_state color; 343 struct radeon_depthbuffer_state depth; 344 struct radeon_scissor_state scissor; 345 struct radeon_stencilbuffer_state stencil; 346 struct radeon_stipple_state stipple; 347 struct radeon_texture_state texture; 348}; 349 350#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 351 (rvb)->address - rmesa->dma.buf0_address + \ 352 (rvb)->start) 353 354struct radeon_dri_mirror { 355 __DRIcontextPrivate *context; /* DRI context */ 356 __DRIscreenPrivate *screen; /* DRI screen */ 357 358 /** 359 * DRI drawable bound to this context for drawing. 360 */ 361 __DRIdrawablePrivate *drawable; 362 363 /** 364 * DRI drawable bound to this context for reading. 365 */ 366 __DRIdrawablePrivate *readable; 367 368 drm_context_t hwContext; 369 drm_hw_lock_t *hwLock; 370 int fd; 371 int drmMinor; 372}; 373 374#define RADEON_CMD_BUF_SZ (8*1024) 375 376struct radeon_store { 377 GLuint statenr; 378 GLuint primnr; 379 char cmd_buf[RADEON_CMD_BUF_SZ]; 380 int cmd_used; 381 int elts_start; 382}; 383 384/* radeon_tcl.c 385 */ 386struct radeon_tcl_info { 387 GLuint vertex_format; 388 GLuint hw_primitive; 389 390 /* Temporary for cases where incoming vertex data is incompatible 391 * with maos code. 392 */ 393 GLvector4f ObjClean; 394 395 struct radeon_dma_region *aos_components[8]; 396 GLuint nr_aos_components; 397 398 GLuint *Elts; 399 400 struct radeon_dma_region indexed_verts; 401 struct radeon_dma_region obj; 402 struct radeon_dma_region rgba; 403 struct radeon_dma_region spec; 404 struct radeon_dma_region fog; 405 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 406 struct radeon_dma_region norm; 407}; 408 409/* radeon_swtcl.c 410 */ 411struct radeon_swtcl_info { 412 GLuint RenderIndex; 413 GLuint vertex_size; 414 GLuint vertex_format; 415 416 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; 417 GLuint vertex_attr_count; 418 419 GLubyte *verts; 420 421 /* Fallback rasterization functions 422 */ 423 radeon_point_func draw_point; 424 radeon_line_func draw_line; 425 radeon_tri_func draw_tri; 426 427 GLuint hw_primitive; 428 GLenum render_primitive; 429 GLuint numverts; 430 431 /** 432 * Offset of the 4UB color data within a hardware (swtcl) vertex. 433 */ 434 GLuint coloroffset; 435 436 /** 437 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 438 */ 439 GLuint specoffset; 440 441 GLboolean needproj; 442 443 struct radeon_dma_region indexed_verts; 444}; 445 446 447 448/* A maximum total of 20 elements per vertex: 3 floats for position, 3 449 * floats for normal, 4 floats for color, 4 bytes for secondary color, 450 * 3 floats for each texture unit (9 floats total). 451 * 452 * The position data is never actually stored here, so 3 elements could be 453 * trimmed out of the buffer. This number is only valid for vtxfmt! 454 */ 455#define RADEON_MAX_VERTEX_SIZE 20 456 457struct radeon_context { 458 GLcontext *glCtx; /* Mesa context */ 459 460 /* Driver and hardware state management 461 */ 462 struct radeon_hw_state hw; 463 struct radeon_state state; 464 465 /* Texture object bookkeeping 466 */ 467 unsigned nr_heaps; 468 driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS]; 469 driTextureObject swapped; 470 int texture_depth; 471 float initialMaxAnisotropy; 472 473 /* Rasterization and vertex state: 474 */ 475 GLuint TclFallback; 476 GLuint Fallback; 477 GLuint NewGLState; 478 DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ 479 480 /* Vertex buffers 481 */ 482 struct radeon_ioctl ioctl; 483 struct radeon_dma dma; 484 struct radeon_store store; 485 /* A full state emit as of the first state emit in the main store, in case 486 * the context is lost. 487 */ 488 struct radeon_store backup_store; 489 490 /* Page flipping 491 */ 492 GLuint doPageFlip; 493 494 /* Busy waiting 495 */ 496 GLuint do_usleeps; 497 GLuint do_irqs; 498 GLuint irqsEmitted; 499 drm_radeon_irq_wait_t iw; 500 501 /* Drawable, cliprect and scissor information 502 */ 503 GLuint numClipRects; /* Cliprects for the draw buffer */ 504 drm_clip_rect_t *pClipRects; 505 unsigned int lastStamp; 506 GLboolean lost_context; 507 GLboolean save_on_next_emit; 508 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 509 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 510 511 /* TCL stuff 512 */ 513 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 514 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 515 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 516 GLuint TexGenEnabled; 517 GLuint NeedTexMatrix; 518 GLuint TexMatColSwap; 519 GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; 520 GLuint last_ReallyEnabled; 521 522 /* VBI 523 */ 524 int64_t swap_ust; 525 int64_t swap_missed_ust; 526 527 GLuint swap_count; 528 GLuint swap_missed_count; 529 530 /* radeon_tcl.c 531 */ 532 struct radeon_tcl_info tcl; 533 534 /* radeon_swtcl.c 535 */ 536 struct radeon_swtcl_info swtcl; 537 538 /* Mirrors of some DRI state 539 */ 540 struct radeon_dri_mirror dri; 541 542 /* Configuration cache 543 */ 544 driOptionCache optionCache; 545 546 GLboolean using_hyperz; 547 GLboolean texmicrotile; 548 549 /* Performance counters 550 */ 551 GLuint boxes; /* Draw performance boxes */ 552 GLuint hardwareWentIdle; 553 GLuint c_clears; 554 GLuint c_drawWaits; 555 GLuint c_textureSwaps; 556 GLuint c_textureBytes; 557 GLuint c_vertexBuffers; 558}; 559 560#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 561 562 563#define RADEON_OLD_PACKETS 1 564 565extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); 566extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 567 __DRIcontextPrivate * driContextPriv, 568 void *sharedContextPrivate); 569extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); 570extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, 571 int x, int y, int w, int h); 572extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, 573 __DRIdrawablePrivate * driDrawPriv, 574 __DRIdrawablePrivate * driReadPriv); 575extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); 576 577/* ================================================================ 578 * Debugging: 579 */ 580#define DO_DEBUG 1 581 582#if DO_DEBUG 583extern int RADEON_DEBUG; 584#else 585#define RADEON_DEBUG 0 586#endif 587 588#define DEBUG_TEXTURE 0x0001 589#define DEBUG_STATE 0x0002 590#define DEBUG_IOCTL 0x0004 591#define DEBUG_PRIMS 0x0008 592#define DEBUG_VERTS 0x0010 593#define DEBUG_FALLBACKS 0x0020 594#define DEBUG_VFMT 0x0040 595#define DEBUG_CODEGEN 0x0080 596#define DEBUG_VERBOSE 0x0100 597#define DEBUG_DRI 0x0200 598#define DEBUG_DMA 0x0400 599#define DEBUG_SANITY 0x0800 600#define DEBUG_SYNC 0x1000 601 602#endif /* __RADEON_CONTEXT_H__ */ 603