radeon_context.h revision 886280763c8dfa7202bdacdeacf84ced69609b98
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */ 2/************************************************************************** 3 4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 5 VA Linux Systems Inc., Fremont, California. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29**************************************************************************/ 30 31/* 32 * Authors: 33 * Kevin E. Martin <martin@valinux.com> 34 * Gareth Hughes <gareth@valinux.com> 35 * Keith Whitwell <keith@tungstengraphics.com> 36 */ 37 38#ifndef __RADEON_CONTEXT_H__ 39#define __RADEON_CONTEXT_H__ 40 41#include "dri_util.h" 42#include "drm.h" 43#include "radeon_drm.h" 44#include "texmem.h" 45 46#include "macros.h" 47#include "mtypes.h" 48#include "colormac.h" 49 50struct radeon_context; 51typedef struct radeon_context radeonContextRec; 52typedef struct radeon_context *radeonContextPtr; 53 54#include "radeon_lock.h" 55#include "radeon_screen.h" 56#include "mm.h" 57 58#include "math/m_vector.h" 59 60/* Flags for software fallback cases */ 61/* See correponding strings in radeon_swtcl.c */ 62#define RADEON_FALLBACK_TEXTURE 0x0001 63#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 64#define RADEON_FALLBACK_STENCIL 0x0004 65#define RADEON_FALLBACK_RENDER_MODE 0x0008 66#define RADEON_FALLBACK_BLEND_EQ 0x0010 67#define RADEON_FALLBACK_BLEND_FUNC 0x0020 68#define RADEON_FALLBACK_DISABLE 0x0040 69#define RADEON_FALLBACK_BORDER_MODE 0x0080 70 71/* The blit width for texture uploads 72 */ 73#define BLIT_WIDTH_BYTES 1024 74 75/* Use the templated vertex format: 76 */ 77#define COLOR_IS_RGBA 78#define TAG(x) radeon##x 79#include "tnl_dd/t_dd_vertex.h" 80#undef TAG 81 82typedef void (*radeon_tri_func)( radeonContextPtr, 83 radeonVertex *, 84 radeonVertex *, 85 radeonVertex * ); 86 87typedef void (*radeon_line_func)( radeonContextPtr, 88 radeonVertex *, 89 radeonVertex * ); 90 91typedef void (*radeon_point_func)( radeonContextPtr, 92 radeonVertex * ); 93 94 95struct radeon_colorbuffer_state { 96 GLuint clear; 97 GLint drawOffset, drawPitch; 98 int roundEnable; 99}; 100 101 102struct radeon_depthbuffer_state { 103 GLuint clear; 104 GLfloat scale; 105}; 106 107struct radeon_pixel_state { 108 GLint readOffset, readPitch; 109}; 110 111struct radeon_scissor_state { 112 drm_clip_rect_t rect; 113 GLboolean enabled; 114 115 GLuint numClipRects; /* Cliprects active */ 116 GLuint numAllocedClipRects; /* Cliprects available */ 117 drm_clip_rect_t *pClipRects; 118}; 119 120struct radeon_stencilbuffer_state { 121 GLboolean hwBuffer; 122 GLuint clear; /* rb3d_stencilrefmask value */ 123}; 124 125struct radeon_stipple_state { 126 GLuint mask[32]; 127}; 128 129 130 131#define TEX_0 0x1 132#define TEX_1 0x2 133#define TEX_ALL 0x3 134 135typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 136 137/* Texture object in locally shared texture space. 138 */ 139struct radeon_tex_obj { 140 driTextureObject base; 141 142 GLuint bufAddr; /* Offset to start of locally 143 shared texture block */ 144 145 GLuint dirty_state; /* Flags (1 per texunit) for 146 whether or not this texobj 147 has dirty hardware state 148 (pp_*) that needs to be 149 brought into the 150 texunit. */ 151 152 drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; 153 /* Six, for the cube faces */ 154 155 GLuint pp_txfilter; /* hardware register values */ 156 GLuint pp_txformat; 157 GLuint pp_txoffset; /* Image location in texmem. 158 All cube faces follow. */ 159 GLuint pp_txsize; /* npot only */ 160 GLuint pp_txpitch; /* npot only */ 161 GLuint pp_border_color; 162 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 163 164 GLboolean border_fallback; 165}; 166 167 168struct radeon_texture_env_state { 169 radeonTexObjPtr texobj; 170 GLenum format; 171 GLenum envMode; 172}; 173 174struct radeon_texture_state { 175 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 176}; 177 178 179struct radeon_state_atom { 180 struct radeon_state_atom *next, *prev; 181 const char *name; /* for debug */ 182 int cmd_size; /* size in bytes */ 183 GLuint is_tcl; 184 int *cmd; /* one or more cmd's */ 185 int *lastcmd; /* one or more cmd's */ 186 GLboolean dirty; /* dirty-mark in emit_state_list */ 187 GLboolean (*check)( GLcontext * ); /* is this state active? */ 188}; 189 190 191 192/* Trying to keep these relatively short as the variables are becoming 193 * extravagently long. Drop the driver name prefix off the front of 194 * everything - I think we know which driver we're in by now, and keep the 195 * prefix to 3 letters unless absolutely impossible. 196 */ 197 198#define CTX_CMD_0 0 199#define CTX_PP_MISC 1 200#define CTX_PP_FOG_COLOR 2 201#define CTX_RE_SOLID_COLOR 3 202#define CTX_RB3D_BLENDCNTL 4 203#define CTX_RB3D_DEPTHOFFSET 5 204#define CTX_RB3D_DEPTHPITCH 6 205#define CTX_RB3D_ZSTENCILCNTL 7 206#define CTX_CMD_1 8 207#define CTX_PP_CNTL 9 208#define CTX_RB3D_CNTL 10 209#define CTX_RB3D_COLOROFFSET 11 210#define CTX_CMD_2 12 211#define CTX_RB3D_COLORPITCH 13 212#define CTX_STATE_SIZE 14 213 214#define SET_CMD_0 0 215#define SET_SE_CNTL 1 216#define SET_SE_COORDFMT 2 217#define SET_CMD_1 3 218#define SET_SE_CNTL_STATUS 4 219#define SET_STATE_SIZE 5 220 221#define LIN_CMD_0 0 222#define LIN_RE_LINE_PATTERN 1 223#define LIN_RE_LINE_STATE 2 224#define LIN_CMD_1 3 225#define LIN_SE_LINE_WIDTH 4 226#define LIN_STATE_SIZE 5 227 228#define MSK_CMD_0 0 229#define MSK_RB3D_STENCILREFMASK 1 230#define MSK_RB3D_ROPCNTL 2 231#define MSK_RB3D_PLANEMASK 3 232#define MSK_STATE_SIZE 4 233 234#define VPT_CMD_0 0 235#define VPT_SE_VPORT_XSCALE 1 236#define VPT_SE_VPORT_XOFFSET 2 237#define VPT_SE_VPORT_YSCALE 3 238#define VPT_SE_VPORT_YOFFSET 4 239#define VPT_SE_VPORT_ZSCALE 5 240#define VPT_SE_VPORT_ZOFFSET 6 241#define VPT_STATE_SIZE 7 242 243#define MSC_CMD_0 0 244#define MSC_RE_MISC 1 245#define MSC_STATE_SIZE 2 246 247#define TEX_CMD_0 0 248#define TEX_PP_TXFILTER 1 249#define TEX_PP_TXFORMAT 2 250#define TEX_PP_TXOFFSET 3 251#define TEX_PP_TXCBLEND 4 252#define TEX_PP_TXABLEND 5 253#define TEX_PP_TFACTOR 6 254#define TEX_CMD_1 7 255#define TEX_PP_BORDER_COLOR 8 256#define TEX_STATE_SIZE 9 257 258#define TXR_CMD_0 0 /* rectangle textures */ 259#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 260#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 261#define TXR_STATE_SIZE 3 262 263#define ZBS_CMD_0 0 264#define ZBS_SE_ZBIAS_FACTOR 1 265#define ZBS_SE_ZBIAS_CONSTANT 2 266#define ZBS_STATE_SIZE 3 267 268#define TCL_CMD_0 0 269#define TCL_OUTPUT_VTXFMT 1 270#define TCL_OUTPUT_VTXSEL 2 271#define TCL_MATRIX_SELECT_0 3 272#define TCL_MATRIX_SELECT_1 4 273#define TCL_UCP_VERT_BLEND_CTL 5 274#define TCL_TEXTURE_PROC_CTL 6 275#define TCL_LIGHT_MODEL_CTL 7 276#define TCL_PER_LIGHT_CTL_0 8 277#define TCL_PER_LIGHT_CTL_1 9 278#define TCL_PER_LIGHT_CTL_2 10 279#define TCL_PER_LIGHT_CTL_3 11 280#define TCL_STATE_SIZE 12 281 282#define MTL_CMD_0 0 283#define MTL_EMMISSIVE_RED 1 284#define MTL_EMMISSIVE_GREEN 2 285#define MTL_EMMISSIVE_BLUE 3 286#define MTL_EMMISSIVE_ALPHA 4 287#define MTL_AMBIENT_RED 5 288#define MTL_AMBIENT_GREEN 6 289#define MTL_AMBIENT_BLUE 7 290#define MTL_AMBIENT_ALPHA 8 291#define MTL_DIFFUSE_RED 9 292#define MTL_DIFFUSE_GREEN 10 293#define MTL_DIFFUSE_BLUE 11 294#define MTL_DIFFUSE_ALPHA 12 295#define MTL_SPECULAR_RED 13 296#define MTL_SPECULAR_GREEN 14 297#define MTL_SPECULAR_BLUE 15 298#define MTL_SPECULAR_ALPHA 16 299#define MTL_SHININESS 17 300#define MTL_STATE_SIZE 18 301 302#define VTX_CMD_0 0 303#define VTX_SE_COORD_FMT 1 304#define VTX_STATE_SIZE 2 305 306#define MAT_CMD_0 0 307#define MAT_ELT_0 1 308#define MAT_STATE_SIZE 17 309 310#define GRD_CMD_0 0 311#define GRD_VERT_GUARD_CLIP_ADJ 1 312#define GRD_VERT_GUARD_DISCARD_ADJ 2 313#define GRD_HORZ_GUARD_CLIP_ADJ 3 314#define GRD_HORZ_GUARD_DISCARD_ADJ 4 315#define GRD_STATE_SIZE 5 316 317/* position changes frequently when lighting in modelpos - separate 318 * out to new state item? 319 */ 320#define LIT_CMD_0 0 321#define LIT_AMBIENT_RED 1 322#define LIT_AMBIENT_GREEN 2 323#define LIT_AMBIENT_BLUE 3 324#define LIT_AMBIENT_ALPHA 4 325#define LIT_DIFFUSE_RED 5 326#define LIT_DIFFUSE_GREEN 6 327#define LIT_DIFFUSE_BLUE 7 328#define LIT_DIFFUSE_ALPHA 8 329#define LIT_SPECULAR_RED 9 330#define LIT_SPECULAR_GREEN 10 331#define LIT_SPECULAR_BLUE 11 332#define LIT_SPECULAR_ALPHA 12 333#define LIT_POSITION_X 13 334#define LIT_POSITION_Y 14 335#define LIT_POSITION_Z 15 336#define LIT_POSITION_W 16 337#define LIT_DIRECTION_X 17 338#define LIT_DIRECTION_Y 18 339#define LIT_DIRECTION_Z 19 340#define LIT_DIRECTION_W 20 341#define LIT_ATTEN_QUADRATIC 21 342#define LIT_ATTEN_LINEAR 22 343#define LIT_ATTEN_CONST 23 344#define LIT_ATTEN_XXX 24 345#define LIT_CMD_1 25 346#define LIT_SPOT_DCD 26 347#define LIT_SPOT_EXPONENT 27 348#define LIT_SPOT_CUTOFF 28 349#define LIT_SPECULAR_THRESH 29 350#define LIT_RANGE_CUTOFF 30 /* ? */ 351#define LIT_ATTEN_CONST_INV 31 352#define LIT_STATE_SIZE 32 353 354/* Fog 355 */ 356#define FOG_CMD_0 0 357#define FOG_R 1 358#define FOG_C 2 359#define FOG_D 3 360#define FOG_PAD 4 361#define FOG_STATE_SIZE 5 362 363/* UCP 364 */ 365#define UCP_CMD_0 0 366#define UCP_X 1 367#define UCP_Y 2 368#define UCP_Z 3 369#define UCP_W 4 370#define UCP_STATE_SIZE 5 371 372/* GLT - Global ambient 373 */ 374#define GLT_CMD_0 0 375#define GLT_RED 1 376#define GLT_GREEN 2 377#define GLT_BLUE 3 378#define GLT_ALPHA 4 379#define GLT_STATE_SIZE 5 380 381/* EYE 382 */ 383#define EYE_CMD_0 0 384#define EYE_X 1 385#define EYE_Y 2 386#define EYE_Z 3 387#define EYE_RESCALE_FACTOR 4 388#define EYE_STATE_SIZE 5 389 390#define SHN_CMD_0 0 391#define SHN_SHININESS 1 392#define SHN_STATE_SIZE 2 393 394 395 396 397 398struct radeon_hw_state { 399 /* Head of the linked list of state atoms. */ 400 struct radeon_state_atom atomlist; 401 402 /* Hardware state, stored as cmdbuf commands: 403 * -- Need to doublebuffer for 404 * - eliding noop statechange loops? (except line stipple count) 405 */ 406 struct radeon_state_atom ctx; 407 struct radeon_state_atom set; 408 struct radeon_state_atom lin; 409 struct radeon_state_atom msk; 410 struct radeon_state_atom vpt; 411 struct radeon_state_atom tcl; 412 struct radeon_state_atom msc; 413 struct radeon_state_atom tex[2]; 414 struct radeon_state_atom zbs; 415 struct radeon_state_atom mtl; 416 struct radeon_state_atom mat[5]; 417 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 418 struct radeon_state_atom ucp[6]; 419 struct radeon_state_atom eye; /* eye pos */ 420 struct radeon_state_atom grd; /* guard band clipping */ 421 struct radeon_state_atom fog; 422 struct radeon_state_atom glt; 423 struct radeon_state_atom txr[2]; /* for NPOT */ 424 425 int max_state_size; /* Number of bytes necessary for a full state emit. */ 426 GLboolean is_dirty, all_dirty; 427}; 428 429struct radeon_state { 430 /* Derived state for internal purposes: 431 */ 432 struct radeon_colorbuffer_state color; 433 struct radeon_depthbuffer_state depth; 434 struct radeon_pixel_state pixel; 435 struct radeon_scissor_state scissor; 436 struct radeon_stencilbuffer_state stencil; 437 struct radeon_stipple_state stipple; 438 struct radeon_texture_state texture; 439}; 440 441 442/* Need refcounting on dma buffers: 443 */ 444struct radeon_dma_buffer { 445 int refcount; /* the number of retained regions in buf */ 446 drmBufPtr buf; 447}; 448 449#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 450 (rvb)->address - rmesa->dma.buf0_address + \ 451 (rvb)->start) 452 453/* A retained region, eg vertices for indexed vertices. 454 */ 455struct radeon_dma_region { 456 struct radeon_dma_buffer *buf; 457 char *address; /* == buf->address */ 458 int start, end, ptr; /* offsets from start of buf */ 459 int aos_start; 460 int aos_stride; 461 int aos_size; 462}; 463 464 465struct radeon_dma { 466 /* Active dma region. Allocations for vertices and retained 467 * regions come from here. Also used for emitting random vertices, 468 * these may be flushed by calling flush_current(); 469 */ 470 struct radeon_dma_region current; 471 472 void (*flush)( radeonContextPtr ); 473 474 char *buf0_address; /* start of buf[0], for index calcs */ 475 GLuint nr_released_bufs; /* flush after so many buffers released */ 476}; 477 478struct radeon_dri_mirror { 479 __DRIcontextPrivate *context; /* DRI context */ 480 __DRIscreenPrivate *screen; /* DRI screen */ 481 __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */ 482 483 drm_context_t hwContext; 484 drm_hw_lock_t *hwLock; 485 int fd; 486 int drmMinor; 487}; 488 489 490#define RADEON_CMD_BUF_SZ (8*1024) 491 492struct radeon_store { 493 GLuint statenr; 494 GLuint primnr; 495 char cmd_buf[RADEON_CMD_BUF_SZ]; 496 int cmd_used; 497 int elts_start; 498}; 499 500 501/* radeon_tcl.c 502 */ 503struct radeon_tcl_info { 504 GLuint vertex_format; 505 GLint last_offset; 506 GLuint hw_primitive; 507 508 /* Temporary for cases where incoming vertex data is incompatible 509 * with maos code. 510 */ 511 GLvector4f ObjClean; 512 513 struct radeon_dma_region *aos_components[8]; 514 GLuint nr_aos_components; 515 516 GLuint *Elts; 517 518 struct radeon_dma_region indexed_verts; 519 struct radeon_dma_region obj; 520 struct radeon_dma_region rgba; 521 struct radeon_dma_region spec; 522 struct radeon_dma_region fog; 523 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 524 struct radeon_dma_region norm; 525}; 526 527 528/* radeon_swtcl.c 529 */ 530struct radeon_swtcl_info { 531 GLuint SetupIndex; 532 GLuint SetupNewInputs; 533 GLuint RenderIndex; 534 GLuint vertex_size; 535 GLuint vertex_stride_shift; 536 GLuint vertex_format; 537 GLubyte *verts; 538 539 /* Fallback rasterization functions 540 */ 541 radeon_point_func draw_point; 542 radeon_line_func draw_line; 543 radeon_tri_func draw_tri; 544 545 GLuint hw_primitive; 546 GLenum render_primitive; 547 GLuint numverts; 548 549 struct radeon_dma_region indexed_verts; 550}; 551 552 553struct radeon_ioctl { 554 GLuint vertex_offset; 555 GLuint vertex_size; 556}; 557 558 559 560#define RADEON_MAX_PRIMS 64 561 562 563/* Want to keep a cache of these around. Each is parameterized by 564 * only a single value which has only a small range. Only expect a 565 * few, so just rescan the list each time? 566 */ 567struct dynfn { 568 struct dynfn *next, *prev; 569 int key; 570 char *code; 571}; 572 573struct dfn_lists { 574 struct dynfn Vertex2f; 575 struct dynfn Vertex2fv; 576 struct dynfn Vertex3f; 577 struct dynfn Vertex3fv; 578 struct dynfn Color4ub; 579 struct dynfn Color4ubv; 580 struct dynfn Color3ub; 581 struct dynfn Color3ubv; 582 struct dynfn Color4f; 583 struct dynfn Color4fv; 584 struct dynfn Color3f; 585 struct dynfn Color3fv; 586 struct dynfn SecondaryColor3ubEXT; 587 struct dynfn SecondaryColor3ubvEXT; 588 struct dynfn SecondaryColor3fEXT; 589 struct dynfn SecondaryColor3fvEXT; 590 struct dynfn Normal3f; 591 struct dynfn Normal3fv; 592 struct dynfn TexCoord2f; 593 struct dynfn TexCoord2fv; 594 struct dynfn TexCoord1f; 595 struct dynfn TexCoord1fv; 596 struct dynfn MultiTexCoord2fARB; 597 struct dynfn MultiTexCoord2fvARB; 598 struct dynfn MultiTexCoord1fARB; 599 struct dynfn MultiTexCoord1fvARB; 600}; 601 602struct dfn_generators { 603 struct dynfn *(*Vertex2f)( GLcontext *, int ); 604 struct dynfn *(*Vertex2fv)( GLcontext *, int ); 605 struct dynfn *(*Vertex3f)( GLcontext *, int ); 606 struct dynfn *(*Vertex3fv)( GLcontext *, int ); 607 struct dynfn *(*Color4ub)( GLcontext *, int ); 608 struct dynfn *(*Color4ubv)( GLcontext *, int ); 609 struct dynfn *(*Color3ub)( GLcontext *, int ); 610 struct dynfn *(*Color3ubv)( GLcontext *, int ); 611 struct dynfn *(*Color4f)( GLcontext *, int ); 612 struct dynfn *(*Color4fv)( GLcontext *, int ); 613 struct dynfn *(*Color3f)( GLcontext *, int ); 614 struct dynfn *(*Color3fv)( GLcontext *, int ); 615 struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int ); 616 struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int ); 617 struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int ); 618 struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int ); 619 struct dynfn *(*Normal3f)( GLcontext *, int ); 620 struct dynfn *(*Normal3fv)( GLcontext *, int ); 621 struct dynfn *(*TexCoord2f)( GLcontext *, int ); 622 struct dynfn *(*TexCoord2fv)( GLcontext *, int ); 623 struct dynfn *(*TexCoord1f)( GLcontext *, int ); 624 struct dynfn *(*TexCoord1fv)( GLcontext *, int ); 625 struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int ); 626 struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int ); 627 struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int ); 628 struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int ); 629}; 630 631 632 633struct radeon_prim { 634 GLuint start; 635 GLuint end; 636 GLuint prim; 637}; 638 639struct radeon_vbinfo { 640 GLint counter, initial_counter; 641 GLint *dmaptr; 642 void (*notify)( void ); 643 GLint vertex_size; 644 645 /* A maximum total of 15 elements per vertex: 3 floats for position, 3 646 * floats for normal, 4 floats for color, 4 bytes for secondary color, 647 * 2 floats for each texture unit (4 floats total). 648 * 649 * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are 650 * supported, this value will grow. 651 * 652 * The position data is never actually stored here, so 3 elements could be 653 * trimmed out of the buffer. 654 */ 655 union { float f; int i; radeon_color_t color; } vertex[15]; 656 657 GLfloat *normalptr; 658 GLfloat *floatcolorptr; 659 radeon_color_t *colorptr; 660 GLfloat *floatspecptr; 661 radeon_color_t *specptr; 662 GLfloat *texcoordptr[2]; 663 664 GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ 665 GLuint primflags; 666 GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */ 667 GLboolean installed; 668 GLboolean fell_back; 669 GLboolean recheck; 670 GLint nrverts; 671 GLuint vertex_format; 672 673 GLuint installed_vertex_format; 674 GLuint installed_color_3f_sz; 675 676 struct radeon_prim primlist[RADEON_MAX_PRIMS]; 677 int nrprims; 678 679 struct dfn_lists dfn_cache; 680 struct dfn_generators codegen; 681 GLvertexformat vtxfmt; 682}; 683 684 685 686 687struct radeon_context { 688 GLcontext *glCtx; /* Mesa context */ 689 690 /* Driver and hardware state management 691 */ 692 struct radeon_hw_state hw; 693 struct radeon_state state; 694 695 /* Texture object bookkeeping 696 */ 697 unsigned nr_heaps; 698 driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 699 driTextureObject swapped; 700 int texture_depth; 701 float initialMaxAnisotropy; 702 703 /* Rasterization and vertex state: 704 */ 705 GLuint TclFallback; 706 GLuint Fallback; 707 GLuint NewGLState; 708 709 /* Vertex buffers 710 */ 711 struct radeon_ioctl ioctl; 712 struct radeon_dma dma; 713 struct radeon_store store; 714 /* A full state emit as of the first state emit in the main store, in case 715 * the context is lost. 716 */ 717 struct radeon_store backup_store; 718 719 /* Page flipping 720 */ 721 GLuint doPageFlip; 722 723 /* Busy waiting 724 */ 725 GLuint do_usleeps; 726 GLuint do_irqs; 727 GLuint irqsEmitted; 728 drm_radeon_irq_wait_t iw; 729 730 /* Drawable, cliprect and scissor information 731 */ 732 GLuint numClipRects; /* Cliprects for the draw buffer */ 733 drm_clip_rect_t *pClipRects; 734 unsigned int lastStamp; 735 GLboolean lost_context; 736 GLboolean save_on_next_emit; 737 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 738 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 739 740 /* TCL stuff 741 */ 742 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 743 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 744 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 745 GLuint TexMatEnabled; 746 GLuint TexGenEnabled; 747 GLmatrix tmpmat; 748 GLuint last_ReallyEnabled; 749 750 /* VBI 751 */ 752 GLuint vbl_seq; 753 GLuint vblank_flags; 754 755 int64_t swap_ust; 756 int64_t swap_missed_ust; 757 758 GLuint swap_count; 759 GLuint swap_missed_count; 760 761 PFNGLXGETUSTPROC get_ust; 762 763 /* radeon_tcl.c 764 */ 765 struct radeon_tcl_info tcl; 766 767 /* radeon_swtcl.c 768 */ 769 struct radeon_swtcl_info swtcl; 770 771 /* radeon_vtxfmt.c 772 */ 773 struct radeon_vbinfo vb; 774 775 /* Mirrors of some DRI state 776 */ 777 struct radeon_dri_mirror dri; 778 779 /* Configuration cache 780 */ 781 driOptionCache optionCache; 782 783 GLboolean using_hyperz; 784 785 /* Performance counters 786 */ 787 GLuint boxes; /* Draw performance boxes */ 788 GLuint hardwareWentIdle; 789 GLuint c_clears; 790 GLuint c_drawWaits; 791 GLuint c_textureSwaps; 792 GLuint c_textureBytes; 793 GLuint c_vertexBuffers; 794}; 795 796#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 797 798 799static __inline GLuint radeonPackColor( GLuint cpp, 800 GLubyte r, GLubyte g, 801 GLubyte b, GLubyte a ) 802{ 803 switch ( cpp ) { 804 case 2: 805 return PACK_COLOR_565( r, g, b ); 806 case 4: 807 return PACK_COLOR_8888( a, r, g, b ); 808 default: 809 return 0; 810 } 811} 812 813#define RADEON_OLD_PACKETS 1 814 815 816extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ); 817extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual, 818 __DRIcontextPrivate *driContextPriv, 819 void *sharedContextPrivate); 820extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv ); 821extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, 822 __DRIdrawablePrivate *driDrawPriv, 823 __DRIdrawablePrivate *driReadPriv ); 824extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv ); 825 826/* ================================================================ 827 * Debugging: 828 */ 829#define DO_DEBUG 1 830 831#if DO_DEBUG 832extern int RADEON_DEBUG; 833#else 834#define RADEON_DEBUG 0 835#endif 836 837#define DEBUG_TEXTURE 0x001 838#define DEBUG_STATE 0x002 839#define DEBUG_IOCTL 0x004 840#define DEBUG_PRIMS 0x008 841#define DEBUG_VERTS 0x010 842#define DEBUG_FALLBACKS 0x020 843#define DEBUG_VFMT 0x040 844#define DEBUG_CODEGEN 0x080 845#define DEBUG_VERBOSE 0x100 846#define DEBUG_DRI 0x200 847#define DEBUG_DMA 0x400 848#define DEBUG_SANITY 0x800 849#define DEBUG_SYNC 0x1000 850 851#endif /* __RADEON_CONTEXT_H__ */ 852