radeon_context.h revision c06b25594e5effe34a90c067e1a3da0f61cf2b13
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_context.h,v 1.6 2002/12/16 16:18:58 dawes Exp $ */ 2/************************************************************************** 3 4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 5 VA Linux Systems Inc., Fremont, California. 6 7All Rights Reserved. 8 9Permission is hereby granted, free of charge, to any person obtaining 10a copy of this software and associated documentation files (the 11"Software"), to deal in the Software without restriction, including 12without limitation the rights to use, copy, modify, merge, publish, 13distribute, sublicense, and/or sell copies of the Software, and to 14permit persons to whom the Software is furnished to do so, subject to 15the following conditions: 16 17The above copyright notice and this permission notice (including the 18next paragraph) shall be included in all copies or substantial 19portions of the Software. 20 21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 29**************************************************************************/ 30 31/* 32 * Authors: 33 * Kevin E. Martin <martin@valinux.com> 34 * Gareth Hughes <gareth@valinux.com> 35 * Keith Whitwell <keith@tungstengraphics.com> 36 */ 37 38#ifndef __RADEON_CONTEXT_H__ 39#define __RADEON_CONTEXT_H__ 40 41#ifdef GLX_DIRECT_RENDERING 42 43#include "dri_util.h" 44#include "drm.h" 45#include "radeon_drm.h" 46#include "texmem.h" 47 48#include "macros.h" 49#include "mtypes.h" 50#include "colormac.h" 51 52struct radeon_context; 53typedef struct radeon_context radeonContextRec; 54typedef struct radeon_context *radeonContextPtr; 55 56#include "radeon_lock.h" 57#include "radeon_screen.h" 58#include "mm.h" 59 60#include "math/m_vector.h" 61 62/* Flags for software fallback cases */ 63/* See correponding strings in radeon_swtcl.c */ 64#define RADEON_FALLBACK_TEXTURE 0x0001 65#define RADEON_FALLBACK_DRAW_BUFFER 0x0002 66#define RADEON_FALLBACK_STENCIL 0x0004 67#define RADEON_FALLBACK_RENDER_MODE 0x0008 68#define RADEON_FALLBACK_BLEND_EQ 0x0010 69#define RADEON_FALLBACK_BLEND_FUNC 0x0020 70#define RADEON_FALLBACK_DISABLE 0x0040 71#define RADEON_FALLBACK_BORDER_MODE 0x0080 72 73/* The blit width for texture uploads 74 */ 75#define BLIT_WIDTH_BYTES 1024 76 77/* Use the templated vertex format: 78 */ 79#define COLOR_IS_RGBA 80#define TAG(x) radeon##x 81#include "tnl_dd/t_dd_vertex.h" 82#undef TAG 83 84typedef void (*radeon_tri_func)( radeonContextPtr, 85 radeonVertex *, 86 radeonVertex *, 87 radeonVertex * ); 88 89typedef void (*radeon_line_func)( radeonContextPtr, 90 radeonVertex *, 91 radeonVertex * ); 92 93typedef void (*radeon_point_func)( radeonContextPtr, 94 radeonVertex * ); 95 96 97struct radeon_colorbuffer_state { 98 GLuint clear; 99 GLint drawOffset, drawPitch; 100 int roundEnable; 101}; 102 103 104struct radeon_depthbuffer_state { 105 GLuint clear; 106 GLfloat scale; 107}; 108 109struct radeon_pixel_state { 110 GLint readOffset, readPitch; 111}; 112 113struct radeon_scissor_state { 114 drm_clip_rect_t rect; 115 GLboolean enabled; 116 117 GLuint numClipRects; /* Cliprects active */ 118 GLuint numAllocedClipRects; /* Cliprects available */ 119 drm_clip_rect_t *pClipRects; 120}; 121 122struct radeon_stencilbuffer_state { 123 GLboolean hwBuffer; 124 GLuint clear; /* rb3d_stencilrefmask value */ 125}; 126 127struct radeon_stipple_state { 128 GLuint mask[32]; 129}; 130 131 132 133#define TEX_0 0x1 134#define TEX_1 0x2 135#define TEX_ALL 0x3 136 137typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; 138 139/* Texture object in locally shared texture space. 140 */ 141struct radeon_tex_obj { 142 driTextureObject base; 143 144 GLuint bufAddr; /* Offset to start of locally 145 shared texture block */ 146 147 GLuint dirty_state; /* Flags (1 per texunit) for 148 whether or not this texobj 149 has dirty hardware state 150 (pp_*) that needs to be 151 brought into the 152 texunit. */ 153 154 drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; 155 /* Six, for the cube faces */ 156 157 GLuint pp_txfilter; /* hardware register values */ 158 GLuint pp_txformat; 159 GLuint pp_txoffset; /* Image location in texmem. 160 All cube faces follow. */ 161 GLuint pp_txsize; /* npot only */ 162 GLuint pp_txpitch; /* npot only */ 163 GLuint pp_border_color; 164 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ 165 166 GLboolean border_fallback; 167}; 168 169 170struct radeon_texture_env_state { 171 radeonTexObjPtr texobj; 172 GLenum format; 173 GLenum envMode; 174}; 175 176struct radeon_texture_state { 177 struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; 178}; 179 180 181struct radeon_state_atom { 182 struct radeon_state_atom *next, *prev; 183 const char *name; /* for debug */ 184 int cmd_size; /* size in bytes */ 185 GLuint is_tcl; 186 int *cmd; /* one or more cmd's */ 187 int *lastcmd; /* one or more cmd's */ 188 GLboolean dirty; /* dirty-mark in emit_state_list */ 189 GLboolean (*check)( GLcontext * ); /* is this state active? */ 190}; 191 192 193 194/* Trying to keep these relatively short as the variables are becoming 195 * extravagently long. Drop the driver name prefix off the front of 196 * everything - I think we know which driver we're in by now, and keep the 197 * prefix to 3 letters unless absolutely impossible. 198 */ 199 200#define CTX_CMD_0 0 201#define CTX_PP_MISC 1 202#define CTX_PP_FOG_COLOR 2 203#define CTX_RE_SOLID_COLOR 3 204#define CTX_RB3D_BLENDCNTL 4 205#define CTX_RB3D_DEPTHOFFSET 5 206#define CTX_RB3D_DEPTHPITCH 6 207#define CTX_RB3D_ZSTENCILCNTL 7 208#define CTX_CMD_1 8 209#define CTX_PP_CNTL 9 210#define CTX_RB3D_CNTL 10 211#define CTX_RB3D_COLOROFFSET 11 212#define CTX_CMD_2 12 213#define CTX_RB3D_COLORPITCH 13 214#define CTX_STATE_SIZE 14 215 216#define SET_CMD_0 0 217#define SET_SE_CNTL 1 218#define SET_SE_COORDFMT 2 219#define SET_CMD_1 3 220#define SET_SE_CNTL_STATUS 4 221#define SET_STATE_SIZE 5 222 223#define LIN_CMD_0 0 224#define LIN_RE_LINE_PATTERN 1 225#define LIN_RE_LINE_STATE 2 226#define LIN_CMD_1 3 227#define LIN_SE_LINE_WIDTH 4 228#define LIN_STATE_SIZE 5 229 230#define MSK_CMD_0 0 231#define MSK_RB3D_STENCILREFMASK 1 232#define MSK_RB3D_ROPCNTL 2 233#define MSK_RB3D_PLANEMASK 3 234#define MSK_STATE_SIZE 4 235 236#define VPT_CMD_0 0 237#define VPT_SE_VPORT_XSCALE 1 238#define VPT_SE_VPORT_XOFFSET 2 239#define VPT_SE_VPORT_YSCALE 3 240#define VPT_SE_VPORT_YOFFSET 4 241#define VPT_SE_VPORT_ZSCALE 5 242#define VPT_SE_VPORT_ZOFFSET 6 243#define VPT_STATE_SIZE 7 244 245#define MSC_CMD_0 0 246#define MSC_RE_MISC 1 247#define MSC_STATE_SIZE 2 248 249#define TEX_CMD_0 0 250#define TEX_PP_TXFILTER 1 251#define TEX_PP_TXFORMAT 2 252#define TEX_PP_TXOFFSET 3 253#define TEX_PP_TXCBLEND 4 254#define TEX_PP_TXABLEND 5 255#define TEX_PP_TFACTOR 6 256#define TEX_CMD_1 7 257#define TEX_PP_BORDER_COLOR 8 258#define TEX_STATE_SIZE 9 259 260#define TXR_CMD_0 0 /* rectangle textures */ 261#define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ 262#define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ 263#define TXR_STATE_SIZE 3 264 265#define ZBS_CMD_0 0 266#define ZBS_SE_ZBIAS_FACTOR 1 267#define ZBS_SE_ZBIAS_CONSTANT 2 268#define ZBS_STATE_SIZE 3 269 270#define TCL_CMD_0 0 271#define TCL_OUTPUT_VTXFMT 1 272#define TCL_OUTPUT_VTXSEL 2 273#define TCL_MATRIX_SELECT_0 3 274#define TCL_MATRIX_SELECT_1 4 275#define TCL_UCP_VERT_BLEND_CTL 5 276#define TCL_TEXTURE_PROC_CTL 6 277#define TCL_LIGHT_MODEL_CTL 7 278#define TCL_PER_LIGHT_CTL_0 8 279#define TCL_PER_LIGHT_CTL_1 9 280#define TCL_PER_LIGHT_CTL_2 10 281#define TCL_PER_LIGHT_CTL_3 11 282#define TCL_STATE_SIZE 12 283 284#define MTL_CMD_0 0 285#define MTL_EMMISSIVE_RED 1 286#define MTL_EMMISSIVE_GREEN 2 287#define MTL_EMMISSIVE_BLUE 3 288#define MTL_EMMISSIVE_ALPHA 4 289#define MTL_AMBIENT_RED 5 290#define MTL_AMBIENT_GREEN 6 291#define MTL_AMBIENT_BLUE 7 292#define MTL_AMBIENT_ALPHA 8 293#define MTL_DIFFUSE_RED 9 294#define MTL_DIFFUSE_GREEN 10 295#define MTL_DIFFUSE_BLUE 11 296#define MTL_DIFFUSE_ALPHA 12 297#define MTL_SPECULAR_RED 13 298#define MTL_SPECULAR_GREEN 14 299#define MTL_SPECULAR_BLUE 15 300#define MTL_SPECULAR_ALPHA 16 301#define MTL_SHININESS 17 302#define MTL_STATE_SIZE 18 303 304#define VTX_CMD_0 0 305#define VTX_SE_COORD_FMT 1 306#define VTX_STATE_SIZE 2 307 308#define MAT_CMD_0 0 309#define MAT_ELT_0 1 310#define MAT_STATE_SIZE 17 311 312#define GRD_CMD_0 0 313#define GRD_VERT_GUARD_CLIP_ADJ 1 314#define GRD_VERT_GUARD_DISCARD_ADJ 2 315#define GRD_HORZ_GUARD_CLIP_ADJ 3 316#define GRD_HORZ_GUARD_DISCARD_ADJ 4 317#define GRD_STATE_SIZE 5 318 319/* position changes frequently when lighting in modelpos - separate 320 * out to new state item? 321 */ 322#define LIT_CMD_0 0 323#define LIT_AMBIENT_RED 1 324#define LIT_AMBIENT_GREEN 2 325#define LIT_AMBIENT_BLUE 3 326#define LIT_AMBIENT_ALPHA 4 327#define LIT_DIFFUSE_RED 5 328#define LIT_DIFFUSE_GREEN 6 329#define LIT_DIFFUSE_BLUE 7 330#define LIT_DIFFUSE_ALPHA 8 331#define LIT_SPECULAR_RED 9 332#define LIT_SPECULAR_GREEN 10 333#define LIT_SPECULAR_BLUE 11 334#define LIT_SPECULAR_ALPHA 12 335#define LIT_POSITION_X 13 336#define LIT_POSITION_Y 14 337#define LIT_POSITION_Z 15 338#define LIT_POSITION_W 16 339#define LIT_DIRECTION_X 17 340#define LIT_DIRECTION_Y 18 341#define LIT_DIRECTION_Z 19 342#define LIT_DIRECTION_W 20 343#define LIT_ATTEN_QUADRATIC 21 344#define LIT_ATTEN_LINEAR 22 345#define LIT_ATTEN_CONST 23 346#define LIT_ATTEN_XXX 24 347#define LIT_CMD_1 25 348#define LIT_SPOT_DCD 26 349#define LIT_SPOT_EXPONENT 27 350#define LIT_SPOT_CUTOFF 28 351#define LIT_SPECULAR_THRESH 29 352#define LIT_RANGE_CUTOFF 30 /* ? */ 353#define LIT_ATTEN_CONST_INV 31 354#define LIT_STATE_SIZE 32 355 356/* Fog 357 */ 358#define FOG_CMD_0 0 359#define FOG_R 1 360#define FOG_C 2 361#define FOG_D 3 362#define FOG_PAD 4 363#define FOG_STATE_SIZE 5 364 365/* UCP 366 */ 367#define UCP_CMD_0 0 368#define UCP_X 1 369#define UCP_Y 2 370#define UCP_Z 3 371#define UCP_W 4 372#define UCP_STATE_SIZE 5 373 374/* GLT - Global ambient 375 */ 376#define GLT_CMD_0 0 377#define GLT_RED 1 378#define GLT_GREEN 2 379#define GLT_BLUE 3 380#define GLT_ALPHA 4 381#define GLT_STATE_SIZE 5 382 383/* EYE 384 */ 385#define EYE_CMD_0 0 386#define EYE_X 1 387#define EYE_Y 2 388#define EYE_Z 3 389#define EYE_RESCALE_FACTOR 4 390#define EYE_STATE_SIZE 5 391 392#define SHN_CMD_0 0 393#define SHN_SHININESS 1 394#define SHN_STATE_SIZE 2 395 396 397 398 399 400struct radeon_hw_state { 401 /* All state should be on one of these lists: 402 */ 403 struct radeon_state_atom dirty; /* dirty list head placeholder */ 404 struct radeon_state_atom clean; /* clean list head placeholder */ 405 406 /* Hardware state, stored as cmdbuf commands: 407 * -- Need to doublebuffer for 408 * - reviving state after loss of context 409 * - eliding noop statechange loops? (except line stipple count) 410 */ 411 struct radeon_state_atom ctx; 412 struct radeon_state_atom set; 413 struct radeon_state_atom lin; 414 struct radeon_state_atom msk; 415 struct radeon_state_atom vpt; 416 struct radeon_state_atom tcl; 417 struct radeon_state_atom msc; 418 struct radeon_state_atom tex[2]; 419 struct radeon_state_atom zbs; 420 struct radeon_state_atom mtl; 421 struct radeon_state_atom mat[5]; 422 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 423 struct radeon_state_atom ucp[6]; 424 struct radeon_state_atom eye; /* eye pos */ 425 struct radeon_state_atom grd; /* guard band clipping */ 426 struct radeon_state_atom fog; 427 struct radeon_state_atom glt; 428 struct radeon_state_atom txr[2]; /* for NPOT */ 429}; 430 431struct radeon_state { 432 /* Derived state for internal purposes: 433 */ 434 struct radeon_colorbuffer_state color; 435 struct radeon_depthbuffer_state depth; 436 struct radeon_pixel_state pixel; 437 struct radeon_scissor_state scissor; 438 struct radeon_stencilbuffer_state stencil; 439 struct radeon_stipple_state stipple; 440 struct radeon_texture_state texture; 441}; 442 443 444/* Need refcounting on dma buffers: 445 */ 446struct radeon_dma_buffer { 447 int refcount; /* the number of retained regions in buf */ 448 drmBufPtr buf; 449}; 450 451#define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ 452 (rvb)->address - rmesa->dma.buf0_address + \ 453 (rvb)->start) 454 455/* A retained region, eg vertices for indexed vertices. 456 */ 457struct radeon_dma_region { 458 struct radeon_dma_buffer *buf; 459 char *address; /* == buf->address */ 460 int start, end, ptr; /* offsets from start of buf */ 461 int aos_start; 462 int aos_stride; 463 int aos_size; 464}; 465 466 467struct radeon_dma { 468 /* Active dma region. Allocations for vertices and retained 469 * regions come from here. Also used for emitting random vertices, 470 * these may be flushed by calling flush_current(); 471 */ 472 struct radeon_dma_region current; 473 474 void (*flush)( radeonContextPtr ); 475 476 char *buf0_address; /* start of buf[0], for index calcs */ 477 GLuint nr_released_bufs; /* flush after so many buffers released */ 478}; 479 480struct radeon_dri_mirror { 481 __DRIcontextPrivate *context; /* DRI context */ 482 __DRIscreenPrivate *screen; /* DRI screen */ 483 __DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */ 484 485 drm_context_t hwContext; 486 drm_hw_lock_t *hwLock; 487 int fd; 488 int drmMinor; 489}; 490 491 492#define RADEON_CMD_BUF_SZ (8*1024) 493 494struct radeon_store { 495 GLuint statenr; 496 GLuint primnr; 497 char cmd_buf[RADEON_CMD_BUF_SZ]; 498 int cmd_used; 499 int elts_start; 500}; 501 502 503/* radeon_tcl.c 504 */ 505struct radeon_tcl_info { 506 GLuint vertex_format; 507 GLint last_offset; 508 GLuint hw_primitive; 509 510 /* Temporary for cases where incoming vertex data is incompatible 511 * with maos code. 512 */ 513 GLvector4f ObjClean; 514 515 struct radeon_dma_region *aos_components[8]; 516 GLuint nr_aos_components; 517 518 GLuint *Elts; 519 520 struct radeon_dma_region indexed_verts; 521 struct radeon_dma_region obj; 522 struct radeon_dma_region rgba; 523 struct radeon_dma_region spec; 524 struct radeon_dma_region fog; 525 struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; 526 struct radeon_dma_region norm; 527}; 528 529 530/* radeon_swtcl.c 531 */ 532struct radeon_swtcl_info { 533 GLuint SetupIndex; 534 GLuint SetupNewInputs; 535 GLuint RenderIndex; 536 GLuint vertex_size; 537 GLuint vertex_stride_shift; 538 GLuint vertex_format; 539 GLubyte *verts; 540 541 /* Fallback rasterization functions 542 */ 543 radeon_point_func draw_point; 544 radeon_line_func draw_line; 545 radeon_tri_func draw_tri; 546 547 GLuint hw_primitive; 548 GLenum render_primitive; 549 GLuint numverts; 550 551 struct radeon_dma_region indexed_verts; 552}; 553 554 555struct radeon_ioctl { 556 GLuint vertex_offset; 557 GLuint vertex_size; 558}; 559 560 561 562#define RADEON_MAX_PRIMS 64 563 564 565/* Want to keep a cache of these around. Each is parameterized by 566 * only a single value which has only a small range. Only expect a 567 * few, so just rescan the list each time? 568 */ 569struct dynfn { 570 struct dynfn *next, *prev; 571 int key; 572 char *code; 573}; 574 575struct dfn_lists { 576 struct dynfn Vertex2f; 577 struct dynfn Vertex2fv; 578 struct dynfn Vertex3f; 579 struct dynfn Vertex3fv; 580 struct dynfn Color4ub; 581 struct dynfn Color4ubv; 582 struct dynfn Color3ub; 583 struct dynfn Color3ubv; 584 struct dynfn Color4f; 585 struct dynfn Color4fv; 586 struct dynfn Color3f; 587 struct dynfn Color3fv; 588 struct dynfn SecondaryColor3ubEXT; 589 struct dynfn SecondaryColor3ubvEXT; 590 struct dynfn SecondaryColor3fEXT; 591 struct dynfn SecondaryColor3fvEXT; 592 struct dynfn Normal3f; 593 struct dynfn Normal3fv; 594 struct dynfn TexCoord2f; 595 struct dynfn TexCoord2fv; 596 struct dynfn TexCoord1f; 597 struct dynfn TexCoord1fv; 598 struct dynfn MultiTexCoord2fARB; 599 struct dynfn MultiTexCoord2fvARB; 600 struct dynfn MultiTexCoord1fARB; 601 struct dynfn MultiTexCoord1fvARB; 602}; 603 604struct dfn_generators { 605 struct dynfn *(*Vertex2f)( GLcontext *, int ); 606 struct dynfn *(*Vertex2fv)( GLcontext *, int ); 607 struct dynfn *(*Vertex3f)( GLcontext *, int ); 608 struct dynfn *(*Vertex3fv)( GLcontext *, int ); 609 struct dynfn *(*Color4ub)( GLcontext *, int ); 610 struct dynfn *(*Color4ubv)( GLcontext *, int ); 611 struct dynfn *(*Color3ub)( GLcontext *, int ); 612 struct dynfn *(*Color3ubv)( GLcontext *, int ); 613 struct dynfn *(*Color4f)( GLcontext *, int ); 614 struct dynfn *(*Color4fv)( GLcontext *, int ); 615 struct dynfn *(*Color3f)( GLcontext *, int ); 616 struct dynfn *(*Color3fv)( GLcontext *, int ); 617 struct dynfn *(*SecondaryColor3ubEXT)( GLcontext *, int ); 618 struct dynfn *(*SecondaryColor3ubvEXT)( GLcontext *, int ); 619 struct dynfn *(*SecondaryColor3fEXT)( GLcontext *, int ); 620 struct dynfn *(*SecondaryColor3fvEXT)( GLcontext *, int ); 621 struct dynfn *(*Normal3f)( GLcontext *, int ); 622 struct dynfn *(*Normal3fv)( GLcontext *, int ); 623 struct dynfn *(*TexCoord2f)( GLcontext *, int ); 624 struct dynfn *(*TexCoord2fv)( GLcontext *, int ); 625 struct dynfn *(*TexCoord1f)( GLcontext *, int ); 626 struct dynfn *(*TexCoord1fv)( GLcontext *, int ); 627 struct dynfn *(*MultiTexCoord2fARB)( GLcontext *, int ); 628 struct dynfn *(*MultiTexCoord2fvARB)( GLcontext *, int ); 629 struct dynfn *(*MultiTexCoord1fARB)( GLcontext *, int ); 630 struct dynfn *(*MultiTexCoord1fvARB)( GLcontext *, int ); 631}; 632 633 634 635struct radeon_prim { 636 GLuint start; 637 GLuint end; 638 GLuint prim; 639}; 640 641struct radeon_vbinfo { 642 GLint counter, initial_counter; 643 GLint *dmaptr; 644 void (*notify)( void ); 645 GLint vertex_size; 646 647 /* A maximum total of 15 elements per vertex: 3 floats for position, 3 648 * floats for normal, 4 floats for color, 4 bytes for secondary color, 649 * 2 floats for each texture unit (4 floats total). 650 * 651 * As soon as the 3rd TMU is supported or cube maps (or 3D textures) are 652 * supported, this value will grow. 653 * 654 * The position data is never actually stored here, so 3 elements could be 655 * trimmed out of the buffer. 656 */ 657 union { float f; int i; radeon_color_t color; } vertex[15]; 658 659 GLfloat *normalptr; 660 GLfloat *floatcolorptr; 661 radeon_color_t *colorptr; 662 GLfloat *floatspecptr; 663 radeon_color_t *specptr; 664 GLfloat *texcoordptr[2]; 665 666 GLenum *prim; /* &ctx->Driver.CurrentExecPrimitive */ 667 GLuint primflags; 668 GLboolean enabled; /* *_NO_VTXFMT / *_NO_TCL env vars */ 669 GLboolean installed; 670 GLboolean fell_back; 671 GLboolean recheck; 672 GLint nrverts; 673 GLuint vertex_format; 674 675 GLuint installed_vertex_format; 676 GLuint installed_color_3f_sz; 677 678 struct radeon_prim primlist[RADEON_MAX_PRIMS]; 679 int nrprims; 680 681 struct dfn_lists dfn_cache; 682 struct dfn_generators codegen; 683 GLvertexformat vtxfmt; 684}; 685 686 687 688 689struct radeon_context { 690 GLcontext *glCtx; /* Mesa context */ 691 692 /* Driver and hardware state management 693 */ 694 struct radeon_hw_state hw; 695 struct radeon_state state; 696 697 /* Texture object bookkeeping 698 */ 699 unsigned nr_heaps; 700 driTexHeap * texture_heaps[ RADEON_NR_TEX_HEAPS ]; 701 driTextureObject swapped; 702 int texture_depth; 703 float initialMaxAnisotropy; 704 705 /* Rasterization and vertex state: 706 */ 707 GLuint TclFallback; 708 GLuint Fallback; 709 GLuint NewGLState; 710 711 /* Vertex buffers 712 */ 713 struct radeon_ioctl ioctl; 714 struct radeon_dma dma; 715 struct radeon_store store; 716 717 /* Page flipping 718 */ 719 GLuint doPageFlip; 720 721 /* Busy waiting 722 */ 723 GLuint do_usleeps; 724 GLuint do_irqs; 725 GLuint irqsEmitted; 726 drm_radeon_irq_wait_t iw; 727 728 /* Drawable, cliprect and scissor information 729 */ 730 GLuint numClipRects; /* Cliprects for the draw buffer */ 731 drm_clip_rect_t *pClipRects; 732 unsigned int lastStamp; 733 GLboolean lost_context; 734 radeonScreenPtr radeonScreen; /* Screen private DRI data */ 735 drm_radeon_sarea_t *sarea; /* Private SAREA data */ 736 737 /* TCL stuff 738 */ 739 GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; 740 GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; 741 GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; 742 GLuint TexMatEnabled; 743 GLuint TexGenEnabled; 744 GLmatrix tmpmat; 745 GLuint last_ReallyEnabled; 746 747 /* VBI 748 */ 749 GLuint vbl_seq; 750 GLuint vblank_flags; 751 752 int64_t swap_ust; 753 int64_t swap_missed_ust; 754 755 GLuint swap_count; 756 GLuint swap_missed_count; 757 758 PFNGLXGETUSTPROC get_ust; 759 760 /* radeon_tcl.c 761 */ 762 struct radeon_tcl_info tcl; 763 764 /* radeon_swtcl.c 765 */ 766 struct radeon_swtcl_info swtcl; 767 768 /* radeon_vtxfmt.c 769 */ 770 struct radeon_vbinfo vb; 771 772 /* Mirrors of some DRI state 773 */ 774 struct radeon_dri_mirror dri; 775 776 /* Configuration cache 777 */ 778 driOptionCache optionCache; 779 780 781 /* Performance counters 782 */ 783 GLuint boxes; /* Draw performance boxes */ 784 GLuint hardwareWentIdle; 785 GLuint c_clears; 786 GLuint c_drawWaits; 787 GLuint c_textureSwaps; 788 GLuint c_textureBytes; 789 GLuint c_vertexBuffers; 790}; 791 792#define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) 793 794 795static __inline GLuint radeonPackColor( GLuint cpp, 796 GLubyte r, GLubyte g, 797 GLubyte b, GLubyte a ) 798{ 799 switch ( cpp ) { 800 case 2: 801 return PACK_COLOR_565( r, g, b ); 802 case 4: 803 return PACK_COLOR_8888( a, r, g, b ); 804 default: 805 return 0; 806 } 807} 808 809#define RADEON_OLD_PACKETS 1 810 811 812extern void radeonDestroyContext( __DRIcontextPrivate *driContextPriv ); 813extern GLboolean radeonCreateContext(const __GLcontextModes *glVisual, 814 __DRIcontextPrivate *driContextPriv, 815 void *sharedContextPrivate); 816extern void radeonSwapBuffers( __DRIdrawablePrivate *dPriv ); 817extern GLboolean radeonMakeCurrent( __DRIcontextPrivate *driContextPriv, 818 __DRIdrawablePrivate *driDrawPriv, 819 __DRIdrawablePrivate *driReadPriv ); 820extern GLboolean radeonUnbindContext( __DRIcontextPrivate *driContextPriv ); 821 822/* ================================================================ 823 * Debugging: 824 */ 825#define DO_DEBUG 1 826 827#if DO_DEBUG 828extern int RADEON_DEBUG; 829#else 830#define RADEON_DEBUG 0 831#endif 832 833#define DEBUG_TEXTURE 0x001 834#define DEBUG_STATE 0x002 835#define DEBUG_IOCTL 0x004 836#define DEBUG_PRIMS 0x008 837#define DEBUG_VERTS 0x010 838#define DEBUG_FALLBACKS 0x020 839#define DEBUG_VFMT 0x040 840#define DEBUG_CODEGEN 0x080 841#define DEBUG_VERBOSE 0x100 842#define DEBUG_DRI 0x200 843#define DEBUG_DMA 0x400 844#define DEBUG_SANITY 0x800 845 846#endif 847#endif /* __RADEON_CONTEXT_H__ */ 848