15df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/************************************************************************** 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul VA Linux Systems Inc., Fremont, California. 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulAll Rights Reserved. 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulPermission is hereby granted, free of charge, to any person obtaining 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paula copy of this software and associated documentation files (the 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul"Software"), to deal in the Software without restriction, including 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulwithout limitation the rights to use, copy, modify, merge, publish, 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Pauldistribute, sublicense, and/or sell copies of the Software, and to 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulpermit persons to whom the Software is furnished to do so, subject to 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulthe following conditions: 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulThe above copyright notice and this permission notice (including the 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulnext paragraph) shall be included in all copies or substantial 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulportions of the Software. 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul**************************************************************************/ 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* 315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Authors: 325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Kevin E. Martin <martin@valinux.com> 335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Gareth Hughes <gareth@valinux.com> 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Keith Whitwell <keith@tungstengraphics.com> 355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 36bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include <sched.h> 387dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle#include <errno.h> 395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 40c6ac53bc40508ab2f0b9e023eee7ec3793fdf917Dave Airlie#include "main/attrib.h" 41c6ac53bc40508ab2f0b9e023eee7ec3793fdf917Dave Airlie#include "main/bufferobj.h" 42c6ac53bc40508ab2f0b9e023eee7ec3793fdf917Dave Airlie#include "swrast/swrast.h" 43c6ac53bc40508ab2f0b9e023eee7ec3793fdf917Dave Airlie 44ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/glheader.h" 45ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/imports.h" 46ecadb51bbcb972a79f3ed79e65a7986b9396e757Brian Paul#include "main/simple_list.h" 475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_context.h" 4923d3559bd4ece1fcab5513ebdaa38600d6654374Dave Airlie#include "radeon_common.h" 505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_ioctl.h" 515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 52462183fe4cb6df6d90632d9e2cee881c8d26b1cbAlan Hourihane#define STANDALONE_MMIO 535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_TIMEOUT 512 555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_IDLE_RETRY 16 565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ============================================================= 595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Kernel command buffer handling 605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 625562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt/* The state atoms will be emitted in the order they appear in the atom list, 635562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt * so this step is important. 645562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt */ 654637235183b80963536f2364e4d50fcb894886ddDave Airlievoid radeonSetUpAtomList( r100ContextPtr rmesa ) 665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 674637235183b80963536f2364e4d50fcb894886ddDave Airlie int i, mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; 685562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 691090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie make_empty_list(&rmesa->radeon.hw.atomlist); 701090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie rmesa->radeon.hw.atomlist.name = "atom-list"; 715562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 721090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx); 731090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set); 741090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin); 751090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk); 761090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt); 771090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl); 781090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc); 795562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt for (i = 0; i < mtu; ++i) { 801090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]); 811090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]); 821090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i]); 8322d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling } 841090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs); 851090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mtl); 865562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt for (i = 0; i < 3 + mtu; ++i) 871090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i]); 8822d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling for (i = 0; i < 8; ++i) 891090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]); 9022d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling for (i = 0; i < 6; ++i) 911090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]); 920973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.stp); 931090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye); 941090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd); 951090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog); 961090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt); 975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 99c3374bf97ecd82b915fb29c7c04951e2b75d4dbcPauli Nieminenstatic void radeonEmitScissor(r100ContextPtr rmesa) 1006141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse{ 1016141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse BATCH_LOCALS(&rmesa->radeon); 1026141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse if (rmesa->radeon.state.scissor.enabled) { 1036141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse BEGIN_BATCH(6); 1046141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); 1056141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); 1066141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 1076141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | 1086141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse rmesa->radeon.state.scissor.rect.x1); 1096141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 110d0cb1036aa98d35ae5233d326fbb0ba592a26e26Dave Airlie OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) | 111d0cb1036aa98d35ae5233d326fbb0ba592a26e26Dave Airlie (rmesa->radeon.state.scissor.rect.x2)); 1126141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse END_BATCH(); 1136141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse } else { 1146141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse BEGIN_BATCH(2); 1156141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); 1166141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); 1176141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse END_BATCH(); 1186141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse } 1196141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse} 1206141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse 1215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Fire a section of the retained (indexed_verts) buffer as a regular 1227dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle * primtive. 1235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 1244637235183b80963536f2364e4d50fcb894886ddDave Airlieextern void radeonEmitVbufPrim( r100ContextPtr rmesa, 1255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format, 1265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint primitive, 1275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_nr ) 1285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 129b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie BATCH_LOCALS(&rmesa->radeon); 1305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); 1327dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 1331090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie radeonEmitState(&rmesa->radeon); 1346141c9ba71df68c44fb4f8c9409f23b557009ca0Jerome Glisse radeonEmitScissor(rmesa); 1355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1363fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#if RADEON_OLD_PACKETS 1379df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie BEGIN_BATCH(8); 1383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 3); 1390973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt OUT_BATCH(rmesa->ioctl.vertex_offset); 1407dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 1413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(vertex_nr); 1423fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(vertex_format); 1433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(primitive | RADEON_CP_VC_CNTL_PRIM_WALK_LIST | 1443fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 1453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | 1463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); 1472972d065265d38c7902ffeaa1e71706895649becDave Airlie 1480973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 1490973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->ioctl.bo, 1500973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt RADEON_GEM_DOMAIN_GTT, 1510973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt 0, 0); 1527dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 1533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 1547dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 1557dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle#else 1563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH(4); 1573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_DRAW_VBUF, 1); 158b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie OUT_BATCH(vertex_format); 159b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie OUT_BATCH(primitive | 160b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie RADEON_CP_VC_CNTL_PRIM_WALK_LIST | 161b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 162b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie RADEON_CP_VC_CNTL_MAOS_ENABLE | 163b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | 164b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); 165b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie END_BATCH(); 1663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#endif 1675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 169f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergvoid radeonFlushElts( struct gl_context *ctx ) 1705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 171ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie r100ContextPtr rmesa = R100_CONTEXT(ctx); 172ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie BATCH_LOCALS(&rmesa->radeon); 173ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie int nr; 1743fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start); 175ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw); 1767dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 1774e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & RADEON_IOCTL) 1785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 1795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1805ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie assert( rmesa->radeon.dma.flush == radeonFlushElts ); 1815ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie rmesa->radeon.dma.flush = NULL; 1825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 183ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie nr = rmesa->tcl.elt_used; 1843fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 1852972d065265d38c7902ffeaa1e71706895649becDave Airlie#if RADEON_OLD_PACKETS 1860973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt dwords -= 2; 1872972d065265d38c7902ffeaa1e71706895649becDave Airlie#endif 1885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 1903fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie cmd[1] |= (dwords + 3) << 16; 1915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; 1925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 193ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie cmd[1] |= (dwords + 2) << 16; 1945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; 1955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 196150ed2e43d5541556d282cae728cebeec692e07aDave Airlie 1972972d065265d38c7902ffeaa1e71706895649becDave Airlie rmesa->radeon.cmdbuf.cs->cdw += dwords; 1983fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->radeon.cmdbuf.cs->section_cdw += dwords; 1992972d065265d38c7902ffeaa1e71706895649becDave Airlie 2002972d065265d38c7902ffeaa1e71706895649becDave Airlie#if RADEON_OLD_PACKETS 2010973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 2020973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt rmesa->ioctl.bo, 2030973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt RADEON_GEM_DOMAIN_GTT, 2040973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt 0, 0); 2052972d065265d38c7902ffeaa1e71706895649becDave Airlie#endif 2062972d065265d38c7902ffeaa1e71706895649becDave Airlie 2073fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 2083fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2094e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & RADEON_SYNC) { 210150ed2e43d5541556d282cae728cebeec692e07aDave Airlie fprintf(stderr, "%s: Syncing\n", __FUNCTION__); 2114637235183b80963536f2364e4d50fcb894886ddDave Airlie radeonFinish( rmesa->radeon.glCtx ); 212150ed2e43d5541556d282cae728cebeec692e07aDave Airlie } 2135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie} 2155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2164637235183b80963536f2364e4d50fcb894886ddDave AirlieGLushort *radeonAllocEltsOpenEnded( r100ContextPtr rmesa, 2175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format, 2185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint primitive, 2195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint min_nr ) 2205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 2215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLushort *retval; 2229df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie int align_min_nr; 2233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&rmesa->radeon); 224639b5fca0c5cea26a9dc393b538508aece16ce6bDave Airlie 2254e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & RADEON_IOCTL) 226639b5fca0c5cea26a9dc393b538508aece16ce6bDave Airlie fprintf(stderr, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); 2275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); 2297dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 2301090d206de011a67d236d8c4ae32d2d42b2f6337Dave Airlie radeonEmitState(&rmesa->radeon); 2313a6dd3ebb33a35779b0d5be2c8cab581a56f245aJerome Glisse radeonEmitScissor(rmesa); 2327dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 2333fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw; 2343fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2359df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie /* round up min_nr to align the state */ 2369df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie align_min_nr = (min_nr + 1) & ~1; 2379df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie 2383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#if RADEON_OLD_PACKETS 2399df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(2+ELTS_BUFSZ(align_min_nr)/4); 2403fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM, 0); 2410973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt OUT_BATCH(rmesa->ioctl.vertex_offset); 24220d9204fbd71aebf870834b612579419d2c278b5Dave Airlie OUT_BATCH(rmesa->ioctl.vertex_max); 2433fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(vertex_format); 2447dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle OUT_BATCH(primitive | 2453fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_PRIM_WALK_IND | 2463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 2473fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); 2483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#else 2499df844b109a9d2cc1d3b16315c34ef84f147c5b6Dave Airlie BEGIN_BATCH_NO_AUTOSTATE(ELTS_BUFSZ(align_min_nr)/4); 2503fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_PACKET3_CLIP(RADEON_CP_PACKET3_DRAW_INDX, 0); 2513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(vertex_format); 2527dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle OUT_BATCH(primitive | 2533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_PRIM_WALK_IND | 2543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 2553fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_MAOS_ENABLE | 2563fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); 2573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie#endif 2583fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw; 261ccf7814a315f0be05cdc36ca358e2917a3d4ac19Dave Airlie rmesa->tcl.elt_used = min_nr; 262b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie 2633fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset); 2647dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 2654e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & RADEON_RENDER) 2663fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie fprintf(stderr, "%s: header prim %x \n", 2673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie __FUNCTION__, primitive); 2685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2695ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie assert(!rmesa->radeon.dma.flush); 2704637235183b80963536f2364e4d50fcb894886ddDave Airlie rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; 2715ba92a5b0543b4ff2c7db6101029ba36cb9843faDave Airlie rmesa->radeon.dma.flush = radeonFlushElts; 2725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return retval; 2745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2764637235183b80963536f2364e4d50fcb894886ddDave Airlievoid radeonEmitVertexAOS( r100ContextPtr rmesa, 2775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_size, 2783fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie struct radeon_bo *bo, 2795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint offset ) 2805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 2815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 2825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->ioctl.vertex_offset = offset; 2833fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie rmesa->ioctl.bo = bo; 2845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 285b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie BATCH_LOCALS(&rmesa->radeon); 2865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2874e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & (RADEON_PRIMS|DEBUG_IOCTL)) 2885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", 2895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, vertex_size, offset); 2905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2913fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH(7); 292b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, 2); 293b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie OUT_BATCH(1); 294b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie OUT_BATCH(vertex_size | (vertex_size << 8)); 295b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); 296b584b0728d3a001a142f76dde22f9e8ed7d2dd16Dave Airlie END_BATCH(); 2973fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 2985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 2995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 3007dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 3015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3024637235183b80963536f2364e4d50fcb894886ddDave Airlievoid radeonEmitAOS( r100ContextPtr rmesa, 3035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint nr, 3045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint offset ) 3055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 3065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 3075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( nr == 1 ); 308e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo; 3097dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle rmesa->ioctl.vertex_offset = 310e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4); 31120d9204fbd71aebf870834b612579419d2c278b5Dave Airlie rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count; 3125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 3133fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BATCH_LOCALS(&rmesa->radeon); 3143fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie uint32_t voffset; 3153fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie // int sz = AOS_BUFSZ(nr); 3163fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; 3175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int i; 3185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3194e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & RADEON_IOCTL) 3205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 3215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3223fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie BEGIN_BATCH(sz+2+(nr * 2)); 3233fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH_PACKET3(RADEON_CP_PACKET3_3D_LOAD_VBPNTR, sz - 1); 3243fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(nr); 3253fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 3260973a1ec78fdedc5401cb1c0f6d027425c492509Eric Anholt { 3273fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie for (i = 0; i + 1 < nr; i += 2) { 328e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | 329e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie (rmesa->radeon.tcl.aos[i].stride << 8) | 330e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie (rmesa->radeon.tcl.aos[i + 1].components << 16) | 331e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie (rmesa->radeon.tcl.aos[i + 1].stride << 24)); 3327dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 333e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie voffset = rmesa->radeon.tcl.aos[i + 0].offset + 334e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; 3353fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(voffset); 336e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie voffset = rmesa->radeon.tcl.aos[i + 1].offset + 337e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; 3383fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(voffset); 3393fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3407dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle 3413fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (nr & 1) { 342e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | 343e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); 344e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie voffset = rmesa->radeon.tcl.aos[nr - 1].offset + 345e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; 3463fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie OUT_BATCH(voffset); 3475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3483fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie for (i = 0; i + 1 < nr; i += 2) { 349e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie voffset = rmesa->radeon.tcl.aos[i + 0].offset + 350e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; 3513fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 352e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie rmesa->radeon.tcl.aos[i+0].bo, 3533fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_GEM_DOMAIN_GTT, 3543fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 0, 0); 355e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie voffset = rmesa->radeon.tcl.aos[i + 1].offset + 356e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; 3573fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 358e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie rmesa->radeon.tcl.aos[i+1].bo, 3593fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_GEM_DOMAIN_GTT, 3603fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 0, 0); 3613fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie } 3623fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie if (nr & 1) { 363e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie voffset = rmesa->radeon.tcl.aos[nr - 1].offset + 364e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; 3653fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 366e00ef43d796f0ae0247b1072bf0aa8cdd8e3034dDave Airlie rmesa->radeon.tcl.aos[nr-1].bo, 3673fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie RADEON_GEM_DOMAIN_GTT, 3683fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie 0, 0); 3695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3713fafaf8959681cc41c988607bb6e387bab4fe1b5Dave Airlie END_BATCH(); 3725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 3745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 3755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ================================================================ 3775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Buffer clear 3785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_MAX_CLEARS 256 3805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 381f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergstatic void radeonClear( struct gl_context *ctx, GLbitfield mask ) 382940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie{ 383940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie r100ContextPtr rmesa = R100_CONTEXT(ctx); 384de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger GLuint hwmask, swmask; 385de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT | 386de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL | 387de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger BUFFER_BIT_COLOR0; 388940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie 389112908c279b0a768eca95a505856a087e479674bDave Airlie if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) { 390112908c279b0a768eca95a505856a087e479674bDave Airlie rmesa->radeon.front_buffer_dirty = GL_TRUE; 391112908c279b0a768eca95a505856a087e479674bDave Airlie } 392112908c279b0a768eca95a505856a087e479674bDave Airlie 3934e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if ( RADEON_DEBUG & RADEON_IOCTL ) { 394940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie fprintf( stderr, "radeonClear\n"); 395940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie } 396940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie 3977dd184dc4da37233471875df6f40cce0560cb7bcNicolai Hähnle radeon_firevertices(&rmesa->radeon); 398940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie 399de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger hwmask = mask & hwbits; 400de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger swmask = mask & ~hwbits; 401940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie 402de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger if ( swmask ) { 4034e0d99a63588c67a955f797733da32d04e6f4ee6Pauli Nieminen if (RADEON_DEBUG & RADEON_FALLBACKS) 404de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask); 405de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger _swrast_Clear( ctx, swmask ); 406940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie } 407940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie 408de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger if ( !hwmask ) 409940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie return; 410940d47de08eedaf5d8471628ba4860663d79a98eDave Airlie 411de694b6b10b7ce23a00cd7296a955f162704ee62Roland Scheidegger radeonUserClear(ctx, hwmask); 4125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 4135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 414f9995b30756140724f41daf963fa06167912be7fKristian Høgsbergvoid radeonInitIoctlFuncs( struct gl_context *ctx ) 4155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 4165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Clear = radeonClear; 4175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Finish = radeonFinish; 4185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Flush = radeonFlush; 4195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 4205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 421