radeon_ioctl.c revision 982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9
15df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c,v 1.11 2003/01/29 22:04:59 dawes Exp $ */ 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/************************************************************************** 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul VA Linux Systems Inc., Fremont, California. 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulAll Rights Reserved. 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulPermission is hereby granted, free of charge, to any person obtaining 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paula copy of this software and associated documentation files (the 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul"Software"), to deal in the Software without restriction, including 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulwithout limitation the rights to use, copy, modify, merge, publish, 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Pauldistribute, sublicense, and/or sell copies of the Software, and to 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulpermit persons to whom the Software is furnished to do so, subject to 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulthe following conditions: 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulThe above copyright notice and this permission notice (including the 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulnext paragraph) shall be included in all copies or substantial 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulportions of the Software. 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul**************************************************************************/ 305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* 325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Authors: 335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Kevin E. Martin <martin@valinux.com> 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Gareth Hughes <gareth@valinux.com> 355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Keith Whitwell <keith@tungstengraphics.com> 365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 37bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include <sched.h> 39bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl#include <errno.h> 405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "glheader.h" 425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "imports.h" 435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "simple_list.h" 445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "swrast/swrast.h" 455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_context.h" 475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_state.h" 485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_ioctl.h" 495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_tcl.h" 505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_sanity.h" 515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 52462183fe4cb6df6d90632d9e2cee881c8d26b1cbAlan Hourihane#define STANDALONE_MMIO 535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_macros.h" /* for INREG() */ 545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "vblank.h" 565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_TIMEOUT 512 585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_IDLE_RETRY 16 595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void radeonWaitForIdle( radeonContextPtr rmesa ); 625562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholtstatic int radeonFlushCmdBufLocked( radeonContextPtr rmesa, 635562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt const char * caller ); 645562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 658e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheideggerstatic void print_state_atom( struct radeon_state_atom *state ) 668e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger{ 678e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger int i; 688e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger 698e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger fprintf(stderr, "emit %s/%d\n", state->name, state->cmd_size); 708e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger 718e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger if (RADEON_DEBUG & DEBUG_VERBOSE) 728e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger for (i = 0 ; i < state->cmd_size ; i++) 738e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger fprintf(stderr, "\t%s[%d]: %x\n", state->name, i, state->cmd[i]); 748e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger 758e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger} 768e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger 777a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholtstatic void radeonSaveHwState( radeonContextPtr rmesa ) 785562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt{ 795562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt struct radeon_state_atom *atom; 807a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt char * dest = rmesa->backup_store.cmd_buf; 815562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 828e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger if (RADEON_DEBUG & DEBUG_STATE) 838e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger fprintf(stderr, "%s\n", __FUNCTION__); 848e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger 857a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->backup_store.cmd_used = 0; 865562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 877a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt foreach( atom, &rmesa->hw.atomlist ) { 887a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt if ( atom->check( rmesa->glCtx ) ) { 897a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt int size = atom->cmd_size * 4; 907a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt memcpy( dest, atom->cmd, size); 917a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt dest += size; 927a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->backup_store.cmd_used += size; 938e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger if (RADEON_DEBUG & DEBUG_STATE) 948e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger print_state_atom( atom ); 957a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt } 965562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt } 977a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt 987a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt assert( rmesa->backup_store.cmd_used <= RADEON_CMD_BUF_SZ ); 998e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger if (RADEON_DEBUG & DEBUG_STATE) 1008e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger fprintf(stderr, "Returning to radeonEmitState\n"); 1015562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt} 1025562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 1035562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt/* At this point we were in FlushCmdBufLocked but we had lost our context, so 1047a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt * we need to unwire our current cmdbuf, hook the one with the saved state in 1057a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt * it, flush it, and then put the current one back. This is so commands at the 1067a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt * start of a cmdbuf can rely on the state being kept from the previous one. 1075562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt */ 1085562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholtstatic void radeonBackUpAndEmitLostStateLocked( radeonContextPtr rmesa ) 1095562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt{ 1108e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger GLuint nr_released_bufs; 1117a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt struct radeon_store saved_store; 1127a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt 1137a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt if (rmesa->backup_store.cmd_used == 0) 1147a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt return; 1157a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt 1167a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt if (RADEON_DEBUG & DEBUG_STATE) 1177a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt fprintf(stderr, "Emitting backup state on lost context\n"); 1185562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 1195562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->lost_context = GL_FALSE; 1205562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 1215562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt nr_released_bufs = rmesa->dma.nr_released_bufs; 1227a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt saved_store = rmesa->store; 1237a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->dma.nr_released_bufs = 0; 1247a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->store = rmesa->backup_store; 1257a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); 1265562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->dma.nr_released_bufs = nr_released_bufs; 1277a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->store = saved_store; 1285562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt} 1295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ============================================================= 1315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Kernel command buffer handling 1325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 1335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1345562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt/* The state atoms will be emitted in the order they appear in the atom list, 1355562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt * so this step is important. 1365562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt */ 1375562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholtvoid radeonSetUpAtomList( radeonContextPtr rmesa ) 1385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 1395562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt int i, mtu = rmesa->glCtx->Const.MaxTextureUnits; 1405562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 1415562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt make_empty_list(&rmesa->hw.atomlist); 1425562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->hw.atomlist.name = "atom-list"; 1435562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 1445562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ctx); 1455562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.set); 1465562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lin); 1475562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msk); 1485562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.vpt); 1495562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tcl); 1505562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.msc); 1515562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt for (i = 0; i < mtu; ++i) { 1525562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.tex[i]); 1535562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.txr[i]); 15422d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling } 1555562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.zbs); 1565562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mtl); 1575562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt for (i = 0; i < 3 + mtu; ++i) 1585562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.mat[i]); 15922d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling for (i = 0; i < 8; ++i) 1605562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.lit[i]); 16122d1acf2ee25280c3294c2cfded232e612ffac2eFelix Kuehling for (i = 0; i < 6; ++i) 1625562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.ucp[i]); 1635562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.eye); 1645562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.grd); 1655562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.fog); 1665562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt insert_at_tail(&rmesa->hw.atomlist, &rmesa->hw.glt); 1675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonEmitState( radeonContextPtr rmesa ) 1705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 1715562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt struct radeon_state_atom *atom; 1725562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt char *dest; 1735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS)) 1755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 1765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1777a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt if (rmesa->save_on_next_emit) { 1787a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt radeonSaveHwState(rmesa); 1797a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->save_on_next_emit = GL_FALSE; 1807a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt } 1817a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt 18272e3664996721263858f3096e4a618a406550402Dave Airlie /* this code used to return here but now it emits zbs */ 1835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1845562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt /* To avoid going across the entire set of states multiple times, just check 1855562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt * for enough space for the case of emitting all state, and inline the 1865562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt * radeonAllocCmdBuf code here without all the checks. 1875562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt */ 1885562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt radeonEnsureCmdBufSpace(rmesa, rmesa->hw.max_state_size); 1895562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt dest = rmesa->store.cmd_buf + rmesa->store.cmd_used; 1905562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 19172e3664996721263858f3096e4a618a406550402Dave Airlie /* We always always emit zbs, this is due to a bug found by keithw in 19272e3664996721263858f3096e4a618a406550402Dave Airlie the hardware and rediscovered after Erics changes by me. 19372e3664996721263858f3096e4a618a406550402Dave Airlie if you ever touch this code make sure you emit zbs otherwise 19472e3664996721263858f3096e4a618a406550402Dave Airlie you get tcl lockups on at least M7/7500 class of chips - airlied */ 19572e3664996721263858f3096e4a618a406550402Dave Airlie rmesa->hw.zbs.dirty=1; 19672e3664996721263858f3096e4a618a406550402Dave Airlie 1975562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (RADEON_DEBUG & DEBUG_STATE) { 1985562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt foreach(atom, &rmesa->hw.atomlist) { 1995562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (atom->dirty || rmesa->hw.all_dirty) { 2005562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (atom->check(rmesa->glCtx)) 2015562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt print_state_atom(atom); 2025562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt else 2035562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt fprintf(stderr, "skip state %s\n", atom->name); 2045562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt } 2055562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt } 2065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 2075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2085562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt foreach(atom, &rmesa->hw.atomlist) { 2095562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (rmesa->hw.all_dirty) 2105562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt atom->dirty = GL_TRUE; 2115562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) && 2125562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt atom->is_tcl) 2135562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt atom->dirty = GL_FALSE; 2145562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (atom->dirty) { 2155562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (atom->check(rmesa->glCtx)) { 2165562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt int size = atom->cmd_size * 4; 2175562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt memcpy(dest, atom->cmd, size); 2185562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt dest += size; 2195562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->store.cmd_used += size; 2205562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt atom->dirty = GL_FALSE; 2215562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt } 2225562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt } 2235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 2245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2255562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt assert(rmesa->store.cmd_used <= RADEON_CMD_BUF_SZ); 2265562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 2275562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->hw.is_dirty = GL_FALSE; 2285562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->hw.all_dirty = GL_FALSE; 2295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Fire a section of the retained (indexed_verts) buffer as a regular 2325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * primtive. 2335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 2345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulextern void radeonEmitVbufPrim( radeonContextPtr rmesa, 2355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format, 2365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint primitive, 2375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_nr ) 2385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 239ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 2405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); 2435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonEmitState( rmesa ); 2455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 2475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s cmd_used/4: %d\n", __FUNCTION__, 2485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->store.cmd_used/4); 2495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2506f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, VBUF_BUFSZ, 2516f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt __FUNCTION__ ); 2525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 2536f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt cmd[0].i = 0; 2545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; 2555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM | (3 << 16); 2565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = rmesa->ioctl.vertex_offset; 2575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3].i = vertex_nr; 2585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[4].i = vertex_format; 2595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[5].i = (primitive | 2605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_PRIM_WALK_LIST | 2615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 2625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | 2635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); 2645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_PRIMS) 2665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: header 0x%x offt 0x%x vfmt 0x%x vfcntl %x \n", 2675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, 2685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i, cmd[2].i, cmd[4].i, cmd[5].i); 2695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 2705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 2715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; 2725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = RADEON_CP_PACKET3_3D_DRAW_VBUF | (1 << 16); 2735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = vertex_format; 2745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3].i = (primitive | 2755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_PRIM_WALK_LIST | 2765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 2775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_MAOS_ENABLE | 2785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | 2795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (vertex_nr << RADEON_CP_VC_CNTL_NUM_SHIFT)); 2805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_PRIMS) 2835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: header 0x%x vfmt 0x%x vfcntl %x \n", 2845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, 2855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i, cmd[2].i, cmd[3].i); 2865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 2875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 2885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonFlushElts( radeonContextPtr rmesa ) 2915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 2925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int *cmd = (int *)(rmesa->store.cmd_buf + rmesa->store.elts_start); 2935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int dwords; 2945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 2955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 24)) / 2; 2965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 2975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int nr = (rmesa->store.cmd_used - (rmesa->store.elts_start + 16)) / 2; 2985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 2995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 3015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 3025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( rmesa->dma.flush == radeonFlushElts ); 3042c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul rmesa->dma.flush = NULL; 3055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Cope with odd number of elts: 3075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2; 3095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4; 3105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 3125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1] |= (dwords - 3) << 16; 3135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[5] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; 3145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 3155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1] |= (dwords - 3) << 16; 3165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3] |= nr << RADEON_CP_VC_CNTL_NUM_SHIFT; 3175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 318150ed2e43d5541556d282cae728cebeec692e07aDave Airlie 319150ed2e43d5541556d282cae728cebeec692e07aDave Airlie if (RADEON_DEBUG & DEBUG_SYNC) { 320150ed2e43d5541556d282cae728cebeec692e07aDave Airlie fprintf(stderr, "%s: Syncing\n", __FUNCTION__); 321150ed2e43d5541556d282cae728cebeec692e07aDave Airlie radeonFinish( rmesa->glCtx ); 322150ed2e43d5541556d282cae728cebeec692e07aDave Airlie } 3235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 3245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulGLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa, 3275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_format, 3285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint primitive, 3295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint min_nr ) 3305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 331ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 3325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLushort *retval; 3335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 3355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s %d\n", __FUNCTION__, min_nr); 3365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert((primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND)); 3385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonEmitState( rmesa ); 3405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3416f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 3426f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt ELTS_BUFSZ(min_nr), 3436f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt __FUNCTION__ ); 3445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 3455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 3465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; 3475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM; 3485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = rmesa->ioctl.vertex_offset; 3495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3].i = 0xffff; 3505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[4].i = vertex_format; 3515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[5].i = (primitive | 3525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_PRIM_WALK_IND | 3535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 3545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); 3555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul retval = (GLushort *)(cmd+6); 3575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 3585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 3595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP; 3605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = RADEON_CP_PACKET3_3D_DRAW_INDX; 3615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = vertex_format; 3625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3].i = (primitive | 3635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_PRIM_WALK_IND | 3645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA | 3655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_MAOS_ENABLE | 3665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE); 3675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul retval = (GLushort *)(cmd+4); 3695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 3705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_PRIMS) 3725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: header 0x%x vfmt 0x%x prim %x \n", 3735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, 3745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i, vertex_format, primitive); 3755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(!rmesa->dma.flush); 3775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; 3785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.flush = radeonFlushElts; 3795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->store.elts_start = ((char *)cmd) - rmesa->store.cmd_buf; 3815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return retval; 3835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 3845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonEmitVertexAOS( radeonContextPtr rmesa, 3885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint vertex_size, 3895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint offset ) 3905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 3915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 3925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->ioctl.vertex_size = vertex_size; 3935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->ioctl.vertex_offset = offset; 3945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 395ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 3965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL)) 3985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n", 3995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, vertex_size, offset); 4005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4016f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, VERT_AOS_BUFSZ, 4025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__ ); 4035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 4055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3; 4065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = RADEON_CP_PACKET3_3D_LOAD_VBPNTR | (2 << 16); 4075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = 1; 4085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3].i = vertex_size | (vertex_size << 8); 4095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[4].i = offset; 4105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 4115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 4125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonEmitAOS( radeonContextPtr rmesa, 4155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region **component, 4165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint nr, 4175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint offset ) 4185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 4195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#if RADEON_OLD_PACKETS 4205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( nr == 1 ); 4215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( component[0]->aos_size == component[0]->aos_stride ); 4225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->ioctl.vertex_size = component[0]->aos_size; 4235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->ioctl.vertex_offset = 4245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (component[0]->aos_start + offset * component[0]->aos_stride * 4); 4255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#else 426ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 4275562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt int sz = AOS_BUFSZ(nr); 4285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int i; 4295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int *tmp; 4305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 4325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 4335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4356f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sz, 4365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__ ); 4375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 4385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3; 4396f3cc6a5226fd4b5d44cca91e2f76216ecaff831Eric Anholt cmd[1].i = RADEON_CP_PACKET3_3D_LOAD_VBPNTR | (((sz / sizeof(int))-3) << 16); 4405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = nr; 4415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul tmp = &cmd[0].i; 4425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd += 3; 4435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < nr ; i++) { 4455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (i & 1) { 4465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i |= ((component[i]->aos_stride << 24) | 4475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (component[i]->aos_size << 16)); 4485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = (component[i]->aos_start + 4495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul offset * component[i]->aos_stride * 4); 4505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd += 3; 4515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else { 4535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = ((component[i]->aos_stride << 8) | 4545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (component[i]->aos_size << 0)); 4555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = (component[i]->aos_start + 4565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul offset * component[i]->aos_stride * 4); 4575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_VERTS) { 4615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s:\n", __FUNCTION__); 4625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < sz ; i++) 4635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, " %d: %x\n", i, tmp[i]); 4645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#endif 4665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 4675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* using already shifted color_fmt! */ 4695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is required? */ 4705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint color_fmt, 4715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint src_pitch, 4725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint src_offset, 4735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint dst_pitch, 4745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint dst_offset, 4755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint srcx, GLint srcy, 4765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint dstx, GLint dsty, 4775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint w, GLuint h ) 4785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 479ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 4805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 4825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n", 4835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, 4845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul src_pitch, src_offset, srcx, srcy, 4855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dst_pitch, dst_offset, dstx, dsty, 4865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul w, h); 4875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( (src_pitch & 63) == 0 ); 4895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( (dst_pitch & 63) == 0 ); 4905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( (src_offset & 1023) == 0 ); 4915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( (dst_offset & 1023) == 0 ); 4925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( w < (1<<16) ); 4935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( h < (1<<16) ); 4945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 495ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int), 4965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__ ); 4975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 5005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].header.cmd_type = RADEON_CMD_PACKET3; 5015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[1].i = RADEON_CP_PACKET3_CNTL_BITBLT_MULTI | (5 << 16); 5025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[2].i = (RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 5035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_GMC_DST_PITCH_OFFSET_CNTL | 5045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_GMC_BRUSH_NONE | 5055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul color_fmt | 5065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_GMC_SRC_DATATYPE_COLOR | 5075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_ROP3_S | 5085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_DP_SRC_SOURCE_MEMORY | 5095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_GMC_CLR_CMP_CNTL_DIS | 5105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_GMC_WR_MSK_DIS ); 5115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[3].i = ((src_pitch/64)<<22) | (src_offset >> 10); 5135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[4].i = ((dst_pitch/64)<<22) | (dst_offset >> 10); 5145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[5].i = (srcx << 16) | srcy; 5155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[6].i = (dstx << 16) | dsty; /* dst */ 5165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[7].i = (w << 16) | h; 5175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 5185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonEmitWait( radeonContextPtr rmesa, GLuint flags ) 5215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 5225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dri.drmMinor >= 6) { 523ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 5245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) ); 5265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 527ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int), 5285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__ ); 5295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].i = 0; 5305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].wait.cmd_type = RADEON_CMD_WAIT; 5315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd[0].wait.flags = flags; 5325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 5345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int radeonFlushCmdBufLocked( radeonContextPtr rmesa, 5375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const char * caller ) 5385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 5395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret, i; 540ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_buffer_t cmd; 5415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5425562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt if (rmesa->lost_context) 5435562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt radeonBackUpAndEmitLostStateLocked(rmesa); 5445562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt 5455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) { 5465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); 5475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_VERBOSE) 5495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for (i = 0 ; i < rmesa->store.cmd_used ; i += 4 ) 5505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%d: %x\n", i/4, 5515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul *(int *)(&rmesa->store.cmd_buf[i])); 5525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_DMA) 5555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: Releasing %d buffers\n", __FUNCTION__, 5565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.nr_released_bufs); 5575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_SANITY) { 5605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->state.scissor.enabled) 5615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = radeonSanityCmdBuffer( rmesa, 5625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->state.scissor.numClipRects, 5635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->state.scissor.pClipRects); 5645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else 5655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = radeonSanityCmdBuffer( rmesa, 5665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->numClipRects, 5675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->pClipRects); 5685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (ret) { 5695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "drmSanityCommandWrite: %d\n", ret); 5705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul goto out; 5715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd.bufsz = rmesa->store.cmd_used; 5765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd.buf = rmesa->store.cmd_buf; 5775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->state.scissor.enabled) { 5795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd.nbox = rmesa->state.scissor.numClipRects; 580ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl cmd.boxes = rmesa->state.scissor.pClipRects; 5815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } else { 5825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd.nbox = rmesa->numClipRects; 583ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl cmd.boxes = rmesa->pClipRects; 5845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 5855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandWrite( rmesa->dri.fd, 5875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul DRM_RADEON_CMDBUF, 5885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &cmd, sizeof(cmd) ); 5895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 5905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (ret) 5915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "drmCommandWrite: %d\n", ret); 5925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 593150ed2e43d5541556d282cae728cebeec692e07aDave Airlie if (RADEON_DEBUG & DEBUG_SYNC) { 594150ed2e43d5541556d282cae728cebeec692e07aDave Airlie fprintf(stderr, "\nSyncing in %s\n\n", __FUNCTION__); 595150ed2e43d5541556d282cae728cebeec692e07aDave Airlie radeonWaitForIdleLocked( rmesa ); 596150ed2e43d5541556d282cae728cebeec692e07aDave Airlie } 597150ed2e43d5541556d282cae728cebeec692e07aDave Airlie 5985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul out: 5995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->store.primnr = 0; 6005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->store.statenr = 0; 6015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->store.cmd_used = 0; 6025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.nr_released_bufs = 0; 6037a086dc05e665a78f7e9d069aa4fc70e844b8988Eric Anholt rmesa->save_on_next_emit = 1; 604626f825bcc91a3068e2e1c68e7467b42826c51eaEric Anholt 6055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return ret; 6065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 6075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Note: does not emit any commands to avoid recursion on 6105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * radeonAllocCmdBuf. 6115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 6125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller ) 6135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 6145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 6155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 6185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = radeonFlushCmdBufLocked( rmesa, caller ); 6205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 6225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (ret) { 624ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret); 6255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit(ret); 6265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 6285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ============================================================= 6305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Hardware vertex buffer handling 6315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 6325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonRefillCurrentDmaRegion( radeonContextPtr rmesa ) 6355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 6365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_buffer *dmabuf; 6375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int fd = rmesa->dri.fd; 6385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int index = 0; 6395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int size = 0; 6405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmDMAReq dma; 6415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 6425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) 6445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 6455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.flush) { 6475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.flush( rmesa ); 6485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.current.buf) 6515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonReleaseDmaRegion( rmesa, &rmesa->dma.current, __FUNCTION__ ); 6525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.nr_released_bufs > 4) 6545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonFlushCmdBuf( rmesa, __FUNCTION__ ); 6555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.context = rmesa->dri.hwContext; 6575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.send_count = 0; 6585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.send_list = NULL; 6595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.send_sizes = NULL; 6605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.flags = 0; 6615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.request_count = 1; 6625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.request_size = RADEON_BUFFER_SIZE; 6635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.request_list = &index; 6645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.request_sizes = &size; 6655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dma.granted_count = 0; 6665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE(rmesa); /* no need to validate */ 6685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmDMA( fd, &dma ); 6705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (ret != 0) { 6725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Free some up this way? 6735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 6745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.nr_released_bufs) { 6755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); 6765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_DMA) 6795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "Waiting for buffers\n"); 6805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitForIdleLocked( rmesa ); 6825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmDMA( fd, &dma ); 6835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret != 0 ) { 6855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 6865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "Error: Could not get dma buffer... exiting\n" ); 6875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( -1 ); 6885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE(rmesa); 6925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_DMA) 6945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "Allocated buffer %d\n", index); 6955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dmabuf = CALLOC_STRUCT( radeon_dma_buffer ); 6975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dmabuf->buf = &rmesa->radeonScreen->buffers->list[index]; 6985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul dmabuf->refcount = 1; 6995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.buf = dmabuf; 7015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.address = dmabuf->buf->address; 7025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.end = dmabuf->buf->total; 7035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.start = 0; 7045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.ptr = 0; 7055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->c_vertexBuffers++; 7075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 7085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonReleaseDmaRegion( radeonContextPtr rmesa, 7105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region *region, 7115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const char *caller ) 7125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 7135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 7145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s from %s\n", __FUNCTION__, caller); 7155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (!region->buf) 7175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return; 7185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.flush) 7205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.flush( rmesa ); 7215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (--region->buf->refcount == 0) { 723ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_cmd_header_t *cmd; 7245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA)) 7265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__, 7275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->buf->buf->idx); 7285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 729ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd), 7305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__ ); 7315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD; 7325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cmd->dma.buf_idx = region->buf->buf->idx; 7335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE(region->buf); 7345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.nr_released_bufs++; 7355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 7365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7372c28dd892cfb43445d7e54df8b6a8331192f4e99Brian Paul region->buf = NULL; 7385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->start = 0; 7395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 7405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Allocates a region from rmesa->dma.current. If there isn't enough 7425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * space in current, grab a new buffer (and discard what was left of current) 7435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonAllocDmaRegion( radeonContextPtr rmesa, 7455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region *region, 7465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int bytes, 7475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int alignment ) 7485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 7495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 7505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s %d\n", __FUNCTION__, bytes); 7515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.flush) 7535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.flush( rmesa ); 7545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (region->buf) 7565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonReleaseDmaRegion( rmesa, region, __FUNCTION__ ); 7575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul alignment--; 7595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.start = rmesa->dma.current.ptr = 7605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (rmesa->dma.current.ptr + alignment) & ~alignment; 7615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end ) 7635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonRefillCurrentDmaRegion( rmesa ); 7645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->start = rmesa->dma.current.start; 7665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->ptr = rmesa->dma.current.start; 7675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->end = rmesa->dma.current.start + bytes; 7685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->address = rmesa->dma.current.address; 7695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->buf = rmesa->dma.current.buf; 7705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul region->buf->refcount++; 7715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.ptr += bytes; /* bug - if alignment > 7 */ 7735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.start = 7745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.current.ptr = (rmesa->dma.current.ptr + 0x7) & ~0x7; 7755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 7765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonAllocDmaRegionVerts( radeonContextPtr rmesa, 7785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul struct radeon_dma_region *region, 7795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int numverts, 7805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int vertsize, 7815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int alignment ) 7825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 7835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonAllocDmaRegion( rmesa, region, vertsize * numverts, alignment ); 7845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 7855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ================================================================ 7875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * SwapBuffers with client-side throttling 7885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 79038b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihanestatic u_int32_t radeonGetLastFrame (radeonContextPtr rmesa) 7915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 7925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map; 7935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 79438b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane u_int32_t frame; 7955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dri.screen->drmMinor >= 4) { 797ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_getparam_t gp; 7985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul gp.param = RADEON_PARAM_LAST_FRAME; 800bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl gp.value = (int *)&frame; 8015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_GETPARAM, 8025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &gp, sizeof(gp) ); 8035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else 8055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = -EINVAL; 8065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret == -EINVAL ) { 8085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul frame = INREG( RADEON_LAST_FRAME_REG ); 8095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = 0; 8105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 812ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret ); 8135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit(1); 8145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return frame; 8175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void radeonEmitIrqLocked( radeonContextPtr rmesa ) 8205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 821ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_irq_emit_t ie; 8225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 8235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ie.irq_seq = &rmesa->iw.irq_seq; 8255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT, 8265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &ie, sizeof(ie) ); 8275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 828ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret ); 8295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit(1); 8305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void radeonWaitIrq( radeonContextPtr rmesa ) 8355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 8365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 8375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul do { 8395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_IRQ_WAIT, 8405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &rmesa->iw, sizeof(rmesa->iw) ); 8415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } while (ret && (errno == EINTR || errno == EAGAIN)); 8425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 8445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "%s: drmRadeonIrqWait: %d\n", __FUNCTION__, ret ); 8455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit(1); 8465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void radeonWaitForFrameCompletion( radeonContextPtr rmesa ) 8515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 852ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_sarea_t *sarea = rmesa->sarea; 8535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->do_irqs) { 8555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (radeonGetLastFrame(rmesa) < sarea->last_frame) { 8565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (!rmesa->irqsEmitted) { 8575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul while (radeonGetLastFrame (rmesa) < sarea->last_frame) 8585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ; 8595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else { 8615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 8625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitIrq( rmesa ); 8635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 8645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->irqsEmitted = 10; 8665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->irqsEmitted) { 8695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonEmitIrqLocked( rmesa ); 8705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->irqsEmitted--; 8715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else { 8745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul while (radeonGetLastFrame (rmesa) < sarea->last_frame) { 8755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 8765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->do_usleeps) 8775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul DO_USLEEP( 1 ); 8785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 8795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Copy the back color buffer to the front color buffer. 8845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonCopyBuffer( const __DRIdrawablePrivate *dPriv ) 8865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 8875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa; 8885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint nbox, i, ret; 8895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean missed_target; 890ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl int64_t ust; 8915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(dPriv); 8935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(dPriv->driContextPriv); 8945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(dPriv->driContextPriv->driverPrivate); 8955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; 8975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( RADEON_DEBUG & DEBUG_IOCTL ) { 899894844a8d956a0ee5f95836331dc318f49fdb845Brian Paul fprintf( stderr, "\n%s( %p )\n\n", __FUNCTION__, (void *) rmesa->glCtx ); 9005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FIREVERTICES( rmesa ); 9035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 9045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Throttle the frame rate -- only allow one pending swap buffers 9065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * request at a time. 9075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 9085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitForFrameCompletion( rmesa ); 9095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 9105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul driWaitForVBlank( dPriv, & rmesa->vbl_seq, rmesa->vblank_flags, & missed_target ); 9115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 9125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul nbox = dPriv->numClipRects; /* must be in locked region */ 9145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( i = 0 ; i < nbox ; ) { 9165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox ); 917ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *box = dPriv->pClipRects; 918ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *b = rmesa->sarea->boxes; 9195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint n = 0; 9205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( ; i < nr ; i++ ) { 9225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul *b++ = box[i]; 9235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul n++; 9245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->sarea->nbox = n; 9265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP ); 9285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 9305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "DRM_RADEON_SWAP_BUFFERS: return = %d\n", ret ); 9315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 9325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( 1 ); 9335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 9375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->swap_count++; 9385f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick (*dri_interface->getUST)( & ust ); 9395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( missed_target ) { 9405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->swap_missed_count++; 9415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->swap_missed_ust = ust - rmesa->swap_ust; 9425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->swap_ust = ust; 9455562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->hw.all_dirty = GL_TRUE; 9465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 9475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonPageFlip( const __DRIdrawablePrivate *dPriv ) 9495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 9505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa; 9515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint ret; 9525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean missed_target; 9535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(dPriv); 9555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(dPriv->driContextPriv); 9565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul assert(dPriv->driContextPriv->driverPrivate); 9575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa = (radeonContextPtr) dPriv->driContextPriv->driverPrivate; 9595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( RADEON_DEBUG & DEBUG_IOCTL ) { 9615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: pfCurrentPage: %d\n", __FUNCTION__, 9625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->sarea->pfCurrentPage); 9635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEON_FIREVERTICES( rmesa ); 9665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 9675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Need to do this for the perf box placement: 9695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 9705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (dPriv->numClipRects) 9715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul { 972ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *box = dPriv->pClipRects; 973ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *b = rmesa->sarea->boxes; 9745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b[0] = box[0]; 9755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->sarea->nbox = 1; 9765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Throttle the frame rate -- only allow a few pending swap buffers 9795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * request at a time. 9805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 9815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitForFrameCompletion( rmesa ); 9825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 9835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul driWaitForVBlank( dPriv, & rmesa->vbl_seq, rmesa->vblank_flags, & missed_target ); 9845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( missed_target ) { 9855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->swap_missed_count++; 9865f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick (void) (*dri_interface->getUST)( & rmesa->swap_missed_ust ); 9875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 9895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_FLIP ); 9915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 9935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 9955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "DRM_RADEON_FLIP: return = %d\n", ret ); 9965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( 1 ); 9975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->swap_count++; 10005f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick (void) (*dri_interface->getUST)( & rmesa->swap_ust ); 10015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1002982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul radeonUpdateDrawBuffer(rmesa->glCtx); 10035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 10045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* ================================================================ 10075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Buffer clear 10085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 10095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#define RADEON_MAX_CLEARS 256 10105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all, 10125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint cx, GLint cy, GLint cw, GLint ch ) 10135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 10145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 10155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIdrawablePrivate *dPriv = rmesa->dri.drawable; 1016ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_sarea_t *sarea = rmesa->sarea; 10175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map; 101838b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane u_int32_t clear; 10195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint flags = 0; 10205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLuint color_mask = 0; 10215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint ret, i; 10225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( RADEON_DEBUG & DEBUG_IOCTL ) { 10245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "%s: all=%d cx=%d cy=%d cw=%d ch=%d\n", 10255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__, all, cx, cy, cw, ch ); 10265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1028ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger { 1029ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger LOCK_HARDWARE( rmesa ); 1030ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger UNLOCK_HARDWARE( rmesa ); 1031ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger if ( dPriv->numClipRects == 0 ) 1032ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger return; 1033ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger } 1034ce055c26f08556a46ee8b4b88e5fd15eb4d2acd1Roland Scheidegger 10358e3926575264d31b3caacb9cbb606f8f2914f57dRoland Scheidegger radeonFlush( ctx ); 10365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1037e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if ( mask & BUFFER_BIT_FRONT_LEFT ) { 10385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul flags |= RADEON_FRONT; 10395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; 1040e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul mask &= ~BUFFER_BIT_FRONT_LEFT; 10415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1043e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if ( mask & BUFFER_BIT_BACK_LEFT ) { 10445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul flags |= RADEON_BACK; 10455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; 1046e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul mask &= ~BUFFER_BIT_BACK_LEFT; 10475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1049e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if ( mask & BUFFER_BIT_DEPTH ) { 1050b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger flags |= RADEON_DEPTH; 1051e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul mask &= ~BUFFER_BIT_DEPTH; 10525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1054e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if ( (mask & BUFFER_BIT_STENCIL) && rmesa->state.stencil.hwBuffer ) { 10555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul flags |= RADEON_STENCIL; 1056e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul mask &= ~BUFFER_BIT_STENCIL; 10575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( mask ) { 10605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_FALLBACKS) 10615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask); 10625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul _swrast_Clear( ctx, mask, all, cx, cy, cw, ch ); 10635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !flags ) 10665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return; 10675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1068b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger if (rmesa->using_hyperz) { 1069b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger flags |= RADEON_USE_COMP_ZBUF; 1070b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger/* if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) 1071b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger flags |= RADEON_USE_HIERZ; */ 1072b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger if (!(rmesa->state.stencil.hwBuffer) || 1073b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger ((flags & RADEON_DEPTH) && (flags & RADEON_STENCIL) && 1074b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger ((rmesa->state.stencil.clear & RADEON_STENCIL_WRITE_MASK) == RADEON_STENCIL_WRITE_MASK))) { 1075b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger flags |= RADEON_CLEAR_FASTZ; 1076b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger } 1077b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger } 10785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Flip top to bottom */ 10805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cx += dPriv->x; 10815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul cy = dPriv->y + dPriv->h - cy - ch; 10825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 10845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Throttle the number of clear ioctls we do. 10865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 10875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul while ( 1 ) { 10885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 10895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dri.screen->drmMinor >= 4) { 1091ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_getparam_t gp; 10925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul gp.param = RADEON_PARAM_LAST_CLEAR; 1094bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl gp.value = (int *)&clear; 10955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandWriteRead( rmesa->dri.fd, 10965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul DRM_RADEON_GETPARAM, &gp, sizeof(gp) ); 10975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } else 10985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = -EINVAL; 10995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret == -EINVAL ) { 11015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear = INREG( RADEON_LAST_CLEAR_REG ); 11025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = 0; 11035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 1105ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret ); 11065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit(1); 11075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( RADEON_DEBUG & DEBUG_IOCTL ) { 11095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "%s( %d )\n", __FUNCTION__, (int)clear ); 11105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) fprintf( stderr, " ( RADEON_LAST_CLEAR register read directly )\n" ); 11115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( sarea->last_clear - clear <= RADEON_MAX_CLEARS ) { 11145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 11155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( rmesa->do_usleeps ) { 11185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 11195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul DO_USLEEP( 1 ); 11205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 11215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1124626f825bcc91a3068e2e1c68e7467b42826c51eaEric Anholt /* Send current state to the hardware */ 1125626f825bcc91a3068e2e1c68e7467b42826c51eaEric Anholt radeonFlushCmdBufLocked( rmesa, __FUNCTION__ ); 1126626f825bcc91a3068e2e1c68e7467b42826c51eaEric Anholt 11275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( i = 0 ; i < dPriv->numClipRects ; ) { 11285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects ); 1129ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *box = dPriv->pClipRects; 1130ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_clip_rect_t *b = rmesa->sarea->boxes; 1131ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_clear_t clear; 1132ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; 11335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint n = 0; 11345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !all ) { 11365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( ; i < nr ; i++ ) { 11375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint x = box[i].x1; 11385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint y = box[i].y1; 11395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint w = box[i].x2 - x; 11405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLint h = box[i].y2 - y; 11415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( x < cx ) w -= cx - x, x = cx; 11435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( y < cy ) h -= cy - y, y = cy; 11445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( x + w > cx + cw ) w = cx + cw - x; 11455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( y + h > cy + ch ) h = cy + ch - y; 11465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( w <= 0 ) continue; 11475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( h <= 0 ) continue; 11485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b->x1 = x; 11505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b->y1 = y; 11515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b->x2 = x + w; 11525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b->y2 = y + h; 11535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b++; 11545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul n++; 11555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } else { 11575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( ; i < nr ; i++ ) { 11585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul *b++ = box[i]; 11595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul n++; 11605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->sarea->nbox = n; 11645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear.flags = flags; 11665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear.clear_color = rmesa->state.color.clear; 11675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear.clear_depth = rmesa->state.depth.clear; 11685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK]; 11695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear.depth_mask = rmesa->state.stencil.clear; 11705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul clear.depth_boxes = depth_boxes; 11715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul n--; 11735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul b = rmesa->sarea->boxes; 11745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul for ( ; n >= 0 ; n-- ) { 1175ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1; 1176ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1; 1177ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2; 1178ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2; 1179ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl depth_boxes[n].f[CLEAR_DEPTH] = 11805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul (float)rmesa->state.depth.clear; 11815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR, 1184ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl &clear, sizeof(drm_radeon_clear_t)); 11855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret ) { 11875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 11885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "DRM_RADEON_CLEAR: return = %d\n", ret ); 11895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( 1 ); 11905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 11925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 11945562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt rmesa->hw.all_dirty = GL_TRUE; 11955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 11965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 11985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonWaitForIdleLocked( radeonContextPtr rmesa ) 11995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 12005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int fd = rmesa->dri.fd; 12015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int to = 0; 12025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret, i = 0; 12035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->c_drawWaits++; 12055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul do { 12075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul do { 12085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ret = drmCommandNone( fd, DRM_RADEON_CP_IDLE); 12095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } while ( ret && errno == EBUSY && i++ < RADEON_IDLE_RETRY ); 12105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } while ( ( ret == -EBUSY ) && ( to++ < RADEON_TIMEOUT ) ); 12115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( ret < 0 ) { 12135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 12145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf( stderr, "Error: Radeon timed out... exiting\n" ); 12155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul exit( -1 ); 12165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 12175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 12185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void radeonWaitForIdle( radeonContextPtr rmesa ) 12215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 12225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE(rmesa); 12235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitForIdleLocked( rmesa ); 12245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE(rmesa); 12255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 12265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonFlush( GLcontext *ctx ) 12295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 12305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa = RADEON_CONTEXT( ctx ); 12315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (RADEON_DEBUG & DEBUG_IOCTL) 12335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul fprintf(stderr, "%s\n", __FUNCTION__); 12345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->dma.flush) 12365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul rmesa->dma.flush( rmesa ); 12375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12385562fe653cf88454bbf2c50f77a8b56b0dafe01bEric Anholt radeonEmitState( rmesa ); 12395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1240bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl if (rmesa->store.cmd_used) 1241bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl radeonFlushCmdBuf( rmesa, __FUNCTION__ ); 12425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 12435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Make sure all commands have been sent to the hardware and have 12455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * completed processing. 12465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 12475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonFinish( GLcontext *ctx ) 12485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 12495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa = RADEON_CONTEXT(ctx); 12505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonFlush( ctx ); 12515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (rmesa->do_irqs) { 12535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul LOCK_HARDWARE( rmesa ); 12545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonEmitIrqLocked( rmesa ); 12555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul UNLOCK_HARDWARE( rmesa ); 12565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitIrq( rmesa ); 12575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 12585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else 12595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonWaitForIdle( rmesa ); 12605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 12615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 12635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulvoid radeonInitIoctlFuncs( GLcontext *ctx ) 12645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 12655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Clear = radeonClear; 12665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Finish = radeonFinish; 12675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ctx->Driver.Flush = radeonFlush; 12685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 12695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1270