radeon_screen.c revision 1bad691a177240e8281592fa66c9e6ab0869f618
1600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang/************************************************************************** 2600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 3600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang VA Linux Systems Inc., Fremont, California. 5600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 6600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangAll Rights Reserved. 7600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 8600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangPermission is hereby granted, free of charge, to any person obtaining 9600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wanga copy of this software and associated documentation files (the 10600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang"Software"), to deal in the Software without restriction, including 11600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangwithout limitation the rights to use, copy, modify, merge, publish, 12600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangdistribute, sublicense, and/or sell copies of the Software, and to 13600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangpermit persons to whom the Software is furnished to do so, subject to 14600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangthe following conditions: 15600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 16600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangThe above copyright notice and this permission notice (including the 17600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangnext paragraph) shall be included in all copies or substantial 18600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangportions of the Software. 19600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 20600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 28600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang**************************************************************************/ 29600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 30600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang/** 31600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang * \file radeon_screen.c 32600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang * Screen initialization functions for the Radeon driver. 33600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang * 34600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang * \author Kevin E. Martin <martin@valinux.com> 35600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang * \author Gareth Hughes <gareth@valinux.com> 36600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang */ 37600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 38600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include <errno.h> 39600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "main/glheader.h" 40600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "main/imports.h" 41600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "main/mtypes.h" 42600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "main/framebuffer.h" 43600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "main/renderbuffer.h" 44600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 45600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#define STANDALONE_MMIO 46600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_chipset.h" 47600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_macros.h" 48600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_screen.h" 49600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_common.h" 50600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_span.h" 51600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#if !RADEON_COMMON 52600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_context.h" 53600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_tex.h" 54600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r200_context.h" 56600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r200_ioctl.h" 57600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r200_tex.h" 58600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r300_context.h" 60600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r300_fragprog.h" 61600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r300_tex.h" 62600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 63600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r600_context.h" 64600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r700_driconf.h" /* +r6/r7 */ 65600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "r600_tex.h" /* +r6/r7 */ 66600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#endif 67600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 68600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "utils.h" 69600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "vblank.h" 70600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "drirenderbuffer.h" 71600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 72600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "radeon_bocs_wrapper.h" 73600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 74600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "GL/internal/dri_interface.h" 75600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 76600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang/* Radeon configuration 77600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang */ 78600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#include "xmlpool.h" 79600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 80600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 81600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangDRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 82600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 83600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 84600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangDRI_CONF_OPT_END 85600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 86600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#if !RADEON_COMMON /* R100 */ 87600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangPUBLIC const char __driConfigOptions[] = 88600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangDRI_CONF_BEGIN 89600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_PERFORMANCE 90600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 91600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 92600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 93600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 94600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_HYPERZ(false) 95600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 96600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 97600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_QUALITY 98600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 99600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 100600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_NO_NEG_LOD_BIAS(false) 101600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_FORCE_S3TC_ENABLE(false) 102600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 103600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 104600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 105600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_ALLOW_LARGE_TEXTURES(2) 106600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 107600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_DEBUG 108600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_NO_RAST(false) 109600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 110600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangDRI_CONF_END; 111600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangstatic const GLuint __driNConfigOptions = 15; 112600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 113600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 114600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 115600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangPUBLIC const char __driConfigOptions[] = 116600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangDRI_CONF_BEGIN 117600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_PERFORMANCE 118600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 119600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 120600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 121600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 122600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_HYPERZ(false) 123600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 124600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 125600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_QUALITY 126600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 127600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 128600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_NO_NEG_LOD_BIAS(false) 129600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_FORCE_S3TC_ENABLE(false) 130600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 131600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 132600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 133600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_ALLOW_LARGE_TEXTURES(2) 134600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 135600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 136600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_DEBUG 137600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_NO_RAST(false) 138600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 139600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_SOFTWARE 140600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_NV_VERTEX_PROGRAM(false) 141600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang DRI_CONF_SECTION_END 142600c7a4bbc7348167293eac928192e695b4ad5baChung-yih WangDRI_CONF_END; 143600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangstatic const GLuint __driNConfigOptions = 17; 144600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wang 145600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangextern const struct dri_extension blend_extensions[]; 146600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangextern const struct dri_extension ARB_vp_extension[]; 147600c7a4bbc7348167293eac928192e695b4ad5baChung-yih Wangextern const struct dri_extension NV_vp_extension[]; 148extern const struct dri_extension ATI_fs_extension[]; 149extern const struct dri_extension point_extensions[]; 150 151#elif RADEON_COMMON && (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 152 153/* TODO: integrate these into xmlpool.h! */ 154#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 155DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 156 DRI_CONF_DESC(en,"Number of texture image units") \ 157 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 158DRI_CONF_OPT_END 159 160#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 161DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 162 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 163 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 164DRI_CONF_OPT_END 165 166 167 168#define DRI_CONF_DISABLE_S3TC(def) \ 169DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 170 DRI_CONF_DESC(en,"Disable S3TC compression") \ 171DRI_CONF_OPT_END 172 173#define DRI_CONF_DISABLE_FALLBACK(def) \ 174DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 175 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 176DRI_CONF_OPT_END 177 178#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 179DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 180 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 181DRI_CONF_OPT_END 182 183#define DRI_CONF_FP_OPTIMIZATION(def) \ 184DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 185 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 186 DRI_CONF_ENUM(0,"Optimize for Speed") \ 187 DRI_CONF_ENUM(1,"Optimize for Quality") \ 188 DRI_CONF_DESC_END \ 189DRI_CONF_OPT_END 190 191PUBLIC const char __driConfigOptions[] = 192DRI_CONF_BEGIN 193 DRI_CONF_SECTION_PERFORMANCE 194 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 195 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 196 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 197 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 198 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 199 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 200 DRI_CONF_DISABLE_FALLBACK(true) 201 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 202 DRI_CONF_SECTION_END 203 DRI_CONF_SECTION_QUALITY 204 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 205 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 206 DRI_CONF_FORCE_S3TC_ENABLE(false) 207 DRI_CONF_DISABLE_S3TC(false) 208 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 209 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 210 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 211 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 212 DRI_CONF_SECTION_END 213 DRI_CONF_SECTION_DEBUG 214 DRI_CONF_NO_RAST(false) 215 DRI_CONF_SECTION_END 216DRI_CONF_END; 217static const GLuint __driNConfigOptions = 17; 218 219extern const struct dri_extension gl_20_extension[]; 220 221#ifndef RADEON_DEBUG 222 223static const struct dri_debug_control debug_control[] = { 224 {"fall", DEBUG_FALLBACKS}, 225 {"tex", DEBUG_TEXTURE}, 226 {"ioctl", DEBUG_IOCTL}, 227 {"prim", DEBUG_PRIMS}, 228 {"vert", DEBUG_VERTS}, 229 {"state", DEBUG_STATE}, 230 {"code", DEBUG_CODEGEN}, 231 {"vfmt", DEBUG_VFMT}, 232 {"vtxf", DEBUG_VFMT}, 233 {"verb", DEBUG_VERBOSE}, 234 {"dri", DEBUG_DRI}, 235 {"dma", DEBUG_DMA}, 236 {"san", DEBUG_SANITY}, 237 {"sync", DEBUG_SYNC}, 238 {"pix", DEBUG_PIXEL}, 239 {"mem", DEBUG_MEMORY}, 240 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 241 {NULL, 0} 242}; 243#endif /* RADEON_DEBUG */ 244 245#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 246 247extern const struct dri_extension card_extensions[]; 248extern const struct dri_extension mm_extensions[]; 249 250static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 251 252static int 253radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) 254{ 255 int ret; 256 drm_radeon_getparam_t gp = { 0 }; 257 struct drm_radeon_info info = { 0 }; 258 259 if (sPriv->drm_version.major >= 2) { 260 info.value = (uint64_t)value; 261 switch (param) { 262 case RADEON_PARAM_DEVICE_ID: 263 info.request = RADEON_INFO_DEVICE_ID; 264 break; 265 case RADEON_PARAM_NUM_GB_PIPES: 266 info.request = RADEON_INFO_NUM_GB_PIPES; 267 break; 268 default: 269 return -EINVAL; 270 } 271 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 272 } else { 273 gp.param = param; 274 gp.value = value; 275 276 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 277 } 278 return ret; 279} 280 281static const __DRIconfig ** 282radeonFillInModes( __DRIscreenPrivate *psp, 283 unsigned pixel_bits, unsigned depth_bits, 284 unsigned stencil_bits, GLboolean have_back_buffer ) 285{ 286 __DRIconfig **configs; 287 __GLcontextModes *m; 288 unsigned depth_buffer_factor; 289 unsigned back_buffer_factor; 290 int i; 291 292 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 293 * enough to add support. Basically, if a context is created with an 294 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 295 * will never be used. 296 */ 297 static const GLenum back_buffer_modes[] = { 298 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 299 }; 300 301 uint8_t depth_bits_array[2]; 302 uint8_t stencil_bits_array[2]; 303 uint8_t msaa_samples_array[1]; 304 305 depth_bits_array[0] = depth_bits; 306 depth_bits_array[1] = depth_bits; 307 308 /* Just like with the accumulation buffer, always provide some modes 309 * with a stencil buffer. It will be a sw fallback, but some apps won't 310 * care about that. 311 */ 312 stencil_bits_array[0] = 0; 313 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 314 315 msaa_samples_array[0] = 0; 316 317 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 318 back_buffer_factor = (have_back_buffer) ? 2 : 1; 319 320 if (pixel_bits == 16) { 321 __DRIconfig **configs_a8r8g8b8; 322 __DRIconfig **configs_r5g6b5; 323 324 configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5, 325 depth_bits_array, stencil_bits_array, 326 depth_buffer_factor, back_buffer_modes, 327 back_buffer_factor, msaa_samples_array, 328 1); 329 configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 330 depth_bits_array, stencil_bits_array, 331 1, back_buffer_modes, 1, 332 msaa_samples_array, 1); 333 configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8); 334 } else 335 configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV, 336 depth_bits_array, stencil_bits_array, 337 depth_buffer_factor, 338 back_buffer_modes, back_buffer_factor, 339 msaa_samples_array, 1); 340 341 if (configs == NULL) { 342 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 343 __func__, __LINE__ ); 344 return NULL; 345 } 346 347 /* Mark the visual as slow if there are "fake" stencil bits. 348 */ 349 for (i = 0; configs[i]; i++) { 350 m = &configs[i]->modes; 351 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 352 m->visualRating = GLX_SLOW_CONFIG; 353 } 354 } 355 356 return (const __DRIconfig **) configs; 357} 358 359#if !RADEON_COMMON 360static const __DRItexOffsetExtension radeonTexOffsetExtension = { 361 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 362 radeonSetTexOffset, 363}; 364 365static const __DRItexBufferExtension radeonTexBufferExtension = { 366 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 367 radeonSetTexBuffer, 368 radeonSetTexBuffer2, 369}; 370#endif 371 372#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 373static const __DRIallocateExtension r200AllocateExtension = { 374 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 375 r200AllocateMemoryMESA, 376 r200FreeMemoryMESA, 377 r200GetMemoryOffsetMESA 378}; 379 380static const __DRItexOffsetExtension r200texOffsetExtension = { 381 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 382 r200SetTexOffset, 383}; 384 385static const __DRItexBufferExtension r200TexBufferExtension = { 386 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 387 r200SetTexBuffer, 388 r200SetTexBuffer2, 389}; 390#endif 391 392#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 393static const __DRItexOffsetExtension r300texOffsetExtension = { 394 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 395 r300SetTexOffset, 396}; 397 398static const __DRItexBufferExtension r300TexBufferExtension = { 399 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 400 r300SetTexBuffer, 401 r300SetTexBuffer2, 402}; 403#endif 404 405#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 406static const __DRItexOffsetExtension r600texOffsetExtension = { 407 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 408 r600SetTexOffset, /* +r6/r7 */ 409}; 410 411static const __DRItexBufferExtension r600TexBufferExtension = { 412 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 413 r600SetTexBuffer, /* +r6/r7 */ 414 r600SetTexBuffer2, /* +r6/r7 */ 415}; 416#endif 417 418static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 419{ 420 screen->device_id = device_id; 421 screen->chip_flags = 0; 422 switch ( device_id ) { 423 case PCI_CHIP_RADEON_LY: 424 case PCI_CHIP_RADEON_LZ: 425 case PCI_CHIP_RADEON_QY: 426 case PCI_CHIP_RADEON_QZ: 427 case PCI_CHIP_RN50_515E: 428 case PCI_CHIP_RN50_5969: 429 screen->chip_family = CHIP_FAMILY_RV100; 430 break; 431 432 case PCI_CHIP_RS100_4136: 433 case PCI_CHIP_RS100_4336: 434 screen->chip_family = CHIP_FAMILY_RS100; 435 break; 436 437 case PCI_CHIP_RS200_4137: 438 case PCI_CHIP_RS200_4337: 439 case PCI_CHIP_RS250_4237: 440 case PCI_CHIP_RS250_4437: 441 screen->chip_family = CHIP_FAMILY_RS200; 442 break; 443 444 case PCI_CHIP_RADEON_QD: 445 case PCI_CHIP_RADEON_QE: 446 case PCI_CHIP_RADEON_QF: 447 case PCI_CHIP_RADEON_QG: 448 /* all original radeons (7200) presumably have a stencil op bug */ 449 screen->chip_family = CHIP_FAMILY_R100; 450 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 451 break; 452 453 case PCI_CHIP_RV200_QW: 454 case PCI_CHIP_RV200_QX: 455 case PCI_CHIP_RADEON_LW: 456 case PCI_CHIP_RADEON_LX: 457 screen->chip_family = CHIP_FAMILY_RV200; 458 screen->chip_flags = RADEON_CHIPSET_TCL; 459 break; 460 461 case PCI_CHIP_R200_BB: 462 case PCI_CHIP_R200_BC: 463 case PCI_CHIP_R200_QH: 464 case PCI_CHIP_R200_QL: 465 case PCI_CHIP_R200_QM: 466 screen->chip_family = CHIP_FAMILY_R200; 467 screen->chip_flags = RADEON_CHIPSET_TCL; 468 break; 469 470 case PCI_CHIP_RV250_If: 471 case PCI_CHIP_RV250_Ig: 472 case PCI_CHIP_RV250_Ld: 473 case PCI_CHIP_RV250_Lf: 474 case PCI_CHIP_RV250_Lg: 475 screen->chip_family = CHIP_FAMILY_RV250; 476 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 477 break; 478 479 case PCI_CHIP_RV280_5960: 480 case PCI_CHIP_RV280_5961: 481 case PCI_CHIP_RV280_5962: 482 case PCI_CHIP_RV280_5964: 483 case PCI_CHIP_RV280_5965: 484 case PCI_CHIP_RV280_5C61: 485 case PCI_CHIP_RV280_5C63: 486 screen->chip_family = CHIP_FAMILY_RV280; 487 screen->chip_flags = RADEON_CHIPSET_TCL; 488 break; 489 490 case PCI_CHIP_RS300_5834: 491 case PCI_CHIP_RS300_5835: 492 case PCI_CHIP_RS350_7834: 493 case PCI_CHIP_RS350_7835: 494 screen->chip_family = CHIP_FAMILY_RS300; 495 break; 496 497 case PCI_CHIP_R300_AD: 498 case PCI_CHIP_R300_AE: 499 case PCI_CHIP_R300_AF: 500 case PCI_CHIP_R300_AG: 501 case PCI_CHIP_R300_ND: 502 case PCI_CHIP_R300_NE: 503 case PCI_CHIP_R300_NF: 504 case PCI_CHIP_R300_NG: 505 screen->chip_family = CHIP_FAMILY_R300; 506 screen->chip_flags = RADEON_CHIPSET_TCL; 507 break; 508 509 case PCI_CHIP_RV350_AP: 510 case PCI_CHIP_RV350_AQ: 511 case PCI_CHIP_RV350_AR: 512 case PCI_CHIP_RV350_AS: 513 case PCI_CHIP_RV350_AT: 514 case PCI_CHIP_RV350_AV: 515 case PCI_CHIP_RV350_AU: 516 case PCI_CHIP_RV350_NP: 517 case PCI_CHIP_RV350_NQ: 518 case PCI_CHIP_RV350_NR: 519 case PCI_CHIP_RV350_NS: 520 case PCI_CHIP_RV350_NT: 521 case PCI_CHIP_RV350_NV: 522 screen->chip_family = CHIP_FAMILY_RV350; 523 screen->chip_flags = RADEON_CHIPSET_TCL; 524 break; 525 526 case PCI_CHIP_R350_AH: 527 case PCI_CHIP_R350_AI: 528 case PCI_CHIP_R350_AJ: 529 case PCI_CHIP_R350_AK: 530 case PCI_CHIP_R350_NH: 531 case PCI_CHIP_R350_NI: 532 case PCI_CHIP_R360_NJ: 533 case PCI_CHIP_R350_NK: 534 screen->chip_family = CHIP_FAMILY_R350; 535 screen->chip_flags = RADEON_CHIPSET_TCL; 536 break; 537 538 case PCI_CHIP_RV370_5460: 539 case PCI_CHIP_RV370_5462: 540 case PCI_CHIP_RV370_5464: 541 case PCI_CHIP_RV370_5B60: 542 case PCI_CHIP_RV370_5B62: 543 case PCI_CHIP_RV370_5B63: 544 case PCI_CHIP_RV370_5B64: 545 case PCI_CHIP_RV370_5B65: 546 case PCI_CHIP_RV380_3150: 547 case PCI_CHIP_RV380_3152: 548 case PCI_CHIP_RV380_3154: 549 case PCI_CHIP_RV380_3E50: 550 case PCI_CHIP_RV380_3E54: 551 screen->chip_family = CHIP_FAMILY_RV380; 552 screen->chip_flags = RADEON_CHIPSET_TCL; 553 break; 554 555 case PCI_CHIP_R420_JN: 556 case PCI_CHIP_R420_JH: 557 case PCI_CHIP_R420_JI: 558 case PCI_CHIP_R420_JJ: 559 case PCI_CHIP_R420_JK: 560 case PCI_CHIP_R420_JL: 561 case PCI_CHIP_R420_JM: 562 case PCI_CHIP_R420_JO: 563 case PCI_CHIP_R420_JP: 564 case PCI_CHIP_R420_JT: 565 case PCI_CHIP_R481_4B49: 566 case PCI_CHIP_R481_4B4A: 567 case PCI_CHIP_R481_4B4B: 568 case PCI_CHIP_R481_4B4C: 569 case PCI_CHIP_R423_UH: 570 case PCI_CHIP_R423_UI: 571 case PCI_CHIP_R423_UJ: 572 case PCI_CHIP_R423_UK: 573 case PCI_CHIP_R430_554C: 574 case PCI_CHIP_R430_554D: 575 case PCI_CHIP_R430_554E: 576 case PCI_CHIP_R430_554F: 577 case PCI_CHIP_R423_5550: 578 case PCI_CHIP_R423_UQ: 579 case PCI_CHIP_R423_UR: 580 case PCI_CHIP_R423_UT: 581 case PCI_CHIP_R430_5D48: 582 case PCI_CHIP_R430_5D49: 583 case PCI_CHIP_R430_5D4A: 584 case PCI_CHIP_R480_5D4C: 585 case PCI_CHIP_R480_5D4D: 586 case PCI_CHIP_R480_5D4E: 587 case PCI_CHIP_R480_5D4F: 588 case PCI_CHIP_R480_5D50: 589 case PCI_CHIP_R480_5D52: 590 case PCI_CHIP_R423_5D57: 591 screen->chip_family = CHIP_FAMILY_R420; 592 screen->chip_flags = RADEON_CHIPSET_TCL; 593 break; 594 595 case PCI_CHIP_RV410_5E4C: 596 case PCI_CHIP_RV410_5E4F: 597 case PCI_CHIP_RV410_564A: 598 case PCI_CHIP_RV410_564B: 599 case PCI_CHIP_RV410_564F: 600 case PCI_CHIP_RV410_5652: 601 case PCI_CHIP_RV410_5653: 602 case PCI_CHIP_RV410_5657: 603 case PCI_CHIP_RV410_5E48: 604 case PCI_CHIP_RV410_5E4A: 605 case PCI_CHIP_RV410_5E4B: 606 case PCI_CHIP_RV410_5E4D: 607 screen->chip_family = CHIP_FAMILY_RV410; 608 screen->chip_flags = RADEON_CHIPSET_TCL; 609 break; 610 611 case PCI_CHIP_RS480_5954: 612 case PCI_CHIP_RS480_5955: 613 case PCI_CHIP_RS482_5974: 614 case PCI_CHIP_RS482_5975: 615 case PCI_CHIP_RS400_5A41: 616 case PCI_CHIP_RS400_5A42: 617 case PCI_CHIP_RC410_5A61: 618 case PCI_CHIP_RC410_5A62: 619 screen->chip_family = CHIP_FAMILY_RS400; 620 break; 621 622 case PCI_CHIP_RS600_793F: 623 case PCI_CHIP_RS600_7941: 624 case PCI_CHIP_RS600_7942: 625 screen->chip_family = CHIP_FAMILY_RS600; 626 break; 627 628 case PCI_CHIP_RS690_791E: 629 case PCI_CHIP_RS690_791F: 630 screen->chip_family = CHIP_FAMILY_RS690; 631 break; 632 case PCI_CHIP_RS740_796C: 633 case PCI_CHIP_RS740_796D: 634 case PCI_CHIP_RS740_796E: 635 case PCI_CHIP_RS740_796F: 636 screen->chip_family = CHIP_FAMILY_RS740; 637 break; 638 639 case PCI_CHIP_R520_7100: 640 case PCI_CHIP_R520_7101: 641 case PCI_CHIP_R520_7102: 642 case PCI_CHIP_R520_7103: 643 case PCI_CHIP_R520_7104: 644 case PCI_CHIP_R520_7105: 645 case PCI_CHIP_R520_7106: 646 case PCI_CHIP_R520_7108: 647 case PCI_CHIP_R520_7109: 648 case PCI_CHIP_R520_710A: 649 case PCI_CHIP_R520_710B: 650 case PCI_CHIP_R520_710C: 651 case PCI_CHIP_R520_710E: 652 case PCI_CHIP_R520_710F: 653 screen->chip_family = CHIP_FAMILY_R520; 654 screen->chip_flags = RADEON_CHIPSET_TCL; 655 break; 656 657 case PCI_CHIP_RV515_7140: 658 case PCI_CHIP_RV515_7141: 659 case PCI_CHIP_RV515_7142: 660 case PCI_CHIP_RV515_7143: 661 case PCI_CHIP_RV515_7144: 662 case PCI_CHIP_RV515_7145: 663 case PCI_CHIP_RV515_7146: 664 case PCI_CHIP_RV515_7147: 665 case PCI_CHIP_RV515_7149: 666 case PCI_CHIP_RV515_714A: 667 case PCI_CHIP_RV515_714B: 668 case PCI_CHIP_RV515_714C: 669 case PCI_CHIP_RV515_714D: 670 case PCI_CHIP_RV515_714E: 671 case PCI_CHIP_RV515_714F: 672 case PCI_CHIP_RV515_7151: 673 case PCI_CHIP_RV515_7152: 674 case PCI_CHIP_RV515_7153: 675 case PCI_CHIP_RV515_715E: 676 case PCI_CHIP_RV515_715F: 677 case PCI_CHIP_RV515_7180: 678 case PCI_CHIP_RV515_7181: 679 case PCI_CHIP_RV515_7183: 680 case PCI_CHIP_RV515_7186: 681 case PCI_CHIP_RV515_7187: 682 case PCI_CHIP_RV515_7188: 683 case PCI_CHIP_RV515_718A: 684 case PCI_CHIP_RV515_718B: 685 case PCI_CHIP_RV515_718C: 686 case PCI_CHIP_RV515_718D: 687 case PCI_CHIP_RV515_718F: 688 case PCI_CHIP_RV515_7193: 689 case PCI_CHIP_RV515_7196: 690 case PCI_CHIP_RV515_719B: 691 case PCI_CHIP_RV515_719F: 692 case PCI_CHIP_RV515_7200: 693 case PCI_CHIP_RV515_7210: 694 case PCI_CHIP_RV515_7211: 695 screen->chip_family = CHIP_FAMILY_RV515; 696 screen->chip_flags = RADEON_CHIPSET_TCL; 697 break; 698 699 case PCI_CHIP_RV530_71C0: 700 case PCI_CHIP_RV530_71C1: 701 case PCI_CHIP_RV530_71C2: 702 case PCI_CHIP_RV530_71C3: 703 case PCI_CHIP_RV530_71C4: 704 case PCI_CHIP_RV530_71C5: 705 case PCI_CHIP_RV530_71C6: 706 case PCI_CHIP_RV530_71C7: 707 case PCI_CHIP_RV530_71CD: 708 case PCI_CHIP_RV530_71CE: 709 case PCI_CHIP_RV530_71D2: 710 case PCI_CHIP_RV530_71D4: 711 case PCI_CHIP_RV530_71D5: 712 case PCI_CHIP_RV530_71D6: 713 case PCI_CHIP_RV530_71DA: 714 case PCI_CHIP_RV530_71DE: 715 screen->chip_family = CHIP_FAMILY_RV530; 716 screen->chip_flags = RADEON_CHIPSET_TCL; 717 break; 718 719 case PCI_CHIP_R580_7240: 720 case PCI_CHIP_R580_7243: 721 case PCI_CHIP_R580_7244: 722 case PCI_CHIP_R580_7245: 723 case PCI_CHIP_R580_7246: 724 case PCI_CHIP_R580_7247: 725 case PCI_CHIP_R580_7248: 726 case PCI_CHIP_R580_7249: 727 case PCI_CHIP_R580_724A: 728 case PCI_CHIP_R580_724B: 729 case PCI_CHIP_R580_724C: 730 case PCI_CHIP_R580_724D: 731 case PCI_CHIP_R580_724E: 732 case PCI_CHIP_R580_724F: 733 case PCI_CHIP_R580_7284: 734 screen->chip_family = CHIP_FAMILY_R580; 735 screen->chip_flags = RADEON_CHIPSET_TCL; 736 break; 737 738 case PCI_CHIP_RV570_7280: 739 case PCI_CHIP_RV560_7281: 740 case PCI_CHIP_RV560_7283: 741 case PCI_CHIP_RV560_7287: 742 case PCI_CHIP_RV570_7288: 743 case PCI_CHIP_RV570_7289: 744 case PCI_CHIP_RV570_728B: 745 case PCI_CHIP_RV570_728C: 746 case PCI_CHIP_RV560_7290: 747 case PCI_CHIP_RV560_7291: 748 case PCI_CHIP_RV560_7293: 749 case PCI_CHIP_RV560_7297: 750 screen->chip_family = CHIP_FAMILY_RV560; 751 screen->chip_flags = RADEON_CHIPSET_TCL; 752 break; 753 754 case PCI_CHIP_R600_9400: 755 case PCI_CHIP_R600_9401: 756 case PCI_CHIP_R600_9402: 757 case PCI_CHIP_R600_9403: 758 case PCI_CHIP_R600_9405: 759 case PCI_CHIP_R600_940A: 760 case PCI_CHIP_R600_940B: 761 case PCI_CHIP_R600_940F: 762 screen->chip_family = CHIP_FAMILY_R600; 763 screen->chip_flags = RADEON_CHIPSET_TCL; 764 break; 765 766 case PCI_CHIP_RV610_94C0: 767 case PCI_CHIP_RV610_94C1: 768 case PCI_CHIP_RV610_94C3: 769 case PCI_CHIP_RV610_94C4: 770 case PCI_CHIP_RV610_94C5: 771 case PCI_CHIP_RV610_94C6: 772 case PCI_CHIP_RV610_94C7: 773 case PCI_CHIP_RV610_94C8: 774 case PCI_CHIP_RV610_94C9: 775 case PCI_CHIP_RV610_94CB: 776 case PCI_CHIP_RV610_94CC: 777 case PCI_CHIP_RV610_94CD: 778 screen->chip_family = CHIP_FAMILY_RV610; 779 screen->chip_flags = RADEON_CHIPSET_TCL; 780 break; 781 782 case PCI_CHIP_RV630_9580: 783 case PCI_CHIP_RV630_9581: 784 case PCI_CHIP_RV630_9583: 785 case PCI_CHIP_RV630_9586: 786 case PCI_CHIP_RV630_9587: 787 case PCI_CHIP_RV630_9588: 788 case PCI_CHIP_RV630_9589: 789 case PCI_CHIP_RV630_958A: 790 case PCI_CHIP_RV630_958B: 791 case PCI_CHIP_RV630_958C: 792 case PCI_CHIP_RV630_958D: 793 case PCI_CHIP_RV630_958E: 794 case PCI_CHIP_RV630_958F: 795 screen->chip_family = CHIP_FAMILY_RV630; 796 screen->chip_flags = RADEON_CHIPSET_TCL; 797 break; 798 799 case PCI_CHIP_RV670_9500: 800 case PCI_CHIP_RV670_9501: 801 case PCI_CHIP_RV670_9504: 802 case PCI_CHIP_RV670_9505: 803 case PCI_CHIP_RV670_9506: 804 case PCI_CHIP_RV670_9507: 805 case PCI_CHIP_RV670_9508: 806 case PCI_CHIP_RV670_9509: 807 case PCI_CHIP_RV670_950F: 808 case PCI_CHIP_RV670_9511: 809 case PCI_CHIP_RV670_9515: 810 case PCI_CHIP_RV670_9517: 811 case PCI_CHIP_RV670_9519: 812 screen->chip_family = CHIP_FAMILY_RV670; 813 screen->chip_flags = RADEON_CHIPSET_TCL; 814 break; 815 816 case PCI_CHIP_RV620_95C0: 817 case PCI_CHIP_RV620_95C2: 818 case PCI_CHIP_RV620_95C4: 819 case PCI_CHIP_RV620_95C5: 820 case PCI_CHIP_RV620_95C6: 821 case PCI_CHIP_RV620_95C7: 822 case PCI_CHIP_RV620_95C9: 823 case PCI_CHIP_RV620_95CC: 824 case PCI_CHIP_RV620_95CD: 825 case PCI_CHIP_RV620_95CE: 826 case PCI_CHIP_RV620_95CF: 827 screen->chip_family = CHIP_FAMILY_RV620; 828 screen->chip_flags = RADEON_CHIPSET_TCL; 829 break; 830 831 case PCI_CHIP_RV635_9590: 832 case PCI_CHIP_RV635_9591: 833 case PCI_CHIP_RV635_9593: 834 case PCI_CHIP_RV635_9595: 835 case PCI_CHIP_RV635_9596: 836 case PCI_CHIP_RV635_9597: 837 case PCI_CHIP_RV635_9598: 838 case PCI_CHIP_RV635_9599: 839 case PCI_CHIP_RV635_959B: 840 screen->chip_family = CHIP_FAMILY_RV635; 841 screen->chip_flags = RADEON_CHIPSET_TCL; 842 break; 843 844 case PCI_CHIP_RS780_9610: 845 case PCI_CHIP_RS780_9611: 846 case PCI_CHIP_RS780_9612: 847 case PCI_CHIP_RS780_9613: 848 case PCI_CHIP_RS780_9614: 849 case PCI_CHIP_RS780_9615: 850 case PCI_CHIP_RS780_9616: 851 screen->chip_family = CHIP_FAMILY_RS780; 852 screen->chip_flags = RADEON_CHIPSET_TCL; 853 break; 854 855 case PCI_CHIP_RV770_9440: 856 case PCI_CHIP_RV770_9441: 857 case PCI_CHIP_RV770_9442: 858 case PCI_CHIP_RV770_9444: 859 case PCI_CHIP_RV770_9446: 860 case PCI_CHIP_RV770_944A: 861 case PCI_CHIP_RV770_944B: 862 case PCI_CHIP_RV770_944C: 863 case PCI_CHIP_RV770_944E: 864 case PCI_CHIP_RV770_9450: 865 case PCI_CHIP_RV770_9452: 866 case PCI_CHIP_RV770_9456: 867 case PCI_CHIP_RV770_945A: 868 case PCI_CHIP_RV770_945B: 869 case PCI_CHIP_RV790_9460: 870 case PCI_CHIP_RV790_9462: 871 case PCI_CHIP_RV770_946A: 872 case PCI_CHIP_RV770_946B: 873 case PCI_CHIP_RV770_947A: 874 case PCI_CHIP_RV770_947B: 875 screen->chip_family = CHIP_FAMILY_RV770; 876 screen->chip_flags = RADEON_CHIPSET_TCL; 877 break; 878 879 case PCI_CHIP_RV730_9487: 880 case PCI_CHIP_RV730_9489: 881 case PCI_CHIP_RV730_948F: 882 case PCI_CHIP_RV730_9490: 883 case PCI_CHIP_RV730_9491: 884 case PCI_CHIP_RV730_9498: 885 case PCI_CHIP_RV730_949C: 886 case PCI_CHIP_RV730_949E: 887 case PCI_CHIP_RV730_949F: 888 screen->chip_family = CHIP_FAMILY_RV730; 889 screen->chip_flags = RADEON_CHIPSET_TCL; 890 break; 891 892 case PCI_CHIP_RV710_9540: 893 case PCI_CHIP_RV710_9541: 894 case PCI_CHIP_RV710_9542: 895 case PCI_CHIP_RV710_954E: 896 case PCI_CHIP_RV710_954F: 897 case PCI_CHIP_RV710_9552: 898 case PCI_CHIP_RV710_9553: 899 case PCI_CHIP_RV710_9555: 900 screen->chip_family = CHIP_FAMILY_RV710; 901 screen->chip_flags = RADEON_CHIPSET_TCL; 902 break; 903 904 case PCI_CHIP_RV740_94A0: 905 case PCI_CHIP_RV740_94A1: 906 case PCI_CHIP_RV740_94B1: 907 case PCI_CHIP_RV740_94B3: 908 case PCI_CHIP_RV740_94B5: 909 screen->chip_family = CHIP_FAMILY_RV740; 910 screen->chip_flags = RADEON_CHIPSET_TCL; 911 break; 912 913 default: 914 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 915 device_id); 916 return -1; 917 } 918 919 return 0; 920} 921 922 923/* Create the device specific screen private data struct. 924 */ 925static radeonScreenPtr 926radeonCreateScreen( __DRIscreenPrivate *sPriv ) 927{ 928 radeonScreenPtr screen; 929 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 930 unsigned char *RADEONMMIO = NULL; 931 int i; 932 int ret; 933 uint32_t temp = 0; 934 935 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 936 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 937 return GL_FALSE; 938 } 939 940 /* Allocate the private area */ 941 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 942 if ( !screen ) { 943 __driUtilMessage("%s: Could not allocate memory for screen structure", 944 __FUNCTION__); 945 return NULL; 946 } 947 948#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 949 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 950#endif 951 /* parse information in __driConfigOptions */ 952 driParseOptionInfo (&screen->optionCache, 953 __driConfigOptions, __driNConfigOptions); 954 955 /* This is first since which regions we map depends on whether or 956 * not we are using a PCI card. 957 */ 958 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 959 { 960 int ret; 961 962 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET, 963 &screen->gart_buffer_offset); 964 965 if (ret) { 966 FREE( screen ); 967 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 968 return NULL; 969 } 970 971 ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE, 972 &screen->gart_base); 973 if (ret) { 974 FREE( screen ); 975 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 976 return NULL; 977 } 978 979 ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR, 980 &screen->irq); 981 if (ret) { 982 FREE( screen ); 983 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 984 return NULL; 985 } 986 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 987 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 988 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 989 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 990 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 991 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 992 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 993 } 994 995 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 996 if (ret == -1) 997 return NULL; 998 999 screen->mmio.handle = dri_priv->registerHandle; 1000 screen->mmio.size = dri_priv->registerSize; 1001 if ( drmMap( sPriv->fd, 1002 screen->mmio.handle, 1003 screen->mmio.size, 1004 &screen->mmio.map ) ) { 1005 FREE( screen ); 1006 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 1007 return NULL; 1008 } 1009 1010 RADEONMMIO = screen->mmio.map; 1011 1012 screen->status.handle = dri_priv->statusHandle; 1013 screen->status.size = dri_priv->statusSize; 1014 if ( drmMap( sPriv->fd, 1015 screen->status.handle, 1016 screen->status.size, 1017 &screen->status.map ) ) { 1018 drmUnmap( screen->mmio.map, screen->mmio.size ); 1019 FREE( screen ); 1020 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 1021 return NULL; 1022 } 1023 if (screen->chip_family < CHIP_FAMILY_R600) 1024 screen->scratch = (__volatile__ uint32_t *) 1025 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1026 else 1027 screen->scratch = (__volatile__ uint32_t *) 1028 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 1029 1030 screen->buffers = drmMapBufs( sPriv->fd ); 1031 if ( !screen->buffers ) { 1032 drmUnmap( screen->status.map, screen->status.size ); 1033 drmUnmap( screen->mmio.map, screen->mmio.size ); 1034 FREE( screen ); 1035 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 1036 return NULL; 1037 } 1038 1039 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 1040 screen->gartTextures.handle = dri_priv->gartTexHandle; 1041 screen->gartTextures.size = dri_priv->gartTexMapSize; 1042 if ( drmMap( sPriv->fd, 1043 screen->gartTextures.handle, 1044 screen->gartTextures.size, 1045 (drmAddressPtr)&screen->gartTextures.map ) ) { 1046 drmUnmapBufs( screen->buffers ); 1047 drmUnmap( screen->status.map, screen->status.size ); 1048 drmUnmap( screen->mmio.map, screen->mmio.size ); 1049 FREE( screen ); 1050 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 1051 return NULL; 1052 } 1053 1054 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 1055 } 1056 1057 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 1058 sPriv->ddx_version.minor < 2) { 1059 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 1060 return NULL; 1061 } 1062 1063 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 1064 fprintf(stderr, "R500 support requires a newer drm.\n"); 1065 return NULL; 1066 } 1067 1068 if (getenv("R300_NO_TCL")) 1069 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1070 1071 if (screen->chip_family <= CHIP_FAMILY_RS200) 1072 screen->chip_flags |= RADEON_CLASS_R100; 1073 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1074 screen->chip_flags |= RADEON_CLASS_R200; 1075 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1076 screen->chip_flags |= RADEON_CLASS_R300; 1077 else 1078 screen->chip_flags |= RADEON_CLASS_R600; 1079 1080 screen->cpp = dri_priv->bpp / 8; 1081 screen->AGPMode = dri_priv->AGPMode; 1082 1083 ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp); 1084 1085 /* +r6/r7 */ 1086 if(screen->chip_family >= CHIP_FAMILY_R600) 1087 { 1088 if (ret) 1089 { 1090 FREE( screen ); 1091 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1092 return NULL; 1093 } 1094 else 1095 { 1096 screen->fbLocation = (temp & 0xffff) << 24; 1097 } 1098 } 1099 else 1100 { 1101 if (ret) 1102 { 1103 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 1104 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 1105 else 1106 { 1107 FREE( screen ); 1108 fprintf(stderr, "Unable to get fb location need newer drm\n"); 1109 return NULL; 1110 } 1111 } 1112 else 1113 { 1114 screen->fbLocation = (temp & 0xffff) << 16; 1115 } 1116 } 1117 1118 if (IS_R300_CLASS(screen)) { 1119 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1120 if (ret) { 1121 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1122 switch (screen->chip_family) { 1123 case CHIP_FAMILY_R300: 1124 case CHIP_FAMILY_R350: 1125 screen->num_gb_pipes = 2; 1126 break; 1127 case CHIP_FAMILY_R420: 1128 case CHIP_FAMILY_R520: 1129 case CHIP_FAMILY_R580: 1130 case CHIP_FAMILY_RV560: 1131 case CHIP_FAMILY_RV570: 1132 screen->num_gb_pipes = 4; 1133 break; 1134 case CHIP_FAMILY_RV350: 1135 case CHIP_FAMILY_RV515: 1136 case CHIP_FAMILY_RV530: 1137 case CHIP_FAMILY_RV410: 1138 default: 1139 screen->num_gb_pipes = 1; 1140 break; 1141 } 1142 } else { 1143 screen->num_gb_pipes = temp; 1144 } 1145 1146 /* pipe overrides */ 1147 switch (dri_priv->deviceID) { 1148 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1149 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1150 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1151 screen->num_gb_pipes = 1; 1152 break; 1153 default: 1154 break; 1155 } 1156 } 1157 1158 if ( sPriv->drm_version.minor >= 10 ) { 1159 drm_radeon_setparam_t sp; 1160 1161 sp.param = RADEON_SETPARAM_FB_LOCATION; 1162 sp.value = screen->fbLocation; 1163 1164 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 1165 &sp, sizeof( sp ) ); 1166 } 1167 1168 screen->frontOffset = dri_priv->frontOffset; 1169 screen->frontPitch = dri_priv->frontPitch; 1170 screen->backOffset = dri_priv->backOffset; 1171 screen->backPitch = dri_priv->backPitch; 1172 screen->depthOffset = dri_priv->depthOffset; 1173 screen->depthPitch = dri_priv->depthPitch; 1174 1175 /* Check if ddx has set up a surface reg to cover depth buffer */ 1176 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 1177 /* these chips don't use tiled z without hyperz. So always pretend 1178 we have set up a surface which will cause linear reads/writes */ 1179 (IS_R100_CLASS(screen) && 1180 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 1181 1182 if ( dri_priv->textureSize == 0 ) { 1183 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 1184 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 1185 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1186 dri_priv->log2GARTTexGran; 1187 } else { 1188 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 1189 + screen->fbLocation; 1190 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 1191 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 1192 dri_priv->log2TexGran; 1193 } 1194 1195 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 1196 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 1197 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 1198 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 1199 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 1200 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 1201 } else { 1202 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 1203 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 1204 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 1205 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 1206 dri_priv->log2GARTTexGran; 1207 } 1208 1209 i = 0; 1210 screen->extensions[i++] = &driCopySubBufferExtension.base; 1211 screen->extensions[i++] = &driFrameTrackingExtension.base; 1212 screen->extensions[i++] = &driReadDrawableExtension; 1213 1214 if ( screen->irq != 0 ) { 1215 screen->extensions[i++] = &driSwapControlExtension.base; 1216 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1217 } 1218 1219#if !RADEON_COMMON 1220 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1221#endif 1222 1223#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1224 if (IS_R200_CLASS(screen)) 1225 screen->extensions[i++] = &r200AllocateExtension.base; 1226 1227 screen->extensions[i++] = &r200texOffsetExtension.base; 1228#endif 1229 1230#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1231 screen->extensions[i++] = &r300texOffsetExtension.base; 1232#endif 1233 1234#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1235 screen->extensions[i++] = &r600texOffsetExtension.base; 1236#endif 1237 1238 screen->extensions[i++] = NULL; 1239 sPriv->extensions = screen->extensions; 1240 1241 screen->driScreen = sPriv; 1242 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1243 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1244 screen->sarea_priv_offset); 1245 1246 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1247 if (screen->bom == NULL) { 1248 free(screen); 1249 return NULL; 1250 } 1251 1252 return screen; 1253} 1254 1255static radeonScreenPtr 1256radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1257{ 1258 radeonScreenPtr screen; 1259 int i; 1260 int ret; 1261 uint32_t device_id = 0; 1262 uint32_t temp = 0; 1263 1264 /* Allocate the private area */ 1265 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1266 if ( !screen ) { 1267 __driUtilMessage("%s: Could not allocate memory for screen structure", 1268 __FUNCTION__); 1269 fprintf(stderr, "leaving here\n"); 1270 return NULL; 1271 } 1272 1273#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1274 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1275#endif 1276 1277 /* parse information in __driConfigOptions */ 1278 driParseOptionInfo (&screen->optionCache, 1279 __driConfigOptions, __driNConfigOptions); 1280 1281 screen->kernel_mm = 1; 1282 screen->chip_flags = 0; 1283 1284 /* if we have kms we can support all of these */ 1285 screen->drmSupportsCubeMapsR200 = 1; 1286 screen->drmSupportsBlendColor = 1; 1287 screen->drmSupportsTriPerf = 1; 1288 screen->drmSupportsFragShader = 1; 1289 screen->drmSupportsPointSprites = 1; 1290 screen->drmSupportsCubeMapsR100 = 1; 1291 screen->drmSupportsVertexProgram = 1; 1292 screen->irq = 1; 1293 1294 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1295 if (ret) { 1296 FREE( screen ); 1297 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1298 return NULL; 1299 } 1300 1301 ret = radeon_set_screen_flags(screen, device_id); 1302 if (ret == -1) 1303 return NULL; 1304 1305 if (getenv("R300_NO_TCL")) 1306 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1307 1308 if (screen->chip_family <= CHIP_FAMILY_RS200) 1309 screen->chip_flags |= RADEON_CLASS_R100; 1310 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1311 screen->chip_flags |= RADEON_CLASS_R200; 1312 else if (screen->chip_family <= CHIP_FAMILY_RV570) 1313 screen->chip_flags |= RADEON_CLASS_R300; 1314 else 1315 screen->chip_flags |= RADEON_CLASS_R600; 1316 1317 if (IS_R300_CLASS(screen)) { 1318 ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp); 1319 if (ret) { 1320 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 1321 switch (screen->chip_family) { 1322 case CHIP_FAMILY_R300: 1323 case CHIP_FAMILY_R350: 1324 screen->num_gb_pipes = 2; 1325 break; 1326 case CHIP_FAMILY_R420: 1327 case CHIP_FAMILY_R520: 1328 case CHIP_FAMILY_R580: 1329 case CHIP_FAMILY_RV560: 1330 case CHIP_FAMILY_RV570: 1331 screen->num_gb_pipes = 4; 1332 break; 1333 case CHIP_FAMILY_RV350: 1334 case CHIP_FAMILY_RV515: 1335 case CHIP_FAMILY_RV530: 1336 case CHIP_FAMILY_RV410: 1337 default: 1338 screen->num_gb_pipes = 1; 1339 break; 1340 } 1341 } else { 1342 screen->num_gb_pipes = temp; 1343 } 1344 1345 /* pipe overrides */ 1346 switch (device_id) { 1347 case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 1348 case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */ 1349 case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */ 1350 screen->num_gb_pipes = 1; 1351 break; 1352 default: 1353 break; 1354 } 1355 1356 } 1357 1358 i = 0; 1359 screen->extensions[i++] = &driCopySubBufferExtension.base; 1360 screen->extensions[i++] = &driFrameTrackingExtension.base; 1361 screen->extensions[i++] = &driReadDrawableExtension; 1362 1363 if ( screen->irq != 0 ) { 1364 screen->extensions[i++] = &driSwapControlExtension.base; 1365 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1366 } 1367 1368#if !RADEON_COMMON 1369 screen->extensions[i++] = &radeonTexBufferExtension.base; 1370#endif 1371 1372#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1373 if (IS_R200_CLASS(screen)) 1374 screen->extensions[i++] = &r200AllocateExtension.base; 1375 1376 screen->extensions[i++] = &r200TexBufferExtension.base; 1377#endif 1378 1379#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1380 screen->extensions[i++] = &r300TexBufferExtension.base; 1381#endif 1382 1383#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1384 screen->extensions[i++] = &r600TexBufferExtension.base; 1385#endif 1386 1387 screen->extensions[i++] = NULL; 1388 sPriv->extensions = screen->extensions; 1389 1390 screen->driScreen = sPriv; 1391 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1392 if (screen->bom == NULL) { 1393 free(screen); 1394 return NULL; 1395 } 1396 return screen; 1397} 1398 1399/* Destroy the device specific screen private data struct. 1400 */ 1401static void 1402radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1403{ 1404 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1405 1406 if (!screen) 1407 return; 1408 1409 if (screen->kernel_mm) { 1410#ifdef RADEON_BO_TRACK 1411 radeon_tracker_print(&screen->bom->tracker, stderr); 1412#endif 1413 radeon_bo_manager_gem_dtor(screen->bom); 1414 } else { 1415 radeon_bo_manager_legacy_dtor(screen->bom); 1416 1417 if ( screen->gartTextures.map ) { 1418 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1419 } 1420 drmUnmapBufs( screen->buffers ); 1421 drmUnmap( screen->status.map, screen->status.size ); 1422 drmUnmap( screen->mmio.map, screen->mmio.size ); 1423 } 1424 1425 /* free all option information */ 1426 driDestroyOptionInfo (&screen->optionCache); 1427 1428 FREE( screen ); 1429 sPriv->private = NULL; 1430} 1431 1432 1433/* Initialize the driver specific screen private data. 1434 */ 1435static GLboolean 1436radeonInitDriver( __DRIscreenPrivate *sPriv ) 1437{ 1438 if (sPriv->dri2.enabled) { 1439 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1440 } else { 1441 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1442 } 1443 if ( !sPriv->private ) { 1444 radeonDestroyScreen( sPriv ); 1445 return GL_FALSE; 1446 } 1447 1448 return GL_TRUE; 1449} 1450 1451 1452 1453/** 1454 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1455 * 1456 * \todo This function (and its interface) will need to be updated to support 1457 * pbuffers. 1458 */ 1459static GLboolean 1460radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1461 __DRIdrawablePrivate *driDrawPriv, 1462 const __GLcontextModes *mesaVis, 1463 GLboolean isPixmap ) 1464{ 1465 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1466 1467 const GLboolean swDepth = GL_FALSE; 1468 const GLboolean swAlpha = GL_FALSE; 1469 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1470 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1471 mesaVis->depthBits != 24; 1472 GLenum rgbFormat; 1473 struct radeon_framebuffer *rfb; 1474 1475 if (isPixmap) 1476 return GL_FALSE; /* not implemented */ 1477 1478 rfb = CALLOC_STRUCT(radeon_framebuffer); 1479 if (!rfb) 1480 return GL_FALSE; 1481 1482 _mesa_initialize_framebuffer(&rfb->base, mesaVis); 1483 1484 if (mesaVis->redBits == 5) 1485 rgbFormat = GL_RGB5; 1486 else if (mesaVis->alphaBits == 0) 1487 rgbFormat = GL_RGB8; 1488 else 1489 rgbFormat = GL_RGBA8; 1490 1491 /* front color renderbuffer */ 1492 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1493 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1494 rfb->color_rb[0]->has_surface = 1; 1495 1496 /* back color renderbuffer */ 1497 if (mesaVis->doubleBufferMode) { 1498 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1499 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1500 rfb->color_rb[1]->has_surface = 1; 1501 } 1502 1503 if (mesaVis->depthBits == 24) { 1504 if (mesaVis->stencilBits == 8) { 1505 struct radeon_renderbuffer *depthStencilRb = radeon_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT, driDrawPriv); 1506 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1507 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1508 depthStencilRb->has_surface = screen->depthHasSurface; 1509 } else { 1510 /* depth renderbuffer */ 1511 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT24, driDrawPriv); 1512 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1513 depth->has_surface = screen->depthHasSurface; 1514 } 1515 } else if (mesaVis->depthBits == 16) { 1516 /* just 16-bit depth buffer, no hw stencil */ 1517 struct radeon_renderbuffer *depth = radeon_create_renderbuffer(GL_DEPTH_COMPONENT16, driDrawPriv); 1518 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1519 depth->has_surface = screen->depthHasSurface; 1520 } 1521 1522 _mesa_add_soft_renderbuffers(&rfb->base, 1523 GL_FALSE, /* color */ 1524 swDepth, 1525 swStencil, 1526 swAccum, 1527 swAlpha, 1528 GL_FALSE /* aux */); 1529 driDrawPriv->driverPrivate = (void *) rfb; 1530 1531 return (driDrawPriv->driverPrivate != NULL); 1532} 1533 1534 1535static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1536{ 1537 struct radeon_renderbuffer *rb; 1538 1539 rb = rfb->color_rb[0]; 1540 if (rb && rb->bo) { 1541 radeon_bo_unref(rb->bo); 1542 rb->bo = NULL; 1543 } 1544 rb = rfb->color_rb[1]; 1545 if (rb && rb->bo) { 1546 radeon_bo_unref(rb->bo); 1547 rb->bo = NULL; 1548 } 1549 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1550 if (rb && rb->bo) { 1551 radeon_bo_unref(rb->bo); 1552 rb->bo = NULL; 1553 } 1554} 1555 1556void 1557radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1558{ 1559 struct radeon_framebuffer *rfb; 1560 if (!driDrawPriv) 1561 return; 1562 1563 rfb = (void*)driDrawPriv->driverPrivate; 1564 if (!rfb) 1565 return; 1566 radeon_cleanup_renderbuffers(rfb); 1567 _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1568} 1569 1570/** 1571 * Choose the appropriate CreateContext function based on the chipset. 1572 * Eventually, all drivers will go through this process. 1573 */ 1574static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1575 __DRIcontextPrivate * driContextPriv, 1576 void *sharedContextPriv) 1577{ 1578 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1579 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1580#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1581 if (IS_R600_CLASS(screen)) 1582 return r600CreateContext(glVisual, driContextPriv, sharedContextPriv); 1583#endif 1584 1585#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1586 if (IS_R300_CLASS(screen)) 1587 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1588#endif 1589 1590#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1591 if (IS_R200_CLASS(screen)) 1592 return r200CreateContext(glVisual, driContextPriv, sharedContextPriv); 1593#endif 1594 1595#if !RADEON_COMMON 1596 (void)screen; 1597 return r100CreateContext(glVisual, driContextPriv, sharedContextPriv); 1598#endif 1599 return GL_FALSE; 1600} 1601 1602 1603/** 1604 * This is the driver specific part of the createNewScreen entry point. 1605 * 1606 * \todo maybe fold this into intelInitDriver 1607 * 1608 * \return the __GLcontextModes supported by this driver 1609 */ 1610static const __DRIconfig ** 1611radeonInitScreen(__DRIscreenPrivate *psp) 1612{ 1613#if !RADEON_COMMON 1614 static const char *driver_name = "Radeon"; 1615 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1616 static const __DRIversion dri_expected = { 4, 0, 0 }; 1617 static const __DRIversion drm_expected = { 1, 6, 0 }; 1618#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1619 static const char *driver_name = "R200"; 1620 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1621 static const __DRIversion dri_expected = { 4, 0, 0 }; 1622 static const __DRIversion drm_expected = { 1, 6, 0 }; 1623#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1624 static const char *driver_name = "R300"; 1625 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1626 static const __DRIversion dri_expected = { 4, 0, 0 }; 1627 static const __DRIversion drm_expected = { 1, 24, 0 }; 1628#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R600) 1629 static const char *driver_name = "R600"; 1630 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1631 static const __DRIversion dri_expected = { 4, 0, 0 }; 1632 static const __DRIversion drm_expected = { 1, 24, 0 }; 1633#endif 1634 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1635 1636 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1637 &psp->dri_version, & dri_expected, 1638 &psp->ddx_version, & ddx_expected, 1639 &psp->drm_version, & drm_expected ) ) { 1640 return NULL; 1641 } 1642 1643 /* Calling driInitExtensions here, with a NULL context pointer, 1644 * does not actually enable the extensions. It just makes sure 1645 * that all the dispatch offsets for all the extensions that 1646 * *might* be enables are known. This is needed because the 1647 * dispatch offsets need to be known when _mesa_context_create 1648 * is called, but we can't enable the extensions until we have a 1649 * context pointer. 1650 * 1651 * Hello chicken. Hello egg. How are you two today? 1652 */ 1653 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1654#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1655 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1656 driInitSingleExtension( NULL, ARB_vp_extension ); 1657 driInitSingleExtension( NULL, NV_vp_extension ); 1658 driInitSingleExtension( NULL, ATI_fs_extension ); 1659 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1660#elif (defined(RADEON_COMMON_FOR_R300) || defined(RADEON_COMMON_FOR_R600)) 1661 driInitSingleExtension( NULL, gl_20_extension ); 1662#endif 1663 1664 if (!radeonInitDriver(psp)) 1665 return NULL; 1666 1667 /* for now fill in all modes */ 1668 return radeonFillInModes( psp, 1669 dri_priv->bpp, 1670 (dri_priv->bpp == 16) ? 16 : 24, 1671 (dri_priv->bpp == 16) ? 0 : 8, 1); 1672} 1673#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1674 1675/** 1676 * This is the driver specific part of the createNewScreen entry point. 1677 * Called when using DRI2. 1678 * 1679 * \return the __GLcontextModes supported by this driver 1680 */ 1681static const 1682__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1683{ 1684 GLenum fb_format[3]; 1685 GLenum fb_type[3]; 1686 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1687 * support pageflipping at all. 1688 */ 1689 static const GLenum back_buffer_modes[] = { 1690 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1691 }; 1692 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1693 int color; 1694 __DRIconfig **configs = NULL; 1695 1696 /* Calling driInitExtensions here, with a NULL context pointer, 1697 * does not actually enable the extensions. It just makes sure 1698 * that all the dispatch offsets for all the extensions that 1699 * *might* be enables are known. This is needed because the 1700 * dispatch offsets need to be known when _mesa_context_create 1701 * is called, but we can't enable the extensions until we have a 1702 * context pointer. 1703 * 1704 * Hello chicken. Hello egg. How are you two today? 1705 */ 1706 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1707 driInitExtensions( NULL, mm_extensions, GL_FALSE ); 1708#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1709 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1710 driInitSingleExtension( NULL, ARB_vp_extension ); 1711 driInitSingleExtension( NULL, NV_vp_extension ); 1712 driInitSingleExtension( NULL, ATI_fs_extension ); 1713 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1714#endif 1715 1716 if (!radeonInitDriver(psp)) { 1717 return NULL; 1718 } 1719 depth_bits[0] = 0; 1720 stencil_bits[0] = 0; 1721 depth_bits[1] = 16; 1722 stencil_bits[1] = 0; 1723 depth_bits[2] = 24; 1724 stencil_bits[2] = 0; 1725 depth_bits[3] = 24; 1726 stencil_bits[3] = 8; 1727 1728 msaa_samples_array[0] = 0; 1729 1730 fb_format[0] = GL_RGB; 1731 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1732 1733 fb_format[1] = GL_BGR; 1734 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1735 1736 fb_format[2] = GL_BGRA; 1737 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1738 1739 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1740 __DRIconfig **new_configs; 1741 1742 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1743 depth_bits, 1744 stencil_bits, 1745 ARRAY_SIZE(depth_bits), 1746 back_buffer_modes, 1747 ARRAY_SIZE(back_buffer_modes), 1748 msaa_samples_array, 1749 ARRAY_SIZE(msaa_samples_array)); 1750 if (configs == NULL) 1751 configs = new_configs; 1752 else 1753 configs = driConcatConfigs(configs, new_configs); 1754 } 1755 1756 if (configs == NULL) { 1757 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1758 __LINE__); 1759 return NULL; 1760 } 1761 1762 return (const __DRIconfig **)configs; 1763} 1764 1765/** 1766 * Get information about previous buffer swaps. 1767 */ 1768static int 1769getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1770{ 1771 struct radeon_framebuffer *rfb; 1772 1773 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1774 || (dPriv->driContextPriv->driverPrivate == NULL) 1775 || (sInfo == NULL) ) { 1776 return -1; 1777 } 1778 1779 rfb = dPriv->driverPrivate; 1780 sInfo->swap_count = rfb->swap_count; 1781 sInfo->swap_ust = rfb->swap_ust; 1782 sInfo->swap_missed_count = rfb->swap_missed_count; 1783 1784 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1785 ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust ) 1786 : 0.0; 1787 1788 return 0; 1789} 1790 1791const struct __DriverAPIRec driDriverAPI = { 1792 .InitScreen = radeonInitScreen, 1793 .DestroyScreen = radeonDestroyScreen, 1794 .CreateContext = radeonCreateContext, 1795 .DestroyContext = radeonDestroyContext, 1796 .CreateBuffer = radeonCreateBuffer, 1797 .DestroyBuffer = radeonDestroyBuffer, 1798 .SwapBuffers = radeonSwapBuffers, 1799 .MakeCurrent = radeonMakeCurrent, 1800 .UnbindContext = radeonUnbindContext, 1801 .GetSwapInfo = getSwapInfo, 1802 .GetDrawableMSC = driDrawableGetMSC32, 1803 .WaitForMSC = driWaitForMSC32, 1804 .WaitForSBC = NULL, 1805 .SwapBuffersMSC = NULL, 1806 .CopySubBuffer = radeonCopySubBuffer, 1807 /* DRI2 */ 1808 .InitScreen2 = radeonInitScreen2, 1809}; 1810 1811