radeon_screen.c revision 4f96000e294fa0d6ba6f5915ff508017d9c26d50 
1/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */
2/**************************************************************************
3
4Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5                     VA Linux Systems Inc., Fremont, California.
6
7All Rights Reserved.
8
9Permission is hereby granted, free of charge, to any person obtaining
10a copy of this software and associated documentation files (the
11"Software"), to deal in the Software without restriction, including
12without limitation the rights to use, copy, modify, merge, publish,
13distribute, sublicense, and/or sell copies of the Software, and to
14permit persons to whom the Software is furnished to do so, subject to
15the following conditions:
16
17The above copyright notice and this permission notice (including the
18next paragraph) shall be included in all copies or substantial
19portions of the Software.
20
21THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29**************************************************************************/
30
31/**
32 * \file radeon_screen.c
33 * Screen initialization functions for the Radeon driver.
34 *
35 * \author Kevin E. Martin <martin@valinux.com>
36 * \author  Gareth Hughes <gareth@valinux.com>
37 */
38
39#include "glheader.h"
40#include "imports.h"
41#include "mtypes.h"
42#include "framebuffer.h"
43#include "renderbuffer.h"
44
45#define STANDALONE_MMIO
46#include "radeon_chipset.h"
47#include "radeon_macros.h"
48#include "radeon_screen.h"
49#if !RADEON_COMMON
50#include "radeon_context.h"
51#include "radeon_span.h"
52#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
53#include "r200_context.h"
54#include "r200_ioctl.h"
55#include "r200_span.h"
56#include "r200_tex.h"
57#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
58#include "r300_context.h"
59#include "r300_fragprog.h"
60#include "r300_tex.h"
61#include "radeon_span.h"
62#endif
63
64#include "utils.h"
65#include "context.h"
66#include "vblank.h"
67#include "drirenderbuffer.h"
68
69#include "GL/internal/dri_interface.h"
70
71/* Radeon configuration
72 */
73#include "xmlpool.h"
74
75#if !RADEON_COMMON	/* R100 */
76PUBLIC const char __driConfigOptions[] =
77DRI_CONF_BEGIN
78    DRI_CONF_SECTION_PERFORMANCE
79        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
80        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
81        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
82        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
83        DRI_CONF_HYPERZ(false)
84    DRI_CONF_SECTION_END
85    DRI_CONF_SECTION_QUALITY
86        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
87        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
88        DRI_CONF_NO_NEG_LOD_BIAS(false)
89        DRI_CONF_FORCE_S3TC_ENABLE(false)
90        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
91        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
92        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
93        DRI_CONF_ALLOW_LARGE_TEXTURES(1)
94    DRI_CONF_SECTION_END
95    DRI_CONF_SECTION_DEBUG
96        DRI_CONF_NO_RAST(false)
97    DRI_CONF_SECTION_END
98DRI_CONF_END;
99static const GLuint __driNConfigOptions = 14;
100
101#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
102
103PUBLIC const char __driConfigOptions[] =
104DRI_CONF_BEGIN
105    DRI_CONF_SECTION_PERFORMANCE
106        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
107        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
108        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
109        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
110        DRI_CONF_HYPERZ(false)
111    DRI_CONF_SECTION_END
112    DRI_CONF_SECTION_QUALITY
113        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
114        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
115        DRI_CONF_NO_NEG_LOD_BIAS(false)
116        DRI_CONF_FORCE_S3TC_ENABLE(false)
117        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
118        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
119        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
120        DRI_CONF_ALLOW_LARGE_TEXTURES(1)
121        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
122    DRI_CONF_SECTION_END
123    DRI_CONF_SECTION_DEBUG
124        DRI_CONF_NO_RAST(false)
125    DRI_CONF_SECTION_END
126    DRI_CONF_SECTION_SOFTWARE
127        DRI_CONF_NV_VERTEX_PROGRAM(false)
128    DRI_CONF_SECTION_END
129DRI_CONF_END;
130static const GLuint __driNConfigOptions = 16;
131
132extern const struct dri_extension blend_extensions[];
133extern const struct dri_extension ARB_vp_extension[];
134extern const struct dri_extension NV_vp_extension[];
135extern const struct dri_extension ATI_fs_extension[];
136extern const struct dri_extension point_extensions[];
137
138#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
139
140/* TODO: integrate these into xmlpool.h! */
141#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
142DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
143        DRI_CONF_DESC(en,"Number of texture image units") \
144        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
145DRI_CONF_OPT_END
146
147#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
148DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
149        DRI_CONF_DESC(en,"Number of texture coordinate units") \
150        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
151DRI_CONF_OPT_END
152
153#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
154DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
155        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
156        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
157DRI_CONF_OPT_END
158
159#define DRI_CONF_DISABLE_S3TC(def) \
160DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
161        DRI_CONF_DESC(en,"Disable S3TC compression") \
162DRI_CONF_OPT_END
163
164#define DRI_CONF_DISABLE_FALLBACK(def) \
165DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
166        DRI_CONF_DESC(en,"Disable Low-impact fallback") \
167DRI_CONF_OPT_END
168
169#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
170DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
171        DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
172DRI_CONF_OPT_END
173
174#define DRI_CONF_FP_OPTIMIZATION(def) \
175DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
176	DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
177                DRI_CONF_ENUM(0,"Optimize for Speed") \
178                DRI_CONF_ENUM(1,"Optimize for Quality") \
179        DRI_CONF_DESC_END \
180DRI_CONF_OPT_END
181
182const char __driConfigOptions[] =
183DRI_CONF_BEGIN
184	DRI_CONF_SECTION_PERFORMANCE
185		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
186		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
187		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
188		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
189		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
190		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
191		DRI_CONF_DISABLE_FALLBACK(false)
192		DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
193	DRI_CONF_SECTION_END
194	DRI_CONF_SECTION_QUALITY
195		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
196		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
197		DRI_CONF_NO_NEG_LOD_BIAS(false)
198                DRI_CONF_FORCE_S3TC_ENABLE(false)
199		DRI_CONF_DISABLE_S3TC(false)
200		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
201		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
202		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
203		DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
204	DRI_CONF_SECTION_END
205	DRI_CONF_SECTION_DEBUG
206		DRI_CONF_NO_RAST(false)
207	DRI_CONF_SECTION_END
208DRI_CONF_END;
209static const GLuint __driNConfigOptions = 18;
210
211#ifndef RADEON_DEBUG
212int RADEON_DEBUG = 0;
213
214static const struct dri_debug_control debug_control[] = {
215	{"fall", DEBUG_FALLBACKS},
216	{"tex", DEBUG_TEXTURE},
217	{"ioctl", DEBUG_IOCTL},
218	{"prim", DEBUG_PRIMS},
219	{"vert", DEBUG_VERTS},
220	{"state", DEBUG_STATE},
221	{"code", DEBUG_CODEGEN},
222	{"vfmt", DEBUG_VFMT},
223	{"vtxf", DEBUG_VFMT},
224	{"verb", DEBUG_VERBOSE},
225	{"dri", DEBUG_DRI},
226	{"dma", DEBUG_DMA},
227	{"san", DEBUG_SANITY},
228	{"sync", DEBUG_SYNC},
229	{"pix", DEBUG_PIXEL},
230	{"mem", DEBUG_MEMORY},
231	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
232	{NULL, 0}
233};
234#endif /* RADEON_DEBUG */
235
236#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
237
238extern const struct dri_extension card_extensions[];
239
240static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
241
242static int
243radeonGetParam(int fd, int param, void *value)
244{
245  int ret;
246  drm_radeon_getparam_t gp;
247
248  gp.param = param;
249  gp.value = value;
250
251  ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
252  return ret;
253}
254
255static __GLcontextModes *
256radeonFillInModes( unsigned pixel_bits, unsigned depth_bits,
257		 unsigned stencil_bits, GLboolean have_back_buffer )
258{
259    __GLcontextModes * modes;
260    __GLcontextModes * m;
261    unsigned num_modes;
262    unsigned depth_buffer_factor;
263    unsigned back_buffer_factor;
264    GLenum fb_format;
265    GLenum fb_type;
266
267    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
268     * enough to add support.  Basically, if a context is created with an
269     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
270     * will never be used.
271     */
272    static const GLenum back_buffer_modes[] = {
273	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
274    };
275
276    u_int8_t depth_bits_array[2];
277    u_int8_t stencil_bits_array[2];
278
279
280    depth_bits_array[0] = depth_bits;
281    depth_bits_array[1] = depth_bits;
282
283    /* Just like with the accumulation buffer, always provide some modes
284     * with a stencil buffer.  It will be a sw fallback, but some apps won't
285     * care about that.
286     */
287    stencil_bits_array[0] = 0;
288    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
289
290    depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
291    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
292
293    num_modes = depth_buffer_factor * back_buffer_factor * 4;
294
295    if ( pixel_bits == 16 ) {
296        fb_format = GL_RGB;
297        fb_type = GL_UNSIGNED_SHORT_5_6_5;
298    }
299    else {
300        fb_format = GL_BGRA;
301        fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
302    }
303
304    modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) );
305    m = modes;
306    if ( ! driFillInModes( & m, fb_format, fb_type,
307			   depth_bits_array, stencil_bits_array, depth_buffer_factor,
308			   back_buffer_modes, back_buffer_factor,
309			   GLX_TRUE_COLOR ) ) {
310	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
311		 __func__, __LINE__ );
312	return NULL;
313    }
314
315    if ( ! driFillInModes( & m, fb_format, fb_type,
316			   depth_bits_array, stencil_bits_array, depth_buffer_factor,
317			   back_buffer_modes, back_buffer_factor,
318			   GLX_DIRECT_COLOR ) ) {
319	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
320		 __func__, __LINE__ );
321	return NULL;
322    }
323
324    /* Mark the visual as slow if there are "fake" stencil bits.
325     */
326    for ( m = modes ; m != NULL ; m = m->next ) {
327	if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) {
328	    m->visualRating = GLX_SLOW_CONFIG;
329	}
330    }
331
332    return modes;
333}
334
335
336/* Create the device specific screen private data struct.
337 */
338static radeonScreenPtr
339radeonCreateScreen( __DRIscreenPrivate *sPriv )
340{
341   radeonScreenPtr screen;
342   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
343   unsigned char *RADEONMMIO;
344   PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension =
345     (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension"));
346   void * const psc = sPriv->psc->screenConfigs;
347
348   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
349      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
350      return GL_FALSE;
351   }
352
353   /* Allocate the private area */
354   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
355   if ( !screen ) {
356      __driUtilMessage("%s: Could not allocate memory for screen structure",
357		       __FUNCTION__);
358      return NULL;
359   }
360
361#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
362	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
363#endif
364
365   /* parse information in __driConfigOptions */
366   driParseOptionInfo (&screen->optionCache,
367		       __driConfigOptions, __driNConfigOptions);
368
369   /* This is first since which regions we map depends on whether or
370    * not we are using a PCI card.
371    */
372   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
373   {
374      int ret;
375      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
376			    &screen->gart_buffer_offset);
377
378      if (ret) {
379	 FREE( screen );
380	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
381	 return NULL;
382      }
383
384      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
385			    &screen->gart_base);
386      if (ret) {
387	 FREE( screen );
388	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
389	 return NULL;
390      }
391
392      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
393			    &screen->irq);
394      if (ret) {
395	 FREE( screen );
396	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
397	 return NULL;
398      }
399      screen->drmSupportsCubeMapsR200 = (sPriv->drmMinor >= 7);
400      screen->drmSupportsBlendColor = (sPriv->drmMinor >= 11);
401      screen->drmSupportsTriPerf = (sPriv->drmMinor >= 16);
402      screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
403      screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
404      screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15);
405      screen->drmSupportsVertexProgram = (sPriv->drmMinor >= 25);
406   }
407
408   screen->mmio.handle = dri_priv->registerHandle;
409   screen->mmio.size   = dri_priv->registerSize;
410   if ( drmMap( sPriv->fd,
411		screen->mmio.handle,
412		screen->mmio.size,
413		&screen->mmio.map ) ) {
414      FREE( screen );
415      __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
416      return NULL;
417   }
418
419   RADEONMMIO = screen->mmio.map;
420
421   screen->status.handle = dri_priv->statusHandle;
422   screen->status.size   = dri_priv->statusSize;
423   if ( drmMap( sPriv->fd,
424		screen->status.handle,
425		screen->status.size,
426		&screen->status.map ) ) {
427      drmUnmap( screen->mmio.map, screen->mmio.size );
428      FREE( screen );
429      __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
430      return NULL;
431   }
432   screen->scratch = (__volatile__ u_int32_t *)
433      ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
434
435   screen->buffers = drmMapBufs( sPriv->fd );
436   if ( !screen->buffers ) {
437      drmUnmap( screen->status.map, screen->status.size );
438      drmUnmap( screen->mmio.map, screen->mmio.size );
439      FREE( screen );
440      __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
441      return NULL;
442   }
443
444   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
445      screen->gartTextures.handle = dri_priv->gartTexHandle;
446      screen->gartTextures.size   = dri_priv->gartTexMapSize;
447      if ( drmMap( sPriv->fd,
448		   screen->gartTextures.handle,
449		   screen->gartTextures.size,
450		   (drmAddressPtr)&screen->gartTextures.map ) ) {
451	 drmUnmapBufs( screen->buffers );
452	 drmUnmap( screen->status.map, screen->status.size );
453	 drmUnmap( screen->mmio.map, screen->mmio.size );
454	 FREE( screen );
455	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
456	 return NULL;
457      }
458
459      screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
460   }
461
462   screen->chip_flags = 0;
463   /* XXX: add more chipsets */
464   switch ( dri_priv->deviceID ) {
465   case PCI_CHIP_RADEON_LY:
466   case PCI_CHIP_RADEON_LZ:
467   case PCI_CHIP_RADEON_QY:
468   case PCI_CHIP_RADEON_QZ:
469   case PCI_CHIP_RN50_515E:
470   case PCI_CHIP_RN50_5969:
471      screen->chip_family = CHIP_FAMILY_RV100;
472      break;
473
474   case PCI_CHIP_RS100_4136:
475   case PCI_CHIP_RS100_4336:
476      screen->chip_family = CHIP_FAMILY_RS100;
477      break;
478
479   case PCI_CHIP_RS200_4137:
480   case PCI_CHIP_RS200_4337:
481   case PCI_CHIP_RS250_4237:
482   case PCI_CHIP_RS250_4437:
483      screen->chip_family = CHIP_FAMILY_RS200;
484      break;
485
486   case PCI_CHIP_RADEON_QD:
487   case PCI_CHIP_RADEON_QE:
488   case PCI_CHIP_RADEON_QF:
489   case PCI_CHIP_RADEON_QG:
490      /* all original radeons (7200) presumably have a stencil op bug */
491      screen->chip_family = CHIP_FAMILY_R100;
492      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
493      break;
494
495   case PCI_CHIP_RV200_QW:
496   case PCI_CHIP_RV200_QX:
497   case PCI_CHIP_RADEON_LW:
498   case PCI_CHIP_RADEON_LX:
499      screen->chip_family = CHIP_FAMILY_RV200;
500      screen->chip_flags = RADEON_CHIPSET_TCL;
501      break;
502
503   case PCI_CHIP_R200_BB:
504   case PCI_CHIP_R200_BC:
505   case PCI_CHIP_R200_QH:
506   case PCI_CHIP_R200_QL:
507   case PCI_CHIP_R200_QM:
508      screen->chip_family = CHIP_FAMILY_R200;
509      screen->chip_flags = RADEON_CHIPSET_TCL;
510      break;
511
512   case PCI_CHIP_RV250_If:
513   case PCI_CHIP_RV250_Ig:
514   case PCI_CHIP_RV250_Ld:
515   case PCI_CHIP_RV250_Lf:
516   case PCI_CHIP_RV250_Lg:
517      screen->chip_family = CHIP_FAMILY_RV250;
518      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
519      break;
520
521   case PCI_CHIP_RV280_5960:
522   case PCI_CHIP_RV280_5961:
523   case PCI_CHIP_RV280_5962:
524   case PCI_CHIP_RV280_5964:
525   case PCI_CHIP_RV280_5965:
526   case PCI_CHIP_RV280_5C61:
527   case PCI_CHIP_RV280_5C63:
528      screen->chip_family = CHIP_FAMILY_RV280;
529      screen->chip_flags = RADEON_CHIPSET_TCL;
530      break;
531
532   case PCI_CHIP_RS300_5834:
533   case PCI_CHIP_RS300_5835:
534   case PCI_CHIP_RS350_7834:
535   case PCI_CHIP_RS350_7835:
536      screen->chip_family = CHIP_FAMILY_RS300;
537      break;
538
539   case PCI_CHIP_R300_AD:
540   case PCI_CHIP_R300_AE:
541   case PCI_CHIP_R300_AF:
542   case PCI_CHIP_R300_AG:
543   case PCI_CHIP_R300_ND:
544   case PCI_CHIP_R300_NE:
545   case PCI_CHIP_R300_NF:
546   case PCI_CHIP_R300_NG:
547      screen->chip_family = CHIP_FAMILY_R300;
548      screen->chip_flags = RADEON_CHIPSET_TCL;
549      break;
550
551   case PCI_CHIP_RV350_AP:
552   case PCI_CHIP_RV350_AQ:
553   case PCI_CHIP_RV350_AR:
554   case PCI_CHIP_RV350_AS:
555   case PCI_CHIP_RV350_AT:
556   case PCI_CHIP_RV350_AV:
557   case PCI_CHIP_RV350_AU:
558   case PCI_CHIP_RV350_NP:
559   case PCI_CHIP_RV350_NQ:
560   case PCI_CHIP_RV350_NR:
561   case PCI_CHIP_RV350_NS:
562   case PCI_CHIP_RV350_NT:
563   case PCI_CHIP_RV350_NV:
564      screen->chip_family = CHIP_FAMILY_RV350;
565      screen->chip_flags = RADEON_CHIPSET_TCL;
566      break;
567
568   case PCI_CHIP_R350_AH:
569   case PCI_CHIP_R350_AI:
570   case PCI_CHIP_R350_AJ:
571   case PCI_CHIP_R350_AK:
572   case PCI_CHIP_R350_NH:
573   case PCI_CHIP_R350_NI:
574   case PCI_CHIP_R360_NJ:
575   case PCI_CHIP_R350_NK:
576      screen->chip_family = CHIP_FAMILY_R350;
577      screen->chip_flags = RADEON_CHIPSET_TCL;
578      break;
579
580   case PCI_CHIP_RV370_5460:
581   case PCI_CHIP_RV370_5462:
582   case PCI_CHIP_RV370_5464:
583   case PCI_CHIP_RV370_5B60:
584   case PCI_CHIP_RV370_5B62:
585   case PCI_CHIP_RV370_5B63:
586   case PCI_CHIP_RV370_5B64:
587   case PCI_CHIP_RV370_5B65:
588   case PCI_CHIP_RV380_3150:
589   case PCI_CHIP_RV380_3152:
590   case PCI_CHIP_RV380_3154:
591   case PCI_CHIP_RV380_3E50:
592   case PCI_CHIP_RV380_3E54:
593      screen->chip_family = CHIP_FAMILY_RV380;
594      screen->chip_flags = RADEON_CHIPSET_TCL;
595      break;
596
597   case PCI_CHIP_R420_JN:
598   case PCI_CHIP_R420_JH:
599   case PCI_CHIP_R420_JI:
600   case PCI_CHIP_R420_JJ:
601   case PCI_CHIP_R420_JK:
602   case PCI_CHIP_R420_JL:
603   case PCI_CHIP_R420_JM:
604   case PCI_CHIP_R420_JO:
605   case PCI_CHIP_R420_JP:
606   case PCI_CHIP_R420_JT:
607   case PCI_CHIP_R481_4B49:
608   case PCI_CHIP_R481_4B4A:
609   case PCI_CHIP_R481_4B4B:
610   case PCI_CHIP_R481_4B4C:
611   case PCI_CHIP_R423_UH:
612   case PCI_CHIP_R423_UI:
613   case PCI_CHIP_R423_UJ:
614   case PCI_CHIP_R423_UK:
615   case PCI_CHIP_R430_554C:
616   case PCI_CHIP_R430_554D:
617   case PCI_CHIP_R430_554E:
618   case PCI_CHIP_R430_554F:
619   case PCI_CHIP_R423_5550:
620   case PCI_CHIP_R423_UQ:
621   case PCI_CHIP_R423_UR:
622   case PCI_CHIP_R423_UT:
623   case PCI_CHIP_R430_5D48:
624   case PCI_CHIP_R430_5D49:
625   case PCI_CHIP_R430_5D4A:
626   case PCI_CHIP_R480_5D4C:
627   case PCI_CHIP_R480_5D4D:
628   case PCI_CHIP_R480_5D4E:
629   case PCI_CHIP_R480_5D4F:
630   case PCI_CHIP_R480_5D50:
631   case PCI_CHIP_R480_5D52:
632   case PCI_CHIP_R423_5D57:
633      screen->chip_family = CHIP_FAMILY_R420;
634      screen->chip_flags = RADEON_CHIPSET_TCL;
635      break;
636
637   case PCI_CHIP_RV410_564A:
638   case PCI_CHIP_RV410_564B:
639   case PCI_CHIP_RV410_564F:
640   case PCI_CHIP_RV410_5652:
641   case PCI_CHIP_RV410_5653:
642   case PCI_CHIP_RV410_5E48:
643   case PCI_CHIP_RV410_5E4A:
644   case PCI_CHIP_RV410_5E4B:
645   case PCI_CHIP_RV410_5E4C:
646   case PCI_CHIP_RV410_5E4D:
647   case PCI_CHIP_RV410_5E4F:
648      screen->chip_family = CHIP_FAMILY_RV410;
649      screen->chip_flags = RADEON_CHIPSET_TCL;
650      break;
651
652   case PCI_CHIP_RS480_5954:
653   case PCI_CHIP_RS480_5955:
654   case PCI_CHIP_RS482_5974:
655   case PCI_CHIP_RS482_5975:
656   case PCI_CHIP_RS400_5A41:
657   case PCI_CHIP_RS400_5A42:
658   case PCI_CHIP_RC410_5A61:
659   case PCI_CHIP_RC410_5A62:
660      screen->chip_family = CHIP_FAMILY_RS400;
661      fprintf(stderr, "Warning, xpress200 detected.\n");
662      break;
663
664   default:
665      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
666	      dri_priv->deviceID);
667      return NULL;
668   }
669   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
670       sPriv->ddxMinor < 2) {
671      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
672      return NULL;
673   }
674
675   if (screen->chip_family <= CHIP_FAMILY_RS200)
676      screen->chip_flags |= RADEON_CLASS_R100;
677   else if (screen->chip_family <= CHIP_FAMILY_RV280)
678      screen->chip_flags |= RADEON_CLASS_R200;
679   else
680      screen->chip_flags |= RADEON_CLASS_R300;
681
682   screen->cpp = dri_priv->bpp / 8;
683   screen->AGPMode = dri_priv->AGPMode;
684
685   screen->fbLocation	= ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
686
687   if ( sPriv->drmMinor >= 10 ) {
688      drm_radeon_setparam_t sp;
689
690      sp.param = RADEON_SETPARAM_FB_LOCATION;
691      sp.value = screen->fbLocation;
692
693      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
694		       &sp, sizeof( sp ) );
695   }
696
697   screen->frontOffset	= dri_priv->frontOffset;
698   screen->frontPitch	= dri_priv->frontPitch;
699   screen->backOffset	= dri_priv->backOffset;
700   screen->backPitch	= dri_priv->backPitch;
701   screen->depthOffset	= dri_priv->depthOffset;
702   screen->depthPitch	= dri_priv->depthPitch;
703
704   /* Check if ddx has set up a surface reg to cover depth buffer */
705   screen->depthHasSurface = ((sPriv->ddxMajor > 4) &&
706      (screen->chip_flags & RADEON_CHIPSET_TCL));
707
708   if ( dri_priv->textureSize == 0 ) {
709      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
710      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
711      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
712	 dri_priv->log2GARTTexGran;
713   } else {
714      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
715				               + screen->fbLocation;
716      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
717      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
718	 dri_priv->log2TexGran;
719   }
720
721   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
722	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
723      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
724      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
725      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
726      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
727   } else {
728      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
729      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
730      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
731      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
732	 dri_priv->log2GARTTexGran;
733   }
734
735   if ( glx_enable_extension != NULL ) {
736      if ( screen->irq != 0 ) {
737	 (*glx_enable_extension)( psc, "GLX_SGI_swap_control" );
738	 (*glx_enable_extension)( psc, "GLX_SGI_video_sync" );
739	 (*glx_enable_extension)( psc, "GLX_MESA_swap_control" );
740      }
741
742      (*glx_enable_extension)( psc, "GLX_MESA_swap_frame_usage" );
743      if (IS_R200_CLASS(screen))
744	 (*glx_enable_extension)( psc, "GLX_MESA_allocate_memory" );
745
746      (*glx_enable_extension)( psc, "GLX_MESA_copy_sub_buffer" );
747      (*glx_enable_extension)( psc, "GLX_SGI_make_current_read" );
748   }
749
750#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
751   if (IS_R200_CLASS(screen)) {
752      sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA;
753      sPriv->psc->freeMemory     = (void *) r200FreeMemoryMESA;
754      sPriv->psc->memoryOffset   = (void *) r200GetMemoryOffsetMESA;
755   }
756#endif
757
758   screen->driScreen = sPriv;
759   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
760   return screen;
761}
762
763/* Destroy the device specific screen private data struct.
764 */
765static void
766radeonDestroyScreen( __DRIscreenPrivate *sPriv )
767{
768   radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
769
770   if (!screen)
771      return;
772
773   if ( screen->gartTextures.map ) {
774      drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
775   }
776   drmUnmapBufs( screen->buffers );
777   drmUnmap( screen->status.map, screen->status.size );
778   drmUnmap( screen->mmio.map, screen->mmio.size );
779
780   /* free all option information */
781   driDestroyOptionInfo (&screen->optionCache);
782
783   FREE( screen );
784   sPriv->private = NULL;
785}
786
787
788/* Initialize the driver specific screen private data.
789 */
790static GLboolean
791radeonInitDriver( __DRIscreenPrivate *sPriv )
792{
793   sPriv->private = (void *) radeonCreateScreen( sPriv );
794   if ( !sPriv->private ) {
795      radeonDestroyScreen( sPriv );
796      return GL_FALSE;
797   }
798
799   return GL_TRUE;
800}
801
802
803/**
804 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
805 *
806 * \todo This function (and its interface) will need to be updated to support
807 * pbuffers.
808 */
809static GLboolean
810radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
811                    __DRIdrawablePrivate *driDrawPriv,
812                    const __GLcontextModes *mesaVis,
813                    GLboolean isPixmap )
814{
815   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
816
817   if (isPixmap) {
818      return GL_FALSE; /* not implemented */
819   }
820   else {
821      const GLboolean swDepth = GL_FALSE;
822      const GLboolean swAlpha = GL_FALSE;
823      const GLboolean swAccum = mesaVis->accumRedBits > 0;
824      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
825         mesaVis->depthBits != 24;
826      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
827
828      /* front color renderbuffer */
829      {
830         driRenderbuffer *frontRb
831            = driNewRenderbuffer(GL_RGBA,
832                                 driScrnPriv->pFB + screen->frontOffset,
833                                 screen->cpp,
834                                 screen->frontOffset, screen->frontPitch,
835                                 driDrawPriv);
836         radeonSetSpanFunctions(frontRb, mesaVis);
837         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
838      }
839
840      /* back color renderbuffer */
841      if (mesaVis->doubleBufferMode) {
842         driRenderbuffer *backRb
843            = driNewRenderbuffer(GL_RGBA,
844                                 driScrnPriv->pFB + screen->backOffset,
845                                 screen->cpp,
846                                 screen->backOffset, screen->backPitch,
847                                 driDrawPriv);
848         radeonSetSpanFunctions(backRb, mesaVis);
849         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
850      }
851
852      /* depth renderbuffer */
853      if (mesaVis->depthBits == 16) {
854         driRenderbuffer *depthRb
855            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
856                                 driScrnPriv->pFB + screen->depthOffset,
857                                 screen->cpp,
858                                 screen->depthOffset, screen->depthPitch,
859                                 driDrawPriv);
860         radeonSetSpanFunctions(depthRb, mesaVis);
861         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
862	 depthRb->depthHasSurface = screen->depthHasSurface;
863      }
864      else if (mesaVis->depthBits == 24) {
865         driRenderbuffer *depthRb
866            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
867                                 driScrnPriv->pFB + screen->depthOffset,
868                                 screen->cpp,
869                                 screen->depthOffset, screen->depthPitch,
870                                 driDrawPriv);
871         radeonSetSpanFunctions(depthRb, mesaVis);
872         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
873	 depthRb->depthHasSurface = screen->depthHasSurface;
874      }
875
876      /* stencil renderbuffer */
877      if (mesaVis->stencilBits > 0 && !swStencil) {
878         driRenderbuffer *stencilRb
879            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
880                                 driScrnPriv->pFB + screen->depthOffset,
881                                 screen->cpp,
882                                 screen->depthOffset, screen->depthPitch,
883                                 driDrawPriv);
884         radeonSetSpanFunctions(stencilRb, mesaVis);
885         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
886	 stencilRb->depthHasSurface = screen->depthHasSurface;
887      }
888
889      _mesa_add_soft_renderbuffers(fb,
890                                   GL_FALSE, /* color */
891                                   swDepth,
892                                   swStencil,
893                                   swAccum,
894                                   swAlpha,
895                                   GL_FALSE /* aux */);
896      driDrawPriv->driverPrivate = (void *) fb;
897
898      return (driDrawPriv->driverPrivate != NULL);
899   }
900}
901
902
903static void
904radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
905{
906   _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
907}
908
909#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
910/**
911 * Choose the appropriate CreateContext function based on the chipset.
912 * Eventually, all drivers will go through this process.
913 */
914static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
915				     __DRIcontextPrivate * driContextPriv,
916				     void *sharedContextPriv)
917{
918	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
919	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
920
921	if (IS_R300_CLASS(screen))
922		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
923        return GL_FALSE;
924}
925
926/**
927 * Choose the appropriate DestroyContext function based on the chipset.
928 */
929static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
930{
931	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
932
933	if (IS_R300_CLASS(radeon->radeonScreen))
934		return r300DestroyContext(driContextPriv);
935}
936
937
938#endif
939
940#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
941static struct __DriverAPIRec radeonAPI = {
942   .InitDriver      = radeonInitDriver,
943   .DestroyScreen   = radeonDestroyScreen,
944   .CreateContext   = radeonCreateContext,
945   .DestroyContext  = radeonDestroyContext,
946   .CreateBuffer    = radeonCreateBuffer,
947   .DestroyBuffer   = radeonDestroyBuffer,
948   .SwapBuffers     = radeonSwapBuffers,
949   .MakeCurrent     = radeonMakeCurrent,
950   .UnbindContext   = radeonUnbindContext,
951   .GetSwapInfo     = getSwapInfo,
952   .GetMSC          = driGetMSC32,
953   .WaitForMSC      = driWaitForMSC32,
954   .WaitForSBC      = NULL,
955   .SwapBuffersMSC  = NULL,
956   .CopySubBuffer   = radeonCopySubBuffer,
957#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
958   .setTexOffset    = r300SetTexOffset,
959#endif
960};
961#else
962static const struct __DriverAPIRec r200API = {
963   .InitDriver      = radeonInitDriver,
964   .DestroyScreen   = radeonDestroyScreen,
965   .CreateContext   = r200CreateContext,
966   .DestroyContext  = r200DestroyContext,
967   .CreateBuffer    = radeonCreateBuffer,
968   .DestroyBuffer   = radeonDestroyBuffer,
969   .SwapBuffers     = r200SwapBuffers,
970   .MakeCurrent     = r200MakeCurrent,
971   .UnbindContext   = r200UnbindContext,
972   .GetSwapInfo     = getSwapInfo,
973   .GetMSC          = driGetMSC32,
974   .WaitForMSC      = driWaitForMSC32,
975   .WaitForSBC      = NULL,
976   .SwapBuffersMSC  = NULL,
977   .CopySubBuffer   = r200CopySubBuffer,
978   .setTexOffset    = r200SetTexOffset
979};
980#endif
981
982/**
983 * This is the bootstrap function for the driver.  libGL supplies all of the
984 * requisite information about the system, and the driver initializes itself.
985 * This routine also fills in the linked list pointed to by \c driver_modes
986 * with the \c __GLcontextModes that the driver can support for windows or
987 * pbuffers.
988 *
989 * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on
990 *         failure.
991 */
992PUBLIC void *
993__driCreateNewScreen_20050727( __DRInativeDisplay *dpy,
994                             int scrn, __DRIscreen *psc,
995			     const __GLcontextModes * modes,
996			     const __DRIversion * ddx_version,
997			     const __DRIversion * dri_version,
998			     const __DRIversion * drm_version,
999			     const __DRIframebuffer * frame_buffer,
1000			     drmAddress pSAREA, int fd,
1001			     int internal_api_version,
1002			     const __DRIinterfaceMethods * interface,
1003			     __GLcontextModes ** driver_modes )
1004{
1005   __DRIscreenPrivate *psp;
1006#if !RADEON_COMMON
1007   static const char *driver_name = "Radeon";
1008   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1009   static const __DRIversion dri_expected = { 4, 0, 0 };
1010   static const __DRIversion drm_expected = { 1, 6, 0 };
1011#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1012   static const char *driver_name = "R200";
1013   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1014   static const __DRIversion dri_expected = { 4, 0, 0 };
1015   static const __DRIversion drm_expected = { 1, 6, 0 };
1016#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1017   static const char *driver_name = "R300";
1018   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1019   static const __DRIversion dri_expected = { 4, 0, 0 };
1020   static const __DRIversion drm_expected = { 1, 24, 0 };
1021#endif
1022
1023   dri_interface = interface;
1024
1025   if ( ! driCheckDriDdxDrmVersions3( driver_name,
1026				      dri_version, & dri_expected,
1027				      ddx_version, & ddx_expected,
1028				      drm_version, & drm_expected ) ) {
1029      return NULL;
1030   }
1031#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1032   psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
1033				  ddx_version, dri_version, drm_version,
1034				  frame_buffer, pSAREA, fd,
1035				  internal_api_version, &radeonAPI);
1036#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1037   psp = __driUtilCreateNewScreen(dpy, scrn, psc, NULL,
1038				  ddx_version, dri_version, drm_version,
1039				  frame_buffer, pSAREA, fd,
1040				  internal_api_version, &r200API);
1041#endif
1042
1043   if ( psp != NULL ) {
1044      RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1045      if (driver_modes) {
1046         *driver_modes = radeonFillInModes( dri_priv->bpp,
1047                                            (dri_priv->bpp == 16) ? 16 : 24,
1048                                            (dri_priv->bpp == 16) ? 0  : 8,
1049                                            (dri_priv->backOffset != dri_priv->depthOffset) );
1050      }
1051
1052      /* Calling driInitExtensions here, with a NULL context pointer,
1053       * does not actually enable the extensions.  It just makes sure
1054       * that all the dispatch offsets for all the extensions that
1055       * *might* be enables are known.  This is needed because the
1056       * dispatch offsets need to be known when _mesa_context_create
1057       * is called, but we can't enable the extensions until we have a
1058       * context pointer.
1059       *
1060       * Hello chicken.  Hello egg.  How are you two today?
1061       */
1062      driInitExtensions( NULL, card_extensions, GL_FALSE );
1063#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1064      driInitExtensions( NULL, blend_extensions, GL_FALSE );
1065      driInitSingleExtension( NULL, ARB_vp_extension );
1066      driInitSingleExtension( NULL, NV_vp_extension );
1067      driInitSingleExtension( NULL, ATI_fs_extension );
1068      driInitExtensions( NULL, point_extensions, GL_FALSE );
1069#endif
1070   }
1071
1072   return (void *) psp;
1073}
1074
1075
1076/**
1077 * Get information about previous buffer swaps.
1078 */
1079static int
1080getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1081{
1082#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1083   radeonContextPtr  rmesa;
1084#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1085   r200ContextPtr  rmesa;
1086#endif
1087
1088   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1089	|| (dPriv->driContextPriv->driverPrivate == NULL)
1090	|| (sInfo == NULL) ) {
1091      return -1;
1092   }
1093
1094   rmesa = dPriv->driContextPriv->driverPrivate;
1095   sInfo->swap_count = rmesa->swap_count;
1096   sInfo->swap_ust = rmesa->swap_ust;
1097   sInfo->swap_missed_count = rmesa->swap_missed_count;
1098
1099   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1100       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1101       : 0.0;
1102
1103   return 0;
1104}
1105