radeon_screen.c revision 863c76a7bb0ecf0cd492d9ddb0dcac8e12da75e0
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44 45#define STANDALONE_MMIO 46#include "radeon_chipset.h" 47#include "radeon_macros.h" 48#include "radeon_screen.h" 49#include "radeon_common.h" 50#include "radeon_span.h" 51#if !RADEON_COMMON 52#include "radeon_context.h" 53#include "radeon_tex.h" 54#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 55#include "r200_context.h" 56#include "r200_ioctl.h" 57#include "r200_tex.h" 58#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 59#include "r300_context.h" 60#include "r300_fragprog.h" 61#include "r300_tex.h" 62#endif 63 64#include "utils.h" 65#include "vblank.h" 66#include "drirenderbuffer.h" 67 68#include "radeon_bocs_wrapper.h" 69 70#include "GL/internal/dri_interface.h" 71 72/* Radeon configuration 73 */ 74#include "xmlpool.h" 75 76#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 77DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 78 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 79 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 80DRI_CONF_OPT_END 81 82#if !RADEON_COMMON /* R100 */ 83PUBLIC const char __driConfigOptions[] = 84DRI_CONF_BEGIN 85 DRI_CONF_SECTION_PERFORMANCE 86 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 87 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 88 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 89 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 90 DRI_CONF_HYPERZ(false) 91 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 92 DRI_CONF_SECTION_END 93 DRI_CONF_SECTION_QUALITY 94 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 95 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 96 DRI_CONF_NO_NEG_LOD_BIAS(false) 97 DRI_CONF_FORCE_S3TC_ENABLE(false) 98 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 99 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 100 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 101 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 102 DRI_CONF_SECTION_END 103 DRI_CONF_SECTION_DEBUG 104 DRI_CONF_NO_RAST(false) 105 DRI_CONF_SECTION_END 106DRI_CONF_END; 107static const GLuint __driNConfigOptions = 15; 108 109#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 110 111PUBLIC const char __driConfigOptions[] = 112DRI_CONF_BEGIN 113 DRI_CONF_SECTION_PERFORMANCE 114 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 115 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 116 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 117 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 118 DRI_CONF_HYPERZ(false) 119 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 120 DRI_CONF_SECTION_END 121 DRI_CONF_SECTION_QUALITY 122 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 123 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 124 DRI_CONF_NO_NEG_LOD_BIAS(false) 125 DRI_CONF_FORCE_S3TC_ENABLE(false) 126 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 127 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 128 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 129 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 130 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 131 DRI_CONF_SECTION_END 132 DRI_CONF_SECTION_DEBUG 133 DRI_CONF_NO_RAST(false) 134 DRI_CONF_SECTION_END 135 DRI_CONF_SECTION_SOFTWARE 136 DRI_CONF_NV_VERTEX_PROGRAM(false) 137 DRI_CONF_SECTION_END 138DRI_CONF_END; 139static const GLuint __driNConfigOptions = 17; 140 141extern const struct dri_extension blend_extensions[]; 142extern const struct dri_extension ARB_vp_extension[]; 143extern const struct dri_extension NV_vp_extension[]; 144extern const struct dri_extension ATI_fs_extension[]; 145extern const struct dri_extension point_extensions[]; 146 147#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 148 149/* TODO: integrate these into xmlpool.h! */ 150#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 151DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 152 DRI_CONF_DESC(en,"Number of texture image units") \ 153 DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 154DRI_CONF_OPT_END 155 156#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 157DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 158 DRI_CONF_DESC(en,"Number of texture coordinate units") \ 159 DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 160DRI_CONF_OPT_END 161 162 163 164#define DRI_CONF_DISABLE_S3TC(def) \ 165DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 166 DRI_CONF_DESC(en,"Disable S3TC compression") \ 167DRI_CONF_OPT_END 168 169#define DRI_CONF_DISABLE_FALLBACK(def) \ 170DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 171 DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 172DRI_CONF_OPT_END 173 174#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 175DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 176 DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 177DRI_CONF_OPT_END 178 179#define DRI_CONF_FP_OPTIMIZATION(def) \ 180DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 181 DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 182 DRI_CONF_ENUM(0,"Optimize for Speed") \ 183 DRI_CONF_ENUM(1,"Optimize for Quality") \ 184 DRI_CONF_DESC_END \ 185DRI_CONF_OPT_END 186 187PUBLIC const char __driConfigOptions[] = 188DRI_CONF_BEGIN 189 DRI_CONF_SECTION_PERFORMANCE 190 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 191 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 192 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 193 DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 194 DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 195 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 196 DRI_CONF_DISABLE_FALLBACK(true) 197 DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 198 DRI_CONF_SECTION_END 199 DRI_CONF_SECTION_QUALITY 200 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 201 DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 202 DRI_CONF_FORCE_S3TC_ENABLE(false) 203 DRI_CONF_DISABLE_S3TC(false) 204 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 205 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 206 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 207 DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 208 DRI_CONF_SECTION_END 209 DRI_CONF_SECTION_DEBUG 210 DRI_CONF_NO_RAST(false) 211 DRI_CONF_SECTION_END 212DRI_CONF_END; 213static const GLuint __driNConfigOptions = 17; 214 215extern const struct dri_extension gl_20_extension[]; 216 217#ifndef RADEON_DEBUG 218 219static const struct dri_debug_control debug_control[] = { 220 {"fall", DEBUG_FALLBACKS}, 221 {"tex", DEBUG_TEXTURE}, 222 {"ioctl", DEBUG_IOCTL}, 223 {"prim", DEBUG_PRIMS}, 224 {"vert", DEBUG_VERTS}, 225 {"state", DEBUG_STATE}, 226 {"code", DEBUG_CODEGEN}, 227 {"vfmt", DEBUG_VFMT}, 228 {"vtxf", DEBUG_VFMT}, 229 {"verb", DEBUG_VERBOSE}, 230 {"dri", DEBUG_DRI}, 231 {"dma", DEBUG_DMA}, 232 {"san", DEBUG_SANITY}, 233 {"sync", DEBUG_SYNC}, 234 {"pix", DEBUG_PIXEL}, 235 {"mem", DEBUG_MEMORY}, 236 {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 237 {NULL, 0} 238}; 239#endif /* RADEON_DEBUG */ 240 241#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 242 243extern const struct dri_extension card_extensions[]; 244 245static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 246 247static int 248radeonGetParam(int fd, int param, void *value) 249{ 250 int ret; 251 drm_radeon_getparam_t gp; 252 253 gp.param = param; 254 gp.value = value; 255 256 ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 257 return ret; 258} 259 260static const __DRIconfig ** 261radeonFillInModes( __DRIscreenPrivate *psp, 262 unsigned pixel_bits, unsigned depth_bits, 263 unsigned stencil_bits, GLboolean have_back_buffer ) 264{ 265 __DRIconfig **configs; 266 __GLcontextModes *m; 267 unsigned depth_buffer_factor; 268 unsigned back_buffer_factor; 269 GLenum fb_format; 270 GLenum fb_type; 271 int i; 272 273 /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 274 * enough to add support. Basically, if a context is created with an 275 * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 276 * will never be used. 277 */ 278 static const GLenum back_buffer_modes[] = { 279 GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 280 }; 281 282 uint8_t depth_bits_array[2]; 283 uint8_t stencil_bits_array[2]; 284 uint8_t msaa_samples_array[1]; 285 286 depth_bits_array[0] = depth_bits; 287 depth_bits_array[1] = depth_bits; 288 289 /* Just like with the accumulation buffer, always provide some modes 290 * with a stencil buffer. It will be a sw fallback, but some apps won't 291 * care about that. 292 */ 293 stencil_bits_array[0] = 0; 294 stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 295 296 msaa_samples_array[0] = 0; 297 298 depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 299 back_buffer_factor = (have_back_buffer) ? 2 : 1; 300 301 if ( pixel_bits == 16 ) { 302 fb_format = GL_RGB; 303 fb_type = GL_UNSIGNED_SHORT_5_6_5; 304 } 305 else { 306 fb_format = GL_BGRA; 307 fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 308 } 309 310 configs = driCreateConfigs(fb_format, fb_type, 311 depth_bits_array, stencil_bits_array, 312 depth_buffer_factor, 313 back_buffer_modes, back_buffer_factor, 314 msaa_samples_array, 1); 315 if (configs == NULL) { 316 fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 317 __func__, __LINE__ ); 318 return NULL; 319 } 320 321 /* Mark the visual as slow if there are "fake" stencil bits. 322 */ 323 for (i = 0; configs[i]; i++) { 324 m = &configs[i]->modes; 325 if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 326 m->visualRating = GLX_SLOW_CONFIG; 327 } 328 } 329 330 return (const __DRIconfig **) configs; 331} 332 333#if !RADEON_COMMON 334static const __DRItexOffsetExtension radeonTexOffsetExtension = { 335 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 336 radeonSetTexOffset, 337}; 338#endif 339 340#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 341static const __DRIallocateExtension r200AllocateExtension = { 342 { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 343 r200AllocateMemoryMESA, 344 r200FreeMemoryMESA, 345 r200GetMemoryOffsetMESA 346}; 347 348static const __DRItexOffsetExtension r200texOffsetExtension = { 349 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 350 r200SetTexOffset, 351}; 352#endif 353 354#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 355static const __DRItexOffsetExtension r300texOffsetExtension = { 356 { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 357 r300SetTexOffset, 358}; 359 360static const __DRItexBufferExtension r300TexBufferExtension = { 361 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 362 r300SetTexBuffer, 363}; 364#endif 365 366static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 367{ 368 screen->chip_flags = 0; 369 switch ( device_id ) { 370 case PCI_CHIP_RADEON_LY: 371 case PCI_CHIP_RADEON_LZ: 372 case PCI_CHIP_RADEON_QY: 373 case PCI_CHIP_RADEON_QZ: 374 case PCI_CHIP_RN50_515E: 375 case PCI_CHIP_RN50_5969: 376 screen->chip_family = CHIP_FAMILY_RV100; 377 break; 378 379 case PCI_CHIP_RS100_4136: 380 case PCI_CHIP_RS100_4336: 381 screen->chip_family = CHIP_FAMILY_RS100; 382 break; 383 384 case PCI_CHIP_RS200_4137: 385 case PCI_CHIP_RS200_4337: 386 case PCI_CHIP_RS250_4237: 387 case PCI_CHIP_RS250_4437: 388 screen->chip_family = CHIP_FAMILY_RS200; 389 break; 390 391 case PCI_CHIP_RADEON_QD: 392 case PCI_CHIP_RADEON_QE: 393 case PCI_CHIP_RADEON_QF: 394 case PCI_CHIP_RADEON_QG: 395 /* all original radeons (7200) presumably have a stencil op bug */ 396 screen->chip_family = CHIP_FAMILY_R100; 397 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 398 break; 399 400 case PCI_CHIP_RV200_QW: 401 case PCI_CHIP_RV200_QX: 402 case PCI_CHIP_RADEON_LW: 403 case PCI_CHIP_RADEON_LX: 404 screen->chip_family = CHIP_FAMILY_RV200; 405 screen->chip_flags = RADEON_CHIPSET_TCL; 406 break; 407 408 case PCI_CHIP_R200_BB: 409 case PCI_CHIP_R200_BC: 410 case PCI_CHIP_R200_QH: 411 case PCI_CHIP_R200_QL: 412 case PCI_CHIP_R200_QM: 413 screen->chip_family = CHIP_FAMILY_R200; 414 screen->chip_flags = RADEON_CHIPSET_TCL; 415 break; 416 417 case PCI_CHIP_RV250_If: 418 case PCI_CHIP_RV250_Ig: 419 case PCI_CHIP_RV250_Ld: 420 case PCI_CHIP_RV250_Lf: 421 case PCI_CHIP_RV250_Lg: 422 screen->chip_family = CHIP_FAMILY_RV250; 423 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 424 break; 425 426 case PCI_CHIP_RV280_5960: 427 case PCI_CHIP_RV280_5961: 428 case PCI_CHIP_RV280_5962: 429 case PCI_CHIP_RV280_5964: 430 case PCI_CHIP_RV280_5965: 431 case PCI_CHIP_RV280_5C61: 432 case PCI_CHIP_RV280_5C63: 433 screen->chip_family = CHIP_FAMILY_RV280; 434 screen->chip_flags = RADEON_CHIPSET_TCL; 435 break; 436 437 case PCI_CHIP_RS300_5834: 438 case PCI_CHIP_RS300_5835: 439 case PCI_CHIP_RS350_7834: 440 case PCI_CHIP_RS350_7835: 441 screen->chip_family = CHIP_FAMILY_RS300; 442 break; 443 444 /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 445 case PCI_CHIP_R300_AD: 446 screen->chip_family = CHIP_FAMILY_RV350; 447 screen->chip_flags = RADEON_CHIPSET_TCL; 448 break; 449 case PCI_CHIP_R300_AE: 450 case PCI_CHIP_R300_AF: 451 case PCI_CHIP_R300_AG: 452 case PCI_CHIP_R300_ND: 453 case PCI_CHIP_R300_NE: 454 case PCI_CHIP_R300_NF: 455 case PCI_CHIP_R300_NG: 456 screen->chip_family = CHIP_FAMILY_R300; 457 screen->chip_flags = RADEON_CHIPSET_TCL; 458 break; 459 460 case PCI_CHIP_RV350_AP: 461 case PCI_CHIP_RV350_AQ: 462 case PCI_CHIP_RV350_AR: 463 case PCI_CHIP_RV350_AS: 464 case PCI_CHIP_RV350_AT: 465 case PCI_CHIP_RV350_AV: 466 case PCI_CHIP_RV350_AU: 467 case PCI_CHIP_RV350_NP: 468 case PCI_CHIP_RV350_NQ: 469 case PCI_CHIP_RV350_NR: 470 case PCI_CHIP_RV350_NS: 471 case PCI_CHIP_RV350_NT: 472 case PCI_CHIP_RV350_NV: 473 screen->chip_family = CHIP_FAMILY_RV350; 474 screen->chip_flags = RADEON_CHIPSET_TCL; 475 break; 476 477 case PCI_CHIP_R350_AH: 478 case PCI_CHIP_R350_AI: 479 case PCI_CHIP_R350_AJ: 480 case PCI_CHIP_R350_AK: 481 case PCI_CHIP_R350_NH: 482 case PCI_CHIP_R350_NI: 483 case PCI_CHIP_R360_NJ: 484 case PCI_CHIP_R350_NK: 485 screen->chip_family = CHIP_FAMILY_R350; 486 screen->chip_flags = RADEON_CHIPSET_TCL; 487 break; 488 489 case PCI_CHIP_RV370_5460: 490 case PCI_CHIP_RV370_5462: 491 case PCI_CHIP_RV370_5464: 492 case PCI_CHIP_RV370_5B60: 493 case PCI_CHIP_RV370_5B62: 494 case PCI_CHIP_RV370_5B63: 495 case PCI_CHIP_RV370_5B64: 496 case PCI_CHIP_RV370_5B65: 497 case PCI_CHIP_RV380_3150: 498 case PCI_CHIP_RV380_3152: 499 case PCI_CHIP_RV380_3154: 500 case PCI_CHIP_RV380_3E50: 501 case PCI_CHIP_RV380_3E54: 502 screen->chip_family = CHIP_FAMILY_RV380; 503 screen->chip_flags = RADEON_CHIPSET_TCL; 504 break; 505 506 case PCI_CHIP_R420_JN: 507 case PCI_CHIP_R420_JH: 508 case PCI_CHIP_R420_JI: 509 case PCI_CHIP_R420_JJ: 510 case PCI_CHIP_R420_JK: 511 case PCI_CHIP_R420_JL: 512 case PCI_CHIP_R420_JM: 513 case PCI_CHIP_R420_JO: 514 case PCI_CHIP_R420_JP: 515 case PCI_CHIP_R420_JT: 516 case PCI_CHIP_R481_4B49: 517 case PCI_CHIP_R481_4B4A: 518 case PCI_CHIP_R481_4B4B: 519 case PCI_CHIP_R481_4B4C: 520 case PCI_CHIP_R423_UH: 521 case PCI_CHIP_R423_UI: 522 case PCI_CHIP_R423_UJ: 523 case PCI_CHIP_R423_UK: 524 case PCI_CHIP_R430_554C: 525 case PCI_CHIP_R430_554D: 526 case PCI_CHIP_R430_554E: 527 case PCI_CHIP_R430_554F: 528 case PCI_CHIP_R423_5550: 529 case PCI_CHIP_R423_UQ: 530 case PCI_CHIP_R423_UR: 531 case PCI_CHIP_R423_UT: 532 case PCI_CHIP_R430_5D48: 533 case PCI_CHIP_R430_5D49: 534 case PCI_CHIP_R430_5D4A: 535 case PCI_CHIP_R480_5D4C: 536 case PCI_CHIP_R480_5D4D: 537 case PCI_CHIP_R480_5D4E: 538 case PCI_CHIP_R480_5D4F: 539 case PCI_CHIP_R480_5D50: 540 case PCI_CHIP_R480_5D52: 541 case PCI_CHIP_R423_5D57: 542 screen->chip_family = CHIP_FAMILY_R420; 543 screen->chip_flags = RADEON_CHIPSET_TCL; 544 break; 545 546 case PCI_CHIP_RV410_5E4C: 547 case PCI_CHIP_RV410_5E4F: 548 case PCI_CHIP_RV410_564A: 549 case PCI_CHIP_RV410_564B: 550 case PCI_CHIP_RV410_564F: 551 case PCI_CHIP_RV410_5652: 552 case PCI_CHIP_RV410_5653: 553 case PCI_CHIP_RV410_5657: 554 case PCI_CHIP_RV410_5E48: 555 case PCI_CHIP_RV410_5E4A: 556 case PCI_CHIP_RV410_5E4B: 557 case PCI_CHIP_RV410_5E4D: 558 screen->chip_family = CHIP_FAMILY_RV410; 559 screen->chip_flags = RADEON_CHIPSET_TCL; 560 break; 561 562 case PCI_CHIP_RS480_5954: 563 case PCI_CHIP_RS480_5955: 564 case PCI_CHIP_RS482_5974: 565 case PCI_CHIP_RS482_5975: 566 case PCI_CHIP_RS400_5A41: 567 case PCI_CHIP_RS400_5A42: 568 case PCI_CHIP_RC410_5A61: 569 case PCI_CHIP_RC410_5A62: 570 screen->chip_family = CHIP_FAMILY_RS400; 571 break; 572 573 case PCI_CHIP_RS600_793F: 574 case PCI_CHIP_RS600_7941: 575 case PCI_CHIP_RS600_7942: 576 screen->chip_family = CHIP_FAMILY_RS600; 577 break; 578 579 case PCI_CHIP_RS690_791E: 580 case PCI_CHIP_RS690_791F: 581 screen->chip_family = CHIP_FAMILY_RS690; 582 break; 583 case PCI_CHIP_RS740_796C: 584 case PCI_CHIP_RS740_796D: 585 case PCI_CHIP_RS740_796E: 586 case PCI_CHIP_RS740_796F: 587 screen->chip_family = CHIP_FAMILY_RS740; 588 break; 589 590 case PCI_CHIP_R520_7100: 591 case PCI_CHIP_R520_7101: 592 case PCI_CHIP_R520_7102: 593 case PCI_CHIP_R520_7103: 594 case PCI_CHIP_R520_7104: 595 case PCI_CHIP_R520_7105: 596 case PCI_CHIP_R520_7106: 597 case PCI_CHIP_R520_7108: 598 case PCI_CHIP_R520_7109: 599 case PCI_CHIP_R520_710A: 600 case PCI_CHIP_R520_710B: 601 case PCI_CHIP_R520_710C: 602 case PCI_CHIP_R520_710E: 603 case PCI_CHIP_R520_710F: 604 screen->chip_family = CHIP_FAMILY_R520; 605 screen->chip_flags = RADEON_CHIPSET_TCL; 606 break; 607 608 case PCI_CHIP_RV515_7140: 609 case PCI_CHIP_RV515_7141: 610 case PCI_CHIP_RV515_7142: 611 case PCI_CHIP_RV515_7143: 612 case PCI_CHIP_RV515_7144: 613 case PCI_CHIP_RV515_7145: 614 case PCI_CHIP_RV515_7146: 615 case PCI_CHIP_RV515_7147: 616 case PCI_CHIP_RV515_7149: 617 case PCI_CHIP_RV515_714A: 618 case PCI_CHIP_RV515_714B: 619 case PCI_CHIP_RV515_714C: 620 case PCI_CHIP_RV515_714D: 621 case PCI_CHIP_RV515_714E: 622 case PCI_CHIP_RV515_714F: 623 case PCI_CHIP_RV515_7151: 624 case PCI_CHIP_RV515_7152: 625 case PCI_CHIP_RV515_7153: 626 case PCI_CHIP_RV515_715E: 627 case PCI_CHIP_RV515_715F: 628 case PCI_CHIP_RV515_7180: 629 case PCI_CHIP_RV515_7181: 630 case PCI_CHIP_RV515_7183: 631 case PCI_CHIP_RV515_7186: 632 case PCI_CHIP_RV515_7187: 633 case PCI_CHIP_RV515_7188: 634 case PCI_CHIP_RV515_718A: 635 case PCI_CHIP_RV515_718B: 636 case PCI_CHIP_RV515_718C: 637 case PCI_CHIP_RV515_718D: 638 case PCI_CHIP_RV515_718F: 639 case PCI_CHIP_RV515_7193: 640 case PCI_CHIP_RV515_7196: 641 case PCI_CHIP_RV515_719B: 642 case PCI_CHIP_RV515_719F: 643 case PCI_CHIP_RV515_7200: 644 case PCI_CHIP_RV515_7210: 645 case PCI_CHIP_RV515_7211: 646 screen->chip_family = CHIP_FAMILY_RV515; 647 screen->chip_flags = RADEON_CHIPSET_TCL; 648 break; 649 650 case PCI_CHIP_RV530_71C0: 651 case PCI_CHIP_RV530_71C1: 652 case PCI_CHIP_RV530_71C2: 653 case PCI_CHIP_RV530_71C3: 654 case PCI_CHIP_RV530_71C4: 655 case PCI_CHIP_RV530_71C5: 656 case PCI_CHIP_RV530_71C6: 657 case PCI_CHIP_RV530_71C7: 658 case PCI_CHIP_RV530_71CD: 659 case PCI_CHIP_RV530_71CE: 660 case PCI_CHIP_RV530_71D2: 661 case PCI_CHIP_RV530_71D4: 662 case PCI_CHIP_RV530_71D5: 663 case PCI_CHIP_RV530_71D6: 664 case PCI_CHIP_RV530_71DA: 665 case PCI_CHIP_RV530_71DE: 666 screen->chip_family = CHIP_FAMILY_RV530; 667 screen->chip_flags = RADEON_CHIPSET_TCL; 668 break; 669 670 case PCI_CHIP_R580_7240: 671 case PCI_CHIP_R580_7243: 672 case PCI_CHIP_R580_7244: 673 case PCI_CHIP_R580_7245: 674 case PCI_CHIP_R580_7246: 675 case PCI_CHIP_R580_7247: 676 case PCI_CHIP_R580_7248: 677 case PCI_CHIP_R580_7249: 678 case PCI_CHIP_R580_724A: 679 case PCI_CHIP_R580_724B: 680 case PCI_CHIP_R580_724C: 681 case PCI_CHIP_R580_724D: 682 case PCI_CHIP_R580_724E: 683 case PCI_CHIP_R580_724F: 684 case PCI_CHIP_R580_7284: 685 screen->chip_family = CHIP_FAMILY_R580; 686 screen->chip_flags = RADEON_CHIPSET_TCL; 687 break; 688 689 case PCI_CHIP_RV570_7280: 690 case PCI_CHIP_RV560_7281: 691 case PCI_CHIP_RV560_7283: 692 case PCI_CHIP_RV560_7287: 693 case PCI_CHIP_RV570_7288: 694 case PCI_CHIP_RV570_7289: 695 case PCI_CHIP_RV570_728B: 696 case PCI_CHIP_RV570_728C: 697 case PCI_CHIP_RV560_7290: 698 case PCI_CHIP_RV560_7291: 699 case PCI_CHIP_RV560_7293: 700 case PCI_CHIP_RV560_7297: 701 screen->chip_family = CHIP_FAMILY_RV560; 702 screen->chip_flags = RADEON_CHIPSET_TCL; 703 break; 704 705 default: 706 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 707 device_id); 708 return -1; 709 } 710 711 return 0; 712} 713 714 715/* Create the device specific screen private data struct. 716 */ 717static radeonScreenPtr 718radeonCreateScreen( __DRIscreenPrivate *sPriv ) 719{ 720 radeonScreenPtr screen; 721 RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 722 unsigned char *RADEONMMIO = NULL; 723 int i; 724 int ret; 725 uint32_t temp; 726 727 if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 728 fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 729 return GL_FALSE; 730 } 731 732 /* Allocate the private area */ 733 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 734 if ( !screen ) { 735 __driUtilMessage("%s: Could not allocate memory for screen structure", 736 __FUNCTION__); 737 return NULL; 738 } 739 740#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 741 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 742#endif 743 744 /* parse information in __driConfigOptions */ 745 driParseOptionInfo (&screen->optionCache, 746 __driConfigOptions, __driNConfigOptions); 747 748 /* This is first since which regions we map depends on whether or 749 * not we are using a PCI card. 750 */ 751 screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 752 { 753 int ret; 754 755#ifdef RADEON_PARAM_KERNEL_MM 756 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM, 757 &screen->kernel_mm); 758 759 if (ret && ret != -EINVAL) { 760 FREE( screen ); 761 fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret); 762 return NULL; 763 } 764 765 if (ret == -EINVAL) 766 screen->kernel_mm = 0; 767#endif 768 769 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 770 &screen->gart_buffer_offset); 771 772 if (ret) { 773 FREE( screen ); 774 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 775 return NULL; 776 } 777 778 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 779 &screen->gart_base); 780 if (ret) { 781 FREE( screen ); 782 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 783 return NULL; 784 } 785 786 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 787 &screen->irq); 788 if (ret) { 789 FREE( screen ); 790 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 791 return NULL; 792 } 793 screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 794 screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 795 screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 796 screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 797 screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 798 screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 799 screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 800 } 801 802 if (!screen->kernel_mm) { 803 screen->mmio.handle = dri_priv->registerHandle; 804 screen->mmio.size = dri_priv->registerSize; 805 if ( drmMap( sPriv->fd, 806 screen->mmio.handle, 807 screen->mmio.size, 808 &screen->mmio.map ) ) { 809 FREE( screen ); 810 __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 811 return NULL; 812 } 813 814 RADEONMMIO = screen->mmio.map; 815 816 screen->status.handle = dri_priv->statusHandle; 817 screen->status.size = dri_priv->statusSize; 818 if ( drmMap( sPriv->fd, 819 screen->status.handle, 820 screen->status.size, 821 &screen->status.map ) ) { 822 drmUnmap( screen->mmio.map, screen->mmio.size ); 823 FREE( screen ); 824 __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 825 return NULL; 826 } 827 screen->scratch = (__volatile__ uint32_t *) 828 ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 829 830 screen->buffers = drmMapBufs( sPriv->fd ); 831 if ( !screen->buffers ) { 832 drmUnmap( screen->status.map, screen->status.size ); 833 drmUnmap( screen->mmio.map, screen->mmio.size ); 834 FREE( screen ); 835 __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 836 return NULL; 837 } 838 839 if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 840 screen->gartTextures.handle = dri_priv->gartTexHandle; 841 screen->gartTextures.size = dri_priv->gartTexMapSize; 842 if ( drmMap( sPriv->fd, 843 screen->gartTextures.handle, 844 screen->gartTextures.size, 845 (drmAddressPtr)&screen->gartTextures.map ) ) { 846 drmUnmapBufs( screen->buffers ); 847 drmUnmap( screen->status.map, screen->status.size ); 848 drmUnmap( screen->mmio.map, screen->mmio.size ); 849 FREE( screen ); 850 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 851 return NULL; 852 } 853 854 screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 855 } 856 } 857 858 859 ret = radeon_set_screen_flags(screen, dri_priv->deviceID); 860 if (ret == -1) 861 return NULL; 862 863 if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 864 sPriv->ddx_version.minor < 2) { 865 fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 866 return NULL; 867 } 868 869 if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) { 870 fprintf(stderr, "R500 support requires a newer drm.\n"); 871 return NULL; 872 } 873 874 if (getenv("R300_NO_TCL")) 875 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 876 877 if (screen->chip_family <= CHIP_FAMILY_RS200) 878 screen->chip_flags |= RADEON_CLASS_R100; 879 else if (screen->chip_family <= CHIP_FAMILY_RV280) 880 screen->chip_flags |= RADEON_CLASS_R200; 881 else 882 screen->chip_flags |= RADEON_CLASS_R300; 883 884 screen->cpp = dri_priv->bpp / 8; 885 screen->AGPMode = dri_priv->AGPMode; 886 887 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 888 &temp); 889 if (ret) { 890 if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm) 891 screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 892 else { 893 FREE( screen ); 894 fprintf(stderr, "Unable to get fb location need newer drm\n"); 895 return NULL; 896 } 897 } else { 898 screen->fbLocation = (temp & 0xffff) << 16; 899 } 900 901 if (screen->chip_family >= CHIP_FAMILY_R300) { 902 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES, 903 &temp); 904 if (ret) { 905 fprintf(stderr, "Unable to get num_pipes, need newer drm\n"); 906 switch (screen->chip_family) { 907 case CHIP_FAMILY_R300: 908 case CHIP_FAMILY_R350: 909 screen->num_gb_pipes = 2; 910 break; 911 case CHIP_FAMILY_R420: 912 case CHIP_FAMILY_R520: 913 case CHIP_FAMILY_R580: 914 case CHIP_FAMILY_RV560: 915 case CHIP_FAMILY_RV570: 916 screen->num_gb_pipes = 4; 917 break; 918 case CHIP_FAMILY_RV350: 919 case CHIP_FAMILY_RV515: 920 case CHIP_FAMILY_RV530: 921 case CHIP_FAMILY_RV410: 922 default: 923 screen->num_gb_pipes = 1; 924 break; 925 } 926 } else { 927 screen->num_gb_pipes = temp; 928 } 929 } 930 931 if ( sPriv->drm_version.minor >= 10 ) { 932 drm_radeon_setparam_t sp; 933 934 sp.param = RADEON_SETPARAM_FB_LOCATION; 935 sp.value = screen->fbLocation; 936 937 drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 938 &sp, sizeof( sp ) ); 939 } 940 941 screen->frontOffset = dri_priv->frontOffset; 942 screen->frontPitch = dri_priv->frontPitch; 943 screen->backOffset = dri_priv->backOffset; 944 screen->backPitch = dri_priv->backPitch; 945 screen->depthOffset = dri_priv->depthOffset; 946 screen->depthPitch = dri_priv->depthPitch; 947 948 /* Check if ddx has set up a surface reg to cover depth buffer */ 949 screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 950 /* these chips don't use tiled z without hyperz. So always pretend 951 we have set up a surface which will cause linear reads/writes */ 952 (IS_R100_CLASS(screen) && 953 !(screen->chip_flags & RADEON_CHIPSET_TCL)); 954 955 if ( dri_priv->textureSize == 0 ) { 956 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 957 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 958 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 959 dri_priv->log2GARTTexGran; 960 } else { 961 screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 962 + screen->fbLocation; 963 screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 964 screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 965 dri_priv->log2TexGran; 966 } 967 968 if ( !screen->gartTextures.map || dri_priv->textureSize == 0 969 || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 970 screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 971 screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 972 screen->texSize[RADEON_GART_TEX_HEAP] = 0; 973 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 974 } else { 975 screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 976 screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 977 screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 978 screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 979 dri_priv->log2GARTTexGran; 980 } 981 982 i = 0; 983 screen->extensions[i++] = &driCopySubBufferExtension.base; 984 screen->extensions[i++] = &driFrameTrackingExtension.base; 985 screen->extensions[i++] = &driReadDrawableExtension; 986 987 if ( screen->irq != 0 ) { 988 screen->extensions[i++] = &driSwapControlExtension.base; 989 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 990 } 991 992 if (!screen->kernel_mm) { 993#if !RADEON_COMMON 994 screen->extensions[i++] = &radeonTexOffsetExtension.base; 995#endif 996 997#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 998 if (IS_R200_CLASS(screen)) 999 screen->extensions[i++] = &r200AllocateExtension.base; 1000 1001 screen->extensions[i++] = &r200texOffsetExtension.base; 1002#endif 1003 1004#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1005 screen->extensions[i++] = &r300texOffsetExtension.base; 1006#endif 1007 } 1008 1009 screen->extensions[i++] = NULL; 1010 sPriv->extensions = screen->extensions; 1011 1012 screen->driScreen = sPriv; 1013 screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 1014 screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA + 1015 screen->sarea_priv_offset); 1016 1017 if (screen->kernel_mm) 1018 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1019 else 1020 screen->bom = radeon_bo_manager_legacy_ctor(screen); 1021 if (screen->bom == NULL) { 1022 free(screen); 1023 return NULL; 1024 } 1025 1026 return screen; 1027} 1028 1029static radeonScreenPtr 1030radeonCreateScreen2(__DRIscreenPrivate *sPriv) 1031{ 1032 radeonScreenPtr screen; 1033 int i; 1034 int ret; 1035 uint32_t device_id; 1036 1037 /* Allocate the private area */ 1038 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1039 if ( !screen ) { 1040 __driUtilMessage("%s: Could not allocate memory for screen structure", 1041 __FUNCTION__); 1042 fprintf(stderr, "leaving here\n"); 1043 return NULL; 1044 } 1045 1046#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1047 RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 1048#endif 1049 1050 /* parse information in __driConfigOptions */ 1051 driParseOptionInfo (&screen->optionCache, 1052 __driConfigOptions, __driNConfigOptions); 1053 1054 screen->kernel_mm = 1; 1055 screen->chip_flags = 0; 1056 1057 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 1058 &screen->irq); 1059 1060 ret = radeonGetParam( sPriv->fd, RADEON_PARAM_DEVICE_ID, 1061 &device_id); 1062 if (ret) { 1063 FREE( screen ); 1064 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1065 return NULL; 1066 } 1067 1068 ret = radeon_set_screen_flags(screen, device_id); 1069 if (ret == -1) 1070 return NULL; 1071 1072 if (screen->chip_family <= CHIP_FAMILY_RS200) 1073 screen->chip_flags |= RADEON_CLASS_R100; 1074 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1075 screen->chip_flags |= RADEON_CLASS_R200; 1076 else 1077 screen->chip_flags |= RADEON_CLASS_R300; 1078 1079 i = 0; 1080 screen->extensions[i++] = &driCopySubBufferExtension.base; 1081 screen->extensions[i++] = &driFrameTrackingExtension.base; 1082 screen->extensions[i++] = &driReadDrawableExtension; 1083 1084 if ( screen->irq != 0 ) { 1085 screen->extensions[i++] = &driSwapControlExtension.base; 1086 screen->extensions[i++] = &driMediaStreamCounterExtension.base; 1087 } 1088 1089#if !RADEON_COMMON 1090 screen->extensions[i++] = &radeonTexOffsetExtension.base; 1091#endif 1092 1093#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1094 if (IS_R200_CLASS(screen)) 1095 screen->extensions[i++] = &r200AllocateExtension.base; 1096 1097 screen->extensions[i++] = &r200texOffsetExtension.base; 1098#endif 1099 1100#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1101 //screen->extensions[i++] = &r300texOffsetExtension.base; 1102 screen->extensions[i++] = &r300TexBufferExtension.base; 1103#endif 1104 1105 screen->extensions[i++] = NULL; 1106 sPriv->extensions = screen->extensions; 1107 1108 screen->driScreen = sPriv; 1109 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1110 if (screen->bom == NULL) { 1111 free(screen); 1112 return NULL; 1113 } 1114 return screen; 1115} 1116 1117/* Destroy the device specific screen private data struct. 1118 */ 1119static void 1120radeonDestroyScreen( __DRIscreenPrivate *sPriv ) 1121{ 1122 radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 1123 1124 if (!screen) 1125 return; 1126 1127 if (screen->kernel_mm) { 1128#ifdef RADEON_BO_TRACK 1129 radeon_tracker_print(&screen->bom->tracker, stderr); 1130#endif 1131 radeon_bo_manager_gem_dtor(screen->bom); 1132 } else { 1133 radeon_bo_manager_legacy_dtor(screen->bom); 1134 1135 if ( screen->gartTextures.map ) { 1136 drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 1137 } 1138 drmUnmapBufs( screen->buffers ); 1139 drmUnmap( screen->status.map, screen->status.size ); 1140 drmUnmap( screen->mmio.map, screen->mmio.size ); 1141 } 1142 1143 /* free all option information */ 1144 driDestroyOptionInfo (&screen->optionCache); 1145 1146 FREE( screen ); 1147 sPriv->private = NULL; 1148} 1149 1150 1151/* Initialize the driver specific screen private data. 1152 */ 1153static GLboolean 1154radeonInitDriver( __DRIscreenPrivate *sPriv ) 1155{ 1156 if (sPriv->dri2.enabled) { 1157 sPriv->private = (void *) radeonCreateScreen2( sPriv ); 1158 } else { 1159 sPriv->private = (void *) radeonCreateScreen( sPriv ); 1160 } 1161 if ( !sPriv->private ) { 1162 radeonDestroyScreen( sPriv ); 1163 return GL_FALSE; 1164 } 1165 1166 return GL_TRUE; 1167} 1168 1169static GLboolean 1170radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb, 1171 GLenum intFormat, GLuint w, GLuint h) 1172{ 1173 rb->Width = w; 1174 rb->Height = h; 1175 rb->_ActualFormat = intFormat; 1176 1177 return GL_TRUE; 1178} 1179 1180 1181static struct radeon_renderbuffer * 1182radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv) 1183{ 1184 struct radeon_renderbuffer *ret; 1185 1186 ret = CALLOC_STRUCT(radeon_renderbuffer); 1187 if (!ret) 1188 return NULL; 1189 1190 _mesa_init_renderbuffer(&ret->base, 0); 1191 1192 /* XXX format junk */ 1193 switch (format) { 1194 case GL_RGB5: 1195 ret->base._ActualFormat = GL_RGB5; 1196 ret->base._BaseFormat = GL_RGBA; 1197 ret->base.RedBits = 5; 1198 ret->base.GreenBits = 6; 1199 ret->base.BlueBits = 5; 1200 ret->base.DataType = GL_UNSIGNED_BYTE; 1201 break; 1202 case GL_RGBA8: 1203 ret->base._ActualFormat = GL_RGBA8; 1204 ret->base._BaseFormat = GL_RGBA; 1205 ret->base.RedBits = 8; 1206 ret->base.GreenBits = 8; 1207 ret->base.BlueBits = 8; 1208 ret->base.AlphaBits = 8; 1209 ret->base.DataType = GL_UNSIGNED_BYTE; 1210 break; 1211 case GL_STENCIL_INDEX8_EXT: 1212 ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT; 1213 ret->base._BaseFormat = GL_STENCIL_INDEX; 1214 ret->base.StencilBits = 8; 1215 ret->base.DataType = GL_UNSIGNED_BYTE; 1216 break; 1217 case GL_DEPTH_COMPONENT16: 1218 ret->base._ActualFormat = GL_DEPTH_COMPONENT16; 1219 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1220 ret->base.DepthBits = 16; 1221 ret->base.DataType = GL_UNSIGNED_SHORT; 1222 break; 1223 case GL_DEPTH_COMPONENT24: 1224 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1225 ret->base._BaseFormat = GL_DEPTH_COMPONENT; 1226 ret->base.DepthBits = 24; 1227 ret->base.DataType = GL_UNSIGNED_INT; 1228 break; 1229 case GL_DEPTH24_STENCIL8_EXT: 1230 ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; 1231 ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT; 1232 ret->base.DepthBits = 24; 1233 ret->base.StencilBits = 8; 1234 ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT; 1235 break; 1236 default: 1237 fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format); 1238 _mesa_delete_renderbuffer(&ret->base); 1239 return NULL; 1240 } 1241 1242 ret->dPriv = driDrawPriv; 1243 ret->base.InternalFormat = format; 1244 1245 ret->base.AllocStorage = radeon_alloc_window_storage; 1246 1247 radeonSetSpanFunctions(ret); 1248 1249 ret->bo = NULL; 1250 return ret; 1251} 1252 1253/** 1254 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1255 * 1256 * \todo This function (and its interface) will need to be updated to support 1257 * pbuffers. 1258 */ 1259static GLboolean 1260radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 1261 __DRIdrawablePrivate *driDrawPriv, 1262 const __GLcontextModes *mesaVis, 1263 GLboolean isPixmap ) 1264{ 1265 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 1266 1267 const GLboolean swDepth = GL_FALSE; 1268 const GLboolean swAlpha = GL_FALSE; 1269 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1270 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1271 mesaVis->depthBits != 24; 1272 GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8); 1273 GLenum depthFormat = GL_NONE; 1274 struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 1275 1276 if (mesaVis->depthBits == 16) 1277 depthFormat = GL_DEPTH_COMPONENT16; 1278 else if (mesaVis->depthBits == 24) 1279 depthFormat = GL_DEPTH_COMPONENT24; 1280 1281 /* front color renderbuffer */ 1282 { 1283 struct radeon_renderbuffer *front = 1284 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1285 _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base); 1286 front->has_surface = 1; 1287 } 1288 1289 /* back color renderbuffer */ 1290 if (mesaVis->doubleBufferMode) { 1291 struct radeon_renderbuffer *back = 1292 radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1293 _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base); 1294 back->has_surface = 1; 1295 } 1296 1297 /* depth renderbuffer */ 1298 if (depthFormat != GL_NONE) { 1299 struct radeon_renderbuffer *depth = 1300 radeon_create_renderbuffer(depthFormat, driDrawPriv); 1301 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base); 1302 depth->has_surface = screen->depthHasSurface; 1303 } 1304 1305 /* stencil renderbuffer */ 1306 if (mesaVis->stencilBits > 0 && !swStencil) { 1307 struct radeon_renderbuffer *stencil = 1308 radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv); 1309 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base); 1310 stencil->has_surface = screen->depthHasSurface; 1311 } 1312 1313 _mesa_add_soft_renderbuffers(fb, 1314 GL_FALSE, /* color */ 1315 swDepth, 1316 swStencil, 1317 swAccum, 1318 swAlpha, 1319 GL_FALSE /* aux */); 1320 driDrawPriv->driverPrivate = (void *) fb; 1321 1322 return (driDrawPriv->driverPrivate != NULL); 1323} 1324 1325static void 1326radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 1327{ 1328 struct radeon_renderbuffer *rb; 1329 GLframebuffer *fb; 1330 1331 fb = (void*)driDrawPriv->driverPrivate; 1332 rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; 1333 if (rb && rb->bo) { 1334 radeon_bo_unref(rb->bo); 1335 rb->bo = NULL; 1336 } 1337 rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer; 1338 if (rb && rb->bo) { 1339 radeon_bo_unref(rb->bo); 1340 rb->bo = NULL; 1341 } 1342 rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer; 1343 if (rb && rb->bo) { 1344 radeon_bo_unref(rb->bo); 1345 rb->bo = NULL; 1346 } 1347 _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 1348} 1349 1350#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1351/** 1352 * Choose the appropriate CreateContext function based on the chipset. 1353 * Eventually, all drivers will go through this process. 1354 */ 1355static GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 1356 __DRIcontextPrivate * driContextPriv, 1357 void *sharedContextPriv) 1358{ 1359 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 1360 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 1361 1362 if (IS_R300_CLASS(screen)) 1363 return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 1364 return GL_FALSE; 1365} 1366 1367/** 1368 * Choose the appropriate DestroyContext function based on the chipset. 1369 */ 1370static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 1371{ 1372 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 1373 1374 if (IS_R300_CLASS(radeon->radeonScreen)) 1375 return r300DestroyContext(driContextPriv); 1376} 1377 1378 1379#endif 1380 1381 1382/** 1383 * This is the driver specific part of the createNewScreen entry point. 1384 * 1385 * \todo maybe fold this into intelInitDriver 1386 * 1387 * \return the __GLcontextModes supported by this driver 1388 */ 1389static const __DRIconfig ** 1390radeonInitScreen(__DRIscreenPrivate *psp) 1391{ 1392#if !RADEON_COMMON 1393 static const char *driver_name = "Radeon"; 1394 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1395 static const __DRIversion dri_expected = { 4, 0, 0 }; 1396 static const __DRIversion drm_expected = { 1, 6, 0 }; 1397#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1398 static const char *driver_name = "R200"; 1399 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1400 static const __DRIversion dri_expected = { 4, 0, 0 }; 1401 static const __DRIversion drm_expected = { 1, 6, 0 }; 1402#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1403 static const char *driver_name = "R300"; 1404 static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 1405 static const __DRIversion dri_expected = { 4, 0, 0 }; 1406 static const __DRIversion drm_expected = { 1, 24, 0 }; 1407#endif 1408 RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 1409 1410 if ( ! driCheckDriDdxDrmVersions3( driver_name, 1411 &psp->dri_version, & dri_expected, 1412 &psp->ddx_version, & ddx_expected, 1413 &psp->drm_version, & drm_expected ) ) { 1414 return NULL; 1415 } 1416 1417 /* Calling driInitExtensions here, with a NULL context pointer, 1418 * does not actually enable the extensions. It just makes sure 1419 * that all the dispatch offsets for all the extensions that 1420 * *might* be enables are known. This is needed because the 1421 * dispatch offsets need to be known when _mesa_context_create 1422 * is called, but we can't enable the extensions until we have a 1423 * context pointer. 1424 * 1425 * Hello chicken. Hello egg. How are you two today? 1426 */ 1427 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1428#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1429 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1430 driInitSingleExtension( NULL, ARB_vp_extension ); 1431 driInitSingleExtension( NULL, NV_vp_extension ); 1432 driInitSingleExtension( NULL, ATI_fs_extension ); 1433 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1434#elif defined(RADEON_COMMON_FOR_R300) 1435 driInitSingleExtension( NULL, gl_20_extension ); 1436#endif 1437 1438 if (!radeonInitDriver(psp)) 1439 return NULL; 1440 1441 /* for now fill in all modes */ 1442 return radeonFillInModes( psp, 1443 dri_priv->bpp, 1444 (dri_priv->bpp == 16) ? 16 : 24, 1445 (dri_priv->bpp == 16) ? 0 : 8, 1); 1446} 1447#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1448 1449/** 1450 * This is the driver specific part of the createNewScreen entry point. 1451 * Called when using DRI2. 1452 * 1453 * \return the __GLcontextModes supported by this driver 1454 */ 1455static const 1456__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) 1457{ 1458 GLenum fb_format[3]; 1459 GLenum fb_type[3]; 1460 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1461 * support pageflipping at all. 1462 */ 1463 static const GLenum back_buffer_modes[] = { 1464 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1465 }; 1466 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1467 int color; 1468 __DRIconfig **configs = NULL; 1469 1470 /* Calling driInitExtensions here, with a NULL context pointer, 1471 * does not actually enable the extensions. It just makes sure 1472 * that all the dispatch offsets for all the extensions that 1473 * *might* be enables are known. This is needed because the 1474 * dispatch offsets need to be known when _mesa_context_create 1475 * is called, but we can't enable the extensions until we have a 1476 * context pointer. 1477 * 1478 * Hello chicken. Hello egg. How are you two today? 1479 */ 1480 driInitExtensions( NULL, card_extensions, GL_FALSE ); 1481#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1482 driInitExtensions( NULL, blend_extensions, GL_FALSE ); 1483 driInitSingleExtension( NULL, ARB_vp_extension ); 1484 driInitSingleExtension( NULL, NV_vp_extension ); 1485 driInitSingleExtension( NULL, ATI_fs_extension ); 1486 driInitExtensions( NULL, point_extensions, GL_FALSE ); 1487#endif 1488 1489 if (!radeonInitDriver(psp)) { 1490 return NULL; 1491 } 1492 depth_bits[0] = 0; 1493 stencil_bits[0] = 0; 1494 depth_bits[1] = 16; 1495 stencil_bits[1] = 0; 1496 depth_bits[2] = 24; 1497 stencil_bits[2] = 0; 1498 depth_bits[3] = 24; 1499 stencil_bits[3] = 8; 1500 1501 msaa_samples_array[0] = 0; 1502 1503 fb_format[0] = GL_RGB; 1504 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1505 1506 fb_format[1] = GL_BGR; 1507 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1508 1509 fb_format[2] = GL_BGRA; 1510 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1511 1512 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1513 __DRIconfig **new_configs; 1514 1515 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1516 depth_bits, 1517 stencil_bits, 1518 ARRAY_SIZE(depth_bits), 1519 back_buffer_modes, 1520 ARRAY_SIZE(back_buffer_modes), 1521 msaa_samples_array, 1522 ARRAY_SIZE(msaa_samples_array)); 1523 if (configs == NULL) 1524 configs = new_configs; 1525 else 1526 configs = driConcatConfigs(configs, new_configs); 1527 } 1528 1529 if (configs == NULL) { 1530 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1531 __LINE__); 1532 return NULL; 1533 } 1534 1535 return (const __DRIconfig **)configs; 1536} 1537 1538/** 1539 * Get information about previous buffer swaps. 1540 */ 1541static int 1542getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 1543{ 1544 radeonContextPtr rmesa; 1545 1546 if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 1547 || (dPriv->driContextPriv->driverPrivate == NULL) 1548 || (sInfo == NULL) ) { 1549 return -1; 1550 } 1551 1552 rmesa = dPriv->driContextPriv->driverPrivate; 1553 sInfo->swap_count = rmesa->swap_count; 1554 sInfo->swap_ust = rmesa->swap_ust; 1555 sInfo->swap_missed_count = rmesa->swap_missed_count; 1556 1557 sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 1558 ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 1559 : 0.0; 1560 1561 return 0; 1562} 1563 1564#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1565const struct __DriverAPIRec driDriverAPI = { 1566 .InitScreen = radeonInitScreen, 1567 .DestroyScreen = radeonDestroyScreen, 1568 .CreateContext = radeonCreateContext, 1569 .DestroyContext = radeonDestroyContext, 1570 .CreateBuffer = radeonCreateBuffer, 1571 .DestroyBuffer = radeonDestroyBuffer, 1572 .SwapBuffers = radeonSwapBuffers, 1573 .MakeCurrent = radeonMakeCurrent, 1574 .UnbindContext = radeonUnbindContext, 1575 .GetSwapInfo = getSwapInfo, 1576 .GetDrawableMSC = driDrawableGetMSC32, 1577 .WaitForMSC = driWaitForMSC32, 1578 .WaitForSBC = NULL, 1579 .SwapBuffersMSC = NULL, 1580 .CopySubBuffer = radeonCopySubBuffer, 1581 /* DRI2 */ 1582 .InitScreen2 = radeonInitScreen2, 1583}; 1584#else 1585const struct __DriverAPIRec driDriverAPI = { 1586 .InitScreen = radeonInitScreen, 1587 .DestroyScreen = radeonDestroyScreen, 1588 .CreateContext = r200CreateContext, 1589 .DestroyContext = r200DestroyContext, 1590 .CreateBuffer = radeonCreateBuffer, 1591 .DestroyBuffer = radeonDestroyBuffer, 1592 .SwapBuffers = radeonSwapBuffers, 1593 .MakeCurrent = radeonMakeCurrent, 1594 .UnbindContext = radeonUnbindContext, 1595 .GetSwapInfo = getSwapInfo, 1596 .GetDrawableMSC = driDrawableGetMSC32, 1597 .WaitForMSC = driWaitForMSC32, 1598 .WaitForSBC = NULL, 1599 .SwapBuffersMSC = NULL, 1600 .CopySubBuffer = radeonCopySubBuffer, 1601 .InitScreen2 = radeonInitScreen2, 1602}; 1603#endif 1604 1605