radeon_screen.c revision 875a757ddd103722cfe9a2b21035024aa5a23d32
1/************************************************************************** 2 3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 4 VA Linux Systems Inc., Fremont, California. 5 6All Rights Reserved. 7 8Permission is hereby granted, free of charge, to any person obtaining 9a copy of this software and associated documentation files (the 10"Software"), to deal in the Software without restriction, including 11without limitation the rights to use, copy, modify, merge, publish, 12distribute, sublicense, and/or sell copies of the Software, and to 13permit persons to whom the Software is furnished to do so, subject to 14the following conditions: 15 16The above copyright notice and this permission notice (including the 17next paragraph) shall be included in all copies or substantial 18portions of the Software. 19 20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28**************************************************************************/ 29 30/** 31 * \file radeon_screen.c 32 * Screen initialization functions for the Radeon driver. 33 * 34 * \author Kevin E. Martin <martin@valinux.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include <errno.h> 39#include "main/glheader.h" 40#include "main/imports.h" 41#include "main/mtypes.h" 42#include "main/framebuffer.h" 43#include "main/renderbuffer.h" 44#include "main/fbobject.h" 45 46#define STANDALONE_MMIO 47#include "radeon_chipset.h" 48#include "radeon_macros.h" 49#include "radeon_screen.h" 50#include "radeon_common.h" 51#include "radeon_common_context.h" 52#if defined(RADEON_R100) 53#include "radeon_context.h" 54#include "radeon_tex.h" 55#elif defined(RADEON_R200) 56#include "r200_context.h" 57#include "r200_tex.h" 58#endif 59 60#include "utils.h" 61 62#include "GL/internal/dri_interface.h" 63 64/* Radeon configuration 65 */ 66#include "xmlpool.h" 67 68#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 69DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 70 DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 71 DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 72DRI_CONF_OPT_END 73 74#if defined(RADEON_R100) /* R100 */ 75PUBLIC const char __driConfigOptions[] = 76DRI_CONF_BEGIN 77 DRI_CONF_SECTION_PERFORMANCE 78 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 79 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 80 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 81 DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 82 DRI_CONF_HYPERZ(false) 83 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 84 DRI_CONF_SECTION_END 85 DRI_CONF_SECTION_QUALITY 86 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 87 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 88 DRI_CONF_NO_NEG_LOD_BIAS(false) 89 DRI_CONF_FORCE_S3TC_ENABLE(false) 90 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 91 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 92 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 93 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 94 DRI_CONF_SECTION_END 95 DRI_CONF_SECTION_DEBUG 96 DRI_CONF_NO_RAST(false) 97 DRI_CONF_SECTION_END 98DRI_CONF_END; 99static const GLuint __driNConfigOptions = 15; 100 101#elif defined(RADEON_R200) 102 103PUBLIC const char __driConfigOptions[] = 104DRI_CONF_BEGIN 105 DRI_CONF_SECTION_PERFORMANCE 106 DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 107 DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 108 DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 109 DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 110 DRI_CONF_HYPERZ(false) 111 DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 112 DRI_CONF_SECTION_END 113 DRI_CONF_SECTION_QUALITY 114 DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 115 DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 116 DRI_CONF_NO_NEG_LOD_BIAS(false) 117 DRI_CONF_FORCE_S3TC_ENABLE(false) 118 DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 119 DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 120 DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 121 DRI_CONF_ALLOW_LARGE_TEXTURES(2) 122 DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 123 DRI_CONF_SECTION_END 124 DRI_CONF_SECTION_DEBUG 125 DRI_CONF_NO_RAST(false) 126 DRI_CONF_SECTION_END 127 DRI_CONF_SECTION_SOFTWARE 128 DRI_CONF_NV_VERTEX_PROGRAM(false) 129 DRI_CONF_SECTION_END 130DRI_CONF_END; 131static const GLuint __driNConfigOptions = 17; 132 133#endif 134 135#ifndef RADEON_INFO_TILE_CONFIG 136#define RADEON_INFO_TILE_CONFIG 0x6 137#endif 138 139static int 140radeonGetParam(__DRIscreen *sPriv, int param, void *value) 141{ 142 int ret; 143 drm_radeon_getparam_t gp = { 0 }; 144 struct drm_radeon_info info = { 0 }; 145 146 if (sPriv->drm_version.major >= 2) { 147 info.value = (uint64_t)(uintptr_t)value; 148 switch (param) { 149 case RADEON_PARAM_DEVICE_ID: 150 info.request = RADEON_INFO_DEVICE_ID; 151 break; 152 case RADEON_PARAM_NUM_GB_PIPES: 153 info.request = RADEON_INFO_NUM_GB_PIPES; 154 break; 155 case RADEON_PARAM_NUM_Z_PIPES: 156 info.request = RADEON_INFO_NUM_Z_PIPES; 157 break; 158 case RADEON_INFO_TILE_CONFIG: 159 info.request = RADEON_INFO_TILE_CONFIG; 160 break; 161 default: 162 return -EINVAL; 163 } 164 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info)); 165 } else { 166 gp.param = param; 167 gp.value = value; 168 169 ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 170 } 171 return ret; 172} 173 174#if defined(RADEON_R100) 175static const __DRItexBufferExtension radeonTexBufferExtension = { 176 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 177 radeonSetTexBuffer, 178 radeonSetTexBuffer2, 179}; 180#endif 181 182#if defined(RADEON_R200) 183static const __DRItexBufferExtension r200TexBufferExtension = { 184 { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION }, 185 r200SetTexBuffer, 186 r200SetTexBuffer2, 187}; 188#endif 189 190static void 191radeonDRI2Flush(__DRIdrawable *drawable) 192{ 193 radeonContextPtr rmesa; 194 195 rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate; 196 radeonFlush(rmesa->glCtx); 197} 198 199static const struct __DRI2flushExtensionRec radeonFlushExtension = { 200 { __DRI2_FLUSH, __DRI2_FLUSH_VERSION }, 201 radeonDRI2Flush, 202 dri2InvalidateDrawable, 203}; 204 205static __DRIimage * 206radeon_create_image_from_name(__DRIscreen *screen, 207 int width, int height, int format, 208 int name, int pitch, void *loaderPrivate) 209{ 210 __DRIimage *image; 211 radeonScreenPtr radeonScreen = screen->driverPrivate; 212 213 if (name == 0) 214 return NULL; 215 216 image = CALLOC(sizeof *image); 217 if (image == NULL) 218 return NULL; 219 220 switch (format) { 221 case __DRI_IMAGE_FORMAT_RGB565: 222 image->format = MESA_FORMAT_RGB565; 223 image->internal_format = GL_RGB; 224 image->data_type = GL_UNSIGNED_BYTE; 225 break; 226 case __DRI_IMAGE_FORMAT_XRGB8888: 227 image->format = MESA_FORMAT_XRGB8888; 228 image->internal_format = GL_RGB; 229 image->data_type = GL_UNSIGNED_BYTE; 230 break; 231 case __DRI_IMAGE_FORMAT_ARGB8888: 232 image->format = MESA_FORMAT_ARGB8888; 233 image->internal_format = GL_RGBA; 234 image->data_type = GL_UNSIGNED_BYTE; 235 break; 236 default: 237 free(image); 238 return NULL; 239 } 240 241 image->data = loaderPrivate; 242 image->cpp = _mesa_get_format_bytes(image->format); 243 image->width = width; 244 image->pitch = pitch; 245 image->height = height; 246 247 image->bo = radeon_bo_open(radeonScreen->bom, 248 (uint32_t)name, 249 image->pitch * image->height * image->cpp, 250 0, 251 RADEON_GEM_DOMAIN_VRAM, 252 0); 253 254 if (image->bo == NULL) { 255 FREE(image); 256 return NULL; 257 } 258 259 return image; 260} 261 262static __DRIimage * 263radeon_create_image_from_renderbuffer(__DRIcontext *context, 264 int renderbuffer, void *loaderPrivate) 265{ 266 __DRIimage *image; 267 radeonContextPtr radeon = context->driverPrivate; 268 struct gl_renderbuffer *rb; 269 struct radeon_renderbuffer *rrb; 270 271 rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer); 272 if (!rb) { 273 _mesa_error(radeon->glCtx, 274 GL_INVALID_OPERATION, "glRenderbufferExternalMESA"); 275 return NULL; 276 } 277 278 rrb = radeon_renderbuffer(rb); 279 image = CALLOC(sizeof *image); 280 if (image == NULL) 281 return NULL; 282 283 image->internal_format = rb->InternalFormat; 284 image->format = rb->Format; 285 image->cpp = rrb->cpp; 286 image->data_type = rb->DataType; 287 image->data = loaderPrivate; 288 radeon_bo_ref(rrb->bo); 289 image->bo = rrb->bo; 290 291 image->width = rb->Width; 292 image->height = rb->Height; 293 image->pitch = rrb->pitch / image->cpp; 294 295 return image; 296} 297 298static void 299radeon_destroy_image(__DRIimage *image) 300{ 301 radeon_bo_unref(image->bo); 302 FREE(image); 303} 304 305static __DRIimage * 306radeon_create_image(__DRIscreen *screen, 307 int width, int height, int format, 308 unsigned int use, 309 void *loaderPrivate) 310{ 311 __DRIimage *image; 312 radeonScreenPtr radeonScreen = screen->driverPrivate; 313 314 image = CALLOC(sizeof *image); 315 if (image == NULL) 316 return NULL; 317 318 switch (format) { 319 case __DRI_IMAGE_FORMAT_RGB565: 320 image->format = MESA_FORMAT_RGB565; 321 image->internal_format = GL_RGB; 322 image->data_type = GL_UNSIGNED_BYTE; 323 break; 324 case __DRI_IMAGE_FORMAT_XRGB8888: 325 image->format = MESA_FORMAT_XRGB8888; 326 image->internal_format = GL_RGB; 327 image->data_type = GL_UNSIGNED_BYTE; 328 break; 329 case __DRI_IMAGE_FORMAT_ARGB8888: 330 image->format = MESA_FORMAT_ARGB8888; 331 image->internal_format = GL_RGBA; 332 image->data_type = GL_UNSIGNED_BYTE; 333 break; 334 default: 335 free(image); 336 return NULL; 337 } 338 339 image->data = loaderPrivate; 340 image->cpp = _mesa_get_format_bytes(image->format); 341 image->width = width; 342 image->height = height; 343 image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp; 344 345 image->bo = radeon_bo_open(radeonScreen->bom, 346 0, 347 image->pitch * image->height * image->cpp, 348 0, 349 RADEON_GEM_DOMAIN_VRAM, 350 0); 351 352 if (image->bo == NULL) { 353 FREE(image); 354 return NULL; 355 } 356 357 return image; 358} 359 360static GLboolean 361radeon_query_image(__DRIimage *image, int attrib, int *value) 362{ 363 switch (attrib) { 364 case __DRI_IMAGE_ATTRIB_STRIDE: 365 *value = image->pitch * image->cpp; 366 return GL_TRUE; 367 case __DRI_IMAGE_ATTRIB_HANDLE: 368 *value = image->bo->handle; 369 return GL_TRUE; 370 case __DRI_IMAGE_ATTRIB_NAME: 371 radeon_gem_get_kernel_name(image->bo, (uint32_t *) value); 372 return GL_TRUE; 373 default: 374 return GL_FALSE; 375 } 376} 377 378static struct __DRIimageExtensionRec radeonImageExtension = { 379 { __DRI_IMAGE, __DRI_IMAGE_VERSION }, 380 radeon_create_image_from_name, 381 radeon_create_image_from_renderbuffer, 382 radeon_destroy_image, 383 radeon_create_image, 384 radeon_query_image 385}; 386 387static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) 388{ 389 screen->device_id = device_id; 390 screen->chip_flags = 0; 391 switch ( device_id ) { 392 case PCI_CHIP_RN50_515E: 393 case PCI_CHIP_RN50_5969: 394 return -1; 395 396 case PCI_CHIP_RADEON_LY: 397 case PCI_CHIP_RADEON_LZ: 398 case PCI_CHIP_RADEON_QY: 399 case PCI_CHIP_RADEON_QZ: 400 screen->chip_family = CHIP_FAMILY_RV100; 401 break; 402 403 case PCI_CHIP_RS100_4136: 404 case PCI_CHIP_RS100_4336: 405 screen->chip_family = CHIP_FAMILY_RS100; 406 break; 407 408 case PCI_CHIP_RS200_4137: 409 case PCI_CHIP_RS200_4337: 410 case PCI_CHIP_RS250_4237: 411 case PCI_CHIP_RS250_4437: 412 screen->chip_family = CHIP_FAMILY_RS200; 413 break; 414 415 case PCI_CHIP_RADEON_QD: 416 case PCI_CHIP_RADEON_QE: 417 case PCI_CHIP_RADEON_QF: 418 case PCI_CHIP_RADEON_QG: 419 /* all original radeons (7200) presumably have a stencil op bug */ 420 screen->chip_family = CHIP_FAMILY_R100; 421 screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 422 break; 423 424 case PCI_CHIP_RV200_QW: 425 case PCI_CHIP_RV200_QX: 426 case PCI_CHIP_RADEON_LW: 427 case PCI_CHIP_RADEON_LX: 428 screen->chip_family = CHIP_FAMILY_RV200; 429 screen->chip_flags = RADEON_CHIPSET_TCL; 430 break; 431 432 case PCI_CHIP_R200_BB: 433 case PCI_CHIP_R200_QH: 434 case PCI_CHIP_R200_QL: 435 case PCI_CHIP_R200_QM: 436 screen->chip_family = CHIP_FAMILY_R200; 437 screen->chip_flags = RADEON_CHIPSET_TCL; 438 break; 439 440 case PCI_CHIP_RV250_If: 441 case PCI_CHIP_RV250_Ig: 442 case PCI_CHIP_RV250_Ld: 443 case PCI_CHIP_RV250_Lf: 444 case PCI_CHIP_RV250_Lg: 445 screen->chip_family = CHIP_FAMILY_RV250; 446 screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 447 break; 448 449 case PCI_CHIP_RV280_5960: 450 case PCI_CHIP_RV280_5961: 451 case PCI_CHIP_RV280_5962: 452 case PCI_CHIP_RV280_5964: 453 case PCI_CHIP_RV280_5965: 454 case PCI_CHIP_RV280_5C61: 455 case PCI_CHIP_RV280_5C63: 456 screen->chip_family = CHIP_FAMILY_RV280; 457 screen->chip_flags = RADEON_CHIPSET_TCL; 458 break; 459 460 case PCI_CHIP_RS300_5834: 461 case PCI_CHIP_RS300_5835: 462 case PCI_CHIP_RS350_7834: 463 case PCI_CHIP_RS350_7835: 464 screen->chip_family = CHIP_FAMILY_RS300; 465 break; 466 467 case PCI_CHIP_R300_AD: 468 case PCI_CHIP_R300_AE: 469 case PCI_CHIP_R300_AF: 470 case PCI_CHIP_R300_AG: 471 case PCI_CHIP_R300_ND: 472 case PCI_CHIP_R300_NE: 473 case PCI_CHIP_R300_NF: 474 case PCI_CHIP_R300_NG: 475 screen->chip_family = CHIP_FAMILY_R300; 476 screen->chip_flags = RADEON_CHIPSET_TCL; 477 break; 478 479 case PCI_CHIP_RV350_AP: 480 case PCI_CHIP_RV350_AQ: 481 case PCI_CHIP_RV350_AR: 482 case PCI_CHIP_RV350_AS: 483 case PCI_CHIP_RV350_AT: 484 case PCI_CHIP_RV350_AV: 485 case PCI_CHIP_RV350_AU: 486 case PCI_CHIP_RV350_NP: 487 case PCI_CHIP_RV350_NQ: 488 case PCI_CHIP_RV350_NR: 489 case PCI_CHIP_RV350_NS: 490 case PCI_CHIP_RV350_NT: 491 case PCI_CHIP_RV350_NV: 492 screen->chip_family = CHIP_FAMILY_RV350; 493 screen->chip_flags = RADEON_CHIPSET_TCL; 494 break; 495 496 case PCI_CHIP_R350_AH: 497 case PCI_CHIP_R350_AI: 498 case PCI_CHIP_R350_AJ: 499 case PCI_CHIP_R350_AK: 500 case PCI_CHIP_R350_NH: 501 case PCI_CHIP_R350_NI: 502 case PCI_CHIP_R360_NJ: 503 case PCI_CHIP_R350_NK: 504 screen->chip_family = CHIP_FAMILY_R350; 505 screen->chip_flags = RADEON_CHIPSET_TCL; 506 break; 507 508 case PCI_CHIP_RV370_5460: 509 case PCI_CHIP_RV370_5462: 510 case PCI_CHIP_RV370_5464: 511 case PCI_CHIP_RV370_5B60: 512 case PCI_CHIP_RV370_5B62: 513 case PCI_CHIP_RV370_5B63: 514 case PCI_CHIP_RV370_5B64: 515 case PCI_CHIP_RV370_5B65: 516 case PCI_CHIP_RV380_3150: 517 case PCI_CHIP_RV380_3152: 518 case PCI_CHIP_RV380_3154: 519 case PCI_CHIP_RV380_3155: 520 case PCI_CHIP_RV380_3E50: 521 case PCI_CHIP_RV380_3E54: 522 screen->chip_family = CHIP_FAMILY_RV380; 523 screen->chip_flags = RADEON_CHIPSET_TCL; 524 break; 525 526 case PCI_CHIP_R420_JN: 527 case PCI_CHIP_R420_JH: 528 case PCI_CHIP_R420_JI: 529 case PCI_CHIP_R420_JJ: 530 case PCI_CHIP_R420_JK: 531 case PCI_CHIP_R420_JL: 532 case PCI_CHIP_R420_JM: 533 case PCI_CHIP_R420_JO: 534 case PCI_CHIP_R420_JP: 535 case PCI_CHIP_R420_JT: 536 case PCI_CHIP_R481_4B49: 537 case PCI_CHIP_R481_4B4A: 538 case PCI_CHIP_R481_4B4B: 539 case PCI_CHIP_R481_4B4C: 540 case PCI_CHIP_R423_UH: 541 case PCI_CHIP_R423_UI: 542 case PCI_CHIP_R423_UJ: 543 case PCI_CHIP_R423_UK: 544 case PCI_CHIP_R430_554C: 545 case PCI_CHIP_R430_554D: 546 case PCI_CHIP_R430_554E: 547 case PCI_CHIP_R430_554F: 548 case PCI_CHIP_R423_5550: 549 case PCI_CHIP_R423_UQ: 550 case PCI_CHIP_R423_UR: 551 case PCI_CHIP_R423_UT: 552 case PCI_CHIP_R430_5D48: 553 case PCI_CHIP_R430_5D49: 554 case PCI_CHIP_R430_5D4A: 555 case PCI_CHIP_R480_5D4C: 556 case PCI_CHIP_R480_5D4D: 557 case PCI_CHIP_R480_5D4E: 558 case PCI_CHIP_R480_5D4F: 559 case PCI_CHIP_R480_5D50: 560 case PCI_CHIP_R480_5D52: 561 case PCI_CHIP_R423_5D57: 562 screen->chip_family = CHIP_FAMILY_R420; 563 screen->chip_flags = RADEON_CHIPSET_TCL; 564 break; 565 566 case PCI_CHIP_RV410_5E4C: 567 case PCI_CHIP_RV410_5E4F: 568 case PCI_CHIP_RV410_564A: 569 case PCI_CHIP_RV410_564B: 570 case PCI_CHIP_RV410_564F: 571 case PCI_CHIP_RV410_5652: 572 case PCI_CHIP_RV410_5653: 573 case PCI_CHIP_RV410_5657: 574 case PCI_CHIP_RV410_5E48: 575 case PCI_CHIP_RV410_5E4A: 576 case PCI_CHIP_RV410_5E4B: 577 case PCI_CHIP_RV410_5E4D: 578 screen->chip_family = CHIP_FAMILY_RV410; 579 screen->chip_flags = RADEON_CHIPSET_TCL; 580 break; 581 582 case PCI_CHIP_RS480_5954: 583 case PCI_CHIP_RS480_5955: 584 case PCI_CHIP_RS482_5974: 585 case PCI_CHIP_RS482_5975: 586 case PCI_CHIP_RS400_5A41: 587 case PCI_CHIP_RS400_5A42: 588 case PCI_CHIP_RC410_5A61: 589 case PCI_CHIP_RC410_5A62: 590 screen->chip_family = CHIP_FAMILY_RS400; 591 break; 592 593 case PCI_CHIP_RS600_793F: 594 case PCI_CHIP_RS600_7941: 595 case PCI_CHIP_RS600_7942: 596 screen->chip_family = CHIP_FAMILY_RS600; 597 break; 598 599 case PCI_CHIP_RS690_791E: 600 case PCI_CHIP_RS690_791F: 601 screen->chip_family = CHIP_FAMILY_RS690; 602 break; 603 case PCI_CHIP_RS740_796C: 604 case PCI_CHIP_RS740_796D: 605 case PCI_CHIP_RS740_796E: 606 case PCI_CHIP_RS740_796F: 607 screen->chip_family = CHIP_FAMILY_RS740; 608 break; 609 610 case PCI_CHIP_R520_7100: 611 case PCI_CHIP_R520_7101: 612 case PCI_CHIP_R520_7102: 613 case PCI_CHIP_R520_7103: 614 case PCI_CHIP_R520_7104: 615 case PCI_CHIP_R520_7105: 616 case PCI_CHIP_R520_7106: 617 case PCI_CHIP_R520_7108: 618 case PCI_CHIP_R520_7109: 619 case PCI_CHIP_R520_710A: 620 case PCI_CHIP_R520_710B: 621 case PCI_CHIP_R520_710C: 622 case PCI_CHIP_R520_710E: 623 case PCI_CHIP_R520_710F: 624 screen->chip_family = CHIP_FAMILY_R520; 625 screen->chip_flags = RADEON_CHIPSET_TCL; 626 break; 627 628 case PCI_CHIP_RV515_7140: 629 case PCI_CHIP_RV515_7141: 630 case PCI_CHIP_RV515_7142: 631 case PCI_CHIP_RV515_7143: 632 case PCI_CHIP_RV515_7144: 633 case PCI_CHIP_RV515_7145: 634 case PCI_CHIP_RV515_7146: 635 case PCI_CHIP_RV515_7147: 636 case PCI_CHIP_RV515_7149: 637 case PCI_CHIP_RV515_714A: 638 case PCI_CHIP_RV515_714B: 639 case PCI_CHIP_RV515_714C: 640 case PCI_CHIP_RV515_714D: 641 case PCI_CHIP_RV515_714E: 642 case PCI_CHIP_RV515_714F: 643 case PCI_CHIP_RV515_7151: 644 case PCI_CHIP_RV515_7152: 645 case PCI_CHIP_RV515_7153: 646 case PCI_CHIP_RV515_715E: 647 case PCI_CHIP_RV515_715F: 648 case PCI_CHIP_RV515_7180: 649 case PCI_CHIP_RV515_7181: 650 case PCI_CHIP_RV515_7183: 651 case PCI_CHIP_RV515_7186: 652 case PCI_CHIP_RV515_7187: 653 case PCI_CHIP_RV515_7188: 654 case PCI_CHIP_RV515_718A: 655 case PCI_CHIP_RV515_718B: 656 case PCI_CHIP_RV515_718C: 657 case PCI_CHIP_RV515_718D: 658 case PCI_CHIP_RV515_718F: 659 case PCI_CHIP_RV515_7193: 660 case PCI_CHIP_RV515_7196: 661 case PCI_CHIP_RV515_719B: 662 case PCI_CHIP_RV515_719F: 663 case PCI_CHIP_RV515_7200: 664 case PCI_CHIP_RV515_7210: 665 case PCI_CHIP_RV515_7211: 666 screen->chip_family = CHIP_FAMILY_RV515; 667 screen->chip_flags = RADEON_CHIPSET_TCL; 668 break; 669 670 case PCI_CHIP_RV530_71C0: 671 case PCI_CHIP_RV530_71C1: 672 case PCI_CHIP_RV530_71C2: 673 case PCI_CHIP_RV530_71C3: 674 case PCI_CHIP_RV530_71C4: 675 case PCI_CHIP_RV530_71C5: 676 case PCI_CHIP_RV530_71C6: 677 case PCI_CHIP_RV530_71C7: 678 case PCI_CHIP_RV530_71CD: 679 case PCI_CHIP_RV530_71CE: 680 case PCI_CHIP_RV530_71D2: 681 case PCI_CHIP_RV530_71D4: 682 case PCI_CHIP_RV530_71D5: 683 case PCI_CHIP_RV530_71D6: 684 case PCI_CHIP_RV530_71DA: 685 case PCI_CHIP_RV530_71DE: 686 screen->chip_family = CHIP_FAMILY_RV530; 687 screen->chip_flags = RADEON_CHIPSET_TCL; 688 break; 689 690 case PCI_CHIP_R580_7240: 691 case PCI_CHIP_R580_7243: 692 case PCI_CHIP_R580_7244: 693 case PCI_CHIP_R580_7245: 694 case PCI_CHIP_R580_7246: 695 case PCI_CHIP_R580_7247: 696 case PCI_CHIP_R580_7248: 697 case PCI_CHIP_R580_7249: 698 case PCI_CHIP_R580_724A: 699 case PCI_CHIP_R580_724B: 700 case PCI_CHIP_R580_724C: 701 case PCI_CHIP_R580_724D: 702 case PCI_CHIP_R580_724E: 703 case PCI_CHIP_R580_724F: 704 case PCI_CHIP_R580_7284: 705 screen->chip_family = CHIP_FAMILY_R580; 706 screen->chip_flags = RADEON_CHIPSET_TCL; 707 break; 708 709 case PCI_CHIP_RV570_7280: 710 case PCI_CHIP_RV560_7281: 711 case PCI_CHIP_RV560_7283: 712 case PCI_CHIP_RV560_7287: 713 case PCI_CHIP_RV570_7288: 714 case PCI_CHIP_RV570_7289: 715 case PCI_CHIP_RV570_728B: 716 case PCI_CHIP_RV570_728C: 717 case PCI_CHIP_RV560_7290: 718 case PCI_CHIP_RV560_7291: 719 case PCI_CHIP_RV560_7293: 720 case PCI_CHIP_RV560_7297: 721 screen->chip_family = CHIP_FAMILY_RV560; 722 screen->chip_flags = RADEON_CHIPSET_TCL; 723 break; 724 725 case PCI_CHIP_R600_9400: 726 case PCI_CHIP_R600_9401: 727 case PCI_CHIP_R600_9402: 728 case PCI_CHIP_R600_9403: 729 case PCI_CHIP_R600_9405: 730 case PCI_CHIP_R600_940A: 731 case PCI_CHIP_R600_940B: 732 case PCI_CHIP_R600_940F: 733 screen->chip_family = CHIP_FAMILY_R600; 734 screen->chip_flags = RADEON_CHIPSET_TCL; 735 break; 736 737 case PCI_CHIP_RV610_94C0: 738 case PCI_CHIP_RV610_94C1: 739 case PCI_CHIP_RV610_94C3: 740 case PCI_CHIP_RV610_94C4: 741 case PCI_CHIP_RV610_94C5: 742 case PCI_CHIP_RV610_94C6: 743 case PCI_CHIP_RV610_94C7: 744 case PCI_CHIP_RV610_94C8: 745 case PCI_CHIP_RV610_94C9: 746 case PCI_CHIP_RV610_94CB: 747 case PCI_CHIP_RV610_94CC: 748 case PCI_CHIP_RV610_94CD: 749 screen->chip_family = CHIP_FAMILY_RV610; 750 screen->chip_flags = RADEON_CHIPSET_TCL; 751 break; 752 753 case PCI_CHIP_RV630_9580: 754 case PCI_CHIP_RV630_9581: 755 case PCI_CHIP_RV630_9583: 756 case PCI_CHIP_RV630_9586: 757 case PCI_CHIP_RV630_9587: 758 case PCI_CHIP_RV630_9588: 759 case PCI_CHIP_RV630_9589: 760 case PCI_CHIP_RV630_958A: 761 case PCI_CHIP_RV630_958B: 762 case PCI_CHIP_RV630_958C: 763 case PCI_CHIP_RV630_958D: 764 case PCI_CHIP_RV630_958E: 765 case PCI_CHIP_RV630_958F: 766 screen->chip_family = CHIP_FAMILY_RV630; 767 screen->chip_flags = RADEON_CHIPSET_TCL; 768 break; 769 770 case PCI_CHIP_RV670_9500: 771 case PCI_CHIP_RV670_9501: 772 case PCI_CHIP_RV670_9504: 773 case PCI_CHIP_RV670_9505: 774 case PCI_CHIP_RV670_9506: 775 case PCI_CHIP_RV670_9507: 776 case PCI_CHIP_RV670_9508: 777 case PCI_CHIP_RV670_9509: 778 case PCI_CHIP_RV670_950F: 779 case PCI_CHIP_RV670_9511: 780 case PCI_CHIP_RV670_9515: 781 case PCI_CHIP_RV670_9517: 782 case PCI_CHIP_RV670_9519: 783 screen->chip_family = CHIP_FAMILY_RV670; 784 screen->chip_flags = RADEON_CHIPSET_TCL; 785 break; 786 787 case PCI_CHIP_RV620_95C0: 788 case PCI_CHIP_RV620_95C2: 789 case PCI_CHIP_RV620_95C4: 790 case PCI_CHIP_RV620_95C5: 791 case PCI_CHIP_RV620_95C6: 792 case PCI_CHIP_RV620_95C7: 793 case PCI_CHIP_RV620_95C9: 794 case PCI_CHIP_RV620_95CC: 795 case PCI_CHIP_RV620_95CD: 796 case PCI_CHIP_RV620_95CE: 797 case PCI_CHIP_RV620_95CF: 798 screen->chip_family = CHIP_FAMILY_RV620; 799 screen->chip_flags = RADEON_CHIPSET_TCL; 800 break; 801 802 case PCI_CHIP_RV635_9590: 803 case PCI_CHIP_RV635_9591: 804 case PCI_CHIP_RV635_9593: 805 case PCI_CHIP_RV635_9595: 806 case PCI_CHIP_RV635_9596: 807 case PCI_CHIP_RV635_9597: 808 case PCI_CHIP_RV635_9598: 809 case PCI_CHIP_RV635_9599: 810 case PCI_CHIP_RV635_959B: 811 screen->chip_family = CHIP_FAMILY_RV635; 812 screen->chip_flags = RADEON_CHIPSET_TCL; 813 break; 814 815 case PCI_CHIP_RS780_9610: 816 case PCI_CHIP_RS780_9611: 817 case PCI_CHIP_RS780_9612: 818 case PCI_CHIP_RS780_9613: 819 case PCI_CHIP_RS780_9614: 820 case PCI_CHIP_RS780_9615: 821 case PCI_CHIP_RS780_9616: 822 screen->chip_family = CHIP_FAMILY_RS780; 823 screen->chip_flags = RADEON_CHIPSET_TCL; 824 break; 825 case PCI_CHIP_RS880_9710: 826 case PCI_CHIP_RS880_9711: 827 case PCI_CHIP_RS880_9712: 828 case PCI_CHIP_RS880_9713: 829 case PCI_CHIP_RS880_9714: 830 case PCI_CHIP_RS880_9715: 831 screen->chip_family = CHIP_FAMILY_RS880; 832 screen->chip_flags = RADEON_CHIPSET_TCL; 833 break; 834 835 case PCI_CHIP_RV770_9440: 836 case PCI_CHIP_RV770_9441: 837 case PCI_CHIP_RV770_9442: 838 case PCI_CHIP_RV770_9443: 839 case PCI_CHIP_RV770_9444: 840 case PCI_CHIP_RV770_9446: 841 case PCI_CHIP_RV770_944A: 842 case PCI_CHIP_RV770_944B: 843 case PCI_CHIP_RV770_944C: 844 case PCI_CHIP_RV770_944E: 845 case PCI_CHIP_RV770_9450: 846 case PCI_CHIP_RV770_9452: 847 case PCI_CHIP_RV770_9456: 848 case PCI_CHIP_RV770_945A: 849 case PCI_CHIP_RV770_945B: 850 case PCI_CHIP_RV770_945E: 851 case PCI_CHIP_RV790_9460: 852 case PCI_CHIP_RV790_9462: 853 case PCI_CHIP_RV770_946A: 854 case PCI_CHIP_RV770_946B: 855 case PCI_CHIP_RV770_947A: 856 case PCI_CHIP_RV770_947B: 857 screen->chip_family = CHIP_FAMILY_RV770; 858 screen->chip_flags = RADEON_CHIPSET_TCL; 859 break; 860 861 case PCI_CHIP_RV730_9480: 862 case PCI_CHIP_RV730_9487: 863 case PCI_CHIP_RV730_9488: 864 case PCI_CHIP_RV730_9489: 865 case PCI_CHIP_RV730_948A: 866 case PCI_CHIP_RV730_948F: 867 case PCI_CHIP_RV730_9490: 868 case PCI_CHIP_RV730_9491: 869 case PCI_CHIP_RV730_9495: 870 case PCI_CHIP_RV730_9498: 871 case PCI_CHIP_RV730_949C: 872 case PCI_CHIP_RV730_949E: 873 case PCI_CHIP_RV730_949F: 874 screen->chip_family = CHIP_FAMILY_RV730; 875 screen->chip_flags = RADEON_CHIPSET_TCL; 876 break; 877 878 case PCI_CHIP_RV710_9540: 879 case PCI_CHIP_RV710_9541: 880 case PCI_CHIP_RV710_9542: 881 case PCI_CHIP_RV710_954E: 882 case PCI_CHIP_RV710_954F: 883 case PCI_CHIP_RV710_9552: 884 case PCI_CHIP_RV710_9553: 885 case PCI_CHIP_RV710_9555: 886 case PCI_CHIP_RV710_9557: 887 case PCI_CHIP_RV710_955F: 888 screen->chip_family = CHIP_FAMILY_RV710; 889 screen->chip_flags = RADEON_CHIPSET_TCL; 890 break; 891 892 case PCI_CHIP_RV740_94A0: 893 case PCI_CHIP_RV740_94A1: 894 case PCI_CHIP_RV740_94A3: 895 case PCI_CHIP_RV740_94B1: 896 case PCI_CHIP_RV740_94B3: 897 case PCI_CHIP_RV740_94B4: 898 case PCI_CHIP_RV740_94B5: 899 case PCI_CHIP_RV740_94B9: 900 screen->chip_family = CHIP_FAMILY_RV740; 901 screen->chip_flags = RADEON_CHIPSET_TCL; 902 break; 903 904 case PCI_CHIP_CEDAR_68E0: 905 case PCI_CHIP_CEDAR_68E1: 906 case PCI_CHIP_CEDAR_68E4: 907 case PCI_CHIP_CEDAR_68E5: 908 case PCI_CHIP_CEDAR_68E8: 909 case PCI_CHIP_CEDAR_68E9: 910 case PCI_CHIP_CEDAR_68F1: 911 case PCI_CHIP_CEDAR_68F2: 912 case PCI_CHIP_CEDAR_68F8: 913 case PCI_CHIP_CEDAR_68F9: 914 case PCI_CHIP_CEDAR_68FE: 915 screen->chip_family = CHIP_FAMILY_CEDAR; 916 screen->chip_flags = RADEON_CHIPSET_TCL; 917 break; 918 919 case PCI_CHIP_REDWOOD_68C0: 920 case PCI_CHIP_REDWOOD_68C1: 921 case PCI_CHIP_REDWOOD_68C8: 922 case PCI_CHIP_REDWOOD_68C9: 923 case PCI_CHIP_REDWOOD_68D8: 924 case PCI_CHIP_REDWOOD_68D9: 925 case PCI_CHIP_REDWOOD_68DA: 926 case PCI_CHIP_REDWOOD_68DE: 927 screen->chip_family = CHIP_FAMILY_REDWOOD; 928 screen->chip_flags = RADEON_CHIPSET_TCL; 929 break; 930 931 case PCI_CHIP_JUNIPER_68A0: 932 case PCI_CHIP_JUNIPER_68A1: 933 case PCI_CHIP_JUNIPER_68A8: 934 case PCI_CHIP_JUNIPER_68A9: 935 case PCI_CHIP_JUNIPER_68B0: 936 case PCI_CHIP_JUNIPER_68B8: 937 case PCI_CHIP_JUNIPER_68B9: 938 case PCI_CHIP_JUNIPER_68BA: 939 case PCI_CHIP_JUNIPER_68BE: 940 case PCI_CHIP_JUNIPER_68BF: 941 screen->chip_family = CHIP_FAMILY_JUNIPER; 942 screen->chip_flags = RADEON_CHIPSET_TCL; 943 break; 944 945 case PCI_CHIP_CYPRESS_6880: 946 case PCI_CHIP_CYPRESS_6888: 947 case PCI_CHIP_CYPRESS_6889: 948 case PCI_CHIP_CYPRESS_688A: 949 case PCI_CHIP_CYPRESS_6898: 950 case PCI_CHIP_CYPRESS_6899: 951 case PCI_CHIP_CYPRESS_689B: 952 case PCI_CHIP_CYPRESS_689E: 953 screen->chip_family = CHIP_FAMILY_CYPRESS; 954 screen->chip_flags = RADEON_CHIPSET_TCL; 955 break; 956 957 case PCI_CHIP_HEMLOCK_689C: 958 case PCI_CHIP_HEMLOCK_689D: 959 screen->chip_family = CHIP_FAMILY_HEMLOCK; 960 screen->chip_flags = RADEON_CHIPSET_TCL; 961 break; 962 963 case PCI_CHIP_PALM_9802: 964 case PCI_CHIP_PALM_9803: 965 case PCI_CHIP_PALM_9804: 966 case PCI_CHIP_PALM_9805: 967 case PCI_CHIP_PALM_9806: 968 case PCI_CHIP_PALM_9807: 969 screen->chip_family = CHIP_FAMILY_PALM; 970 screen->chip_flags = RADEON_CHIPSET_TCL; 971 break; 972 973 case PCI_CHIP_SUMO_9640: 974 case PCI_CHIP_SUMO_9641: 975 case PCI_CHIP_SUMO_9647: 976 case PCI_CHIP_SUMO_9648: 977 case PCI_CHIP_SUMO_964A: 978 case PCI_CHIP_SUMO_964E: 979 case PCI_CHIP_SUMO_964F: 980 screen->chip_family = CHIP_FAMILY_SUMO; 981 screen->chip_flags = RADEON_CHIPSET_TCL; 982 break; 983 984 case PCI_CHIP_SUMO2_9642: 985 case PCI_CHIP_SUMO2_9643: 986 case PCI_CHIP_SUMO2_9644: 987 case PCI_CHIP_SUMO2_9645: 988 screen->chip_family = CHIP_FAMILY_SUMO2; 989 screen->chip_flags = RADEON_CHIPSET_TCL; 990 break; 991 992 case PCI_CHIP_BARTS_6720: 993 case PCI_CHIP_BARTS_6721: 994 case PCI_CHIP_BARTS_6722: 995 case PCI_CHIP_BARTS_6723: 996 case PCI_CHIP_BARTS_6724: 997 case PCI_CHIP_BARTS_6725: 998 case PCI_CHIP_BARTS_6726: 999 case PCI_CHIP_BARTS_6727: 1000 case PCI_CHIP_BARTS_6728: 1001 case PCI_CHIP_BARTS_6729: 1002 case PCI_CHIP_BARTS_6738: 1003 case PCI_CHIP_BARTS_6739: 1004 case PCI_CHIP_BARTS_673E: 1005 screen->chip_family = CHIP_FAMILY_BARTS; 1006 screen->chip_flags = RADEON_CHIPSET_TCL; 1007 break; 1008 1009 case PCI_CHIP_TURKS_6740: 1010 case PCI_CHIP_TURKS_6741: 1011 case PCI_CHIP_TURKS_6742: 1012 case PCI_CHIP_TURKS_6743: 1013 case PCI_CHIP_TURKS_6744: 1014 case PCI_CHIP_TURKS_6745: 1015 case PCI_CHIP_TURKS_6746: 1016 case PCI_CHIP_TURKS_6747: 1017 case PCI_CHIP_TURKS_6748: 1018 case PCI_CHIP_TURKS_6749: 1019 case PCI_CHIP_TURKS_6750: 1020 case PCI_CHIP_TURKS_6758: 1021 case PCI_CHIP_TURKS_6759: 1022 case PCI_CHIP_TURKS_675F: 1023 screen->chip_family = CHIP_FAMILY_TURKS; 1024 screen->chip_flags = RADEON_CHIPSET_TCL; 1025 break; 1026 1027 case PCI_CHIP_CAICOS_6760: 1028 case PCI_CHIP_CAICOS_6761: 1029 case PCI_CHIP_CAICOS_6762: 1030 case PCI_CHIP_CAICOS_6763: 1031 case PCI_CHIP_CAICOS_6764: 1032 case PCI_CHIP_CAICOS_6765: 1033 case PCI_CHIP_CAICOS_6766: 1034 case PCI_CHIP_CAICOS_6767: 1035 case PCI_CHIP_CAICOS_6768: 1036 case PCI_CHIP_CAICOS_6770: 1037 case PCI_CHIP_CAICOS_6778: 1038 case PCI_CHIP_CAICOS_6779: 1039 screen->chip_family = CHIP_FAMILY_CAICOS; 1040 screen->chip_flags = RADEON_CHIPSET_TCL; 1041 break; 1042 1043 default: 1044 fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 1045 device_id); 1046 return -1; 1047 } 1048 1049 return 0; 1050} 1051 1052static radeonScreenPtr 1053radeonCreateScreen2(__DRIscreen *sPriv) 1054{ 1055 radeonScreenPtr screen; 1056 int i; 1057 int ret; 1058 uint32_t device_id = 0; 1059 1060 /* Allocate the private area */ 1061 screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 1062 if ( !screen ) { 1063 __driUtilMessage("%s: Could not allocate memory for screen structure", 1064 __FUNCTION__); 1065 fprintf(stderr, "leaving here\n"); 1066 return NULL; 1067 } 1068 1069 radeon_init_debug(); 1070 1071 /* parse information in __driConfigOptions */ 1072 driParseOptionInfo (&screen->optionCache, 1073 __driConfigOptions, __driNConfigOptions); 1074 1075 screen->chip_flags = 0; 1076 1077 screen->irq = 1; 1078 1079 ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id); 1080 if (ret) { 1081 FREE( screen ); 1082 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret); 1083 return NULL; 1084 } 1085 1086 ret = radeon_set_screen_flags(screen, device_id); 1087 if (ret == -1) 1088 return NULL; 1089 1090 if (getenv("R300_NO_TCL")) 1091 screen->chip_flags &= ~RADEON_CHIPSET_TCL; 1092 1093 if (screen->chip_family <= CHIP_FAMILY_RS200) 1094 screen->chip_flags |= RADEON_CLASS_R100; 1095 else if (screen->chip_family <= CHIP_FAMILY_RV280) 1096 screen->chip_flags |= RADEON_CLASS_R200; 1097 1098 i = 0; 1099 screen->extensions[i++] = &dri2ConfigQueryExtension.base; 1100 1101#if defined(RADEON_R100) 1102 screen->extensions[i++] = &radeonTexBufferExtension.base; 1103#endif 1104 1105#if defined(RADEON_R200) 1106 screen->extensions[i++] = &r200TexBufferExtension.base; 1107#endif 1108 1109 screen->extensions[i++] = &radeonFlushExtension.base; 1110 screen->extensions[i++] = &radeonImageExtension.base; 1111 1112 screen->extensions[i++] = NULL; 1113 sPriv->extensions = screen->extensions; 1114 1115 screen->driScreen = sPriv; 1116 screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd); 1117 if (screen->bom == NULL) { 1118 free(screen); 1119 return NULL; 1120 } 1121 return screen; 1122} 1123 1124/* Destroy the device specific screen private data struct. 1125 */ 1126static void 1127radeonDestroyScreen( __DRIscreen *sPriv ) 1128{ 1129 radeonScreenPtr screen = (radeonScreenPtr)sPriv->driverPrivate; 1130 1131 if (!screen) 1132 return; 1133 1134#ifdef RADEON_BO_TRACK 1135 radeon_tracker_print(&screen->bom->tracker, stderr); 1136#endif 1137 radeon_bo_manager_gem_dtor(screen->bom); 1138 1139 /* free all option information */ 1140 driDestroyOptionInfo (&screen->optionCache); 1141 1142 FREE( screen ); 1143 sPriv->driverPrivate = NULL; 1144} 1145 1146 1147/* Initialize the driver specific screen private data. 1148 */ 1149static GLboolean 1150radeonInitDriver( __DRIscreen *sPriv ) 1151{ 1152 sPriv->driverPrivate = (void *) radeonCreateScreen2( sPriv ); 1153 if ( !sPriv->driverPrivate ) { 1154 radeonDestroyScreen( sPriv ); 1155 return GL_FALSE; 1156 } 1157 1158 return GL_TRUE; 1159} 1160 1161 1162 1163/** 1164 * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 1165 * 1166 * \todo This function (and its interface) will need to be updated to support 1167 * pbuffers. 1168 */ 1169static GLboolean 1170radeonCreateBuffer( __DRIscreen *driScrnPriv, 1171 __DRIdrawable *driDrawPriv, 1172 const struct gl_config *mesaVis, 1173 GLboolean isPixmap ) 1174{ 1175 radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->driverPrivate; 1176 1177 const GLboolean swDepth = GL_FALSE; 1178 const GLboolean swAlpha = GL_FALSE; 1179 const GLboolean swAccum = mesaVis->accumRedBits > 0; 1180 const GLboolean swStencil = mesaVis->stencilBits > 0 && 1181 mesaVis->depthBits != 24; 1182 gl_format rgbFormat; 1183 struct radeon_framebuffer *rfb; 1184 1185 if (isPixmap) 1186 return GL_FALSE; /* not implemented */ 1187 1188 rfb = CALLOC_STRUCT(radeon_framebuffer); 1189 if (!rfb) 1190 return GL_FALSE; 1191 1192 _mesa_initialize_window_framebuffer(&rfb->base, mesaVis); 1193 1194 if (mesaVis->redBits == 5) 1195 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV; 1196 else if (mesaVis->alphaBits == 0) 1197 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV; 1198 else 1199 rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV; 1200 1201 /* front color renderbuffer */ 1202 rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1203 _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base); 1204 rfb->color_rb[0]->has_surface = 1; 1205 1206 /* back color renderbuffer */ 1207 if (mesaVis->doubleBufferMode) { 1208 rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv); 1209 _mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base); 1210 rfb->color_rb[1]->has_surface = 1; 1211 } 1212 1213 if (mesaVis->depthBits == 24) { 1214 if (mesaVis->stencilBits == 8) { 1215 struct radeon_renderbuffer *depthStencilRb = 1216 radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv); 1217 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base); 1218 _mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base); 1219 depthStencilRb->has_surface = screen->depthHasSurface; 1220 } else { 1221 /* depth renderbuffer */ 1222 struct radeon_renderbuffer *depth = 1223 radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv); 1224 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1225 depth->has_surface = screen->depthHasSurface; 1226 } 1227 } else if (mesaVis->depthBits == 16) { 1228 /* just 16-bit depth buffer, no hw stencil */ 1229 struct radeon_renderbuffer *depth = 1230 radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv); 1231 _mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base); 1232 depth->has_surface = screen->depthHasSurface; 1233 } 1234 1235 _mesa_add_soft_renderbuffers(&rfb->base, 1236 GL_FALSE, /* color */ 1237 swDepth, 1238 swStencil, 1239 swAccum, 1240 swAlpha, 1241 GL_FALSE /* aux */); 1242 driDrawPriv->driverPrivate = (void *) rfb; 1243 1244 return (driDrawPriv->driverPrivate != NULL); 1245} 1246 1247 1248static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) 1249{ 1250 struct radeon_renderbuffer *rb; 1251 1252 rb = rfb->color_rb[0]; 1253 if (rb && rb->bo) { 1254 radeon_bo_unref(rb->bo); 1255 rb->bo = NULL; 1256 } 1257 rb = rfb->color_rb[1]; 1258 if (rb && rb->bo) { 1259 radeon_bo_unref(rb->bo); 1260 rb->bo = NULL; 1261 } 1262 rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH); 1263 if (rb && rb->bo) { 1264 radeon_bo_unref(rb->bo); 1265 rb->bo = NULL; 1266 } 1267} 1268 1269void 1270radeonDestroyBuffer(__DRIdrawable *driDrawPriv) 1271{ 1272 struct radeon_framebuffer *rfb; 1273 if (!driDrawPriv) 1274 return; 1275 1276 rfb = (void*)driDrawPriv->driverPrivate; 1277 if (!rfb) 1278 return; 1279 radeon_cleanup_renderbuffers(rfb); 1280 _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL); 1281} 1282 1283#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) 1284 1285/** 1286 * This is the driver specific part of the createNewScreen entry point. 1287 * Called when using DRI2. 1288 * 1289 * \return the struct gl_config supported by this driver 1290 */ 1291static const 1292__DRIconfig **radeonInitScreen2(__DRIscreen *psp) 1293{ 1294 GLenum fb_format[3]; 1295 GLenum fb_type[3]; 1296 /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't 1297 * support pageflipping at all. 1298 */ 1299 static const GLenum back_buffer_modes[] = { 1300 GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/ 1301 }; 1302 uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1]; 1303 int color; 1304 __DRIconfig **configs = NULL; 1305 1306 if (!radeonInitDriver(psp)) { 1307 return NULL; 1308 } 1309 depth_bits[0] = 0; 1310 stencil_bits[0] = 0; 1311 depth_bits[1] = 16; 1312 stencil_bits[1] = 0; 1313 depth_bits[2] = 24; 1314 stencil_bits[2] = 0; 1315 depth_bits[3] = 24; 1316 stencil_bits[3] = 8; 1317 1318 msaa_samples_array[0] = 0; 1319 1320 fb_format[0] = GL_RGB; 1321 fb_type[0] = GL_UNSIGNED_SHORT_5_6_5; 1322 1323 fb_format[1] = GL_BGR; 1324 fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV; 1325 1326 fb_format[2] = GL_BGRA; 1327 fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV; 1328 1329 for (color = 0; color < ARRAY_SIZE(fb_format); color++) { 1330 __DRIconfig **new_configs; 1331 1332 new_configs = driCreateConfigs(fb_format[color], fb_type[color], 1333 depth_bits, 1334 stencil_bits, 1335 ARRAY_SIZE(depth_bits), 1336 back_buffer_modes, 1337 ARRAY_SIZE(back_buffer_modes), 1338 msaa_samples_array, 1339 ARRAY_SIZE(msaa_samples_array), 1340 GL_TRUE); 1341 if (configs == NULL) 1342 configs = new_configs; 1343 else 1344 configs = driConcatConfigs(configs, new_configs); 1345 } 1346 1347 if (configs == NULL) { 1348 fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__, 1349 __LINE__); 1350 return NULL; 1351 } 1352 1353 return (const __DRIconfig **)configs; 1354} 1355 1356const struct __DriverAPIRec driDriverAPI = { 1357 .InitScreen = radeonInitScreen2, 1358 .DestroyScreen = radeonDestroyScreen, 1359#if defined(RADEON_R200) 1360 .CreateContext = r200CreateContext, 1361 .DestroyContext = r200DestroyContext, 1362#else 1363 .CreateContext = r100CreateContext, 1364 .DestroyContext = radeonDestroyContext, 1365#endif 1366 .CreateBuffer = radeonCreateBuffer, 1367 .DestroyBuffer = radeonDestroyBuffer, 1368 .MakeCurrent = radeonMakeCurrent, 1369 .UnbindContext = radeonUnbindContext, 1370}; 1371 1372/* This is the table of extensions that the loader will dlsym() for. */ 1373PUBLIC const __DRIextension *__driDriverExtensions[] = { 1374 &driCoreExtension.base, 1375 &driDRI2Extension.base, 1376 NULL 1377}; 1378