radeon_screen.c revision 9f2732d3128a1482d4d7feacd98efaf7bdcc4eef 
1/**************************************************************************
2
3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4                     VA Linux Systems Inc., Fremont, California.
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining
9a copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sublicense, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial
18portions of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author  Gareth Hughes <gareth@valinux.com>
36 */
37
38#include <errno.h>
39#include "main/glheader.h"
40#include "main/imports.h"
41#include "main/mtypes.h"
42#include "main/framebuffer.h"
43#include "main/renderbuffer.h"
44
45#define STANDALONE_MMIO
46#include "radeon_chipset.h"
47#include "radeon_macros.h"
48#include "radeon_screen.h"
49#include "radeon_buffer.h"
50#if !RADEON_COMMON
51#include "radeon_context.h"
52#include "radeon_span.h"
53#include "radeon_tex.h"
54#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
55#include "r200_context.h"
56#include "r200_ioctl.h"
57#include "r200_span.h"
58#include "r200_tex.h"
59#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
60#include "r300_context.h"
61#include "r300_fragprog.h"
62#include "r300_tex.h"
63#include "radeon_span.h"
64#endif
65
66#include "utils.h"
67#include "vblank.h"
68#include "drirenderbuffer.h"
69
70#include "GL/internal/dri_interface.h"
71
72/* Radeon configuration
73 */
74#include "xmlpool.h"
75#include "radeon_bo_legacy.h"
76#include "radeon_bo_gem.h"
77
78#if !RADEON_COMMON	/* R100 */
79PUBLIC const char __driConfigOptions[] =
80DRI_CONF_BEGIN
81    DRI_CONF_SECTION_PERFORMANCE
82        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
83        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
84        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
85        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
86        DRI_CONF_HYPERZ(false)
87    DRI_CONF_SECTION_END
88    DRI_CONF_SECTION_QUALITY
89        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
90        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
91        DRI_CONF_NO_NEG_LOD_BIAS(false)
92        DRI_CONF_FORCE_S3TC_ENABLE(false)
93        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
94        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
95        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
96        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
97    DRI_CONF_SECTION_END
98    DRI_CONF_SECTION_DEBUG
99        DRI_CONF_NO_RAST(false)
100    DRI_CONF_SECTION_END
101DRI_CONF_END;
102static const GLuint __driNConfigOptions = 14;
103
104#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
105
106PUBLIC const char __driConfigOptions[] =
107DRI_CONF_BEGIN
108    DRI_CONF_SECTION_PERFORMANCE
109        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
110        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
111        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
112        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
113        DRI_CONF_HYPERZ(false)
114    DRI_CONF_SECTION_END
115    DRI_CONF_SECTION_QUALITY
116        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
117        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
118        DRI_CONF_NO_NEG_LOD_BIAS(false)
119        DRI_CONF_FORCE_S3TC_ENABLE(false)
120        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
121        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
122        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
123        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
124        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
125    DRI_CONF_SECTION_END
126    DRI_CONF_SECTION_DEBUG
127        DRI_CONF_NO_RAST(false)
128    DRI_CONF_SECTION_END
129    DRI_CONF_SECTION_SOFTWARE
130        DRI_CONF_NV_VERTEX_PROGRAM(false)
131    DRI_CONF_SECTION_END
132DRI_CONF_END;
133static const GLuint __driNConfigOptions = 16;
134
135extern const struct dri_extension blend_extensions[];
136extern const struct dri_extension ARB_vp_extension[];
137extern const struct dri_extension NV_vp_extension[];
138extern const struct dri_extension ATI_fs_extension[];
139extern const struct dri_extension point_extensions[];
140
141#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
142
143/* TODO: integrate these into xmlpool.h! */
144#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
145DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
146        DRI_CONF_DESC(en,"Number of texture image units") \
147        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
148DRI_CONF_OPT_END
149
150#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
151DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
152        DRI_CONF_DESC(en,"Number of texture coordinate units") \
153        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
154DRI_CONF_OPT_END
155
156#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
157DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
158        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
159        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
160DRI_CONF_OPT_END
161
162#define DRI_CONF_DISABLE_S3TC(def) \
163DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
164        DRI_CONF_DESC(en,"Disable S3TC compression") \
165DRI_CONF_OPT_END
166
167#define DRI_CONF_DISABLE_FALLBACK(def) \
168DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
169        DRI_CONF_DESC(en,"Disable Low-impact fallback") \
170DRI_CONF_OPT_END
171
172#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
173DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
174        DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
175DRI_CONF_OPT_END
176
177#define DRI_CONF_FP_OPTIMIZATION(def) \
178DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
179	DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
180                DRI_CONF_ENUM(0,"Optimize for Speed") \
181                DRI_CONF_ENUM(1,"Optimize for Quality") \
182        DRI_CONF_DESC_END \
183DRI_CONF_OPT_END
184
185PUBLIC const char __driConfigOptions[] =
186DRI_CONF_BEGIN
187	DRI_CONF_SECTION_PERFORMANCE
188		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
189		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
190		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
191		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
192		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
193		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
194		DRI_CONF_DISABLE_FALLBACK(true)
195		DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
196	DRI_CONF_SECTION_END
197	DRI_CONF_SECTION_QUALITY
198		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
199		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
200		DRI_CONF_FORCE_S3TC_ENABLE(false)
201		DRI_CONF_DISABLE_S3TC(false)
202		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
203		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
204		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
205		DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
206	DRI_CONF_SECTION_END
207	DRI_CONF_SECTION_DEBUG
208		DRI_CONF_NO_RAST(false)
209	DRI_CONF_SECTION_END
210DRI_CONF_END;
211static const GLuint __driNConfigOptions = 17;
212
213#ifndef RADEON_DEBUG
214int RADEON_DEBUG = 0;
215
216static const struct dri_debug_control debug_control[] = {
217	{"fall", DEBUG_FALLBACKS},
218	{"tex", DEBUG_TEXTURE},
219	{"ioctl", DEBUG_IOCTL},
220	{"prim", DEBUG_PRIMS},
221	{"vert", DEBUG_VERTS},
222	{"state", DEBUG_STATE},
223	{"code", DEBUG_CODEGEN},
224	{"vfmt", DEBUG_VFMT},
225	{"vtxf", DEBUG_VFMT},
226	{"verb", DEBUG_VERBOSE},
227	{"dri", DEBUG_DRI},
228	{"dma", DEBUG_DMA},
229	{"san", DEBUG_SANITY},
230	{"sync", DEBUG_SYNC},
231	{"pix", DEBUG_PIXEL},
232	{"mem", DEBUG_MEMORY},
233	{"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */
234	{NULL, 0}
235};
236#endif /* RADEON_DEBUG */
237
238#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */
239
240extern const struct dri_extension card_extensions[];
241
242static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
243
244static int
245radeonGetParam(int fd, int param, void *value)
246{
247  int ret;
248  drm_radeon_getparam_t gp;
249
250  gp.param = param;
251  gp.value = value;
252
253  ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
254  return ret;
255}
256
257static const __DRIconfig **
258radeonFillInModes( __DRIscreenPrivate *psp,
259		   unsigned pixel_bits, unsigned depth_bits,
260		   unsigned stencil_bits, GLboolean have_back_buffer )
261{
262    __DRIconfig **configs;
263    __GLcontextModes *m;
264    unsigned depth_buffer_factor;
265    unsigned back_buffer_factor;
266    GLenum fb_format;
267    GLenum fb_type;
268    int i;
269
270    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
271     * enough to add support.  Basically, if a context is created with an
272     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
273     * will never be used.
274     */
275    static const GLenum back_buffer_modes[] = {
276	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
277    };
278
279    uint8_t depth_bits_array[2];
280    uint8_t stencil_bits_array[2];
281
282
283    depth_bits_array[0] = depth_bits;
284    depth_bits_array[1] = depth_bits;
285
286    /* Just like with the accumulation buffer, always provide some modes
287     * with a stencil buffer.  It will be a sw fallback, but some apps won't
288     * care about that.
289     */
290    stencil_bits_array[0] = 0;
291    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
292
293    depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1;
294    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
295
296    if ( pixel_bits == 16 ) {
297        fb_format = GL_RGB;
298        fb_type = GL_UNSIGNED_SHORT_5_6_5;
299    }
300    else {
301        fb_format = GL_BGRA;
302        fb_type = GL_UNSIGNED_INT_8_8_8_8_REV;
303    }
304
305    configs = driCreateConfigs(fb_format, fb_type,
306			       depth_bits_array, stencil_bits_array,
307			       depth_buffer_factor,
308			       back_buffer_modes, back_buffer_factor);
309    if (configs == NULL) {
310	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
311		 __func__, __LINE__ );
312	return NULL;
313    }
314
315    /* Mark the visual as slow if there are "fake" stencil bits.
316     */
317    for (i = 0; configs[i]; i++) {
318	m = &configs[i]->modes;
319	if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
320	    m->visualRating = GLX_SLOW_CONFIG;
321	}
322    }
323
324    return (const __DRIconfig **) configs;
325}
326
327#if !RADEON_COMMON
328static const __DRItexOffsetExtension radeonTexOffsetExtension = {
329    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
330    radeonSetTexOffset,
331};
332#endif
333
334#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
335static const __DRIallocateExtension r200AllocateExtension = {
336    { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION },
337    r200AllocateMemoryMESA,
338    r200FreeMemoryMESA,
339    r200GetMemoryOffsetMESA
340};
341
342static const __DRItexOffsetExtension r200texOffsetExtension = {
343    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
344   r200SetTexOffset,
345};
346#endif
347
348#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
349static const __DRItexOffsetExtension r300texOffsetExtension = {
350    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
351   r300SetTexOffset,
352};
353
354void r300SetTexBuffer(__DRIcontext *pDRICtx,
355                      GLint target,
356                      __DRIdrawable *dPriv);
357static const __DRItexBufferExtension r300TexBufferExtension = {
358    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
359   r300SetTexBuffer,
360};
361#endif
362
363/* Create the device specific screen private data struct.
364 */
365static radeonScreenPtr
366radeonCreateScreen( __DRIscreenPrivate *sPriv )
367{
368   radeonScreenPtr screen;
369   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
370   unsigned char *RADEONMMIO = NULL;
371   int i;
372   int ret;
373   uint32_t temp;
374
375   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
376      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
377      return GL_FALSE;
378   }
379
380   /* Allocate the private area */
381   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
382   if ( !screen ) {
383      __driUtilMessage("%s: Could not allocate memory for screen structure",
384		       __FUNCTION__);
385      return NULL;
386   }
387
388#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
389	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
390#endif
391
392   /* parse information in __driConfigOptions */
393   driParseOptionInfo (&screen->optionCache,
394		       __driConfigOptions, __driNConfigOptions);
395
396   /* This is first since which regions we map depends on whether or
397    * not we are using a PCI card.
398    */
399   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
400   {
401      int ret;
402
403#ifdef RADEON_PARAM_KERNEL_MM
404     ret = radeonGetParam( sPriv->fd, RADEON_PARAM_KERNEL_MM,
405                            &screen->kernel_mm);
406
407      if (ret && ret != -EINVAL) {
408         FREE( screen );
409         fprintf(stderr, "drm_radeon_getparam_t (RADEON_OFFSET): %d\n", ret);
410         return NULL;
411      }
412
413      if (ret == -EINVAL)
414          screen->kernel_mm = 0;
415#endif
416
417      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET,
418			    &screen->gart_buffer_offset);
419
420      if (ret) {
421	 FREE( screen );
422	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
423	 return NULL;
424      }
425
426      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE,
427			    &screen->gart_base);
428      if (ret) {
429	 FREE( screen );
430	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
431	 return NULL;
432      }
433
434      ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR,
435			    &screen->irq);
436      if (ret) {
437	 FREE( screen );
438	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
439	 return NULL;
440      }
441      screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
442      screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
443      screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
444      screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
445      screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
446      screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
447      screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
448   }
449
450   if (!screen->kernel_mm) {
451     screen->mmio.handle = dri_priv->registerHandle;
452     screen->mmio.size   = dri_priv->registerSize;
453     if ( drmMap( sPriv->fd,
454		  screen->mmio.handle,
455		  screen->mmio.size,
456		  &screen->mmio.map ) ) {
457       FREE( screen );
458       __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
459       return NULL;
460     }
461
462     RADEONMMIO = screen->mmio.map;
463
464     screen->status.handle = dri_priv->statusHandle;
465     screen->status.size   = dri_priv->statusSize;
466     if ( drmMap( sPriv->fd,
467		  screen->status.handle,
468		  screen->status.size,
469		  &screen->status.map ) ) {
470       drmUnmap( screen->mmio.map, screen->mmio.size );
471       FREE( screen );
472       __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
473       return NULL;
474     }
475     screen->scratch = (__volatile__ uint32_t *)
476       ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
477
478     screen->buffers = drmMapBufs( sPriv->fd );
479     if ( !screen->buffers ) {
480       drmUnmap( screen->status.map, screen->status.size );
481       drmUnmap( screen->mmio.map, screen->mmio.size );
482       FREE( screen );
483       __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
484       return NULL;
485     }
486
487     if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
488       screen->gartTextures.handle = dri_priv->gartTexHandle;
489       screen->gartTextures.size   = dri_priv->gartTexMapSize;
490       if ( drmMap( sPriv->fd,
491		    screen->gartTextures.handle,
492		    screen->gartTextures.size,
493		    (drmAddressPtr)&screen->gartTextures.map ) ) {
494	 drmUnmapBufs( screen->buffers );
495	 drmUnmap( screen->status.map, screen->status.size );
496	 drmUnmap( screen->mmio.map, screen->mmio.size );
497	 FREE( screen );
498	 __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
499	 return NULL;
500       }
501
502       screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
503     }
504   }
505
506   screen->chip_flags = 0;
507   /* XXX: add more chipsets */
508   switch ( dri_priv->deviceID ) {
509   case PCI_CHIP_RADEON_LY:
510   case PCI_CHIP_RADEON_LZ:
511   case PCI_CHIP_RADEON_QY:
512   case PCI_CHIP_RADEON_QZ:
513   case PCI_CHIP_RN50_515E:
514   case PCI_CHIP_RN50_5969:
515      screen->chip_family = CHIP_FAMILY_RV100;
516      break;
517
518   case PCI_CHIP_RS100_4136:
519   case PCI_CHIP_RS100_4336:
520      screen->chip_family = CHIP_FAMILY_RS100;
521      break;
522
523   case PCI_CHIP_RS200_4137:
524   case PCI_CHIP_RS200_4337:
525   case PCI_CHIP_RS250_4237:
526   case PCI_CHIP_RS250_4437:
527      screen->chip_family = CHIP_FAMILY_RS200;
528      break;
529
530   case PCI_CHIP_RADEON_QD:
531   case PCI_CHIP_RADEON_QE:
532   case PCI_CHIP_RADEON_QF:
533   case PCI_CHIP_RADEON_QG:
534      /* all original radeons (7200) presumably have a stencil op bug */
535      screen->chip_family = CHIP_FAMILY_R100;
536      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
537      break;
538
539   case PCI_CHIP_RV200_QW:
540   case PCI_CHIP_RV200_QX:
541   case PCI_CHIP_RADEON_LW:
542   case PCI_CHIP_RADEON_LX:
543      screen->chip_family = CHIP_FAMILY_RV200;
544      screen->chip_flags = RADEON_CHIPSET_TCL;
545      break;
546
547   case PCI_CHIP_R200_BB:
548   case PCI_CHIP_R200_BC:
549   case PCI_CHIP_R200_QH:
550   case PCI_CHIP_R200_QL:
551   case PCI_CHIP_R200_QM:
552      screen->chip_family = CHIP_FAMILY_R200;
553      screen->chip_flags = RADEON_CHIPSET_TCL;
554      break;
555
556   case PCI_CHIP_RV250_If:
557   case PCI_CHIP_RV250_Ig:
558   case PCI_CHIP_RV250_Ld:
559   case PCI_CHIP_RV250_Lf:
560   case PCI_CHIP_RV250_Lg:
561      screen->chip_family = CHIP_FAMILY_RV250;
562      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
563      break;
564
565   case PCI_CHIP_RV280_5960:
566   case PCI_CHIP_RV280_5961:
567   case PCI_CHIP_RV280_5962:
568   case PCI_CHIP_RV280_5964:
569   case PCI_CHIP_RV280_5965:
570   case PCI_CHIP_RV280_5C61:
571   case PCI_CHIP_RV280_5C63:
572      screen->chip_family = CHIP_FAMILY_RV280;
573      screen->chip_flags = RADEON_CHIPSET_TCL;
574      break;
575
576   case PCI_CHIP_RS300_5834:
577   case PCI_CHIP_RS300_5835:
578   case PCI_CHIP_RS350_7834:
579   case PCI_CHIP_RS350_7835:
580      screen->chip_family = CHIP_FAMILY_RS300;
581      break;
582
583      /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
584   case PCI_CHIP_R300_AD:
585      screen->chip_family = CHIP_FAMILY_RV350;
586      screen->chip_flags = RADEON_CHIPSET_TCL;
587      break;
588   case PCI_CHIP_R300_AE:
589   case PCI_CHIP_R300_AF:
590   case PCI_CHIP_R300_AG:
591   case PCI_CHIP_R300_ND:
592   case PCI_CHIP_R300_NE:
593   case PCI_CHIP_R300_NF:
594   case PCI_CHIP_R300_NG:
595      screen->chip_family = CHIP_FAMILY_R300;
596      screen->chip_flags = RADEON_CHIPSET_TCL;
597      break;
598
599   case PCI_CHIP_RV350_AP:
600   case PCI_CHIP_RV350_AQ:
601   case PCI_CHIP_RV350_AR:
602   case PCI_CHIP_RV350_AS:
603   case PCI_CHIP_RV350_AT:
604   case PCI_CHIP_RV350_AV:
605   case PCI_CHIP_RV350_AU:
606   case PCI_CHIP_RV350_NP:
607   case PCI_CHIP_RV350_NQ:
608   case PCI_CHIP_RV350_NR:
609   case PCI_CHIP_RV350_NS:
610   case PCI_CHIP_RV350_NT:
611   case PCI_CHIP_RV350_NV:
612      screen->chip_family = CHIP_FAMILY_RV350;
613      screen->chip_flags = RADEON_CHIPSET_TCL;
614      break;
615
616   case PCI_CHIP_R350_AH:
617   case PCI_CHIP_R350_AI:
618   case PCI_CHIP_R350_AJ:
619   case PCI_CHIP_R350_AK:
620   case PCI_CHIP_R350_NH:
621   case PCI_CHIP_R350_NI:
622   case PCI_CHIP_R360_NJ:
623   case PCI_CHIP_R350_NK:
624      screen->chip_family = CHIP_FAMILY_R350;
625      screen->chip_flags = RADEON_CHIPSET_TCL;
626      break;
627
628   case PCI_CHIP_RV370_5460:
629   case PCI_CHIP_RV370_5462:
630   case PCI_CHIP_RV370_5464:
631   case PCI_CHIP_RV370_5B60:
632   case PCI_CHIP_RV370_5B62:
633   case PCI_CHIP_RV370_5B63:
634   case PCI_CHIP_RV370_5B64:
635   case PCI_CHIP_RV370_5B65:
636   case PCI_CHIP_RV380_3150:
637   case PCI_CHIP_RV380_3152:
638   case PCI_CHIP_RV380_3154:
639   case PCI_CHIP_RV380_3E50:
640   case PCI_CHIP_RV380_3E54:
641      screen->chip_family = CHIP_FAMILY_RV380;
642      screen->chip_flags = RADEON_CHIPSET_TCL;
643      break;
644
645   case PCI_CHIP_R420_JN:
646   case PCI_CHIP_R420_JH:
647   case PCI_CHIP_R420_JI:
648   case PCI_CHIP_R420_JJ:
649   case PCI_CHIP_R420_JK:
650   case PCI_CHIP_R420_JL:
651   case PCI_CHIP_R420_JM:
652   case PCI_CHIP_R420_JO:
653   case PCI_CHIP_R420_JP:
654   case PCI_CHIP_R420_JT:
655   case PCI_CHIP_R481_4B49:
656   case PCI_CHIP_R481_4B4A:
657   case PCI_CHIP_R481_4B4B:
658   case PCI_CHIP_R481_4B4C:
659   case PCI_CHIP_R423_UH:
660   case PCI_CHIP_R423_UI:
661   case PCI_CHIP_R423_UJ:
662   case PCI_CHIP_R423_UK:
663   case PCI_CHIP_R430_554C:
664   case PCI_CHIP_R430_554D:
665   case PCI_CHIP_R430_554E:
666   case PCI_CHIP_R430_554F:
667   case PCI_CHIP_R423_5550:
668   case PCI_CHIP_R423_UQ:
669   case PCI_CHIP_R423_UR:
670   case PCI_CHIP_R423_UT:
671   case PCI_CHIP_R430_5D48:
672   case PCI_CHIP_R430_5D49:
673   case PCI_CHIP_R430_5D4A:
674   case PCI_CHIP_R480_5D4C:
675   case PCI_CHIP_R480_5D4D:
676   case PCI_CHIP_R480_5D4E:
677   case PCI_CHIP_R480_5D4F:
678   case PCI_CHIP_R480_5D50:
679   case PCI_CHIP_R480_5D52:
680   case PCI_CHIP_R423_5D57:
681      screen->chip_family = CHIP_FAMILY_R420;
682      screen->chip_flags = RADEON_CHIPSET_TCL;
683      break;
684
685   case PCI_CHIP_RV410_5E4C:
686   case PCI_CHIP_RV410_5E4F:
687   case PCI_CHIP_RV410_564A:
688   case PCI_CHIP_RV410_564B:
689   case PCI_CHIP_RV410_564F:
690   case PCI_CHIP_RV410_5652:
691   case PCI_CHIP_RV410_5653:
692   case PCI_CHIP_RV410_5657:
693   case PCI_CHIP_RV410_5E48:
694   case PCI_CHIP_RV410_5E4A:
695   case PCI_CHIP_RV410_5E4B:
696   case PCI_CHIP_RV410_5E4D:
697      screen->chip_family = CHIP_FAMILY_RV410;
698      screen->chip_flags = RADEON_CHIPSET_TCL;
699      break;
700
701   case PCI_CHIP_RS480_5954:
702   case PCI_CHIP_RS480_5955:
703   case PCI_CHIP_RS482_5974:
704   case PCI_CHIP_RS482_5975:
705   case PCI_CHIP_RS400_5A41:
706   case PCI_CHIP_RS400_5A42:
707   case PCI_CHIP_RC410_5A61:
708   case PCI_CHIP_RC410_5A62:
709      screen->chip_family = CHIP_FAMILY_RS400;
710      break;
711
712   case PCI_CHIP_RS690_791E:
713   case PCI_CHIP_RS690_791F:
714      screen->chip_family = CHIP_FAMILY_RS690;
715      break;
716   case PCI_CHIP_RS740_796C:
717   case PCI_CHIP_RS740_796D:
718   case PCI_CHIP_RS740_796E:
719   case PCI_CHIP_RS740_796F:
720      screen->chip_family = CHIP_FAMILY_RS740;
721      break;
722
723   case PCI_CHIP_R520_7100:
724   case PCI_CHIP_R520_7101:
725   case PCI_CHIP_R520_7102:
726   case PCI_CHIP_R520_7103:
727   case PCI_CHIP_R520_7104:
728   case PCI_CHIP_R520_7105:
729   case PCI_CHIP_R520_7106:
730   case PCI_CHIP_R520_7108:
731   case PCI_CHIP_R520_7109:
732   case PCI_CHIP_R520_710A:
733   case PCI_CHIP_R520_710B:
734   case PCI_CHIP_R520_710C:
735   case PCI_CHIP_R520_710E:
736   case PCI_CHIP_R520_710F:
737      screen->chip_family = CHIP_FAMILY_R520;
738      screen->chip_flags = RADEON_CHIPSET_TCL;
739      break;
740
741   case PCI_CHIP_RV515_7140:
742   case PCI_CHIP_RV515_7141:
743   case PCI_CHIP_RV515_7142:
744   case PCI_CHIP_RV515_7143:
745   case PCI_CHIP_RV515_7144:
746   case PCI_CHIP_RV515_7145:
747   case PCI_CHIP_RV515_7146:
748   case PCI_CHIP_RV515_7147:
749   case PCI_CHIP_RV515_7149:
750   case PCI_CHIP_RV515_714A:
751   case PCI_CHIP_RV515_714B:
752   case PCI_CHIP_RV515_714C:
753   case PCI_CHIP_RV515_714D:
754   case PCI_CHIP_RV515_714E:
755   case PCI_CHIP_RV515_714F:
756   case PCI_CHIP_RV515_7151:
757   case PCI_CHIP_RV515_7152:
758   case PCI_CHIP_RV515_7153:
759   case PCI_CHIP_RV515_715E:
760   case PCI_CHIP_RV515_715F:
761   case PCI_CHIP_RV515_7180:
762   case PCI_CHIP_RV515_7181:
763   case PCI_CHIP_RV515_7183:
764   case PCI_CHIP_RV515_7186:
765   case PCI_CHIP_RV515_7187:
766   case PCI_CHIP_RV515_7188:
767   case PCI_CHIP_RV515_718A:
768   case PCI_CHIP_RV515_718B:
769   case PCI_CHIP_RV515_718C:
770   case PCI_CHIP_RV515_718D:
771   case PCI_CHIP_RV515_718F:
772   case PCI_CHIP_RV515_7193:
773   case PCI_CHIP_RV515_7196:
774   case PCI_CHIP_RV515_719B:
775   case PCI_CHIP_RV515_719F:
776   case PCI_CHIP_RV515_7200:
777   case PCI_CHIP_RV515_7210:
778   case PCI_CHIP_RV515_7211:
779      screen->chip_family = CHIP_FAMILY_RV515;
780      screen->chip_flags = RADEON_CHIPSET_TCL;
781      break;
782
783   case PCI_CHIP_RV530_71C0:
784   case PCI_CHIP_RV530_71C1:
785   case PCI_CHIP_RV530_71C2:
786   case PCI_CHIP_RV530_71C3:
787   case PCI_CHIP_RV530_71C4:
788   case PCI_CHIP_RV530_71C5:
789   case PCI_CHIP_RV530_71C6:
790   case PCI_CHIP_RV530_71C7:
791   case PCI_CHIP_RV530_71CD:
792   case PCI_CHIP_RV530_71CE:
793   case PCI_CHIP_RV530_71D2:
794   case PCI_CHIP_RV530_71D4:
795   case PCI_CHIP_RV530_71D5:
796   case PCI_CHIP_RV530_71D6:
797   case PCI_CHIP_RV530_71DA:
798   case PCI_CHIP_RV530_71DE:
799      screen->chip_family = CHIP_FAMILY_RV530;
800      screen->chip_flags = RADEON_CHIPSET_TCL;
801      break;
802
803   case PCI_CHIP_R580_7240:
804   case PCI_CHIP_R580_7243:
805   case PCI_CHIP_R580_7244:
806   case PCI_CHIP_R580_7245:
807   case PCI_CHIP_R580_7246:
808   case PCI_CHIP_R580_7247:
809   case PCI_CHIP_R580_7248:
810   case PCI_CHIP_R580_7249:
811   case PCI_CHIP_R580_724A:
812   case PCI_CHIP_R580_724B:
813   case PCI_CHIP_R580_724C:
814   case PCI_CHIP_R580_724D:
815   case PCI_CHIP_R580_724E:
816   case PCI_CHIP_R580_724F:
817   case PCI_CHIP_R580_7284:
818      screen->chip_family = CHIP_FAMILY_R580;
819      screen->chip_flags = RADEON_CHIPSET_TCL;
820      break;
821
822   case PCI_CHIP_RV570_7280:
823   case PCI_CHIP_RV560_7281:
824   case PCI_CHIP_RV560_7283:
825   case PCI_CHIP_RV560_7287:
826   case PCI_CHIP_RV570_7288:
827   case PCI_CHIP_RV570_7289:
828   case PCI_CHIP_RV570_728B:
829   case PCI_CHIP_RV570_728C:
830   case PCI_CHIP_RV560_7290:
831   case PCI_CHIP_RV560_7291:
832   case PCI_CHIP_RV560_7293:
833   case PCI_CHIP_RV560_7297:
834      screen->chip_family = CHIP_FAMILY_RV560;
835      screen->chip_flags = RADEON_CHIPSET_TCL;
836      break;
837
838   default:
839      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
840	      dri_priv->deviceID);
841      return NULL;
842   }
843   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
844       sPriv->ddx_version.minor < 2) {
845      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
846      return NULL;
847   }
848
849   if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
850      fprintf(stderr, "R500 support requires a newer drm.\n");
851      return NULL;
852   }
853
854   if (getenv("R300_NO_TCL"))
855     screen->chip_flags &= ~RADEON_CHIPSET_TCL;
856
857   if (screen->chip_family <= CHIP_FAMILY_RS200)
858      screen->chip_flags |= RADEON_CLASS_R100;
859   else if (screen->chip_family <= CHIP_FAMILY_RV280)
860      screen->chip_flags |= RADEON_CLASS_R200;
861   else
862      screen->chip_flags |= RADEON_CLASS_R300;
863
864   screen->cpp = dri_priv->bpp / 8;
865   screen->AGPMode = dri_priv->AGPMode;
866
867   ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION,
868                         &temp);
869   if (ret) {
870       if (screen->chip_family < CHIP_FAMILY_RS690 && !screen->kernel_mm)
871	   screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
872       else {
873           FREE( screen );
874           fprintf(stderr, "Unable to get fb location need newer drm\n");
875           return NULL;
876       }
877   } else {
878       screen->fbLocation = (temp & 0xffff) << 16;
879   }
880
881   if (screen->chip_family >= CHIP_FAMILY_RV515) {
882       ret = radeonGetParam( sPriv->fd, RADEON_PARAM_NUM_GB_PIPES,
883			     &temp);
884       if (ret) {
885	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
886	   switch (screen->chip_family) {
887	   case CHIP_FAMILY_R300:
888	   case CHIP_FAMILY_R350:
889	       screen->num_gb_pipes = 2;
890	       break;
891	   case CHIP_FAMILY_R420:
892	   case CHIP_FAMILY_R520:
893	   case CHIP_FAMILY_R580:
894	   case CHIP_FAMILY_RV560:
895	   case CHIP_FAMILY_RV570:
896	       screen->num_gb_pipes = 4;
897	       break;
898	   case CHIP_FAMILY_RV350:
899	   case CHIP_FAMILY_RV515:
900	   case CHIP_FAMILY_RV530:
901	   case CHIP_FAMILY_RV410:
902	   default:
903	       screen->num_gb_pipes = 1;
904	       break;
905	   }
906       } else {
907	   screen->num_gb_pipes = temp;
908       }
909   }
910
911   if ( sPriv->drm_version.minor >= 10 ) {
912      drm_radeon_setparam_t sp;
913
914      sp.param = RADEON_SETPARAM_FB_LOCATION;
915      sp.value = screen->fbLocation;
916
917      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
918		       &sp, sizeof( sp ) );
919   }
920
921   screen->frontOffset	= dri_priv->frontOffset;
922   screen->frontPitch	= dri_priv->frontPitch;
923   screen->backOffset	= dri_priv->backOffset;
924   screen->backPitch	= dri_priv->backPitch;
925   screen->depthOffset	= dri_priv->depthOffset;
926   screen->depthPitch	= dri_priv->depthPitch;
927
928   /* Check if ddx has set up a surface reg to cover depth buffer */
929   screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
930      /* these chips don't use tiled z without hyperz. So always pretend
931         we have set up a surface which will cause linear reads/writes */
932      (IS_R100_CLASS(screen) &&
933      !(screen->chip_flags & RADEON_CHIPSET_TCL));
934
935   if ( dri_priv->textureSize == 0 ) {
936      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
937      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
938      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
939	 dri_priv->log2GARTTexGran;
940   } else {
941      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
942				               + screen->fbLocation;
943      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
944      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
945	 dri_priv->log2TexGran;
946   }
947
948   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
949	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
950      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
951      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
952      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
953      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
954   } else {
955      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
956      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
957      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
958      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
959	 dri_priv->log2GARTTexGran;
960   }
961
962   i = 0;
963   screen->extensions[i++] = &driCopySubBufferExtension.base;
964   screen->extensions[i++] = &driFrameTrackingExtension.base;
965   screen->extensions[i++] = &driReadDrawableExtension;
966
967   if ( screen->irq != 0 ) {
968       screen->extensions[i++] = &driSwapControlExtension.base;
969       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
970   }
971
972#if !RADEON_COMMON
973   screen->extensions[i++] = &radeonTexOffsetExtension.base;
974#endif
975
976#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
977   if (IS_R200_CLASS(screen))
978       screen->extensions[i++] = &r200AllocateExtension.base;
979
980   screen->extensions[i++] = &r200texOffsetExtension.base;
981#endif
982
983#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
984   screen->extensions[i++] = &r300texOffsetExtension.base;
985#endif
986
987   screen->extensions[i++] = NULL;
988   sPriv->extensions = screen->extensions;
989
990   screen->driScreen = sPriv;
991   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
992   screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
993					       screen->sarea_priv_offset);
994
995   if (screen->kernel_mm)
996     screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
997   else
998     screen->bom = radeon_bo_manager_legacy_ctor(screen);
999   if (screen->bom == NULL) {
1000     free(screen);
1001     return NULL;
1002   }
1003   return screen;
1004}
1005
1006static radeonScreenPtr
1007radeonCreateScreen2(__DRIscreenPrivate *sPriv)
1008{
1009   radeonScreenPtr screen;
1010   int i;
1011
1012   /* Allocate the private area */
1013   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1014   if ( !screen ) {
1015      __driUtilMessage("%s: Could not allocate memory for screen structure",
1016		       __FUNCTION__);
1017      fprintf(stderr, "leaving here\n");
1018      return NULL;
1019   }
1020
1021#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1022	RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control);
1023#endif
1024
1025   /* parse information in __driConfigOptions */
1026   driParseOptionInfo (&screen->optionCache,
1027		       __driConfigOptions, __driNConfigOptions);
1028
1029   screen->kernel_mm = 1;
1030   screen->chip_flags = 0;
1031   /* FIXME: do either an ioctl (bad) or a sysfs file for driver to
1032    * information about which chipset is their */
1033   screen->chip_family = CHIP_FAMILY_RV350;
1034   screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CLASS_R300;
1035
1036   i = 0;
1037   screen->extensions[i++] = &driCopySubBufferExtension.base;
1038   screen->extensions[i++] = &driFrameTrackingExtension.base;
1039   screen->extensions[i++] = &driReadDrawableExtension;
1040
1041   if ( screen->irq != 0 ) {
1042       screen->extensions[i++] = &driSwapControlExtension.base;
1043       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1044   }
1045
1046#if !RADEON_COMMON
1047   screen->extensions[i++] = &radeonTexOffsetExtension.base;
1048#endif
1049
1050#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1051   if (IS_R200_CLASS(screen))
1052       screen->extensions[i++] = &r200AllocateExtension.base;
1053
1054   screen->extensions[i++] = &r200texOffsetExtension.base;
1055#endif
1056
1057#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1058   screen->extensions[i++] = &r300texOffsetExtension.base;
1059   screen->extensions[i++] = &r300TexBufferExtension.base;
1060#endif
1061
1062   screen->extensions[i++] = NULL;
1063   sPriv->extensions = screen->extensions;
1064
1065   screen->driScreen = sPriv;
1066   screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1067   if (screen->bom == NULL) {
1068       free(screen);
1069       return NULL;
1070   }
1071   return screen;
1072}
1073
1074/* Destroy the device specific screen private data struct.
1075 */
1076static void
1077radeonDestroyScreen( __DRIscreenPrivate *sPriv )
1078{
1079    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1080
1081    if (!screen)
1082        return;
1083
1084    if (screen->kernel_mm) {
1085        radeon_tracker_print(&screen->bom->tracker, stderr);
1086        radeon_bo_manager_gem_dtor(screen->bom);
1087    } else {
1088        radeon_bo_manager_legacy_dtor(screen->bom);
1089
1090        if ( screen->gartTextures.map ) {
1091            drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1092        }
1093        drmUnmapBufs( screen->buffers );
1094        drmUnmap( screen->status.map, screen->status.size );
1095        drmUnmap( screen->mmio.map, screen->mmio.size );
1096    }
1097
1098    /* free all option information */
1099    driDestroyOptionInfo (&screen->optionCache);
1100
1101    FREE( screen );
1102    sPriv->private = NULL;
1103}
1104
1105
1106/* Initialize the driver specific screen private data.
1107 */
1108static GLboolean
1109radeonInitDriver( __DRIscreenPrivate *sPriv )
1110{
1111    if (sPriv->dri2.enabled) {
1112        sPriv->private = (void *) radeonCreateScreen2( sPriv );
1113    } else {
1114        sPriv->private = (void *) radeonCreateScreen( sPriv );
1115    }
1116    if ( !sPriv->private ) {
1117        radeonDestroyScreen( sPriv );
1118        return GL_FALSE;
1119    }
1120
1121    return GL_TRUE;
1122}
1123
1124#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1125static GLboolean
1126radeon_alloc_window_storage(GLcontext *ctx, struct gl_renderbuffer *rb,
1127			    GLenum intFormat, GLuint w, GLuint h)
1128{
1129    rb->Width = w;
1130    rb->Height = h;
1131    rb->_ActualFormat = intFormat;
1132
1133    return GL_TRUE;
1134}
1135
1136
1137static struct radeon_renderbuffer *
1138radeon_create_renderbuffer(GLenum format, __DRIdrawablePrivate *driDrawPriv)
1139{
1140    struct radeon_renderbuffer *ret;
1141
1142    ret = CALLOC_STRUCT(radeon_renderbuffer);
1143    if (!ret)
1144	return NULL;
1145
1146    _mesa_init_renderbuffer(&ret->base, 0);
1147
1148    /* XXX format junk */
1149    switch (format) {
1150	case GL_RGB5:
1151	    ret->base._ActualFormat = GL_RGB5;
1152	    ret->base._BaseFormat = GL_RGBA;
1153	    ret->base.RedBits = 5;
1154	    ret->base.GreenBits = 6;
1155	    ret->base.BlueBits = 5;
1156	    ret->base.DataType = GL_UNSIGNED_BYTE;
1157	    break;
1158	case GL_RGBA8:
1159	    ret->base._ActualFormat = GL_RGBA8;
1160	    ret->base._BaseFormat = GL_RGBA;
1161	    ret->base.RedBits = 8;
1162	    ret->base.GreenBits = 8;
1163	    ret->base.BlueBits = 8;
1164	    ret->base.AlphaBits = 8;
1165	    ret->base.DataType = GL_UNSIGNED_BYTE;
1166	    break;
1167	case GL_STENCIL_INDEX8_EXT:
1168	    ret->base._ActualFormat = GL_STENCIL_INDEX8_EXT;
1169	    ret->base._BaseFormat = GL_STENCIL_INDEX;
1170	    ret->base.StencilBits = 8;
1171	    ret->base.DataType = GL_UNSIGNED_BYTE;
1172	    break;
1173	case GL_DEPTH_COMPONENT16:
1174	    ret->base._ActualFormat = GL_DEPTH_COMPONENT16;
1175	    ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1176	    ret->base.DepthBits = 16;
1177	    ret->base.DataType = GL_UNSIGNED_SHORT;
1178	    break;
1179	case GL_DEPTH_COMPONENT24:
1180	    ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1181	    ret->base._BaseFormat = GL_DEPTH_COMPONENT;
1182	    ret->base.DepthBits = 24;
1183	    ret->base.DataType = GL_UNSIGNED_INT;
1184	    break;
1185	case GL_DEPTH24_STENCIL8_EXT:
1186	    ret->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT;
1187	    ret->base._BaseFormat = GL_DEPTH_STENCIL_EXT;
1188	    ret->base.DepthBits = 24;
1189	    ret->base.StencilBits = 8;
1190	    ret->base.DataType = GL_UNSIGNED_INT_24_8_EXT;
1191	    break;
1192	default:
1193	    fprintf(stderr, "%s: Unknown format 0x%04x\n", __FUNCTION__, format);
1194	    _mesa_delete_renderbuffer(&ret->base);
1195	    return NULL;
1196    }
1197
1198    ret->dPriv = driDrawPriv;
1199    ret->base.InternalFormat = format;
1200
1201    ret->base.AllocStorage = radeon_alloc_window_storage;
1202
1203    radeonSetSpanFunctions(ret);
1204
1205    ret->bo = NULL;
1206    return ret;
1207}
1208
1209/**
1210 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1211 *
1212 * \todo This function (and its interface) will need to be updated to support
1213 * pbuffers.
1214 */
1215static GLboolean
1216radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1217                    __DRIdrawablePrivate *driDrawPriv,
1218                    const __GLcontextModes *mesaVis,
1219                    GLboolean isPixmap )
1220{
1221   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1222
1223    const GLboolean swDepth = GL_FALSE;
1224    const GLboolean swAlpha = GL_FALSE;
1225    const GLboolean swAccum = mesaVis->accumRedBits > 0;
1226    const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1227	mesaVis->depthBits != 24;
1228    GLenum rgbFormat = (mesaVis->redBits == 5 ? GL_RGB5 : GL_RGBA8);
1229    GLenum depthFormat = GL_NONE;
1230    struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1231
1232    if (mesaVis->depthBits == 16)
1233	depthFormat = GL_DEPTH_COMPONENT16;
1234    else if (mesaVis->depthBits == 24)
1235	depthFormat = GL_DEPTH_COMPONENT24;
1236
1237    /* front color renderbuffer */
1238    {
1239	struct radeon_renderbuffer *front =
1240	    radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1241	_mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &front->base);
1242	front->has_surface = 1;
1243    }
1244
1245    /* back color renderbuffer */
1246    if (mesaVis->doubleBufferMode) {
1247	struct radeon_renderbuffer *back =
1248	    radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1249	_mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &back->base);
1250	back->has_surface = 1;
1251    }
1252
1253    /* depth renderbuffer */
1254    if (depthFormat != GL_NONE) {
1255	struct radeon_renderbuffer *depth =
1256	    radeon_create_renderbuffer(depthFormat, driDrawPriv);
1257	_mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depth->base);
1258	depth->has_surface = screen->depthHasSurface;
1259    }
1260
1261    /* stencil renderbuffer */
1262    if (mesaVis->stencilBits > 0 && !swStencil) {
1263	struct radeon_renderbuffer *stencil =
1264	    radeon_create_renderbuffer(GL_STENCIL_INDEX8_EXT, driDrawPriv);
1265	_mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencil->base);
1266	stencil->has_surface = screen->depthHasSurface;
1267    }
1268
1269    _mesa_add_soft_renderbuffers(fb,
1270	    GL_FALSE, /* color */
1271	    swDepth,
1272	    swStencil,
1273	    swAccum,
1274	    swAlpha,
1275	    GL_FALSE /* aux */);
1276    driDrawPriv->driverPrivate = (void *) fb;
1277
1278    return (driDrawPriv->driverPrivate != NULL);
1279}
1280#else
1281
1282/**
1283 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1284 *
1285 * \todo This function (and its interface) will need to be updated to support
1286 * pbuffers.
1287 */
1288static GLboolean
1289radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv,
1290                    __DRIdrawablePrivate *driDrawPriv,
1291                    const __GLcontextModes *mesaVis,
1292                    GLboolean isPixmap )
1293{
1294   radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1295
1296   if (isPixmap) {
1297      return GL_FALSE; /* not implemented */
1298   }
1299   else {
1300      const GLboolean swDepth = GL_FALSE;
1301      const GLboolean swAlpha = GL_FALSE;
1302      const GLboolean swAccum = mesaVis->accumRedBits > 0;
1303      const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1304         mesaVis->depthBits != 24;
1305      struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis);
1306
1307      /* front color renderbuffer */
1308      {
1309         driRenderbuffer *frontRb
1310            = driNewRenderbuffer(GL_RGBA,
1311                                 driScrnPriv->pFB + screen->frontOffset,
1312                                 screen->cpp,
1313                                 screen->frontOffset, screen->frontPitch,
1314                                 driDrawPriv);
1315         radeonSetSpanFunctions(frontRb, mesaVis);
1316         _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base);
1317      }
1318
1319      /* back color renderbuffer */
1320      if (mesaVis->doubleBufferMode) {
1321         driRenderbuffer *backRb
1322            = driNewRenderbuffer(GL_RGBA,
1323                                 driScrnPriv->pFB + screen->backOffset,
1324                                 screen->cpp,
1325                                 screen->backOffset, screen->backPitch,
1326                                 driDrawPriv);
1327         radeonSetSpanFunctions(backRb, mesaVis);
1328         _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base);
1329      }
1330
1331      /* depth renderbuffer */
1332      if (mesaVis->depthBits == 16) {
1333         driRenderbuffer *depthRb
1334            = driNewRenderbuffer(GL_DEPTH_COMPONENT16,
1335                                 driScrnPriv->pFB + screen->depthOffset,
1336                                 screen->cpp,
1337                                 screen->depthOffset, screen->depthPitch,
1338                                 driDrawPriv);
1339         radeonSetSpanFunctions(depthRb, mesaVis);
1340         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1341    	// depthRb->has_surface = screen->depthHasSurface;
1342      }
1343      else if (mesaVis->depthBits == 24) {
1344         driRenderbuffer *depthRb
1345            = driNewRenderbuffer(GL_DEPTH_COMPONENT24,
1346                                 driScrnPriv->pFB + screen->depthOffset,
1347                                 screen->cpp,
1348                                 screen->depthOffset, screen->depthPitch,
1349                                 driDrawPriv);
1350         radeonSetSpanFunctions(depthRb, mesaVis);
1351         _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
1352 	 //    depthRb->has_surface = screen->depthHasSurface;
1353      }
1354
1355      /* stencil renderbuffer */
1356      if (mesaVis->stencilBits > 0 && !swStencil) {
1357         driRenderbuffer *stencilRb
1358            = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT,
1359                                 driScrnPriv->pFB + screen->depthOffset,
1360                                 screen->cpp,
1361                                 screen->depthOffset, screen->depthPitch,
1362                                 driDrawPriv);
1363         radeonSetSpanFunctions(stencilRb, mesaVis);
1364         _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base);
1365         //stencilRb->has_surface = screen->depthHasSurface;
1366      }
1367
1368      _mesa_add_soft_renderbuffers(fb,
1369                                   GL_FALSE, /* color */
1370                                   swDepth,
1371                                   swStencil,
1372                                   swAccum,
1373                                   swAlpha,
1374                                   GL_FALSE /* aux */);
1375      driDrawPriv->driverPrivate = (void *) fb;
1376
1377      return (driDrawPriv->driverPrivate != NULL);
1378   }
1379}
1380#endif
1381
1382static void
1383radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv)
1384{
1385	struct radeon_renderbuffer *rb;
1386	GLframebuffer *fb;
1387
1388    fb = (void*)driDrawPriv->driverPrivate;
1389    rb = (void *)fb->Attachment[BUFFER_FRONT_LEFT].Renderbuffer;
1390    if (rb && rb->bo) {
1391        radeon_bo_unref(rb->bo);
1392        rb->bo = NULL;
1393    }
1394    rb = (void *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
1395    if (rb && rb->bo) {
1396        radeon_bo_unref(rb->bo);
1397        rb->bo = NULL;
1398    }
1399    rb = (void *)fb->Attachment[BUFFER_DEPTH].Renderbuffer;
1400    if (rb && rb->bo) {
1401        radeon_bo_unref(rb->bo);
1402        rb->bo = NULL;
1403    }
1404   _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)));
1405}
1406
1407#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1408/**
1409 * Choose the appropriate CreateContext function based on the chipset.
1410 * Eventually, all drivers will go through this process.
1411 */
1412static GLboolean radeonCreateContext(const __GLcontextModes * glVisual,
1413				     __DRIcontextPrivate * driContextPriv,
1414				     void *sharedContextPriv)
1415{
1416	__DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
1417	radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
1418
1419	if (IS_R300_CLASS(screen))
1420		return r300CreateContext(glVisual, driContextPriv, sharedContextPriv);
1421        return GL_FALSE;
1422}
1423
1424/**
1425 * Choose the appropriate DestroyContext function based on the chipset.
1426 */
1427static void radeonDestroyContext(__DRIcontextPrivate * driContextPriv)
1428{
1429	radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
1430
1431	if (IS_R300_CLASS(radeon->radeonScreen))
1432		return r300DestroyContext(driContextPriv);
1433}
1434
1435
1436#endif
1437
1438/**
1439 * This is the driver specific part of the createNewScreen entry point.
1440 *
1441 * \todo maybe fold this into intelInitDriver
1442 *
1443 * \return the __GLcontextModes supported by this driver
1444 */
1445static const __DRIconfig **
1446radeonInitScreen(__DRIscreenPrivate *psp)
1447{
1448#if !RADEON_COMMON
1449   static const char *driver_name = "Radeon";
1450   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1451   static const __DRIversion dri_expected = { 4, 0, 0 };
1452   static const __DRIversion drm_expected = { 1, 6, 0 };
1453#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1454   static const char *driver_name = "R200";
1455   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1456   static const __DRIversion dri_expected = { 4, 0, 0 };
1457   static const __DRIversion drm_expected = { 1, 6, 0 };
1458#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)
1459   static const char *driver_name = "R300";
1460   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1461   static const __DRIversion dri_expected = { 4, 0, 0 };
1462   static const __DRIversion drm_expected = { 1, 24, 0 };
1463#endif
1464   RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1465
1466   if ( ! driCheckDriDdxDrmVersions3( driver_name,
1467				      &psp->dri_version, & dri_expected,
1468				      &psp->ddx_version, & ddx_expected,
1469				      &psp->drm_version, & drm_expected ) ) {
1470      return NULL;
1471   }
1472
1473   /* Calling driInitExtensions here, with a NULL context pointer,
1474    * does not actually enable the extensions.  It just makes sure
1475    * that all the dispatch offsets for all the extensions that
1476    * *might* be enables are known.  This is needed because the
1477    * dispatch offsets need to be known when _mesa_context_create
1478    * is called, but we can't enable the extensions until we have a
1479    * context pointer.
1480    *
1481    * Hello chicken.  Hello egg.  How are you two today?
1482    */
1483   driInitExtensions( NULL, card_extensions, GL_FALSE );
1484#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1485   driInitExtensions( NULL, blend_extensions, GL_FALSE );
1486   driInitSingleExtension( NULL, ARB_vp_extension );
1487   driInitSingleExtension( NULL, NV_vp_extension );
1488   driInitSingleExtension( NULL, ATI_fs_extension );
1489   driInitExtensions( NULL, point_extensions, GL_FALSE );
1490#endif
1491
1492   if (!radeonInitDriver(psp))
1493       return NULL;
1494
1495   /* for now fill in all modes */
1496   return radeonFillInModes( psp,
1497			     dri_priv->bpp,
1498			     (dri_priv->bpp == 16) ? 16 : 24,
1499			     (dri_priv->bpp == 16) ? 0  : 8, 1);
1500}
1501
1502/**
1503 * This is the driver specific part of the createNewScreen entry point.
1504 * Called when using DRI2.
1505 *
1506 * \return the __GLcontextModes supported by this driver
1507 */
1508static const
1509__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp)
1510{
1511   /* Calling driInitExtensions here, with a NULL context pointer,
1512    * does not actually enable the extensions.  It just makes sure
1513    * that all the dispatch offsets for all the extensions that
1514    * *might* be enables are known.  This is needed because the
1515    * dispatch offsets need to be known when _mesa_context_create
1516    * is called, but we can't enable the extensions until we have a
1517    * context pointer.
1518    *
1519    * Hello chicken.  Hello egg.  How are you two today?
1520    */
1521   driInitExtensions( NULL, card_extensions, GL_FALSE );
1522#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1523   driInitExtensions( NULL, blend_extensions, GL_FALSE );
1524   driInitSingleExtension( NULL, ARB_vp_extension );
1525   driInitSingleExtension( NULL, NV_vp_extension );
1526   driInitSingleExtension( NULL, ATI_fs_extension );
1527   driInitExtensions( NULL, point_extensions, GL_FALSE );
1528#endif
1529
1530   if (!radeonInitDriver(psp)) {
1531       return NULL;
1532    }
1533
1534   /* for now fill in all modes */
1535   return radeonFillInModes( psp, 24, 24, 8, 1);
1536}
1537
1538/**
1539 * Get information about previous buffer swaps.
1540 */
1541static int
1542getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo )
1543{
1544#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1545   radeonContextPtr  rmesa;
1546#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200)
1547   r200ContextPtr  rmesa;
1548#endif
1549
1550   if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1551	|| (dPriv->driContextPriv->driverPrivate == NULL)
1552	|| (sInfo == NULL) ) {
1553      return -1;
1554   }
1555
1556   rmesa = dPriv->driContextPriv->driverPrivate;
1557   sInfo->swap_count = rmesa->swap_count;
1558   sInfo->swap_ust = rmesa->swap_ust;
1559   sInfo->swap_missed_count = rmesa->swap_missed_count;
1560
1561   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1562       ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust )
1563       : 0.0;
1564
1565   return 0;
1566}
1567
1568#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300))
1569const struct __DriverAPIRec driDriverAPI = {
1570   .InitScreen      = radeonInitScreen,
1571   .DestroyScreen   = radeonDestroyScreen,
1572   .CreateContext   = radeonCreateContext,
1573   .DestroyContext  = radeonDestroyContext,
1574   .CreateBuffer    = radeonCreateBuffer,
1575   .DestroyBuffer   = radeonDestroyBuffer,
1576   .SwapBuffers     = radeonSwapBuffers,
1577   .MakeCurrent     = radeonMakeCurrent,
1578   .UnbindContext   = radeonUnbindContext,
1579   .GetSwapInfo     = getSwapInfo,
1580   .GetDrawableMSC  = driDrawableGetMSC32,
1581   .WaitForMSC      = driWaitForMSC32,
1582   .WaitForSBC      = NULL,
1583   .SwapBuffersMSC  = NULL,
1584   .CopySubBuffer   = radeonCopySubBuffer,
1585    /* DRI2 */
1586   .InitScreen2     = radeonInitScreen2,
1587};
1588#else
1589const struct __DriverAPIRec driDriverAPI = {
1590   .InitScreen      = radeonInitScreen,
1591   .DestroyScreen   = radeonDestroyScreen,
1592   .CreateContext   = r200CreateContext,
1593   .DestroyContext  = r200DestroyContext,
1594   .CreateBuffer    = radeonCreateBuffer,
1595   .DestroyBuffer   = radeonDestroyBuffer,
1596   .SwapBuffers     = r200SwapBuffers,
1597   .MakeCurrent     = r200MakeCurrent,
1598   .UnbindContext   = r200UnbindContext,
1599   .GetSwapInfo     = getSwapInfo,
1600   .GetDrawableMSC  = driDrawableGetMSC32,
1601   .WaitForMSC      = driWaitForMSC32,
1602   .WaitForSBC      = NULL,
1603   .SwapBuffersMSC  = NULL,
1604   .CopySubBuffer   = r200CopySubBuffer,
1605};
1606#endif
1607
1608