radeon_screen.c revision b0da65bd0e5ecb443cfd0dbae15f5ae5638bcf72 
1/**************************************************************************
2
3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4                     VA Linux Systems Inc., Fremont, California.
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining
9a copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sublicense, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial
18portions of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author  Gareth Hughes <gareth@valinux.com>
36 */
37
38#include <errno.h>
39#include "main/glheader.h"
40#include "main/imports.h"
41#include "main/mtypes.h"
42#include "main/framebuffer.h"
43#include "main/renderbuffer.h"
44#include "main/fbobject.h"
45
46#define STANDALONE_MMIO
47#include "radeon_chipset.h"
48#include "radeon_macros.h"
49#include "radeon_screen.h"
50#include "radeon_common.h"
51#include "radeon_common_context.h"
52#if defined(RADEON_R100)
53#include "radeon_context.h"
54#include "radeon_tex.h"
55#elif defined(RADEON_R200)
56#include "r200_context.h"
57#include "r200_tex.h"
58#elif defined(RADEON_R300)
59#include "r300_context.h"
60#include "r300_tex.h"
61#elif defined(RADEON_R600)
62#include "r600_context.h"
63#include "r700_driconf.h" /* +r6/r7 */
64#include "r600_tex.h"     /* +r6/r7 */
65#endif
66
67#include "utils.h"
68#include "vblank.h"
69
70#include "radeon_bocs_wrapper.h"
71
72#include "GL/internal/dri_interface.h"
73
74/* Radeon configuration
75 */
76#include "xmlpool.h"
77
78#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
79DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
80        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
81        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
82DRI_CONF_OPT_END
83
84#if defined(RADEON_R100)	/* R100 */
85PUBLIC const char __driConfigOptions[] =
86DRI_CONF_BEGIN
87    DRI_CONF_SECTION_PERFORMANCE
88        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
89        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
90        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
91        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
92        DRI_CONF_HYPERZ(false)
93        DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
94    DRI_CONF_SECTION_END
95    DRI_CONF_SECTION_QUALITY
96        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
97        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
98        DRI_CONF_NO_NEG_LOD_BIAS(false)
99        DRI_CONF_FORCE_S3TC_ENABLE(false)
100        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
101        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
102        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
103        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
104    DRI_CONF_SECTION_END
105    DRI_CONF_SECTION_DEBUG
106        DRI_CONF_NO_RAST(false)
107    DRI_CONF_SECTION_END
108DRI_CONF_END;
109static const GLuint __driNConfigOptions = 15;
110
111#elif defined(RADEON_R200)
112
113PUBLIC const char __driConfigOptions[] =
114DRI_CONF_BEGIN
115    DRI_CONF_SECTION_PERFORMANCE
116        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
117        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
118        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
119        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
120        DRI_CONF_HYPERZ(false)
121        DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
122    DRI_CONF_SECTION_END
123    DRI_CONF_SECTION_QUALITY
124        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
125        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
126        DRI_CONF_NO_NEG_LOD_BIAS(false)
127        DRI_CONF_FORCE_S3TC_ENABLE(false)
128        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
129        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
130        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
131        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
132        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
133    DRI_CONF_SECTION_END
134    DRI_CONF_SECTION_DEBUG
135        DRI_CONF_NO_RAST(false)
136    DRI_CONF_SECTION_END
137    DRI_CONF_SECTION_SOFTWARE
138        DRI_CONF_NV_VERTEX_PROGRAM(false)
139    DRI_CONF_SECTION_END
140DRI_CONF_END;
141static const GLuint __driNConfigOptions = 17;
142
143#elif defined(RADEON_R300) || defined(RADEON_R600)
144
145#define DRI_CONF_FP_OPTIMIZATION_SPEED   0
146#define DRI_CONF_FP_OPTIMIZATION_QUALITY 1
147
148/* TODO: integrate these into xmlpool.h! */
149#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \
150DRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \
151        DRI_CONF_DESC(en,"Number of texture image units") \
152        DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \
153DRI_CONF_OPT_END
154
155#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \
156DRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \
157        DRI_CONF_DESC(en,"Number of texture coordinate units") \
158        DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \
159DRI_CONF_OPT_END
160
161
162
163#define DRI_CONF_DISABLE_S3TC(def) \
164DRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \
165        DRI_CONF_DESC(en,"Disable S3TC compression") \
166DRI_CONF_OPT_END
167
168#define DRI_CONF_DISABLE_FALLBACK(def) \
169DRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \
170        DRI_CONF_DESC(en,"Disable Low-impact fallback") \
171DRI_CONF_OPT_END
172
173#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \
174DRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \
175        DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \
176DRI_CONF_OPT_END
177
178#define DRI_CONF_FP_OPTIMIZATION(def) \
179DRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \
180	DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \
181                DRI_CONF_ENUM(0,"Optimize for Speed") \
182                DRI_CONF_ENUM(1,"Optimize for Quality") \
183        DRI_CONF_DESC_END \
184DRI_CONF_OPT_END
185
186PUBLIC const char __driConfigOptions[] =
187DRI_CONF_BEGIN
188	DRI_CONF_SECTION_PERFORMANCE
189		DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
190		DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
191		DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
192		DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8)
193		DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8)
194		DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
195		DRI_CONF_DISABLE_FALLBACK(true)
196		DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false)
197	DRI_CONF_SECTION_END
198	DRI_CONF_SECTION_QUALITY
199		DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
200		DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0")
201		DRI_CONF_FORCE_S3TC_ENABLE(false)
202		DRI_CONF_DISABLE_S3TC(false)
203		DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
204		DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
205		DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
206		DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED)
207	DRI_CONF_SECTION_END
208	DRI_CONF_SECTION_DEBUG
209		DRI_CONF_NO_RAST(false)
210	DRI_CONF_SECTION_END
211DRI_CONF_END;
212static const GLuint __driNConfigOptions = 17;
213
214#endif
215
216static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
217
218#ifndef RADEON_INFO_TILE_CONFIG
219#define RADEON_INFO_TILE_CONFIG 0x6
220#endif
221
222static int
223radeonGetParam(__DRIscreen *sPriv, int param, void *value)
224{
225  int ret;
226  drm_radeon_getparam_t gp = { 0 };
227  struct drm_radeon_info info = { 0 };
228
229  if (sPriv->drm_version.major >= 2) {
230      info.value = (uint64_t)(uintptr_t)value;
231      switch (param) {
232      case RADEON_PARAM_DEVICE_ID:
233          info.request = RADEON_INFO_DEVICE_ID;
234          break;
235      case RADEON_PARAM_NUM_GB_PIPES:
236          info.request = RADEON_INFO_NUM_GB_PIPES;
237          break;
238      case RADEON_PARAM_NUM_Z_PIPES:
239          info.request = RADEON_INFO_NUM_Z_PIPES;
240          break;
241      case RADEON_INFO_TILE_CONFIG:
242	  info.request = RADEON_INFO_TILE_CONFIG;
243          break;
244      default:
245          return -EINVAL;
246      }
247      ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
248  } else {
249      gp.param = param;
250      gp.value = value;
251
252      ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
253  }
254  return ret;
255}
256
257static const __DRIconfig **
258radeonFillInModes( __DRIscreen *psp,
259		   unsigned pixel_bits, unsigned depth_bits,
260		   unsigned stencil_bits, GLboolean have_back_buffer )
261{
262    __DRIconfig **configs;
263    struct gl_config *m;
264    unsigned depth_buffer_factor;
265    unsigned back_buffer_factor;
266    int i;
267
268    /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy
269     * enough to add support.  Basically, if a context is created with an
270     * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping
271     * will never be used.
272     */
273    static const GLenum back_buffer_modes[] = {
274	GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */
275    };
276
277    uint8_t depth_bits_array[2];
278    uint8_t stencil_bits_array[2];
279    uint8_t msaa_samples_array[1];
280
281    depth_bits_array[0] = depth_bits;
282    depth_bits_array[1] = depth_bits;
283
284    /* Just like with the accumulation buffer, always provide some modes
285     * with a stencil buffer.  It will be a sw fallback, but some apps won't
286     * care about that.
287     */
288    stencil_bits_array[0] = stencil_bits;
289    stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits;
290
291    msaa_samples_array[0] = 0;
292
293    depth_buffer_factor = (stencil_bits == 0) ? 2 : 1;
294    back_buffer_factor  = (have_back_buffer) ? 2 : 1;
295
296    if (pixel_bits == 16) {
297	__DRIconfig **configs_a8r8g8b8;
298	__DRIconfig **configs_r5g6b5;
299
300	configs_r5g6b5 = driCreateConfigs(GL_RGB, GL_UNSIGNED_SHORT_5_6_5,
301					  depth_bits_array, stencil_bits_array,
302					  depth_buffer_factor, back_buffer_modes,
303					  back_buffer_factor, msaa_samples_array,
304					  1, GL_TRUE);
305	configs_a8r8g8b8 = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
306					    depth_bits_array, stencil_bits_array,
307					    1, back_buffer_modes, 1,
308					    msaa_samples_array, 1, GL_TRUE);
309	configs = driConcatConfigs(configs_r5g6b5, configs_a8r8g8b8);
310   } else
311	configs = driCreateConfigs(GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV,
312				   depth_bits_array, stencil_bits_array,
313				   depth_buffer_factor,
314				   back_buffer_modes, back_buffer_factor,
315				   msaa_samples_array, 1, GL_TRUE);
316
317    if (configs == NULL) {
318	fprintf( stderr, "[%s:%u] Error creating FBConfig!\n",
319		 __func__, __LINE__ );
320	return NULL;
321    }
322
323    /* Mark the visual as slow if there are "fake" stencil bits.
324     */
325    for (i = 0; configs[i]; i++) {
326	m = &configs[i]->modes;
327	if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) {
328	    m->visualRating = GLX_SLOW_CONFIG;
329	}
330    }
331
332    return (const __DRIconfig **) configs;
333}
334
335#if defined(RADEON_R100)
336static const __DRItexOffsetExtension radeonTexOffsetExtension = {
337    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
338    radeonSetTexOffset,
339};
340
341static const __DRItexBufferExtension radeonTexBufferExtension = {
342    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
343   radeonSetTexBuffer,
344   radeonSetTexBuffer2,
345};
346#endif
347
348#if defined(RADEON_R200)
349
350static const __DRItexOffsetExtension r200texOffsetExtension = {
351    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
352   r200SetTexOffset,
353};
354
355static const __DRItexBufferExtension r200TexBufferExtension = {
356    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
357   r200SetTexBuffer,
358   r200SetTexBuffer2,
359};
360#endif
361
362#if defined(RADEON_R300)
363static const __DRItexOffsetExtension r300texOffsetExtension = {
364    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
365   r300SetTexOffset,
366};
367
368static const __DRItexBufferExtension r300TexBufferExtension = {
369    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
370   r300SetTexBuffer,
371   r300SetTexBuffer2,
372};
373#endif
374
375#if defined(RADEON_R600)
376static const __DRItexOffsetExtension r600texOffsetExtension = {
377    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
378   r600SetTexOffset, /* +r6/r7 */
379};
380
381static const __DRItexBufferExtension r600TexBufferExtension = {
382    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
383   r600SetTexBuffer,  /* +r6/r7 */
384   r600SetTexBuffer2, /* +r6/r7 */
385};
386#endif
387
388static void
389radeonDRI2Flush(__DRIdrawable *drawable)
390{
391    radeonContextPtr rmesa;
392
393    rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
394    radeonFlush(rmesa->glCtx);
395}
396
397static const struct __DRI2flushExtensionRec radeonFlushExtension = {
398    { __DRI2_FLUSH, __DRI2_FLUSH_VERSION },
399    radeonDRI2Flush,
400    dri2InvalidateDrawable,
401};
402
403static __DRIimage *
404radeon_create_image_from_name(__DRIscreen *screen,
405                              int width, int height, int format,
406                              int name, int pitch, void *loaderPrivate)
407{
408   __DRIimage *image;
409   radeonScreenPtr radeonScreen = screen->private;
410
411   if (name == 0)
412      return NULL;
413
414   image = CALLOC(sizeof *image);
415   if (image == NULL)
416      return NULL;
417
418   switch (format) {
419   case __DRI_IMAGE_FORMAT_RGB565:
420      image->format = MESA_FORMAT_RGB565;
421      image->internal_format = GL_RGB;
422      image->data_type = GL_UNSIGNED_BYTE;
423      break;
424   case __DRI_IMAGE_FORMAT_XRGB8888:
425      image->format = MESA_FORMAT_XRGB8888;
426      image->internal_format = GL_RGB;
427      image->data_type = GL_UNSIGNED_BYTE;
428      break;
429   case __DRI_IMAGE_FORMAT_ARGB8888:
430      image->format = MESA_FORMAT_ARGB8888;
431      image->internal_format = GL_RGBA;
432      image->data_type = GL_UNSIGNED_BYTE;
433      break;
434   default:
435      free(image);
436      return NULL;
437   }
438
439   image->data = loaderPrivate;
440   image->cpp = _mesa_get_format_bytes(image->format);
441   image->width = width;
442   image->pitch = pitch;
443   image->height = height;
444
445   image->bo = radeon_bo_open(radeonScreen->bom,
446                              (uint32_t)name,
447                              image->pitch * image->height * image->cpp,
448                              0,
449                              RADEON_GEM_DOMAIN_VRAM,
450                              0);
451
452   if (image->bo == NULL) {
453      FREE(image);
454      return NULL;
455   }
456
457   return image;
458}
459
460static __DRIimage *
461radeon_create_image_from_renderbuffer(__DRIcontext *context,
462                                      int renderbuffer, void *loaderPrivate)
463{
464   __DRIimage *image;
465   radeonContextPtr radeon = context->driverPrivate;
466   struct gl_renderbuffer *rb;
467   struct radeon_renderbuffer *rrb;
468
469   rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer);
470   if (!rb) {
471      _mesa_error(radeon->glCtx,
472                  GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
473      return NULL;
474   }
475
476   rrb = radeon_renderbuffer(rb);
477   image = CALLOC(sizeof *image);
478   if (image == NULL)
479      return NULL;
480
481   image->internal_format = rb->InternalFormat;
482   image->format = rb->Format;
483   image->cpp = rrb->cpp;
484   image->data_type = rb->DataType;
485   image->data = loaderPrivate;
486   radeon_bo_ref(rrb->bo);
487   image->bo = rrb->bo;
488
489   image->width = rb->Width;
490   image->height = rb->Height;
491   image->pitch = rrb->pitch / image->cpp;
492
493   return image;
494}
495
496static void
497radeon_destroy_image(__DRIimage *image)
498{
499   radeon_bo_unref(image->bo);
500   FREE(image);
501}
502
503static __DRIimage *
504radeon_create_image(__DRIscreen *screen,
505                    int width, int height, int format,
506                    unsigned int use,
507                    void *loaderPrivate)
508{
509   __DRIimage *image;
510   radeonScreenPtr radeonScreen = screen->private;
511
512   image = CALLOC(sizeof *image);
513   if (image == NULL)
514      return NULL;
515
516   switch (format) {
517   case __DRI_IMAGE_FORMAT_RGB565:
518      image->format = MESA_FORMAT_RGB565;
519      image->internal_format = GL_RGB;
520      image->data_type = GL_UNSIGNED_BYTE;
521      break;
522   case __DRI_IMAGE_FORMAT_XRGB8888:
523      image->format = MESA_FORMAT_XRGB8888;
524      image->internal_format = GL_RGB;
525      image->data_type = GL_UNSIGNED_BYTE;
526      break;
527   case __DRI_IMAGE_FORMAT_ARGB8888:
528      image->format = MESA_FORMAT_ARGB8888;
529      image->internal_format = GL_RGBA;
530      image->data_type = GL_UNSIGNED_BYTE;
531      break;
532   default:
533      free(image);
534      return NULL;
535   }
536
537   image->data = loaderPrivate;
538   image->cpp = _mesa_get_format_bytes(image->format);
539   image->width = width;
540   image->height = height;
541   image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
542
543   image->bo = radeon_bo_open(radeonScreen->bom,
544                              0,
545                              image->pitch * image->height * image->cpp,
546                              0,
547                              RADEON_GEM_DOMAIN_VRAM,
548                              0);
549
550   if (image->bo == NULL) {
551      FREE(image);
552      return NULL;
553   }
554
555   return image;
556}
557
558static GLboolean
559radeon_query_image(__DRIimage *image, int attrib, int *value)
560{
561   switch (attrib) {
562   case __DRI_IMAGE_ATTRIB_STRIDE:
563      *value = image->pitch * image->cpp;
564      return GL_TRUE;
565   case __DRI_IMAGE_ATTRIB_HANDLE:
566      *value = image->bo->handle;
567      return GL_TRUE;
568   case __DRI_IMAGE_ATTRIB_NAME:
569      radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
570      return GL_TRUE;
571   default:
572      return GL_FALSE;
573   }
574}
575
576static struct __DRIimageExtensionRec radeonImageExtension = {
577    { __DRI_IMAGE, __DRI_IMAGE_VERSION },
578   radeon_create_image_from_name,
579   radeon_create_image_from_renderbuffer,
580   radeon_destroy_image,
581   radeon_create_image,
582   radeon_query_image
583};
584
585static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
586{
587   screen->device_id = device_id;
588   screen->chip_flags = 0;
589   switch ( device_id ) {
590   case PCI_CHIP_RN50_515E:
591   case PCI_CHIP_RN50_5969:
592	return -1;
593
594   case PCI_CHIP_RADEON_LY:
595   case PCI_CHIP_RADEON_LZ:
596   case PCI_CHIP_RADEON_QY:
597   case PCI_CHIP_RADEON_QZ:
598      screen->chip_family = CHIP_FAMILY_RV100;
599      break;
600
601   case PCI_CHIP_RS100_4136:
602   case PCI_CHIP_RS100_4336:
603      screen->chip_family = CHIP_FAMILY_RS100;
604      break;
605
606   case PCI_CHIP_RS200_4137:
607   case PCI_CHIP_RS200_4337:
608   case PCI_CHIP_RS250_4237:
609   case PCI_CHIP_RS250_4437:
610      screen->chip_family = CHIP_FAMILY_RS200;
611      break;
612
613   case PCI_CHIP_RADEON_QD:
614   case PCI_CHIP_RADEON_QE:
615   case PCI_CHIP_RADEON_QF:
616   case PCI_CHIP_RADEON_QG:
617      /* all original radeons (7200) presumably have a stencil op bug */
618      screen->chip_family = CHIP_FAMILY_R100;
619      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
620      break;
621
622   case PCI_CHIP_RV200_QW:
623   case PCI_CHIP_RV200_QX:
624   case PCI_CHIP_RADEON_LW:
625   case PCI_CHIP_RADEON_LX:
626      screen->chip_family = CHIP_FAMILY_RV200;
627      screen->chip_flags = RADEON_CHIPSET_TCL;
628      break;
629
630   case PCI_CHIP_R200_BB:
631   case PCI_CHIP_R200_QH:
632   case PCI_CHIP_R200_QL:
633   case PCI_CHIP_R200_QM:
634      screen->chip_family = CHIP_FAMILY_R200;
635      screen->chip_flags = RADEON_CHIPSET_TCL;
636      break;
637
638   case PCI_CHIP_RV250_If:
639   case PCI_CHIP_RV250_Ig:
640   case PCI_CHIP_RV250_Ld:
641   case PCI_CHIP_RV250_Lf:
642   case PCI_CHIP_RV250_Lg:
643      screen->chip_family = CHIP_FAMILY_RV250;
644      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
645      break;
646
647   case PCI_CHIP_RV280_5960:
648   case PCI_CHIP_RV280_5961:
649   case PCI_CHIP_RV280_5962:
650   case PCI_CHIP_RV280_5964:
651   case PCI_CHIP_RV280_5965:
652   case PCI_CHIP_RV280_5C61:
653   case PCI_CHIP_RV280_5C63:
654      screen->chip_family = CHIP_FAMILY_RV280;
655      screen->chip_flags = RADEON_CHIPSET_TCL;
656      break;
657
658   case PCI_CHIP_RS300_5834:
659   case PCI_CHIP_RS300_5835:
660   case PCI_CHIP_RS350_7834:
661   case PCI_CHIP_RS350_7835:
662      screen->chip_family = CHIP_FAMILY_RS300;
663      break;
664
665   case PCI_CHIP_R300_AD:
666   case PCI_CHIP_R300_AE:
667   case PCI_CHIP_R300_AF:
668   case PCI_CHIP_R300_AG:
669   case PCI_CHIP_R300_ND:
670   case PCI_CHIP_R300_NE:
671   case PCI_CHIP_R300_NF:
672   case PCI_CHIP_R300_NG:
673      screen->chip_family = CHIP_FAMILY_R300;
674      screen->chip_flags = RADEON_CHIPSET_TCL;
675      break;
676
677   case PCI_CHIP_RV350_AP:
678   case PCI_CHIP_RV350_AQ:
679   case PCI_CHIP_RV350_AR:
680   case PCI_CHIP_RV350_AS:
681   case PCI_CHIP_RV350_AT:
682   case PCI_CHIP_RV350_AV:
683   case PCI_CHIP_RV350_AU:
684   case PCI_CHIP_RV350_NP:
685   case PCI_CHIP_RV350_NQ:
686   case PCI_CHIP_RV350_NR:
687   case PCI_CHIP_RV350_NS:
688   case PCI_CHIP_RV350_NT:
689   case PCI_CHIP_RV350_NV:
690      screen->chip_family = CHIP_FAMILY_RV350;
691      screen->chip_flags = RADEON_CHIPSET_TCL;
692      break;
693
694   case PCI_CHIP_R350_AH:
695   case PCI_CHIP_R350_AI:
696   case PCI_CHIP_R350_AJ:
697   case PCI_CHIP_R350_AK:
698   case PCI_CHIP_R350_NH:
699   case PCI_CHIP_R350_NI:
700   case PCI_CHIP_R360_NJ:
701   case PCI_CHIP_R350_NK:
702      screen->chip_family = CHIP_FAMILY_R350;
703      screen->chip_flags = RADEON_CHIPSET_TCL;
704      break;
705
706   case PCI_CHIP_RV370_5460:
707   case PCI_CHIP_RV370_5462:
708   case PCI_CHIP_RV370_5464:
709   case PCI_CHIP_RV370_5B60:
710   case PCI_CHIP_RV370_5B62:
711   case PCI_CHIP_RV370_5B63:
712   case PCI_CHIP_RV370_5B64:
713   case PCI_CHIP_RV370_5B65:
714   case PCI_CHIP_RV380_3150:
715   case PCI_CHIP_RV380_3152:
716   case PCI_CHIP_RV380_3154:
717   case PCI_CHIP_RV380_3155:
718   case PCI_CHIP_RV380_3E50:
719   case PCI_CHIP_RV380_3E54:
720      screen->chip_family = CHIP_FAMILY_RV380;
721      screen->chip_flags = RADEON_CHIPSET_TCL;
722      break;
723
724   case PCI_CHIP_R420_JN:
725   case PCI_CHIP_R420_JH:
726   case PCI_CHIP_R420_JI:
727   case PCI_CHIP_R420_JJ:
728   case PCI_CHIP_R420_JK:
729   case PCI_CHIP_R420_JL:
730   case PCI_CHIP_R420_JM:
731   case PCI_CHIP_R420_JO:
732   case PCI_CHIP_R420_JP:
733   case PCI_CHIP_R420_JT:
734   case PCI_CHIP_R481_4B49:
735   case PCI_CHIP_R481_4B4A:
736   case PCI_CHIP_R481_4B4B:
737   case PCI_CHIP_R481_4B4C:
738   case PCI_CHIP_R423_UH:
739   case PCI_CHIP_R423_UI:
740   case PCI_CHIP_R423_UJ:
741   case PCI_CHIP_R423_UK:
742   case PCI_CHIP_R430_554C:
743   case PCI_CHIP_R430_554D:
744   case PCI_CHIP_R430_554E:
745   case PCI_CHIP_R430_554F:
746   case PCI_CHIP_R423_5550:
747   case PCI_CHIP_R423_UQ:
748   case PCI_CHIP_R423_UR:
749   case PCI_CHIP_R423_UT:
750   case PCI_CHIP_R430_5D48:
751   case PCI_CHIP_R430_5D49:
752   case PCI_CHIP_R430_5D4A:
753   case PCI_CHIP_R480_5D4C:
754   case PCI_CHIP_R480_5D4D:
755   case PCI_CHIP_R480_5D4E:
756   case PCI_CHIP_R480_5D4F:
757   case PCI_CHIP_R480_5D50:
758   case PCI_CHIP_R480_5D52:
759   case PCI_CHIP_R423_5D57:
760      screen->chip_family = CHIP_FAMILY_R420;
761      screen->chip_flags = RADEON_CHIPSET_TCL;
762      break;
763
764   case PCI_CHIP_RV410_5E4C:
765   case PCI_CHIP_RV410_5E4F:
766   case PCI_CHIP_RV410_564A:
767   case PCI_CHIP_RV410_564B:
768   case PCI_CHIP_RV410_564F:
769   case PCI_CHIP_RV410_5652:
770   case PCI_CHIP_RV410_5653:
771   case PCI_CHIP_RV410_5657:
772   case PCI_CHIP_RV410_5E48:
773   case PCI_CHIP_RV410_5E4A:
774   case PCI_CHIP_RV410_5E4B:
775   case PCI_CHIP_RV410_5E4D:
776      screen->chip_family = CHIP_FAMILY_RV410;
777      screen->chip_flags = RADEON_CHIPSET_TCL;
778      break;
779
780   case PCI_CHIP_RS480_5954:
781   case PCI_CHIP_RS480_5955:
782   case PCI_CHIP_RS482_5974:
783   case PCI_CHIP_RS482_5975:
784   case PCI_CHIP_RS400_5A41:
785   case PCI_CHIP_RS400_5A42:
786   case PCI_CHIP_RC410_5A61:
787   case PCI_CHIP_RC410_5A62:
788      screen->chip_family = CHIP_FAMILY_RS400;
789      break;
790
791   case PCI_CHIP_RS600_793F:
792   case PCI_CHIP_RS600_7941:
793   case PCI_CHIP_RS600_7942:
794      screen->chip_family = CHIP_FAMILY_RS600;
795      break;
796
797   case PCI_CHIP_RS690_791E:
798   case PCI_CHIP_RS690_791F:
799      screen->chip_family = CHIP_FAMILY_RS690;
800      break;
801   case PCI_CHIP_RS740_796C:
802   case PCI_CHIP_RS740_796D:
803   case PCI_CHIP_RS740_796E:
804   case PCI_CHIP_RS740_796F:
805      screen->chip_family = CHIP_FAMILY_RS740;
806      break;
807
808   case PCI_CHIP_R520_7100:
809   case PCI_CHIP_R520_7101:
810   case PCI_CHIP_R520_7102:
811   case PCI_CHIP_R520_7103:
812   case PCI_CHIP_R520_7104:
813   case PCI_CHIP_R520_7105:
814   case PCI_CHIP_R520_7106:
815   case PCI_CHIP_R520_7108:
816   case PCI_CHIP_R520_7109:
817   case PCI_CHIP_R520_710A:
818   case PCI_CHIP_R520_710B:
819   case PCI_CHIP_R520_710C:
820   case PCI_CHIP_R520_710E:
821   case PCI_CHIP_R520_710F:
822      screen->chip_family = CHIP_FAMILY_R520;
823      screen->chip_flags = RADEON_CHIPSET_TCL;
824      break;
825
826   case PCI_CHIP_RV515_7140:
827   case PCI_CHIP_RV515_7141:
828   case PCI_CHIP_RV515_7142:
829   case PCI_CHIP_RV515_7143:
830   case PCI_CHIP_RV515_7144:
831   case PCI_CHIP_RV515_7145:
832   case PCI_CHIP_RV515_7146:
833   case PCI_CHIP_RV515_7147:
834   case PCI_CHIP_RV515_7149:
835   case PCI_CHIP_RV515_714A:
836   case PCI_CHIP_RV515_714B:
837   case PCI_CHIP_RV515_714C:
838   case PCI_CHIP_RV515_714D:
839   case PCI_CHIP_RV515_714E:
840   case PCI_CHIP_RV515_714F:
841   case PCI_CHIP_RV515_7151:
842   case PCI_CHIP_RV515_7152:
843   case PCI_CHIP_RV515_7153:
844   case PCI_CHIP_RV515_715E:
845   case PCI_CHIP_RV515_715F:
846   case PCI_CHIP_RV515_7180:
847   case PCI_CHIP_RV515_7181:
848   case PCI_CHIP_RV515_7183:
849   case PCI_CHIP_RV515_7186:
850   case PCI_CHIP_RV515_7187:
851   case PCI_CHIP_RV515_7188:
852   case PCI_CHIP_RV515_718A:
853   case PCI_CHIP_RV515_718B:
854   case PCI_CHIP_RV515_718C:
855   case PCI_CHIP_RV515_718D:
856   case PCI_CHIP_RV515_718F:
857   case PCI_CHIP_RV515_7193:
858   case PCI_CHIP_RV515_7196:
859   case PCI_CHIP_RV515_719B:
860   case PCI_CHIP_RV515_719F:
861   case PCI_CHIP_RV515_7200:
862   case PCI_CHIP_RV515_7210:
863   case PCI_CHIP_RV515_7211:
864      screen->chip_family = CHIP_FAMILY_RV515;
865      screen->chip_flags = RADEON_CHIPSET_TCL;
866      break;
867
868   case PCI_CHIP_RV530_71C0:
869   case PCI_CHIP_RV530_71C1:
870   case PCI_CHIP_RV530_71C2:
871   case PCI_CHIP_RV530_71C3:
872   case PCI_CHIP_RV530_71C4:
873   case PCI_CHIP_RV530_71C5:
874   case PCI_CHIP_RV530_71C6:
875   case PCI_CHIP_RV530_71C7:
876   case PCI_CHIP_RV530_71CD:
877   case PCI_CHIP_RV530_71CE:
878   case PCI_CHIP_RV530_71D2:
879   case PCI_CHIP_RV530_71D4:
880   case PCI_CHIP_RV530_71D5:
881   case PCI_CHIP_RV530_71D6:
882   case PCI_CHIP_RV530_71DA:
883   case PCI_CHIP_RV530_71DE:
884      screen->chip_family = CHIP_FAMILY_RV530;
885      screen->chip_flags = RADEON_CHIPSET_TCL;
886      break;
887
888   case PCI_CHIP_R580_7240:
889   case PCI_CHIP_R580_7243:
890   case PCI_CHIP_R580_7244:
891   case PCI_CHIP_R580_7245:
892   case PCI_CHIP_R580_7246:
893   case PCI_CHIP_R580_7247:
894   case PCI_CHIP_R580_7248:
895   case PCI_CHIP_R580_7249:
896   case PCI_CHIP_R580_724A:
897   case PCI_CHIP_R580_724B:
898   case PCI_CHIP_R580_724C:
899   case PCI_CHIP_R580_724D:
900   case PCI_CHIP_R580_724E:
901   case PCI_CHIP_R580_724F:
902   case PCI_CHIP_R580_7284:
903      screen->chip_family = CHIP_FAMILY_R580;
904      screen->chip_flags = RADEON_CHIPSET_TCL;
905      break;
906
907   case PCI_CHIP_RV570_7280:
908   case PCI_CHIP_RV560_7281:
909   case PCI_CHIP_RV560_7283:
910   case PCI_CHIP_RV560_7287:
911   case PCI_CHIP_RV570_7288:
912   case PCI_CHIP_RV570_7289:
913   case PCI_CHIP_RV570_728B:
914   case PCI_CHIP_RV570_728C:
915   case PCI_CHIP_RV560_7290:
916   case PCI_CHIP_RV560_7291:
917   case PCI_CHIP_RV560_7293:
918   case PCI_CHIP_RV560_7297:
919      screen->chip_family = CHIP_FAMILY_RV560;
920      screen->chip_flags = RADEON_CHIPSET_TCL;
921      break;
922
923   case PCI_CHIP_R600_9400:
924   case PCI_CHIP_R600_9401:
925   case PCI_CHIP_R600_9402:
926   case PCI_CHIP_R600_9403:
927   case PCI_CHIP_R600_9405:
928   case PCI_CHIP_R600_940A:
929   case PCI_CHIP_R600_940B:
930   case PCI_CHIP_R600_940F:
931      screen->chip_family = CHIP_FAMILY_R600;
932      screen->chip_flags = RADEON_CHIPSET_TCL;
933      break;
934
935   case PCI_CHIP_RV610_94C0:
936   case PCI_CHIP_RV610_94C1:
937   case PCI_CHIP_RV610_94C3:
938   case PCI_CHIP_RV610_94C4:
939   case PCI_CHIP_RV610_94C5:
940   case PCI_CHIP_RV610_94C6:
941   case PCI_CHIP_RV610_94C7:
942   case PCI_CHIP_RV610_94C8:
943   case PCI_CHIP_RV610_94C9:
944   case PCI_CHIP_RV610_94CB:
945   case PCI_CHIP_RV610_94CC:
946   case PCI_CHIP_RV610_94CD:
947      screen->chip_family = CHIP_FAMILY_RV610;
948      screen->chip_flags = RADEON_CHIPSET_TCL;
949      break;
950
951   case PCI_CHIP_RV630_9580:
952   case PCI_CHIP_RV630_9581:
953   case PCI_CHIP_RV630_9583:
954   case PCI_CHIP_RV630_9586:
955   case PCI_CHIP_RV630_9587:
956   case PCI_CHIP_RV630_9588:
957   case PCI_CHIP_RV630_9589:
958   case PCI_CHIP_RV630_958A:
959   case PCI_CHIP_RV630_958B:
960   case PCI_CHIP_RV630_958C:
961   case PCI_CHIP_RV630_958D:
962   case PCI_CHIP_RV630_958E:
963   case PCI_CHIP_RV630_958F:
964      screen->chip_family = CHIP_FAMILY_RV630;
965      screen->chip_flags = RADEON_CHIPSET_TCL;
966      break;
967
968   case PCI_CHIP_RV670_9500:
969   case PCI_CHIP_RV670_9501:
970   case PCI_CHIP_RV670_9504:
971   case PCI_CHIP_RV670_9505:
972   case PCI_CHIP_RV670_9506:
973   case PCI_CHIP_RV670_9507:
974   case PCI_CHIP_RV670_9508:
975   case PCI_CHIP_RV670_9509:
976   case PCI_CHIP_RV670_950F:
977   case PCI_CHIP_RV670_9511:
978   case PCI_CHIP_RV670_9515:
979   case PCI_CHIP_RV670_9517:
980   case PCI_CHIP_RV670_9519:
981      screen->chip_family = CHIP_FAMILY_RV670;
982      screen->chip_flags = RADEON_CHIPSET_TCL;
983      break;
984
985   case PCI_CHIP_RV620_95C0:
986   case PCI_CHIP_RV620_95C2:
987   case PCI_CHIP_RV620_95C4:
988   case PCI_CHIP_RV620_95C5:
989   case PCI_CHIP_RV620_95C6:
990   case PCI_CHIP_RV620_95C7:
991   case PCI_CHIP_RV620_95C9:
992   case PCI_CHIP_RV620_95CC:
993   case PCI_CHIP_RV620_95CD:
994   case PCI_CHIP_RV620_95CE:
995   case PCI_CHIP_RV620_95CF:
996      screen->chip_family = CHIP_FAMILY_RV620;
997      screen->chip_flags = RADEON_CHIPSET_TCL;
998      break;
999
1000   case PCI_CHIP_RV635_9590:
1001   case PCI_CHIP_RV635_9591:
1002   case PCI_CHIP_RV635_9593:
1003   case PCI_CHIP_RV635_9595:
1004   case PCI_CHIP_RV635_9596:
1005   case PCI_CHIP_RV635_9597:
1006   case PCI_CHIP_RV635_9598:
1007   case PCI_CHIP_RV635_9599:
1008   case PCI_CHIP_RV635_959B:
1009      screen->chip_family = CHIP_FAMILY_RV635;
1010      screen->chip_flags = RADEON_CHIPSET_TCL;
1011      break;
1012
1013   case PCI_CHIP_RS780_9610:
1014   case PCI_CHIP_RS780_9611:
1015   case PCI_CHIP_RS780_9612:
1016   case PCI_CHIP_RS780_9613:
1017   case PCI_CHIP_RS780_9614:
1018   case PCI_CHIP_RS780_9615:
1019   case PCI_CHIP_RS780_9616:
1020      screen->chip_family = CHIP_FAMILY_RS780;
1021      screen->chip_flags = RADEON_CHIPSET_TCL;
1022      break;
1023   case PCI_CHIP_RS880_9710:
1024   case PCI_CHIP_RS880_9711:
1025   case PCI_CHIP_RS880_9712:
1026   case PCI_CHIP_RS880_9713:
1027   case PCI_CHIP_RS880_9714:
1028   case PCI_CHIP_RS880_9715:
1029      screen->chip_family = CHIP_FAMILY_RS880;
1030      screen->chip_flags = RADEON_CHIPSET_TCL;
1031      break;
1032
1033   case PCI_CHIP_RV770_9440:
1034   case PCI_CHIP_RV770_9441:
1035   case PCI_CHIP_RV770_9442:
1036   case PCI_CHIP_RV770_9443:
1037   case PCI_CHIP_RV770_9444:
1038   case PCI_CHIP_RV770_9446:
1039   case PCI_CHIP_RV770_944A:
1040   case PCI_CHIP_RV770_944B:
1041   case PCI_CHIP_RV770_944C:
1042   case PCI_CHIP_RV770_944E:
1043   case PCI_CHIP_RV770_9450:
1044   case PCI_CHIP_RV770_9452:
1045   case PCI_CHIP_RV770_9456:
1046   case PCI_CHIP_RV770_945A:
1047   case PCI_CHIP_RV770_945B:
1048   case PCI_CHIP_RV770_945E:
1049   case PCI_CHIP_RV790_9460:
1050   case PCI_CHIP_RV790_9462:
1051   case PCI_CHIP_RV770_946A:
1052   case PCI_CHIP_RV770_946B:
1053   case PCI_CHIP_RV770_947A:
1054   case PCI_CHIP_RV770_947B:
1055      screen->chip_family = CHIP_FAMILY_RV770;
1056      screen->chip_flags = RADEON_CHIPSET_TCL;
1057      break;
1058
1059   case PCI_CHIP_RV730_9480:
1060   case PCI_CHIP_RV730_9487:
1061   case PCI_CHIP_RV730_9488:
1062   case PCI_CHIP_RV730_9489:
1063   case PCI_CHIP_RV730_948A:
1064   case PCI_CHIP_RV730_948F:
1065   case PCI_CHIP_RV730_9490:
1066   case PCI_CHIP_RV730_9491:
1067   case PCI_CHIP_RV730_9495:
1068   case PCI_CHIP_RV730_9498:
1069   case PCI_CHIP_RV730_949C:
1070   case PCI_CHIP_RV730_949E:
1071   case PCI_CHIP_RV730_949F:
1072      screen->chip_family = CHIP_FAMILY_RV730;
1073      screen->chip_flags = RADEON_CHIPSET_TCL;
1074      break;
1075
1076   case PCI_CHIP_RV710_9540:
1077   case PCI_CHIP_RV710_9541:
1078   case PCI_CHIP_RV710_9542:
1079   case PCI_CHIP_RV710_954E:
1080   case PCI_CHIP_RV710_954F:
1081   case PCI_CHIP_RV710_9552:
1082   case PCI_CHIP_RV710_9553:
1083   case PCI_CHIP_RV710_9555:
1084   case PCI_CHIP_RV710_9557:
1085   case PCI_CHIP_RV710_955F:
1086      screen->chip_family = CHIP_FAMILY_RV710;
1087      screen->chip_flags = RADEON_CHIPSET_TCL;
1088      break;
1089
1090   case PCI_CHIP_RV740_94A0:
1091   case PCI_CHIP_RV740_94A1:
1092   case PCI_CHIP_RV740_94A3:
1093   case PCI_CHIP_RV740_94B1:
1094   case PCI_CHIP_RV740_94B3:
1095   case PCI_CHIP_RV740_94B4:
1096   case PCI_CHIP_RV740_94B5:
1097   case PCI_CHIP_RV740_94B9:
1098      screen->chip_family = CHIP_FAMILY_RV740;
1099      screen->chip_flags = RADEON_CHIPSET_TCL;
1100      break;
1101
1102    case PCI_CHIP_CEDAR_68E0:
1103    case PCI_CHIP_CEDAR_68E1:
1104    case PCI_CHIP_CEDAR_68E4:
1105    case PCI_CHIP_CEDAR_68E5:
1106    case PCI_CHIP_CEDAR_68E8:
1107    case PCI_CHIP_CEDAR_68E9:
1108    case PCI_CHIP_CEDAR_68F1:
1109    case PCI_CHIP_CEDAR_68F8:
1110    case PCI_CHIP_CEDAR_68F9:
1111    case PCI_CHIP_CEDAR_68FE:
1112       screen->chip_family = CHIP_FAMILY_CEDAR;
1113       screen->chip_flags = RADEON_CHIPSET_TCL;
1114       break;
1115
1116    case PCI_CHIP_REDWOOD_68C0:
1117    case PCI_CHIP_REDWOOD_68C1:
1118    case PCI_CHIP_REDWOOD_68C8:
1119    case PCI_CHIP_REDWOOD_68C9:
1120    case PCI_CHIP_REDWOOD_68D8:
1121    case PCI_CHIP_REDWOOD_68D9:
1122    case PCI_CHIP_REDWOOD_68DA:
1123    case PCI_CHIP_REDWOOD_68DE:
1124       screen->chip_family = CHIP_FAMILY_REDWOOD;
1125       screen->chip_flags = RADEON_CHIPSET_TCL;
1126       break;
1127
1128    case PCI_CHIP_JUNIPER_68A0:
1129    case PCI_CHIP_JUNIPER_68A1:
1130    case PCI_CHIP_JUNIPER_68A8:
1131    case PCI_CHIP_JUNIPER_68A9:
1132    case PCI_CHIP_JUNIPER_68B0:
1133    case PCI_CHIP_JUNIPER_68B8:
1134    case PCI_CHIP_JUNIPER_68B9:
1135    case PCI_CHIP_JUNIPER_68BE:
1136       screen->chip_family = CHIP_FAMILY_JUNIPER;
1137       screen->chip_flags = RADEON_CHIPSET_TCL;
1138       break;
1139
1140    case PCI_CHIP_CYPRESS_6880:
1141    case PCI_CHIP_CYPRESS_6888:
1142    case PCI_CHIP_CYPRESS_6889:
1143    case PCI_CHIP_CYPRESS_688A:
1144    case PCI_CHIP_CYPRESS_6898:
1145    case PCI_CHIP_CYPRESS_6899:
1146    case PCI_CHIP_CYPRESS_689E:
1147       screen->chip_family = CHIP_FAMILY_CYPRESS;
1148       screen->chip_flags = RADEON_CHIPSET_TCL;
1149       break;
1150
1151    case PCI_CHIP_HEMLOCK_689C:
1152    case PCI_CHIP_HEMLOCK_689D:
1153       screen->chip_family = CHIP_FAMILY_HEMLOCK;
1154       screen->chip_flags = RADEON_CHIPSET_TCL;
1155       break;
1156
1157    case PCI_CHIP_PALM_9802:
1158    case PCI_CHIP_PALM_9803:
1159    case PCI_CHIP_PALM_9804:
1160    case PCI_CHIP_PALM_9805:
1161    case PCI_CHIP_PALM_9806:
1162    case PCI_CHIP_PALM_9807:
1163       screen->chip_family = CHIP_FAMILY_PALM;
1164       screen->chip_flags = RADEON_CHIPSET_TCL;
1165       break;
1166
1167   case PCI_CHIP_BARTS_6720:
1168   case PCI_CHIP_BARTS_6721:
1169   case PCI_CHIP_BARTS_6722:
1170   case PCI_CHIP_BARTS_6723:
1171   case PCI_CHIP_BARTS_6724:
1172   case PCI_CHIP_BARTS_6725:
1173   case PCI_CHIP_BARTS_6726:
1174   case PCI_CHIP_BARTS_6727:
1175   case PCI_CHIP_BARTS_6728:
1176   case PCI_CHIP_BARTS_6729:
1177   case PCI_CHIP_BARTS_6738:
1178   case PCI_CHIP_BARTS_6739:
1179       screen->chip_family = CHIP_FAMILY_BARTS;
1180       screen->chip_flags = RADEON_CHIPSET_TCL;
1181       break;
1182
1183   case PCI_CHIP_TURKS_6740:
1184   case PCI_CHIP_TURKS_6741:
1185   case PCI_CHIP_TURKS_6742:
1186   case PCI_CHIP_TURKS_6743:
1187   case PCI_CHIP_TURKS_6744:
1188   case PCI_CHIP_TURKS_6745:
1189   case PCI_CHIP_TURKS_6746:
1190   case PCI_CHIP_TURKS_6747:
1191   case PCI_CHIP_TURKS_6748:
1192   case PCI_CHIP_TURKS_6749:
1193   case PCI_CHIP_TURKS_6750:
1194   case PCI_CHIP_TURKS_6758:
1195   case PCI_CHIP_TURKS_6759:
1196       screen->chip_family = CHIP_FAMILY_TURKS;
1197       screen->chip_flags = RADEON_CHIPSET_TCL;
1198       break;
1199
1200   case PCI_CHIP_CAICOS_6760:
1201   case PCI_CHIP_CAICOS_6761:
1202   case PCI_CHIP_CAICOS_6762:
1203   case PCI_CHIP_CAICOS_6763:
1204   case PCI_CHIP_CAICOS_6764:
1205   case PCI_CHIP_CAICOS_6765:
1206   case PCI_CHIP_CAICOS_6766:
1207   case PCI_CHIP_CAICOS_6767:
1208   case PCI_CHIP_CAICOS_6768:
1209   case PCI_CHIP_CAICOS_6770:
1210   case PCI_CHIP_CAICOS_6779:
1211       screen->chip_family = CHIP_FAMILY_CAICOS;
1212       screen->chip_flags = RADEON_CHIPSET_TCL;
1213       break;
1214
1215   default:
1216      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
1217	      device_id);
1218      return -1;
1219   }
1220
1221   return 0;
1222}
1223
1224
1225/* Create the device specific screen private data struct.
1226 */
1227static radeonScreenPtr
1228radeonCreateScreen( __DRIscreen *sPriv )
1229{
1230   radeonScreenPtr screen;
1231   RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv;
1232   unsigned char *RADEONMMIO = NULL;
1233   int i;
1234   int ret;
1235   uint32_t temp = 0;
1236
1237   if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) {
1238      fprintf(stderr,"\nERROR!  sizeof(RADEONDRIRec) does not match passed size from device driver\n");
1239      return GL_FALSE;
1240   }
1241
1242   /* Allocate the private area */
1243   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1244   if ( !screen ) {
1245      __driUtilMessage("%s: Could not allocate memory for screen structure",
1246		       __FUNCTION__);
1247      return NULL;
1248   }
1249
1250   radeon_init_debug();
1251
1252   /* parse information in __driConfigOptions */
1253   driParseOptionInfo (&screen->optionCache,
1254		       __driConfigOptions, __driNConfigOptions);
1255
1256   /* This is first since which regions we map depends on whether or
1257    * not we are using a PCI card.
1258    */
1259   screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP);
1260   {
1261      int ret;
1262
1263      ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BUFFER_OFFSET,
1264			    &screen->gart_buffer_offset);
1265
1266      if (ret) {
1267	 FREE( screen );
1268	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
1269	 return NULL;
1270      }
1271
1272      ret = radeonGetParam(sPriv, RADEON_PARAM_GART_BASE,
1273			    &screen->gart_base);
1274      if (ret) {
1275	 FREE( screen );
1276	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret);
1277	 return NULL;
1278      }
1279
1280      ret = radeonGetParam(sPriv, RADEON_PARAM_IRQ_NR,
1281			    &screen->irq);
1282      if (ret) {
1283	 FREE( screen );
1284	 fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
1285	 return NULL;
1286      }
1287      screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7);
1288      screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11);
1289      screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16);
1290      screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18);
1291      screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13);
1292      screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15);
1293      screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25);
1294      screen->drmSupportsOcclusionQueries = (sPriv->drm_version.minor >= 30);
1295   }
1296
1297   ret = radeon_set_screen_flags(screen, dri_priv->deviceID);
1298   if (ret == -1)
1299     return NULL;
1300
1301   screen->mmio.handle = dri_priv->registerHandle;
1302   screen->mmio.size   = dri_priv->registerSize;
1303   if ( drmMap( sPriv->fd,
1304		screen->mmio.handle,
1305		screen->mmio.size,
1306		&screen->mmio.map ) ) {
1307     FREE( screen );
1308     __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ );
1309     return NULL;
1310   }
1311
1312   RADEONMMIO = screen->mmio.map;
1313
1314   screen->status.handle = dri_priv->statusHandle;
1315   screen->status.size   = dri_priv->statusSize;
1316   if ( drmMap( sPriv->fd,
1317		screen->status.handle,
1318		screen->status.size,
1319		&screen->status.map ) ) {
1320     drmUnmap( screen->mmio.map, screen->mmio.size );
1321     FREE( screen );
1322     __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ );
1323     return NULL;
1324   }
1325   if (screen->chip_family < CHIP_FAMILY_R600)
1326	   screen->scratch = (__volatile__ uint32_t *)
1327		   ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET);
1328   else
1329	   screen->scratch = (__volatile__ uint32_t *)
1330		   ((GLubyte *)screen->status.map + R600_SCRATCH_REG_OFFSET);
1331
1332   screen->buffers = drmMapBufs( sPriv->fd );
1333   if ( !screen->buffers ) {
1334     drmUnmap( screen->status.map, screen->status.size );
1335     drmUnmap( screen->mmio.map, screen->mmio.size );
1336     FREE( screen );
1337     __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ );
1338     return NULL;
1339   }
1340
1341   if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) {
1342     screen->gartTextures.handle = dri_priv->gartTexHandle;
1343     screen->gartTextures.size   = dri_priv->gartTexMapSize;
1344     if ( drmMap( sPriv->fd,
1345		  screen->gartTextures.handle,
1346		  screen->gartTextures.size,
1347		  (drmAddressPtr)&screen->gartTextures.map ) ) {
1348       drmUnmapBufs( screen->buffers );
1349       drmUnmap( screen->status.map, screen->status.size );
1350       drmUnmap( screen->mmio.map, screen->mmio.size );
1351       FREE( screen );
1352       __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__);
1353       return NULL;
1354    }
1355
1356     screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base;
1357   }
1358
1359   if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) &&
1360       sPriv->ddx_version.minor < 2) {
1361      fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n");
1362      return NULL;
1363   }
1364
1365   if ((sPriv->drm_version.minor < 29) && (screen->chip_family >= CHIP_FAMILY_RV515)) {
1366      fprintf(stderr, "R500 support requires a newer drm.\n");
1367      return NULL;
1368   }
1369
1370   if (getenv("R300_NO_TCL"))
1371	   screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1372
1373   if (screen->chip_family <= CHIP_FAMILY_RS200)
1374	   screen->chip_flags |= RADEON_CLASS_R100;
1375   else if (screen->chip_family <= CHIP_FAMILY_RV280)
1376	   screen->chip_flags |= RADEON_CLASS_R200;
1377   else if (screen->chip_family <= CHIP_FAMILY_RV570)
1378	   screen->chip_flags |= RADEON_CLASS_R300;
1379   else
1380	   screen->chip_flags |= RADEON_CLASS_R600;
1381
1382   /* set group bytes for r6xx+ */
1383   if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1384	   screen->group_bytes = 512;
1385   else
1386	   screen->group_bytes = 256;
1387
1388   screen->cpp = dri_priv->bpp / 8;
1389   screen->AGPMode = dri_priv->AGPMode;
1390
1391   ret = radeonGetParam(sPriv, RADEON_PARAM_FB_LOCATION, &temp);
1392
1393   /* +r6/r7 */
1394   if(screen->chip_family >= CHIP_FAMILY_R600)
1395   {
1396       if (ret)
1397       {
1398            FREE( screen );
1399            fprintf(stderr, "Unable to get fb location need newer drm\n");
1400            return NULL;
1401       }
1402       else
1403       {
1404            screen->fbLocation = (temp & 0xffff) << 24;
1405       }
1406   }
1407   else
1408   {
1409        if (ret)
1410        {
1411            if (screen->chip_family < CHIP_FAMILY_RS600 && !screen->kernel_mm)
1412	            screen->fbLocation      = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16;
1413            else
1414            {
1415                FREE( screen );
1416                fprintf(stderr, "Unable to get fb location need newer drm\n");
1417                return NULL;
1418            }
1419        }
1420        else
1421        {
1422            screen->fbLocation = (temp & 0xffff) << 16;
1423        }
1424   }
1425
1426   if (IS_R300_CLASS(screen)) {
1427       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1428       if (ret) {
1429	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1430	   switch (screen->chip_family) {
1431	   case CHIP_FAMILY_R300:
1432	   case CHIP_FAMILY_R350:
1433	       screen->num_gb_pipes = 2;
1434	       break;
1435	   case CHIP_FAMILY_R420:
1436	   case CHIP_FAMILY_R520:
1437	   case CHIP_FAMILY_R580:
1438	   case CHIP_FAMILY_RV560:
1439	   case CHIP_FAMILY_RV570:
1440	       screen->num_gb_pipes = 4;
1441	       break;
1442	   case CHIP_FAMILY_RV350:
1443	   case CHIP_FAMILY_RV515:
1444	   case CHIP_FAMILY_RV530:
1445	   case CHIP_FAMILY_RV410:
1446	   default:
1447	       screen->num_gb_pipes = 1;
1448	       break;
1449	   }
1450       } else {
1451	   screen->num_gb_pipes = temp;
1452       }
1453
1454       /* pipe overrides */
1455       switch (dri_priv->deviceID) {
1456       case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1457       case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1458       case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1459       case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1460	   screen->num_gb_pipes = 1;
1461	   break;
1462       default:
1463	   break;
1464       }
1465
1466       if ( sPriv->drm_version.minor >= 31 ) {
1467	       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1468	       if (ret)
1469		       screen->num_z_pipes = 2;
1470	       else
1471		       screen->num_z_pipes = temp;
1472       } else
1473	       screen->num_z_pipes = 2;
1474   }
1475
1476   if ( sPriv->drm_version.minor >= 10 ) {
1477      drm_radeon_setparam_t sp;
1478
1479      sp.param = RADEON_SETPARAM_FB_LOCATION;
1480      sp.value = screen->fbLocation;
1481
1482      drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM,
1483		       &sp, sizeof( sp ) );
1484   }
1485
1486   screen->frontOffset	= dri_priv->frontOffset;
1487   screen->frontPitch	= dri_priv->frontPitch;
1488   screen->backOffset	= dri_priv->backOffset;
1489   screen->backPitch	= dri_priv->backPitch;
1490   screen->depthOffset	= dri_priv->depthOffset;
1491   screen->depthPitch	= dri_priv->depthPitch;
1492
1493   /* Check if ddx has set up a surface reg to cover depth buffer */
1494   screen->depthHasSurface = (sPriv->ddx_version.major > 4) ||
1495      /* these chips don't use tiled z without hyperz. So always pretend
1496         we have set up a surface which will cause linear reads/writes */
1497      (IS_R100_CLASS(screen) &&
1498      !(screen->chip_flags & RADEON_CHIPSET_TCL));
1499
1500   if ( dri_priv->textureSize == 0 ) {
1501      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset;
1502      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize;
1503      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1504	 dri_priv->log2GARTTexGran;
1505   } else {
1506      screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
1507				               + screen->fbLocation;
1508      screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
1509      screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
1510	 dri_priv->log2TexGran;
1511   }
1512
1513   if ( !screen->gartTextures.map || dri_priv->textureSize == 0
1514	|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
1515      screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
1516      screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
1517      screen->texSize[RADEON_GART_TEX_HEAP] = 0;
1518      screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
1519   } else {
1520      screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
1521      screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
1522      screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
1523      screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
1524	 dri_priv->log2GARTTexGran;
1525   }
1526
1527   i = 0;
1528   screen->extensions[i++] = &driCopySubBufferExtension.base;
1529   screen->extensions[i++] = &driReadDrawableExtension;
1530
1531   if ( screen->irq != 0 ) {
1532       screen->extensions[i++] = &driSwapControlExtension.base;
1533       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1534   }
1535
1536#if defined(RADEON_R100)
1537   screen->extensions[i++] = &radeonTexOffsetExtension.base;
1538#endif
1539
1540#if defined(RADEON_R200)
1541   screen->extensions[i++] = &r200texOffsetExtension.base;
1542#endif
1543
1544#if defined(RADEON_R300)
1545   screen->extensions[i++] = &r300texOffsetExtension.base;
1546#endif
1547
1548#if defined(RADEON_R600)
1549   screen->extensions[i++] = &r600texOffsetExtension.base;
1550#endif
1551
1552   screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1553
1554   screen->extensions[i++] = NULL;
1555   sPriv->extensions = screen->extensions;
1556
1557   screen->driScreen = sPriv;
1558   screen->sarea_priv_offset = dri_priv->sarea_priv_offset;
1559   screen->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
1560					       screen->sarea_priv_offset);
1561
1562   screen->bom = radeon_bo_manager_legacy_ctor(screen);
1563   if (screen->bom == NULL) {
1564     free(screen);
1565     return NULL;
1566   }
1567
1568   return screen;
1569}
1570
1571static radeonScreenPtr
1572radeonCreateScreen2(__DRIscreen *sPriv)
1573{
1574   radeonScreenPtr screen;
1575   int i;
1576   int ret;
1577   uint32_t device_id = 0;
1578   uint32_t temp = 0;
1579
1580   /* Allocate the private area */
1581   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1582   if ( !screen ) {
1583      __driUtilMessage("%s: Could not allocate memory for screen structure",
1584		       __FUNCTION__);
1585      fprintf(stderr, "leaving here\n");
1586      return NULL;
1587   }
1588
1589   radeon_init_debug();
1590
1591   /* parse information in __driConfigOptions */
1592   driParseOptionInfo (&screen->optionCache,
1593		       __driConfigOptions, __driNConfigOptions);
1594
1595   screen->kernel_mm = 1;
1596   screen->chip_flags = 0;
1597
1598   /* if we have kms we can support all of these */
1599   screen->drmSupportsCubeMapsR200 = 1;
1600   screen->drmSupportsBlendColor = 1;
1601   screen->drmSupportsTriPerf = 1;
1602   screen->drmSupportsFragShader = 1;
1603   screen->drmSupportsPointSprites = 1;
1604   screen->drmSupportsCubeMapsR100 = 1;
1605   screen->drmSupportsVertexProgram = 1;
1606   screen->drmSupportsOcclusionQueries = 1;
1607   screen->irq = 1;
1608
1609   ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1610   if (ret) {
1611     FREE( screen );
1612     fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1613     return NULL;
1614   }
1615
1616   ret = radeon_set_screen_flags(screen, device_id);
1617   if (ret == -1)
1618     return NULL;
1619
1620   if (getenv("R300_NO_TCL"))
1621	   screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1622
1623   if (screen->chip_family <= CHIP_FAMILY_RS200)
1624	   screen->chip_flags |= RADEON_CLASS_R100;
1625   else if (screen->chip_family <= CHIP_FAMILY_RV280)
1626	   screen->chip_flags |= RADEON_CLASS_R200;
1627   else if (screen->chip_family <= CHIP_FAMILY_RV570)
1628	   screen->chip_flags |= RADEON_CLASS_R300;
1629   else
1630	   screen->chip_flags |= RADEON_CLASS_R600;
1631
1632   /* r6xx+ tiling, default group bytes */
1633   if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1634	   screen->group_bytes = 512;
1635   else
1636	   screen->group_bytes = 256;
1637   if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6) &&
1638       (screen->chip_family < CHIP_FAMILY_CEDAR)) {
1639	   ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1640	   if (ret)
1641		   fprintf(stderr, "failed to get tiling info\n");
1642	   else {
1643		   screen->tile_config = temp;
1644		   screen->r7xx_bank_op = 0;
1645		   switch((screen->tile_config & 0xe) >> 1) {
1646		   case 0:
1647			   screen->num_channels = 1;
1648			   break;
1649		   case 1:
1650			   screen->num_channels = 2;
1651			   break;
1652		   case 2:
1653			   screen->num_channels = 4;
1654			   break;
1655		   case 3:
1656			   screen->num_channels = 8;
1657			   break;
1658		   default:
1659			   fprintf(stderr, "bad channels\n");
1660			   break;
1661		   }
1662		   switch((screen->tile_config & 0x30) >> 4) {
1663		   case 0:
1664			   screen->num_banks = 4;
1665			   break;
1666		   case 1:
1667			   screen->num_banks = 8;
1668			   break;
1669		   default:
1670			   fprintf(stderr, "bad banks\n");
1671			   break;
1672		   }
1673		   switch((screen->tile_config & 0xc0) >> 6) {
1674		   case 0:
1675			   screen->group_bytes = 256;
1676			   break;
1677		   case 1:
1678			   screen->group_bytes = 512;
1679			   break;
1680		   default:
1681			   fprintf(stderr, "bad group_bytes\n");
1682			   break;
1683		   }
1684	   }
1685   }
1686
1687   if (IS_R300_CLASS(screen)) {
1688       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1689       if (ret) {
1690	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1691	   switch (screen->chip_family) {
1692	   case CHIP_FAMILY_R300:
1693	   case CHIP_FAMILY_R350:
1694	       screen->num_gb_pipes = 2;
1695	       break;
1696	   case CHIP_FAMILY_R420:
1697	   case CHIP_FAMILY_R520:
1698	   case CHIP_FAMILY_R580:
1699	   case CHIP_FAMILY_RV560:
1700	   case CHIP_FAMILY_RV570:
1701	       screen->num_gb_pipes = 4;
1702	       break;
1703	   case CHIP_FAMILY_RV350:
1704	   case CHIP_FAMILY_RV515:
1705	   case CHIP_FAMILY_RV530:
1706	   case CHIP_FAMILY_RV410:
1707	   default:
1708	       screen->num_gb_pipes = 1;
1709	       break;
1710	   }
1711       } else {
1712	   screen->num_gb_pipes = temp;
1713       }
1714
1715       /* pipe overrides */
1716       switch (device_id) {
1717       case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1718       case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1719       case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1720       case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1721	   screen->num_gb_pipes = 1;
1722	   break;
1723       default:
1724	   break;
1725       }
1726
1727       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1728       if (ret)
1729	       screen->num_z_pipes = 2;
1730       else
1731	       screen->num_z_pipes = temp;
1732
1733   }
1734
1735   i = 0;
1736   screen->extensions[i++] = &driCopySubBufferExtension.base;
1737   screen->extensions[i++] = &driReadDrawableExtension;
1738   screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1739
1740   if ( screen->irq != 0 ) {
1741       screen->extensions[i++] = &driSwapControlExtension.base;
1742       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1743   }
1744
1745#if defined(RADEON_R100)
1746   screen->extensions[i++] = &radeonTexBufferExtension.base;
1747#endif
1748
1749#if defined(RADEON_R200)
1750   screen->extensions[i++] = &r200TexBufferExtension.base;
1751#endif
1752
1753#if defined(RADEON_R300)
1754   screen->extensions[i++] = &r300TexBufferExtension.base;
1755#endif
1756
1757#if defined(RADEON_R600)
1758   screen->extensions[i++] = &r600TexBufferExtension.base;
1759#endif
1760
1761   screen->extensions[i++] = &radeonFlushExtension.base;
1762   screen->extensions[i++] = &radeonImageExtension.base;
1763
1764   screen->extensions[i++] = NULL;
1765   sPriv->extensions = screen->extensions;
1766
1767   screen->driScreen = sPriv;
1768   screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1769   if (screen->bom == NULL) {
1770       free(screen);
1771       return NULL;
1772   }
1773   return screen;
1774}
1775
1776/* Destroy the device specific screen private data struct.
1777 */
1778static void
1779radeonDestroyScreen( __DRIscreen *sPriv )
1780{
1781    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1782
1783    if (!screen)
1784        return;
1785
1786    if (screen->kernel_mm) {
1787#ifdef RADEON_BO_TRACK
1788        radeon_tracker_print(&screen->bom->tracker, stderr);
1789#endif
1790        radeon_bo_manager_gem_dtor(screen->bom);
1791    } else {
1792        radeon_bo_manager_legacy_dtor(screen->bom);
1793
1794        if ( screen->gartTextures.map ) {
1795            drmUnmap( screen->gartTextures.map, screen->gartTextures.size );
1796        }
1797        drmUnmapBufs( screen->buffers );
1798        drmUnmap( screen->status.map, screen->status.size );
1799        drmUnmap( screen->mmio.map, screen->mmio.size );
1800    }
1801
1802    /* free all option information */
1803    driDestroyOptionInfo (&screen->optionCache);
1804
1805    FREE( screen );
1806    sPriv->private = NULL;
1807}
1808
1809
1810/* Initialize the driver specific screen private data.
1811 */
1812static GLboolean
1813radeonInitDriver( __DRIscreen *sPriv )
1814{
1815    if (sPriv->dri2.enabled) {
1816        sPriv->private = (void *) radeonCreateScreen2( sPriv );
1817    } else {
1818        sPriv->private = (void *) radeonCreateScreen( sPriv );
1819    }
1820    if ( !sPriv->private ) {
1821        radeonDestroyScreen( sPriv );
1822        return GL_FALSE;
1823    }
1824
1825    return GL_TRUE;
1826}
1827
1828
1829
1830/**
1831 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1832 *
1833 * \todo This function (and its interface) will need to be updated to support
1834 * pbuffers.
1835 */
1836static GLboolean
1837radeonCreateBuffer( __DRIscreen *driScrnPriv,
1838                    __DRIdrawable *driDrawPriv,
1839                    const struct gl_config *mesaVis,
1840                    GLboolean isPixmap )
1841{
1842    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1843
1844    const GLboolean swDepth = GL_FALSE;
1845    const GLboolean swAlpha = GL_FALSE;
1846    const GLboolean swAccum = mesaVis->accumRedBits > 0;
1847    const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1848	mesaVis->depthBits != 24;
1849    gl_format rgbFormat;
1850    struct radeon_framebuffer *rfb;
1851
1852    if (isPixmap)
1853      return GL_FALSE; /* not implemented */
1854
1855    rfb = CALLOC_STRUCT(radeon_framebuffer);
1856    if (!rfb)
1857      return GL_FALSE;
1858
1859    _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1860
1861    if (mesaVis->redBits == 5)
1862        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1863    else if (mesaVis->alphaBits == 0)
1864        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1865    else
1866        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1867
1868    /* front color renderbuffer */
1869    rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1870    _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1871    rfb->color_rb[0]->has_surface = 1;
1872
1873    /* back color renderbuffer */
1874    if (mesaVis->doubleBufferMode) {
1875      rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1876	_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1877	rfb->color_rb[1]->has_surface = 1;
1878    }
1879
1880    if (mesaVis->depthBits == 24) {
1881      if (mesaVis->stencilBits == 8) {
1882	struct radeon_renderbuffer *depthStencilRb =
1883           radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1884	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1885	_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1886	depthStencilRb->has_surface = screen->depthHasSurface;
1887      } else {
1888	/* depth renderbuffer */
1889	struct radeon_renderbuffer *depth =
1890           radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1891	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1892	depth->has_surface = screen->depthHasSurface;
1893      }
1894    } else if (mesaVis->depthBits == 16) {
1895        /* just 16-bit depth buffer, no hw stencil */
1896	struct radeon_renderbuffer *depth =
1897           radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1898	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1899	depth->has_surface = screen->depthHasSurface;
1900    }
1901
1902    _mesa_add_soft_renderbuffers(&rfb->base,
1903	    GL_FALSE, /* color */
1904	    swDepth,
1905	    swStencil,
1906	    swAccum,
1907	    swAlpha,
1908	    GL_FALSE /* aux */);
1909    driDrawPriv->driverPrivate = (void *) rfb;
1910
1911    return (driDrawPriv->driverPrivate != NULL);
1912}
1913
1914
1915static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1916{
1917	struct radeon_renderbuffer *rb;
1918
1919	rb = rfb->color_rb[0];
1920	if (rb && rb->bo) {
1921		radeon_bo_unref(rb->bo);
1922		rb->bo = NULL;
1923	}
1924	rb = rfb->color_rb[1];
1925	if (rb && rb->bo) {
1926		radeon_bo_unref(rb->bo);
1927		rb->bo = NULL;
1928	}
1929	rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1930	if (rb && rb->bo) {
1931		radeon_bo_unref(rb->bo);
1932		rb->bo = NULL;
1933	}
1934}
1935
1936void
1937radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1938{
1939    struct radeon_framebuffer *rfb;
1940    if (!driDrawPriv)
1941	return;
1942
1943    rfb = (void*)driDrawPriv->driverPrivate;
1944    if (!rfb)
1945	return;
1946    radeon_cleanup_renderbuffers(rfb);
1947    _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1948}
1949
1950
1951/**
1952 * This is the driver specific part of the createNewScreen entry point.
1953 *
1954 * \todo maybe fold this into intelInitDriver
1955 *
1956 * \return the struct gl_config supported by this driver
1957 */
1958static const __DRIconfig **
1959radeonInitScreen(__DRIscreen *psp)
1960{
1961#if defined(RADEON_R100)
1962   static const char *driver_name = "Radeon";
1963   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1964   static const __DRIversion dri_expected = { 4, 0, 0 };
1965   static const __DRIversion drm_expected = { 1, 6, 0 };
1966#elif defined(RADEON_R200)
1967   static const char *driver_name = "R200";
1968   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1969   static const __DRIversion dri_expected = { 4, 0, 0 };
1970   static const __DRIversion drm_expected = { 1, 6, 0 };
1971#elif defined(RADEON_R300)
1972   static const char *driver_name = "R300";
1973   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1974   static const __DRIversion dri_expected = { 4, 0, 0 };
1975   static const __DRIversion drm_expected = { 1, 24, 0 };
1976#elif defined(RADEON_R600)
1977   static const char *driver_name = "R600";
1978   static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 };
1979   static const __DRIversion dri_expected = { 4, 0, 0 };
1980   static const __DRIversion drm_expected = { 1, 24, 0 };
1981#endif
1982   RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv;
1983
1984   if ( ! driCheckDriDdxDrmVersions3( driver_name,
1985				      &psp->dri_version, & dri_expected,
1986				      &psp->ddx_version, & ddx_expected,
1987				      &psp->drm_version, & drm_expected ) ) {
1988      return NULL;
1989   }
1990
1991   if (!radeonInitDriver(psp))
1992       return NULL;
1993
1994   /* for now fill in all modes */
1995   return radeonFillInModes( psp,
1996			     dri_priv->bpp,
1997			     (dri_priv->bpp == 16) ? 16 : 24,
1998			     (dri_priv->bpp == 16) ? 0  : 8, 1);
1999}
2000#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
2001
2002/**
2003 * This is the driver specific part of the createNewScreen entry point.
2004 * Called when using DRI2.
2005 *
2006 * \return the struct gl_config supported by this driver
2007 */
2008static const
2009__DRIconfig **radeonInitScreen2(__DRIscreen *psp)
2010{
2011   GLenum fb_format[3];
2012   GLenum fb_type[3];
2013   /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
2014    * support pageflipping at all.
2015    */
2016   static const GLenum back_buffer_modes[] = {
2017     GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
2018   };
2019   uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
2020   int color;
2021   __DRIconfig **configs = NULL;
2022
2023   if (!radeonInitDriver(psp)) {
2024       return NULL;
2025    }
2026   depth_bits[0] = 0;
2027   stencil_bits[0] = 0;
2028   depth_bits[1] = 16;
2029   stencil_bits[1] = 0;
2030   depth_bits[2] = 24;
2031   stencil_bits[2] = 0;
2032   depth_bits[3] = 24;
2033   stencil_bits[3] = 8;
2034
2035   msaa_samples_array[0] = 0;
2036
2037   fb_format[0] = GL_RGB;
2038   fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
2039
2040   fb_format[1] = GL_BGR;
2041   fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
2042
2043   fb_format[2] = GL_BGRA;
2044   fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
2045
2046   for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
2047      __DRIconfig **new_configs;
2048
2049      new_configs = driCreateConfigs(fb_format[color], fb_type[color],
2050				     depth_bits,
2051				     stencil_bits,
2052				     ARRAY_SIZE(depth_bits),
2053				     back_buffer_modes,
2054				     ARRAY_SIZE(back_buffer_modes),
2055				     msaa_samples_array,
2056				     ARRAY_SIZE(msaa_samples_array),
2057				     GL_TRUE);
2058      if (configs == NULL)
2059	 configs = new_configs;
2060      else
2061	 configs = driConcatConfigs(configs, new_configs);
2062   }
2063
2064   if (configs == NULL) {
2065      fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
2066              __LINE__);
2067      return NULL;
2068   }
2069
2070   return (const __DRIconfig **)configs;
2071}
2072
2073/**
2074 * Get information about previous buffer swaps.
2075 */
2076static int
2077getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
2078{
2079    struct radeon_framebuffer *rfb;
2080
2081    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
2082	 || (dPriv->driContextPriv->driverPrivate == NULL)
2083	 || (sInfo == NULL) ) {
2084	return -1;
2085   }
2086
2087    rfb = dPriv->driverPrivate;
2088    sInfo->swap_count = rfb->swap_count;
2089    sInfo->swap_ust = rfb->swap_ust;
2090    sInfo->swap_missed_count = rfb->swap_missed_count;
2091
2092   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
2093       ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
2094       : 0.0;
2095
2096   return 0;
2097}
2098
2099const struct __DriverAPIRec driDriverAPI = {
2100   .InitScreen      = radeonInitScreen,
2101   .DestroyScreen   = radeonDestroyScreen,
2102#if defined(RADEON_R200)
2103   .CreateContext   = r200CreateContext,
2104   .DestroyContext  = r200DestroyContext,
2105#elif defined(RADEON_R600)
2106   .CreateContext   = r600CreateContext,
2107   .DestroyContext  = radeonDestroyContext,
2108#elif defined(RADEON_R300)
2109   .CreateContext   = r300CreateContext,
2110   .DestroyContext  = radeonDestroyContext,
2111#else
2112   .CreateContext   = r100CreateContext,
2113   .DestroyContext  = radeonDestroyContext,
2114#endif
2115   .CreateBuffer    = radeonCreateBuffer,
2116   .DestroyBuffer   = radeonDestroyBuffer,
2117   .SwapBuffers     = radeonSwapBuffers,
2118   .MakeCurrent     = radeonMakeCurrent,
2119   .UnbindContext   = radeonUnbindContext,
2120   .GetSwapInfo     = getSwapInfo,
2121   .GetDrawableMSC  = driDrawableGetMSC32,
2122   .WaitForMSC      = driWaitForMSC32,
2123   .WaitForSBC      = NULL,
2124   .SwapBuffersMSC  = NULL,
2125   .CopySubBuffer   = radeonCopySubBuffer,
2126    /* DRI2 */
2127   .InitScreen2     = radeonInitScreen2,
2128};
2129
2130/* This is the table of extensions that the loader will dlsym() for. */
2131PUBLIC const __DRIextension *__driDriverExtensions[] = {
2132    &driCoreExtension.base,
2133    &driLegacyExtension.base,
2134    &driDRI2Extension.base,
2135    NULL
2136};
2137